1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
368 directive_literal_prefix
,
370 directive_absolute_literals
,
371 directive_last_directive
377 bfd_boolean can_be_negated
;
380 const directive_infoS directive_info
[] =
383 { "literal", FALSE
},
385 { "transform", TRUE
},
386 { "freeregs", FALSE
},
387 { "longcalls", TRUE
},
388 { "literal_prefix", FALSE
},
389 { "schedule", TRUE
},
390 { "absolute-literals", TRUE
}
393 bfd_boolean directive_state
[] =
397 #if !XCHAL_HAVE_DENSITY
402 TRUE
, /* transform */
403 FALSE
, /* freeregs */
404 FALSE
, /* longcalls */
405 FALSE
, /* literal_prefix */
407 #if XSHAL_USE_ABSOLUTE_LITERALS
408 TRUE
/* absolute_literals */
410 FALSE
/* absolute_literals */
415 /* Directive functions. */
417 static void xtensa_begin_directive (int);
418 static void xtensa_end_directive (int);
419 static void xtensa_literal_prefix (char const *, int);
420 static void xtensa_literal_position (int);
421 static void xtensa_literal_pseudo (int);
422 static void xtensa_frequency_pseudo (int);
423 static void xtensa_elf_cons (int);
425 /* Parsing and Idiom Translation. */
427 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
429 /* Various Other Internal Functions. */
431 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
432 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
433 static void xtensa_mark_literal_pool_location (void);
434 static addressT
get_expanded_loop_offset (xtensa_opcode
);
435 static fragS
*get_literal_pool_location (segT
);
436 static void set_literal_pool_location (segT
, fragS
*);
437 static void xtensa_set_frag_assembly_state (fragS
*);
438 static void finish_vinsn (vliw_insn
*);
439 static bfd_boolean
emit_single_op (TInsn
*);
440 static int total_frag_text_expansion (fragS
*);
442 /* Alignment Functions. */
444 static int get_text_align_power (unsigned);
445 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
446 static int branch_align_power (segT
);
448 /* Helpers for xtensa_relax_frag(). */
450 static long relax_frag_add_nop (fragS
*);
452 /* Accessors for additional per-subsegment information. */
454 static unsigned get_last_insn_flags (segT
, subsegT
);
455 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
456 static float get_subseg_total_freq (segT
, subsegT
);
457 static float get_subseg_target_freq (segT
, subsegT
);
458 static void set_subseg_freq (segT
, subsegT
, float, float);
460 /* Segment list functions. */
462 static void xtensa_move_literals (void);
463 static void xtensa_reorder_segments (void);
464 static void xtensa_switch_to_literal_fragment (emit_state
*);
465 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
466 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
467 static void xtensa_restore_emit_state (emit_state
*);
468 static void cache_literal_section
469 (seg_list
*, const char *, segT
*, bfd_boolean
);
471 /* Import from elf32-xtensa.c in BFD library. */
473 extern char *xtensa_get_property_section_name (asection
*, const char *);
475 /* op_placement_info functions. */
477 static void init_op_placement_info_table (void);
478 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
479 static int xg_get_single_size (xtensa_opcode
);
480 static xtensa_format
xg_get_single_format (xtensa_opcode
);
481 static int xg_get_single_slot (xtensa_opcode
);
483 /* TInsn and IStack functions. */
485 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
486 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
487 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
488 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
489 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
490 static void tinsn_from_chars (TInsn
*, char *, int);
491 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
492 static int get_num_stack_text_bytes (IStack
*);
493 static int get_num_stack_literal_bytes (IStack
*);
495 /* vliw_insn functions. */
497 static void xg_init_vinsn (vliw_insn
*);
498 static void xg_clear_vinsn (vliw_insn
*);
499 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
500 static void xg_free_vinsn (vliw_insn
*);
501 static bfd_boolean vinsn_to_insnbuf
502 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
503 static void vinsn_from_chars (vliw_insn
*, char *);
505 /* Expression Utilities. */
507 bfd_boolean
expr_is_const (const expressionS
*);
508 offsetT
get_expr_const (const expressionS
*);
509 void set_expr_const (expressionS
*, offsetT
);
510 bfd_boolean
expr_is_register (const expressionS
*);
511 offsetT
get_expr_register (const expressionS
*);
512 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
513 static void set_expr_symbol_offset_diff
514 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
515 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
516 static void copy_expr (expressionS
*, const expressionS
*);
518 /* Section renaming. */
520 static void build_section_rename (const char *);
523 /* ISA imported from bfd. */
524 extern xtensa_isa xtensa_default_isa
;
526 extern int target_big_endian
;
528 static xtensa_opcode xtensa_addi_opcode
;
529 static xtensa_opcode xtensa_addmi_opcode
;
530 static xtensa_opcode xtensa_call0_opcode
;
531 static xtensa_opcode xtensa_call4_opcode
;
532 static xtensa_opcode xtensa_call8_opcode
;
533 static xtensa_opcode xtensa_call12_opcode
;
534 static xtensa_opcode xtensa_callx0_opcode
;
535 static xtensa_opcode xtensa_callx4_opcode
;
536 static xtensa_opcode xtensa_callx8_opcode
;
537 static xtensa_opcode xtensa_callx12_opcode
;
538 static xtensa_opcode xtensa_const16_opcode
;
539 static xtensa_opcode xtensa_entry_opcode
;
540 static xtensa_opcode xtensa_movi_opcode
;
541 static xtensa_opcode xtensa_movi_n_opcode
;
542 static xtensa_opcode xtensa_isync_opcode
;
543 static xtensa_opcode xtensa_jx_opcode
;
544 static xtensa_opcode xtensa_l32r_opcode
;
545 static xtensa_opcode xtensa_loop_opcode
;
546 static xtensa_opcode xtensa_loopnez_opcode
;
547 static xtensa_opcode xtensa_loopgtz_opcode
;
548 static xtensa_opcode xtensa_nop_opcode
;
549 static xtensa_opcode xtensa_nop_n_opcode
;
550 static xtensa_opcode xtensa_or_opcode
;
551 static xtensa_opcode xtensa_ret_opcode
;
552 static xtensa_opcode xtensa_ret_n_opcode
;
553 static xtensa_opcode xtensa_retw_opcode
;
554 static xtensa_opcode xtensa_retw_n_opcode
;
555 static xtensa_opcode xtensa_rsr_lcount_opcode
;
556 static xtensa_opcode xtensa_waiti_opcode
;
559 /* Command-line Options. */
561 bfd_boolean use_literal_section
= TRUE
;
562 static bfd_boolean align_targets
= TRUE
;
563 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
564 static bfd_boolean has_a0_b_retw
= FALSE
;
565 static bfd_boolean workaround_a0_b_retw
= FALSE
;
566 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
567 static bfd_boolean workaround_short_loop
= FALSE
;
568 static bfd_boolean maybe_has_short_loop
= FALSE
;
569 static bfd_boolean workaround_close_loop_end
= FALSE
;
570 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
572 /* When workaround_short_loops is TRUE, all loops with early exits must
573 have at least 3 instructions. workaround_all_short_loops is a modifier
574 to the workaround_short_loop flag. In addition to the
575 workaround_short_loop actions, all straightline loopgtz and loopnez
576 must have at least 3 instructions. */
578 static bfd_boolean workaround_all_short_loops
= FALSE
;
582 xtensa_setup_hw_workarounds (int earliest
, int latest
)
584 if (earliest
> latest
)
585 as_fatal (_("illegal range of target hardware versions"));
587 /* Enable all workarounds for pre-T1050.0 hardware. */
588 if (earliest
< 105000 || latest
< 105000)
590 workaround_a0_b_retw
|= TRUE
;
591 workaround_b_j_loop_end
|= TRUE
;
592 workaround_short_loop
|= TRUE
;
593 workaround_close_loop_end
|= TRUE
;
594 workaround_all_short_loops
|= TRUE
;
601 option_density
= OPTION_MD_BASE
,
608 option_no_link_relax
,
616 option_text_section_literals
,
617 option_no_text_section_literals
,
619 option_absolute_literals
,
620 option_no_absolute_literals
,
622 option_align_targets
,
623 option_no_align_targets
,
625 option_warn_unaligned_targets
,
630 option_workaround_a0_b_retw
,
631 option_no_workaround_a0_b_retw
,
633 option_workaround_b_j_loop_end
,
634 option_no_workaround_b_j_loop_end
,
636 option_workaround_short_loop
,
637 option_no_workaround_short_loop
,
639 option_workaround_all_short_loops
,
640 option_no_workaround_all_short_loops
,
642 option_workaround_close_loop_end
,
643 option_no_workaround_close_loop_end
,
645 option_no_workarounds
,
647 option_rename_section_name
,
650 option_prefer_const16
,
652 option_target_hardware
655 const char *md_shortopts
= "";
657 struct option md_longopts
[] =
659 { "density", no_argument
, NULL
, option_density
},
660 { "no-density", no_argument
, NULL
, option_no_density
},
662 /* Both "relax" and "generics" are deprecated and treated as equivalent
663 to the "transform" option. */
664 { "relax", no_argument
, NULL
, option_relax
},
665 { "no-relax", no_argument
, NULL
, option_no_relax
},
666 { "generics", no_argument
, NULL
, option_generics
},
667 { "no-generics", no_argument
, NULL
, option_no_generics
},
669 { "transform", no_argument
, NULL
, option_transform
},
670 { "no-transform", no_argument
, NULL
, option_no_transform
},
671 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
672 { "no-text-section-literals", no_argument
, NULL
,
673 option_no_text_section_literals
},
674 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
675 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
676 /* This option was changed from -align-target to -target-align
677 because it conflicted with the "-al" option. */
678 { "target-align", no_argument
, NULL
, option_align_targets
},
679 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
680 { "warn-unaligned-targets", no_argument
, NULL
,
681 option_warn_unaligned_targets
},
682 { "longcalls", no_argument
, NULL
, option_longcalls
},
683 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
685 { "no-workaround-a0-b-retw", no_argument
, NULL
,
686 option_no_workaround_a0_b_retw
},
687 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
689 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
690 option_no_workaround_b_j_loop_end
},
691 { "workaround-b-j-loop-end", no_argument
, NULL
,
692 option_workaround_b_j_loop_end
},
694 { "no-workaround-short-loops", no_argument
, NULL
,
695 option_no_workaround_short_loop
},
696 { "workaround-short-loops", no_argument
, NULL
,
697 option_workaround_short_loop
},
699 { "no-workaround-all-short-loops", no_argument
, NULL
,
700 option_no_workaround_all_short_loops
},
701 { "workaround-all-short-loop", no_argument
, NULL
,
702 option_workaround_all_short_loops
},
704 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
705 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
707 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
709 { "no-workaround-close-loop-end", no_argument
, NULL
,
710 option_no_workaround_close_loop_end
},
711 { "workaround-close-loop-end", no_argument
, NULL
,
712 option_workaround_close_loop_end
},
714 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
716 { "link-relax", no_argument
, NULL
, option_link_relax
},
717 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
719 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
721 { NULL
, no_argument
, NULL
, 0 }
724 size_t md_longopts_size
= sizeof md_longopts
;
728 md_parse_option (int c
, char *arg
)
733 as_warn (_("--density option is ignored"));
735 case option_no_density
:
736 as_warn (_("--no-density option is ignored"));
738 case option_link_relax
:
741 case option_no_link_relax
:
744 case option_generics
:
745 as_warn (_("--generics is deprecated; use --transform instead"));
746 return md_parse_option (option_transform
, arg
);
747 case option_no_generics
:
748 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
749 return md_parse_option (option_no_transform
, arg
);
751 as_warn (_("--relax is deprecated; use --transform instead"));
752 return md_parse_option (option_transform
, arg
);
753 case option_no_relax
:
754 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform
, arg
);
756 case option_longcalls
:
757 directive_state
[directive_longcalls
] = TRUE
;
759 case option_no_longcalls
:
760 directive_state
[directive_longcalls
] = FALSE
;
762 case option_text_section_literals
:
763 use_literal_section
= FALSE
;
765 case option_no_text_section_literals
:
766 use_literal_section
= TRUE
;
768 case option_absolute_literals
:
769 if (!absolute_literals_supported
)
771 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
774 directive_state
[directive_absolute_literals
] = TRUE
;
776 case option_no_absolute_literals
:
777 directive_state
[directive_absolute_literals
] = FALSE
;
780 case option_workaround_a0_b_retw
:
781 workaround_a0_b_retw
= TRUE
;
783 case option_no_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= FALSE
;
786 case option_workaround_b_j_loop_end
:
787 workaround_b_j_loop_end
= TRUE
;
789 case option_no_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= FALSE
;
793 case option_workaround_short_loop
:
794 workaround_short_loop
= TRUE
;
796 case option_no_workaround_short_loop
:
797 workaround_short_loop
= FALSE
;
800 case option_workaround_all_short_loops
:
801 workaround_all_short_loops
= TRUE
;
803 case option_no_workaround_all_short_loops
:
804 workaround_all_short_loops
= FALSE
;
807 case option_workaround_close_loop_end
:
808 workaround_close_loop_end
= TRUE
;
810 case option_no_workaround_close_loop_end
:
811 workaround_close_loop_end
= FALSE
;
814 case option_no_workarounds
:
815 workaround_a0_b_retw
= FALSE
;
816 workaround_b_j_loop_end
= FALSE
;
817 workaround_short_loop
= FALSE
;
818 workaround_all_short_loops
= FALSE
;
819 workaround_close_loop_end
= FALSE
;
822 case option_align_targets
:
823 align_targets
= TRUE
;
825 case option_no_align_targets
:
826 align_targets
= FALSE
;
829 case option_warn_unaligned_targets
:
830 warn_unaligned_branch_targets
= TRUE
;
833 case option_rename_section_name
:
834 build_section_rename (arg
);
838 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
839 should be emitted or not. FIXME: Not implemented. */
842 case option_prefer_l32r
:
844 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
848 case option_prefer_const16
:
850 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
854 case option_target_hardware
:
856 int earliest
, latest
= 0;
857 if (*arg
== 0 || *arg
== '-')
858 as_fatal (_("invalid target hardware version"));
860 earliest
= strtol (arg
, &arg
, 0);
864 else if (*arg
== '-')
867 as_fatal (_("invalid target hardware version"));
868 latest
= strtol (arg
, &arg
, 0);
871 as_fatal (_("invalid target hardware version"));
873 xtensa_setup_hw_workarounds (earliest
, latest
);
877 case option_transform
:
878 /* This option has no affect other than to use the defaults,
879 which are already set. */
882 case option_no_transform
:
883 /* This option turns off all transformations of any kind.
884 However, because we want to preserve the state of other
885 directives, we only change its own field. Thus, before
886 you perform any transformation, always check if transform
887 is available. If you use the functions we provide for this
888 purpose, you will be ok. */
889 directive_state
[directive_transform
] = FALSE
;
899 md_show_usage (FILE *stream
)
903 --[no-]text-section-literals\n\
904 [Do not] put literals in the text section\n\
905 --[no-]absolute-literals\n\
906 [Do not] default to use non-PC-relative literals\n\
907 --[no-]target-align [Do not] try to align branch targets\n\
908 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
909 --[no-]transform [Do not] transform instructions\n\
910 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
914 /* Functions related to the list of current label symbols. */
917 xtensa_add_insn_label (symbolS
*sym
)
921 if (!free_insn_labels
)
922 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
925 l
= free_insn_labels
;
926 free_insn_labels
= l
->next
;
930 l
->next
= insn_labels
;
936 xtensa_clear_insn_labels (void)
940 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
947 /* The "loops_ok" argument is provided to allow ignoring labels that
948 define loop ends. This fixes a bug where the NOPs to align a
949 loop opcode were included in a previous zero-cost loop:
968 This argument is used to prevent moving the NOP to before the
969 loop-end label, which is what you want in this special case. */
972 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
976 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
978 symbolS
*lit_sym
= lit
->sym
;
979 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
981 S_SET_VALUE (lit_sym
, new_offset
);
982 symbol_set_frag (lit_sym
, new_frag
);
988 /* Directive data and functions. */
990 typedef struct state_stackS_struct
992 directiveE directive
;
994 bfd_boolean old_state
;
998 struct state_stackS_struct
*prev
;
1001 state_stackS
*directive_state_stack
;
1003 const pseudo_typeS md_pseudo_table
[] =
1005 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1006 { "literal_position", xtensa_literal_position
, 0 },
1007 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1008 { "long", xtensa_elf_cons
, 4 },
1009 { "word", xtensa_elf_cons
, 4 },
1010 { "short", xtensa_elf_cons
, 2 },
1011 { "begin", xtensa_begin_directive
, 0 },
1012 { "end", xtensa_end_directive
, 0 },
1013 { "literal", xtensa_literal_pseudo
, 0 },
1014 { "frequency", xtensa_frequency_pseudo
, 0 },
1020 use_transform (void)
1022 /* After md_end, you should be checking frag by frag, rather
1023 than state directives. */
1024 assert (!past_xtensa_end
);
1025 return directive_state
[directive_transform
];
1030 do_align_targets (void)
1032 /* Do not use this function after md_end; just look at align_targets
1033 instead. There is no target-align directive, so alignment is either
1034 enabled for all frags or not done at all. */
1035 assert (!past_xtensa_end
);
1036 return align_targets
&& use_transform ();
1041 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1045 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1047 as_where (&file
, &line
);
1049 stack
->directive
= directive
;
1050 stack
->negated
= negated
;
1051 stack
->old_state
= directive_state
[directive
];
1054 stack
->datum
= datum
;
1055 stack
->prev
= directive_state_stack
;
1056 directive_state_stack
= stack
;
1058 directive_state
[directive
] = !negated
;
1063 directive_pop (directiveE
*directive
,
1064 bfd_boolean
*negated
,
1069 state_stackS
*top
= directive_state_stack
;
1071 if (!directive_state_stack
)
1073 as_bad (_("unmatched end directive"));
1074 *directive
= directive_none
;
1078 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1079 *directive
= top
->directive
;
1080 *negated
= top
->negated
;
1083 *datum
= top
->datum
;
1084 directive_state_stack
= top
->prev
;
1090 directive_balance (void)
1092 while (directive_state_stack
)
1094 directiveE directive
;
1095 bfd_boolean negated
;
1100 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1101 as_warn_where ((char *) file
, line
,
1102 _(".begin directive with no matching .end directive"));
1108 inside_directive (directiveE dir
)
1110 state_stackS
*top
= directive_state_stack
;
1112 while (top
&& top
->directive
!= dir
)
1115 return (top
!= NULL
);
1120 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1124 char *directive_string
;
1126 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1131 input_line_pointer
+= 3;
1134 len
= strspn (input_line_pointer
,
1135 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1137 /* This code is a hack to make .begin [no-][generics|relax] exactly
1138 equivalent to .begin [no-]transform. We should remove it when
1139 we stop accepting those options. */
1141 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1143 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1144 directive_string
= "transform";
1146 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1148 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1152 directive_string
= input_line_pointer
;
1154 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1156 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1158 input_line_pointer
+= len
;
1159 *directive
= (directiveE
) i
;
1160 if (*negated
&& !directive_info
[i
].can_be_negated
)
1161 as_bad (_("directive %s cannot be negated"),
1162 directive_info
[i
].name
);
1167 as_bad (_("unknown directive"));
1168 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1173 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1175 directiveE directive
;
1176 bfd_boolean negated
;
1181 get_directive (&directive
, &negated
);
1182 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1184 discard_rest_of_line ();
1188 if (cur_vinsn
.inside_bundle
)
1189 as_bad (_("directives are not valid inside bundles"));
1193 case directive_literal
:
1194 if (!inside_directive (directive_literal
))
1196 /* Previous labels go with whatever follows this directive, not with
1197 the literal, so save them now. */
1198 saved_insn_labels
= insn_labels
;
1201 as_warn (_(".begin literal is deprecated; use .literal instead"));
1202 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1203 xtensa_switch_to_literal_fragment (state
);
1204 directive_push (directive_literal
, negated
, state
);
1207 case directive_literal_prefix
:
1208 /* Have to flush pending output because a movi relaxed to an l32r
1209 might produce a literal. */
1210 md_flush_pending_output ();
1211 /* Check to see if the current fragment is a literal
1212 fragment. If it is, then this operation is not allowed. */
1213 if (generating_literals
)
1215 as_bad (_("cannot set literal_prefix inside literal fragment"));
1219 /* Allocate the literal state for this section and push
1220 onto the directive stack. */
1221 ls
= xmalloc (sizeof (lit_state
));
1224 *ls
= default_lit_sections
;
1226 directive_push (directive_literal_prefix
, negated
, ls
);
1228 /* Parse the new prefix from the input_line_pointer. */
1230 len
= strspn (input_line_pointer
,
1231 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1232 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1234 /* Process the new prefix. */
1235 xtensa_literal_prefix (input_line_pointer
, len
);
1237 /* Skip the name in the input line. */
1238 input_line_pointer
+= len
;
1241 case directive_freeregs
:
1242 /* This information is currently unused, but we'll accept the statement
1243 and just discard the rest of the line. This won't check the syntax,
1244 but it will accept every correct freeregs directive. */
1245 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1246 directive_push (directive_freeregs
, negated
, 0);
1249 case directive_schedule
:
1250 md_flush_pending_output ();
1251 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1252 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1253 directive_push (directive_schedule
, negated
, 0);
1254 xtensa_set_frag_assembly_state (frag_now
);
1257 case directive_density
:
1258 as_warn (_(".begin [no-]density is ignored"));
1261 case directive_absolute_literals
:
1262 md_flush_pending_output ();
1263 if (!absolute_literals_supported
&& !negated
)
1265 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1268 xtensa_set_frag_assembly_state (frag_now
);
1269 directive_push (directive
, negated
, 0);
1273 md_flush_pending_output ();
1274 xtensa_set_frag_assembly_state (frag_now
);
1275 directive_push (directive
, negated
, 0);
1279 demand_empty_rest_of_line ();
1284 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1286 directiveE begin_directive
, end_directive
;
1287 bfd_boolean begin_negated
, end_negated
;
1291 emit_state
**state_ptr
;
1294 if (cur_vinsn
.inside_bundle
)
1295 as_bad (_("directives are not valid inside bundles"));
1297 get_directive (&end_directive
, &end_negated
);
1299 md_flush_pending_output ();
1301 switch (end_directive
)
1303 case (directiveE
) XTENSA_UNDEFINED
:
1304 discard_rest_of_line ();
1307 case directive_density
:
1308 as_warn (_(".end [no-]density is ignored"));
1309 demand_empty_rest_of_line ();
1312 case directive_absolute_literals
:
1313 if (!absolute_literals_supported
&& !end_negated
)
1315 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1316 demand_empty_rest_of_line ();
1325 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1326 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1327 (const void **) state_ptr
);
1329 if (begin_directive
!= directive_none
)
1331 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1333 as_bad (_("does not match begin %s%s at %s:%d"),
1334 begin_negated
? "no-" : "",
1335 directive_info
[begin_directive
].name
, file
, line
);
1339 switch (end_directive
)
1341 case directive_literal
:
1342 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1343 xtensa_restore_emit_state (state
);
1344 xtensa_set_frag_assembly_state (frag_now
);
1346 if (!inside_directive (directive_literal
))
1348 /* Restore the list of current labels. */
1349 xtensa_clear_insn_labels ();
1350 insn_labels
= saved_insn_labels
;
1354 case directive_literal_prefix
:
1355 /* Restore the default collection sections from saved state. */
1356 s
= (lit_state
*) state
;
1359 default_lit_sections
= *s
;
1361 /* free the state storage */
1365 case directive_schedule
:
1366 case directive_freeregs
:
1370 xtensa_set_frag_assembly_state (frag_now
);
1376 demand_empty_rest_of_line ();
1380 /* Place an aligned literal fragment at the current location. */
1383 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1385 md_flush_pending_output ();
1387 if (inside_directive (directive_literal
))
1388 as_warn (_(".literal_position inside literal directive; ignoring"));
1389 xtensa_mark_literal_pool_location ();
1391 demand_empty_rest_of_line ();
1392 xtensa_clear_insn_labels ();
1396 /* Support .literal label, expr, ... */
1399 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1402 char *p
, *base_name
;
1406 if (inside_directive (directive_literal
))
1408 as_bad (_(".literal not allowed inside .begin literal region"));
1409 ignore_rest_of_line ();
1413 md_flush_pending_output ();
1415 /* Previous labels go with whatever follows this directive, not with
1416 the literal, so save them now. */
1417 saved_insn_labels
= insn_labels
;
1420 /* If we are using text-section literals, then this is the right value... */
1423 base_name
= input_line_pointer
;
1425 xtensa_switch_to_literal_fragment (&state
);
1427 /* ...but if we aren't using text-section-literals, then we
1428 need to put them in the section we just switched to. */
1429 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1432 /* All literals are aligned to four-byte boundaries. */
1433 frag_align (2, 0, 0);
1434 record_alignment (now_seg
, 2);
1436 c
= get_symbol_end ();
1437 /* Just after name is now '\0'. */
1438 p
= input_line_pointer
;
1442 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1444 as_bad (_("expected comma or colon after symbol name; "
1445 "rest of line ignored"));
1446 ignore_rest_of_line ();
1447 xtensa_restore_emit_state (&state
);
1455 input_line_pointer
++; /* skip ',' or ':' */
1457 xtensa_elf_cons (4);
1459 xtensa_restore_emit_state (&state
);
1461 /* Restore the list of current labels. */
1462 xtensa_clear_insn_labels ();
1463 insn_labels
= saved_insn_labels
;
1468 xtensa_literal_prefix (char const *start
, int len
)
1470 char *name
, *linkonce_suffix
;
1471 char *newname
, *newname4
;
1472 size_t linkonce_len
;
1474 /* Get a null-terminated copy of the name. */
1475 name
= xmalloc (len
+ 1);
1478 strncpy (name
, start
, len
);
1481 /* Allocate the sections (interesting note: the memory pointing to
1482 the name is actually used for the name by the new section). */
1484 newname
= xmalloc (len
+ strlen (".literal") + 1);
1485 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1487 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1488 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1489 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1491 strcpy (newname
, ".gnu.linkonce.literal");
1492 strcpy (newname4
, ".gnu.linkonce.lit4");
1494 strcat (newname
, linkonce_suffix
);
1495 strcat (newname4
, linkonce_suffix
);
1499 int suffix_pos
= len
;
1501 /* If the section name ends with ".text", then replace that suffix
1502 instead of appending an additional suffix. */
1503 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1506 strcpy (newname
, name
);
1507 strcpy (newname4
, name
);
1509 strcpy (newname
+ suffix_pos
, ".literal");
1510 strcpy (newname4
+ suffix_pos
, ".lit4");
1513 /* Note that cache_literal_section does not create a segment if
1514 it already exists. */
1515 default_lit_sections
.lit_seg
= NULL
;
1516 default_lit_sections
.lit4_seg
= NULL
;
1518 /* Canonicalizing section names allows renaming literal
1519 sections to occur correctly. */
1520 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1521 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1527 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1530 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1532 float fall_through_f
, target_f
;
1534 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1535 if (fall_through_f
< 0)
1537 as_bad (_("fall through frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1545 as_bad (_("branch target frequency must be greater than 0"));
1546 ignore_rest_of_line ();
1550 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1552 demand_empty_rest_of_line ();
1556 /* Like normal .long/.short/.word, except support @plt, etc.
1557 Clobbers input_line_pointer, checks end-of-line. */
1560 xtensa_elf_cons (int nbytes
)
1563 bfd_reloc_code_real_type reloc
;
1565 md_flush_pending_output ();
1567 if (cur_vinsn
.inside_bundle
)
1568 as_bad (_("directives are not valid inside bundles"));
1570 if (is_it_end_of_statement ())
1572 demand_empty_rest_of_line ();
1579 if (exp
.X_op
== O_symbol
1580 && *input_line_pointer
== '@'
1581 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1584 reloc_howto_type
*reloc_howto
=
1585 bfd_reloc_type_lookup (stdoutput
, reloc
);
1587 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1588 as_bad (_("unsupported relocation"));
1589 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1591 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1592 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1593 as_bad (_("opcode-specific %s relocation used outside "
1594 "an instruction"), reloc_howto
->name
);
1595 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1596 as_bad (_("%s relocations do not fit in %d bytes"),
1597 reloc_howto
->name
, nbytes
);
1600 char *p
= frag_more ((int) nbytes
);
1601 xtensa_set_frag_assembly_state (frag_now
);
1602 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1603 nbytes
, &exp
, 0, reloc
);
1607 emit_expr (&exp
, (unsigned int) nbytes
);
1609 while (*input_line_pointer
++ == ',');
1611 input_line_pointer
--; /* Put terminator back into stream. */
1612 demand_empty_rest_of_line ();
1616 /* Parsing and Idiom Translation. */
1618 /* Parse @plt, etc. and return the desired relocation. */
1619 static bfd_reloc_code_real_type
1620 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1626 bfd_reloc_code_real_type reloc
;
1634 struct map_bfd
*ptr
;
1636 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1638 static struct map_bfd mapping
[] =
1640 MAP ("l", BFD_RELOC_LO16
),
1641 MAP ("h", BFD_RELOC_HI16
),
1642 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1643 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1647 return BFD_RELOC_NONE
;
1649 for (ch
= *str
, str2
= ident
;
1650 (str2
< ident
+ sizeof (ident
) - 1
1651 && (ISALNUM (ch
) || ch
== '@'));
1654 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1661 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1662 if (ch
== ptr
->string
[0]
1663 && len
== ptr
->length
1664 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1666 /* Now check for "identifier@suffix+constant". */
1667 if (*str
== '-' || *str
== '+')
1669 char *orig_line
= input_line_pointer
;
1670 expressionS new_exp
;
1672 input_line_pointer
= str
;
1673 expression (&new_exp
);
1674 if (new_exp
.X_op
== O_constant
)
1676 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1677 str
= input_line_pointer
;
1680 if (&input_line_pointer
!= str_p
)
1681 input_line_pointer
= orig_line
;
1688 return BFD_RELOC_UNUSED
;
1693 expression_end (const char *name
)
1716 #define ERROR_REG_NUM ((unsigned) -1)
1719 tc_get_register (const char *prefix
)
1722 const char *next_expr
;
1723 const char *old_line_pointer
;
1726 old_line_pointer
= input_line_pointer
;
1728 if (*input_line_pointer
== '$')
1729 ++input_line_pointer
;
1731 /* Accept "sp" as a synonym for "a1". */
1732 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1733 && expression_end (input_line_pointer
+ 2))
1735 input_line_pointer
+= 2;
1736 return 1; /* AR[1] */
1739 while (*input_line_pointer
++ == *prefix
++)
1741 --input_line_pointer
;
1746 as_bad (_("bad register name: %s"), old_line_pointer
);
1747 return ERROR_REG_NUM
;
1750 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1752 as_bad (_("bad register number: %s"), input_line_pointer
);
1753 return ERROR_REG_NUM
;
1758 while (ISDIGIT ((int) *input_line_pointer
))
1759 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1761 if (!(next_expr
= expression_end (input_line_pointer
)))
1763 as_bad (_("bad register name: %s"), old_line_pointer
);
1764 return ERROR_REG_NUM
;
1767 input_line_pointer
= (char *) next_expr
;
1774 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1776 xtensa_isa isa
= xtensa_default_isa
;
1778 /* Check if this is an immediate operand. */
1779 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1781 bfd_reloc_code_real_type reloc
;
1782 segT t
= expression (tok
);
1783 if (t
== absolute_section
1784 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1786 assert (tok
->X_op
== O_constant
);
1787 tok
->X_op
= O_symbol
;
1788 tok
->X_add_symbol
= &abs_symbol
;
1791 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1792 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1793 && (reloc
!= BFD_RELOC_NONE
))
1798 case BFD_RELOC_UNUSED
:
1799 as_bad (_("unsupported relocation"));
1802 case BFD_RELOC_XTENSA_PLT
:
1803 tok
->X_op
= O_pltrel
;
1806 case BFD_RELOC_LO16
:
1807 if (tok
->X_op
== O_constant
)
1808 tok
->X_add_number
&= 0xffff;
1813 case BFD_RELOC_HI16
:
1814 if (tok
->X_op
== O_constant
)
1815 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1824 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1825 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1827 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1830 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1831 as_bad (_("register number out of range"));
1834 tok
->X_op
= O_register
;
1835 tok
->X_add_symbol
= 0;
1836 tok
->X_add_number
= reg
;
1841 /* Split up the arguments for an opcode or pseudo-op. */
1844 tokenize_arguments (char **args
, char *str
)
1846 char *old_input_line_pointer
;
1847 bfd_boolean saw_comma
= FALSE
;
1848 bfd_boolean saw_arg
= FALSE
;
1849 bfd_boolean saw_colon
= FALSE
;
1851 char *arg_end
, *arg
;
1854 /* Save and restore input_line_pointer around this function. */
1855 old_input_line_pointer
= input_line_pointer
;
1856 input_line_pointer
= str
;
1858 while (*input_line_pointer
)
1861 switch (*input_line_pointer
)
1868 input_line_pointer
++;
1869 if (saw_comma
|| saw_colon
|| !saw_arg
)
1875 input_line_pointer
++;
1876 if (saw_comma
|| saw_colon
|| !saw_arg
)
1882 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1885 arg_end
= input_line_pointer
+ 1;
1886 while (!expression_end (arg_end
))
1889 arg_len
= arg_end
- input_line_pointer
;
1890 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1891 args
[num_args
] = arg
;
1895 strncpy (arg
, input_line_pointer
, arg_len
);
1896 arg
[arg_len
] = '\0';
1898 input_line_pointer
= arg_end
;
1908 if (saw_comma
|| saw_colon
)
1910 input_line_pointer
= old_input_line_pointer
;
1915 as_bad (_("extra comma"));
1917 as_bad (_("extra colon"));
1919 as_bad (_("missing argument"));
1921 as_bad (_("missing comma or colon"));
1922 input_line_pointer
= old_input_line_pointer
;
1927 /* Parse the arguments to an opcode. Return TRUE on error. */
1930 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1932 expressionS
*tok
, *last_tok
;
1933 xtensa_opcode opcode
= insn
->opcode
;
1934 bfd_boolean had_error
= TRUE
;
1935 xtensa_isa isa
= xtensa_default_isa
;
1936 int n
, num_regs
= 0;
1937 int opcode_operand_count
;
1938 int opnd_cnt
, last_opnd_cnt
;
1939 unsigned int next_reg
= 0;
1940 char *old_input_line_pointer
;
1942 if (insn
->insn_type
== ITYPE_LITERAL
)
1943 opcode_operand_count
= 1;
1945 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1948 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1950 /* Save and restore input_line_pointer around this function. */
1951 old_input_line_pointer
= input_line_pointer
;
1957 /* Skip invisible operands. */
1958 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1964 for (n
= 0; n
< num_args
; n
++)
1966 input_line_pointer
= arg_strings
[n
];
1967 if (*input_line_pointer
== ':')
1969 xtensa_regfile opnd_rf
;
1970 input_line_pointer
++;
1973 assert (opnd_cnt
> 0);
1975 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1977 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1978 as_warn (_("incorrect register number, ignoring"));
1983 if (opnd_cnt
>= opcode_operand_count
)
1985 as_warn (_("too many arguments"));
1988 assert (opnd_cnt
< MAX_INSN_ARGS
);
1990 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1991 next_reg
= tok
->X_add_number
+ 1;
1993 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1995 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1997 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1998 /* minus 1 because we are seeing one right now */
2004 last_opnd_cnt
= opnd_cnt
;
2011 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2015 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2018 insn
->ntok
= tok
- insn
->tok
;
2022 input_line_pointer
= old_input_line_pointer
;
2028 get_invisible_operands (TInsn
*insn
)
2030 xtensa_isa isa
= xtensa_default_isa
;
2031 static xtensa_insnbuf slotbuf
= NULL
;
2033 xtensa_opcode opc
= insn
->opcode
;
2034 int slot
, opnd
, fmt_found
;
2038 slotbuf
= xtensa_insnbuf_alloc (isa
);
2040 /* Find format/slot where this can be encoded. */
2043 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2045 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2047 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2053 if (fmt_found
) break;
2058 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2062 /* First encode all the visible operands
2063 (to deal with shared field operands). */
2064 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2066 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2067 && (insn
->tok
[opnd
].X_op
== O_register
2068 || insn
->tok
[opnd
].X_op
== O_constant
))
2070 val
= insn
->tok
[opnd
].X_add_number
;
2071 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2072 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2076 /* Then pull out the values for the invisible ones. */
2077 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2079 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2081 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2082 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2083 insn
->tok
[opnd
].X_add_number
= val
;
2084 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2085 insn
->tok
[opnd
].X_op
= O_register
;
2087 insn
->tok
[opnd
].X_op
= O_constant
;
2096 xg_reverse_shift_count (char **cnt_argp
)
2098 char *cnt_arg
, *new_arg
;
2099 cnt_arg
= *cnt_argp
;
2101 /* replace the argument with "31-(argument)" */
2102 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2103 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2106 *cnt_argp
= new_arg
;
2110 /* If "arg" is a constant expression, return non-zero with the value
2114 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2117 char *save_ptr
= input_line_pointer
;
2119 input_line_pointer
= arg
;
2121 input_line_pointer
= save_ptr
;
2123 if (exp
.X_op
== O_constant
)
2125 *valp
= exp
.X_add_number
;
2134 xg_replace_opname (char **popname
, char *newop
)
2137 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2138 strcpy (*popname
, newop
);
2143 xg_check_num_args (int *pnum_args
,
2148 int num_args
= *pnum_args
;
2150 if (num_args
< expected_num
)
2152 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2153 num_args
, opname
, expected_num
);
2157 if (num_args
> expected_num
)
2159 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2160 num_args
, opname
, expected_num
);
2161 while (num_args
-- > expected_num
)
2163 free (arg_strings
[num_args
]);
2164 arg_strings
[num_args
] = 0;
2166 *pnum_args
= expected_num
;
2174 /* If the register is not specified as part of the opcode,
2175 then get it from the operand and move it to the opcode. */
2178 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2180 xtensa_isa isa
= xtensa_default_isa
;
2182 char *opname
, *new_opname
;
2183 const char *sr_name
;
2184 int is_user
, is_write
;
2185 bfd_boolean has_underbar
= FALSE
;
2190 has_underbar
= TRUE
;
2193 is_user
= (opname
[1] == 'u');
2194 is_write
= (opname
[0] == 'w');
2196 /* Opname == [rw]ur or [rwx]sr... */
2198 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2201 /* Check if the argument is a symbolic register name. */
2202 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2203 /* Handle WSR to "INTSET" as a special case. */
2204 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2205 && !strcasecmp (arg_strings
[1], "intset"))
2206 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2207 if (sr
== XTENSA_UNDEFINED
2208 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2210 /* Maybe it's a register number.... */
2212 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2214 as_bad (_("invalid register '%s' for '%s' instruction"),
2215 arg_strings
[1], opname
);
2218 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2219 if (sr
== XTENSA_UNDEFINED
)
2221 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2222 (long) val
, opname
);
2227 /* Remove the last argument, which is now part of the opcode. */
2228 free (arg_strings
[1]);
2232 /* Translate the opcode. */
2233 sr_name
= xtensa_sysreg_name (isa
, sr
);
2234 /* Another special case for "WSR.INTSET".... */
2235 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2237 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2238 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2241 *popname
= new_opname
;
2248 xtensa_translate_old_userreg_ops (char **popname
)
2250 xtensa_isa isa
= xtensa_default_isa
;
2252 char *opname
, *new_opname
;
2253 const char *sr_name
;
2254 bfd_boolean has_underbar
= FALSE
;
2257 if (opname
[0] == '_')
2259 has_underbar
= TRUE
;
2263 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2264 if (sr
!= XTENSA_UNDEFINED
)
2266 /* The new default name ("nnn") is different from the old default
2267 name ("URnnn"). The old default is handled below, and we don't
2268 want to recognize [RW]nnn, so do nothing if the name is the (new)
2270 static char namebuf
[10];
2271 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2272 if (strcmp (namebuf
, opname
+ 1) == 0)
2280 /* Only continue if the reg name is "URnnn". */
2281 if (opname
[1] != 'u' || opname
[2] != 'r')
2283 val
= strtoul (opname
+ 3, &end
, 10);
2287 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2288 if (sr
== XTENSA_UNDEFINED
)
2290 as_bad (_("invalid register number (%ld) for '%s'"),
2291 (long) val
, opname
);
2296 /* Translate the opcode. */
2297 sr_name
= xtensa_sysreg_name (isa
, sr
);
2298 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2299 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2300 opname
[0], sr_name
);
2302 *popname
= new_opname
;
2309 xtensa_translate_zero_immed (char *old_op
,
2319 assert (opname
[0] != '_');
2321 if (strcmp (opname
, old_op
) != 0)
2324 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2326 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2328 xg_replace_opname (popname
, new_op
);
2329 free (arg_strings
[1]);
2330 arg_strings
[1] = arg_strings
[2];
2339 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2340 Returns non-zero if an error was found. */
2343 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2345 char *opname
= *popname
;
2346 bfd_boolean has_underbar
= FALSE
;
2348 if (cur_vinsn
.inside_bundle
)
2353 has_underbar
= TRUE
;
2357 if (strcmp (opname
, "mov") == 0)
2359 if (use_transform () && !has_underbar
&& density_supported
)
2360 xg_replace_opname (popname
, "mov.n");
2363 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2365 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2366 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2367 strcpy (arg_strings
[2], arg_strings
[1]);
2373 if (strcmp (opname
, "bbsi.l") == 0)
2375 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2377 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2378 if (target_big_endian
)
2379 xg_reverse_shift_count (&arg_strings
[1]);
2383 if (strcmp (opname
, "bbci.l") == 0)
2385 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2387 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2388 if (target_big_endian
)
2389 xg_reverse_shift_count (&arg_strings
[1]);
2393 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2394 && strcmp (opname
, "nop") == 0)
2396 if (use_transform () && !has_underbar
&& density_supported
)
2397 xg_replace_opname (popname
, "nop.n");
2400 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2402 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2403 arg_strings
[0] = (char *) xmalloc (3);
2404 arg_strings
[1] = (char *) xmalloc (3);
2405 arg_strings
[2] = (char *) xmalloc (3);
2406 strcpy (arg_strings
[0], "a1");
2407 strcpy (arg_strings
[1], "a1");
2408 strcpy (arg_strings
[2], "a1");
2414 /* Recognize [RW]UR and [RWX]SR. */
2415 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2416 && (opname
[1] == 'u' || opname
[1] == 's'))
2417 || (opname
[0] == 'x' && opname
[1] == 's'))
2419 && opname
[3] == '\0')
2420 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2422 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2423 [RW]<name> if <name> is the non-default name of a user register. */
2424 if ((opname
[0] == 'r' || opname
[0] == 'w')
2425 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2426 return xtensa_translate_old_userreg_ops (popname
);
2428 /* Relax branches that don't allow comparisons against an immediate value
2429 of zero to the corresponding branches with implicit zero immediates. */
2430 if (!has_underbar
&& use_transform ())
2432 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2433 pnum_args
, arg_strings
))
2436 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2437 pnum_args
, arg_strings
))
2440 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2441 pnum_args
, arg_strings
))
2444 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2445 pnum_args
, arg_strings
))
2453 /* Functions for dealing with the Xtensa ISA. */
2455 /* Currently the assembler only allows us to use a single target per
2456 fragment. Because of this, only one operand for a given
2457 instruction may be symbolic. If there is a PC-relative operand,
2458 the last one is chosen. Otherwise, the result is the number of the
2459 last immediate operand, and if there are none of those, we fail and
2463 get_relaxable_immed (xtensa_opcode opcode
)
2465 int last_immed
= -1;
2468 if (opcode
== XTENSA_UNDEFINED
)
2471 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2472 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2474 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2476 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2478 if (last_immed
== -1
2479 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2486 static xtensa_opcode
2487 get_opcode_from_buf (const char *buf
, int slot
)
2489 static xtensa_insnbuf insnbuf
= NULL
;
2490 static xtensa_insnbuf slotbuf
= NULL
;
2491 xtensa_isa isa
= xtensa_default_isa
;
2496 insnbuf
= xtensa_insnbuf_alloc (isa
);
2497 slotbuf
= xtensa_insnbuf_alloc (isa
);
2500 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2501 fmt
= xtensa_format_decode (isa
, insnbuf
);
2502 if (fmt
== XTENSA_UNDEFINED
)
2503 return XTENSA_UNDEFINED
;
2505 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2506 return XTENSA_UNDEFINED
;
2508 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2509 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2513 #ifdef TENSILICA_DEBUG
2515 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2518 xtensa_print_insn_table (void)
2520 int num_opcodes
, num_operands
;
2521 xtensa_opcode opcode
;
2522 xtensa_isa isa
= xtensa_default_isa
;
2524 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2525 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2528 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2529 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2530 for (opn
= 0; opn
< num_operands
; opn
++)
2532 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2534 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2536 xtensa_regfile opnd_rf
=
2537 xtensa_operand_regfile (isa
, opcode
, opn
);
2538 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2540 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2541 fputs ("[lLr] ", stderr
);
2543 fputs ("i ", stderr
);
2545 fprintf (stderr
, "\n");
2551 print_vliw_insn (xtensa_insnbuf vbuf
)
2553 xtensa_isa isa
= xtensa_default_isa
;
2554 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2555 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2558 fprintf (stderr
, "format = %d\n", f
);
2560 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2562 xtensa_opcode opcode
;
2566 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2567 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2568 opname
= xtensa_opcode_name (isa
, opcode
);
2570 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2571 fprintf (stderr
, " operands = ");
2573 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2577 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2579 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2580 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2581 fprintf (stderr
, "%d ", val
);
2583 fprintf (stderr
, "\n");
2585 xtensa_insnbuf_free (isa
, sbuf
);
2588 #endif /* TENSILICA_DEBUG */
2592 is_direct_call_opcode (xtensa_opcode opcode
)
2594 xtensa_isa isa
= xtensa_default_isa
;
2595 int n
, num_operands
;
2597 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2600 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2601 for (n
= 0; n
< num_operands
; n
++)
2603 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2604 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2611 /* Convert from BFD relocation type code to slot and operand number.
2612 Returns non-zero on failure. */
2615 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2617 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2618 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2620 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2623 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2624 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2626 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2636 /* Convert from slot number to BFD relocation type code for the
2637 standard PC-relative relocations. Return BFD_RELOC_NONE on
2640 static bfd_reloc_code_real_type
2641 encode_reloc (int slot
)
2643 if (slot
< 0 || slot
> 14)
2644 return BFD_RELOC_NONE
;
2646 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2650 /* Convert from slot numbers to BFD relocation type code for the
2651 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2653 static bfd_reloc_code_real_type
2654 encode_alt_reloc (int slot
)
2656 if (slot
< 0 || slot
> 14)
2657 return BFD_RELOC_NONE
;
2659 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2664 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2667 xtensa_opcode opcode
,
2673 uint32 valbuf
= value
;
2675 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2677 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2679 as_bad_where ((char *) file
, line
,
2680 _("operand %d of '%s' has out of range value '%u'"),
2682 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2685 as_bad_where ((char *) file
, line
,
2686 _("operand %d of '%s' has invalid value '%u'"),
2688 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2693 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2699 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2702 xtensa_opcode opcode
,
2706 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2707 fmt
, slot
, slotbuf
, &val
);
2708 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2713 /* Checks for rules from xtensa-relax tables. */
2715 /* The routine xg_instruction_matches_option_term must return TRUE
2716 when a given option term is true. The meaning of all of the option
2717 terms is given interpretation by this function. This is needed when
2718 an option depends on the state of a directive, but there are no such
2719 options in use right now. */
2722 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2723 const ReqOrOption
*option
)
2725 if (strcmp (option
->option_name
, "realnop") == 0
2726 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2728 /* These conditions were evaluated statically when building the
2729 relaxation table. There's no need to reevaluate them now. */
2734 as_fatal (_("internal error: unknown option name '%s'"),
2735 option
->option_name
);
2741 xg_instruction_matches_or_options (TInsn
*insn
,
2742 const ReqOrOptionList
*or_option
)
2744 const ReqOrOption
*option
;
2745 /* Must match each of the AND terms. */
2746 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2748 if (xg_instruction_matches_option_term (insn
, option
))
2756 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2758 const ReqOption
*req_options
;
2759 /* Must match each of the AND terms. */
2760 for (req_options
= options
;
2761 req_options
!= NULL
;
2762 req_options
= req_options
->next
)
2764 /* Must match one of the OR clauses. */
2765 if (!xg_instruction_matches_or_options (insn
,
2766 req_options
->or_option_terms
))
2773 /* Return the transition rule that matches or NULL if none matches. */
2776 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2778 PreconditionList
*condition_l
;
2780 if (rule
->opcode
!= insn
->opcode
)
2783 for (condition_l
= rule
->conditions
;
2784 condition_l
!= NULL
;
2785 condition_l
= condition_l
->next
)
2789 Precondition
*cond
= condition_l
->precond
;
2794 /* The expression must be the constant. */
2795 assert (cond
->op_num
< insn
->ntok
);
2796 exp1
= &insn
->tok
[cond
->op_num
];
2797 if (expr_is_const (exp1
))
2802 if (get_expr_const (exp1
) != cond
->op_data
)
2806 if (get_expr_const (exp1
) == cond
->op_data
)
2813 else if (expr_is_register (exp1
))
2818 if (get_expr_register (exp1
) != cond
->op_data
)
2822 if (get_expr_register (exp1
) == cond
->op_data
)
2834 assert (cond
->op_num
< insn
->ntok
);
2835 assert (cond
->op_data
< insn
->ntok
);
2836 exp1
= &insn
->tok
[cond
->op_num
];
2837 exp2
= &insn
->tok
[cond
->op_data
];
2842 if (!expr_is_equal (exp1
, exp2
))
2846 if (expr_is_equal (exp1
, exp2
))
2858 if (!xg_instruction_matches_options (insn
, rule
->options
))
2866 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2868 bfd_boolean a_greater
= FALSE
;
2869 bfd_boolean b_greater
= FALSE
;
2871 ReqOptionList
*l_a
= a
->options
;
2872 ReqOptionList
*l_b
= b
->options
;
2874 /* We only care if they both are the same except for
2875 a const16 vs. an l32r. */
2877 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2879 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2880 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2881 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2883 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2885 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2887 /* This is the case we care about. */
2888 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2889 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2896 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2897 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2907 l_or_a
= l_or_a
->next
;
2908 l_or_b
= l_or_b
->next
;
2910 if (l_or_a
|| l_or_b
)
2919 /* Incomparable if the substitution was used differently in two cases. */
2920 if (a_greater
&& b_greater
)
2932 static TransitionRule
*
2933 xg_instruction_match (TInsn
*insn
)
2935 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2937 assert (insn
->opcode
< table
->num_opcodes
);
2939 /* Walk through all of the possible transitions. */
2940 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2942 TransitionRule
*rule
= l
->rule
;
2943 if (xg_instruction_matches_rule (insn
, rule
))
2950 /* Various Other Internal Functions. */
2953 is_unique_insn_expansion (TransitionRule
*r
)
2955 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2957 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2963 /* Check if there is exactly one relaxation for INSN that converts it to
2964 another instruction of equal or larger size. If so, and if TARG is
2965 non-null, go ahead and generate the relaxed instruction into TARG. If
2966 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2967 instruction, i.e., ignore relaxations that convert to an instruction of
2968 equal size. In some contexts where this function is used, only
2969 a single widening is allowed and the NARROW_ONLY argument is used to
2970 exclude cases like ADDI being "widened" to an ADDMI, which may
2971 later be relaxed to an ADDMI/ADDI pair. */
2974 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2976 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2978 TransitionRule
*match
= 0;
2980 assert (insn
->insn_type
== ITYPE_INSN
);
2981 assert (insn
->opcode
< table
->num_opcodes
);
2983 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2985 TransitionRule
*rule
= l
->rule
;
2987 if (xg_instruction_matches_rule (insn
, rule
)
2988 && is_unique_insn_expansion (rule
)
2989 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2990 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3001 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3006 /* Return the maximum number of bytes this opcode can expand to. */
3009 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3011 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3013 int max_size
= xg_get_single_size (opcode
);
3015 assert (opcode
< table
->num_opcodes
);
3017 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3019 TransitionRule
*rule
= l
->rule
;
3020 BuildInstr
*build_list
;
3025 build_list
= rule
->to_instr
;
3026 if (is_unique_insn_expansion (rule
))
3028 assert (build_list
->typ
== INSTR_INSTR
);
3029 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3032 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3034 switch (build_list
->typ
)
3037 this_size
+= xg_get_single_size (build_list
->opcode
);
3039 case INSTR_LITERAL_DEF
:
3040 case INSTR_LABEL_DEF
:
3045 if (this_size
> max_size
)
3046 max_size
= this_size
;
3052 /* Return the maximum number of literal bytes this opcode can generate. */
3055 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3057 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3061 assert (opcode
< table
->num_opcodes
);
3063 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3065 TransitionRule
*rule
= l
->rule
;
3066 BuildInstr
*build_list
;
3071 build_list
= rule
->to_instr
;
3072 if (is_unique_insn_expansion (rule
))
3074 assert (build_list
->typ
== INSTR_INSTR
);
3075 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3078 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3080 switch (build_list
->typ
)
3082 case INSTR_LITERAL_DEF
:
3083 /* Hard-coded 4-byte literal. */
3087 case INSTR_LABEL_DEF
:
3092 if (this_size
> max_size
)
3093 max_size
= this_size
;
3100 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3102 int steps_taken
= 0;
3103 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3106 assert (insn
->insn_type
== ITYPE_INSN
);
3107 assert (insn
->opcode
< table
->num_opcodes
);
3109 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3111 TransitionRule
*rule
= l
->rule
;
3113 if (xg_instruction_matches_rule (insn
, rule
))
3115 if (steps_taken
== lateral_steps
)
3125 get_special_literal_symbol (void)
3127 static symbolS
*sym
= NULL
;
3130 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3136 get_special_label_symbol (void)
3138 static symbolS
*sym
= NULL
;
3141 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3147 xg_valid_literal_expression (const expressionS
*exp
)
3164 /* This will check to see if the value can be converted into the
3165 operand type. It will return TRUE if it does not fit. */
3168 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3170 uint32 valbuf
= value
;
3171 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3177 /* Assumes: All immeds are constants. Check that all constants fit
3178 into their immeds; return FALSE if not. */
3181 xg_immeds_fit (const TInsn
*insn
)
3183 xtensa_isa isa
= xtensa_default_isa
;
3187 assert (insn
->insn_type
== ITYPE_INSN
);
3188 for (i
= 0; i
< n
; ++i
)
3190 const expressionS
*expr
= &insn
->tok
[i
];
3191 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3198 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3203 /* The symbol should have a fixup associated with it. */
3212 /* This should only be called after we have an initial
3213 estimate of the addresses. */
3216 xg_symbolic_immeds_fit (const TInsn
*insn
,
3222 xtensa_isa isa
= xtensa_default_isa
;
3230 assert (insn
->insn_type
== ITYPE_INSN
);
3232 for (i
= 0; i
< n
; ++i
)
3234 const expressionS
*expr
= &insn
->tok
[i
];
3235 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3242 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3248 /* Check for the worst case. */
3249 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3254 /* We only allow symbols for PC-relative references.
3255 If pc_frag == 0, then we don't have frag locations yet. */
3257 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3260 /* If it is a weak symbol, then assume it won't reach. */
3261 if (S_IS_WEAK (expr
->X_add_symbol
))
3264 if (is_direct_call_opcode (insn
->opcode
)
3265 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3267 /* If callee is undefined or in a different segment, be
3268 optimistic and assume it will be in range. */
3269 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3273 /* Only references within a segment can be known to fit in the
3274 operands at assembly time. */
3275 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3278 symbolP
= expr
->X_add_symbol
;
3279 sym_frag
= symbol_get_frag (symbolP
);
3280 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3281 pc
= pc_frag
->fr_address
+ pc_offset
;
3283 /* If frag has yet to be reached on this pass, assume it
3284 will move by STRETCH just as we did. If this is not so,
3285 it will be because some frag between grows, and that will
3286 force another pass. Beware zero-length frags. There
3287 should be a faster way to do this. */
3290 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3291 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3296 new_offset
= target
;
3297 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3298 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3303 /* The symbol should have a fixup associated with it. */
3312 /* Return TRUE on success. */
3315 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3320 memset (targ
, 0, sizeof (TInsn
));
3321 targ
->linenum
= insn
->linenum
;
3326 targ
->opcode
= bi
->opcode
;
3327 targ
->insn_type
= ITYPE_INSN
;
3328 targ
->is_specific_opcode
= FALSE
;
3330 for (; op
!= NULL
; op
= op
->next
)
3332 int op_num
= op
->op_num
;
3333 int op_data
= op
->op_data
;
3335 assert (op
->op_num
< MAX_INSN_ARGS
);
3337 if (targ
->ntok
<= op_num
)
3338 targ
->ntok
= op_num
+ 1;
3343 set_expr_const (&targ
->tok
[op_num
], op_data
);
3346 assert (op_data
< insn
->ntok
);
3347 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3350 sym
= get_special_literal_symbol ();
3351 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3354 sym
= get_special_label_symbol ();
3355 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3357 case OP_OPERAND_HI16U
:
3358 case OP_OPERAND_LOW16U
:
3359 assert (op_data
< insn
->ntok
);
3360 if (expr_is_const (&insn
->tok
[op_data
]))
3363 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3364 val
= xg_apply_userdef_op_fn (op
->typ
,
3367 targ
->tok
[op_num
].X_add_number
= val
;
3371 /* For const16 we can create relocations for these. */
3372 if (targ
->opcode
== XTENSA_UNDEFINED
3373 || (targ
->opcode
!= xtensa_const16_opcode
))
3375 assert (op_data
< insn
->ntok
);
3376 /* Need to build a O_lo16 or O_hi16. */
3377 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3378 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3380 if (op
->typ
== OP_OPERAND_HI16U
)
3381 targ
->tok
[op_num
].X_op
= O_hi16
;
3382 else if (op
->typ
== OP_OPERAND_LOW16U
)
3383 targ
->tok
[op_num
].X_op
= O_lo16
;
3390 /* currently handles:
3393 OP_OPERAND_F32MINUS */
3394 if (xg_has_userdef_op_fn (op
->typ
))
3396 assert (op_data
< insn
->ntok
);
3397 if (expr_is_const (&insn
->tok
[op_data
]))
3400 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3401 val
= xg_apply_userdef_op_fn (op
->typ
,
3404 targ
->tok
[op_num
].X_add_number
= val
;
3407 return FALSE
; /* We cannot use a relocation for this. */
3416 case INSTR_LITERAL_DEF
:
3418 targ
->opcode
= XTENSA_UNDEFINED
;
3419 targ
->insn_type
= ITYPE_LITERAL
;
3420 targ
->is_specific_opcode
= FALSE
;
3421 for (; op
!= NULL
; op
= op
->next
)
3423 int op_num
= op
->op_num
;
3424 int op_data
= op
->op_data
;
3425 assert (op
->op_num
< MAX_INSN_ARGS
);
3427 if (targ
->ntok
<= op_num
)
3428 targ
->ntok
= op_num
+ 1;
3433 assert (op_data
< insn
->ntok
);
3434 /* We can only pass resolvable literals through. */
3435 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3437 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3449 case INSTR_LABEL_DEF
:
3451 targ
->opcode
= XTENSA_UNDEFINED
;
3452 targ
->insn_type
= ITYPE_LABEL
;
3453 targ
->is_specific_opcode
= FALSE
;
3454 /* Literal with no ops is a label? */
3455 assert (op
== NULL
);
3466 /* Return TRUE on success. */
3469 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3471 for (; bi
!= NULL
; bi
= bi
->next
)
3473 TInsn
*next_insn
= istack_push_space (istack
);
3475 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3482 /* Return TRUE on valid expansion. */
3485 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3487 int stack_size
= istack
->ninsn
;
3488 int steps_taken
= 0;
3489 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3492 assert (insn
->insn_type
== ITYPE_INSN
);
3493 assert (insn
->opcode
< table
->num_opcodes
);
3495 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3497 TransitionRule
*rule
= l
->rule
;
3499 if (xg_instruction_matches_rule (insn
, rule
))
3501 if (lateral_steps
== steps_taken
)
3505 /* This is it. Expand the rule to the stack. */
3506 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3509 /* Check to see if it fits. */
3510 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3512 TInsn
*insn
= &istack
->insn
[i
];
3514 if (insn
->insn_type
== ITYPE_INSN
3515 && !tinsn_has_symbolic_operands (insn
)
3516 && !xg_immeds_fit (insn
))
3518 istack
->ninsn
= stack_size
;
3531 /* Relax the assembly instruction at least "min_steps".
3532 Return the number of steps taken. */
3535 xg_assembly_relax (IStack
*istack
,
3538 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3539 offsetT pc_offset
, /* offset in fragment */
3540 int min_steps
, /* minimum conversion steps */
3541 long stretch
) /* number of bytes stretched so far */
3543 int steps_taken
= 0;
3545 /* assert (has no symbolic operands)
3546 Some of its immeds don't fit.
3547 Try to build a relaxed version.
3548 This may go through a couple of stages
3549 of single instruction transformations before
3552 TInsn single_target
;
3554 int lateral_steps
= 0;
3555 int istack_size
= istack
->ninsn
;
3557 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3558 && steps_taken
>= min_steps
)
3560 istack_push (istack
, insn
);
3563 current_insn
= *insn
;
3565 /* Walk through all of the single instruction expansions. */
3566 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3568 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3572 if (steps_taken
>= min_steps
)
3574 istack_push (istack
, &single_target
);
3578 current_insn
= single_target
;
3581 /* Now check for a multi-instruction expansion. */
3582 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3584 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3587 if (steps_taken
>= min_steps
)
3589 istack_push (istack
, ¤t_insn
);
3594 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3596 if (steps_taken
>= min_steps
)
3600 istack
->ninsn
= istack_size
;
3603 /* It's not going to work -- use the original. */
3604 istack_push (istack
, insn
);
3610 xg_force_frag_space (int size
)
3612 /* This may have the side effect of creating a new fragment for the
3613 space to go into. I just do not like the name of the "frag"
3620 xg_finish_frag (char *last_insn
,
3621 enum xtensa_relax_statesE frag_state
,
3622 enum xtensa_relax_statesE slot0_state
,
3624 bfd_boolean is_insn
)
3626 /* Finish off this fragment so that it has at LEAST the desired
3627 max_growth. If it doesn't fit in this fragment, close this one
3628 and start a new one. In either case, return a pointer to the
3629 beginning of the growth area. */
3633 xg_force_frag_space (max_growth
);
3635 old_frag
= frag_now
;
3637 frag_now
->fr_opcode
= last_insn
;
3639 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3641 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3642 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3644 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3645 xtensa_set_frag_assembly_state (frag_now
);
3647 /* Just to make sure that we did not split it up. */
3648 assert (old_frag
->fr_next
== frag_now
);
3652 /* Return TRUE if the target frag is one of the next non-empty frags. */
3655 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3660 for (; fragP
; fragP
= fragP
->fr_next
)
3662 if (fragP
== target
)
3664 if (fragP
->fr_fix
!= 0)
3666 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3668 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3669 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3671 if (fragP
->fr_type
== rs_space
)
3679 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3681 xtensa_isa isa
= xtensa_default_isa
;
3683 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3688 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3689 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3692 for (i
= 0; i
< num_ops
; i
++)
3694 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3700 if (target_op
== -1)
3703 if (insn
->ntok
<= target_op
)
3706 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3709 sym
= insn
->tok
[target_op
].X_add_symbol
;
3713 if (insn
->tok
[target_op
].X_add_number
!= 0)
3716 target_frag
= symbol_get_frag (sym
);
3717 if (target_frag
== NULL
)
3720 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3721 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3729 xg_add_branch_and_loop_targets (TInsn
*insn
)
3731 xtensa_isa isa
= xtensa_default_isa
;
3732 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3734 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3737 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3738 && insn
->tok
[i
].X_op
== O_symbol
)
3739 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3743 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3744 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3748 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3750 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3751 && insn
->tok
[i
].X_op
== O_symbol
)
3753 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3754 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3755 if (S_IS_DEFINED (sym
))
3756 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3763 /* Return FALSE if no error. */
3766 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3771 switch (instr_spec
->typ
)
3774 new_insn
->insn_type
= ITYPE_INSN
;
3775 new_insn
->opcode
= instr_spec
->opcode
;
3776 new_insn
->is_specific_opcode
= FALSE
;
3777 new_insn
->linenum
= old_insn
->linenum
;
3779 case INSTR_LITERAL_DEF
:
3780 new_insn
->insn_type
= ITYPE_LITERAL
;
3781 new_insn
->opcode
= XTENSA_UNDEFINED
;
3782 new_insn
->is_specific_opcode
= FALSE
;
3783 new_insn
->linenum
= old_insn
->linenum
;
3785 case INSTR_LABEL_DEF
:
3786 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3790 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3793 const expressionS
*src_exp
;
3799 /* The expression must be the constant. */
3800 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3801 exp
= &new_insn
->tok
[b_op
->op_num
];
3802 set_expr_const (exp
, b_op
->op_data
);
3806 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3807 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3808 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3809 exp
= &new_insn
->tok
[b_op
->op_num
];
3810 copy_expr (exp
, src_exp
);
3815 as_bad (_("can't handle generation of literal/labels yet"));
3819 as_bad (_("can't handle undefined OP TYPE"));
3824 new_insn
->ntok
= num_ops
;
3829 /* Return TRUE if it was simplified. */
3832 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3834 TransitionRule
*rule
;
3835 BuildInstr
*insn_spec
;
3837 if (old_insn
->is_specific_opcode
|| !density_supported
)
3840 rule
= xg_instruction_match (old_insn
);
3844 insn_spec
= rule
->to_instr
;
3845 /* There should only be one. */
3846 assert (insn_spec
!= NULL
);
3847 assert (insn_spec
->next
== NULL
);
3848 if (insn_spec
->next
!= NULL
)
3851 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3857 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3858 l32i.n. (2) Check the number of operands. (3) Place the instruction
3859 tokens into the stack or relax it and place multiple
3860 instructions/literals onto the stack. Return FALSE if no error. */
3863 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3867 bfd_boolean do_expand
;
3869 memset (&new_insn
, 0, sizeof (TInsn
));
3871 /* Narrow it if we can. xg_simplify_insn now does all the
3872 appropriate checking (e.g., for the density option). */
3873 if (xg_simplify_insn (orig_insn
, &new_insn
))
3874 orig_insn
= &new_insn
;
3876 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3878 if (orig_insn
->ntok
< noperands
)
3880 as_bad (_("found %d operands for '%s': Expected %d"),
3882 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3886 if (orig_insn
->ntok
> noperands
)
3887 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3889 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3892 /* If there are not enough operands, we will assert above. If there
3893 are too many, just cut out the extras here. */
3894 orig_insn
->ntok
= noperands
;
3896 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3899 /* If the instruction will definitely need to be relaxed, it is better
3900 to expand it now for better scheduling. Decide whether to expand
3902 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3904 /* Calls should be expanded to longcalls only in the backend relaxation
3905 so that the assembly scheduler will keep the L32R/CALLX instructions
3907 if (is_direct_call_opcode (orig_insn
->opcode
))
3910 if (tinsn_has_symbolic_operands (orig_insn
))
3912 /* The values of symbolic operands are not known yet, so only expand
3913 now if an operand is "complex" (e.g., difference of symbols) and
3914 will have to be stored as a literal regardless of the value. */
3915 if (!tinsn_has_complex_operands (orig_insn
))
3918 else if (xg_immeds_fit (orig_insn
))
3922 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3924 istack_push (istack
, orig_insn
);
3930 /* Return TRUE if the section flags are marked linkonce
3931 or the name is .gnu.linkonce*. */
3934 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3936 flagword flags
, link_once_flags
;
3938 flags
= bfd_get_section_flags (abfd
, sec
);
3939 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3941 /* Flags might not be set yet. */
3942 if (!link_once_flags
)
3944 static size_t len
= sizeof ".gnu.linkonce.t.";
3946 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3947 link_once_flags
= SEC_LINK_ONCE
;
3949 return (link_once_flags
!= 0);
3954 xtensa_add_literal_sym (symbolS
*sym
)
3958 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3960 l
->next
= literal_syms
;
3966 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3968 static int lit_num
= 0;
3969 static char name
[256];
3972 sprintf (name
, ".L_lit_sym%d", lit_num
);
3974 /* Create a local symbol. If it is in a linkonce section, we have to
3975 be careful to make sure that if it is used in a relocation that the
3976 symbol will be in the output file. */
3977 if (get_is_linkonce_section (stdoutput
, sec
))
3979 symbolP
= symbol_new (name
, sec
, 0, frag
);
3980 S_CLEAR_EXTERNAL (symbolP
);
3981 /* symbolP->local = 1; */
3984 symbolP
= symbol_new (name
, sec
, 0, frag
);
3986 xtensa_add_literal_sym (symbolP
);
3988 frag
->tc_frag_data
.is_literal
= TRUE
;
3994 /* Currently all literals that are generated here are 32-bit L32R targets. */
3997 xg_assemble_literal (/* const */ TInsn
*insn
)
4000 symbolS
*lit_sym
= NULL
;
4002 /* size = 4 for L32R. It could easily be larger when we move to
4003 larger constants. Add a parameter later. */
4004 offsetT litsize
= 4;
4005 offsetT litalign
= 2; /* 2^2 = 4 */
4006 expressionS saved_loc
;
4007 expressionS
* emit_val
;
4009 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4011 assert (insn
->insn_type
== ITYPE_LITERAL
);
4012 assert (insn
->ntok
== 1); /* must be only one token here */
4014 xtensa_switch_to_literal_fragment (&state
);
4016 emit_val
= &insn
->tok
[0];
4017 if (emit_val
->X_op
== O_big
)
4019 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4022 /* This happens when someone writes a "movi a2, big_number". */
4023 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4024 _("invalid immediate"));
4025 xtensa_restore_emit_state (&state
);
4030 /* Force a 4-byte align here. Note that this opens a new frag, so all
4031 literals done with this function have a frag to themselves. That's
4032 important for the way text section literals work. */
4033 frag_align (litalign
, 0, 0);
4034 record_alignment (now_seg
, litalign
);
4036 if (emit_val
->X_op
== O_pltrel
)
4038 char *p
= frag_more (litsize
);
4039 xtensa_set_frag_assembly_state (frag_now
);
4040 if (emit_val
->X_add_symbol
)
4041 emit_val
->X_op
= O_symbol
;
4043 emit_val
->X_op
= O_constant
;
4044 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4045 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4048 emit_expr (emit_val
, litsize
);
4050 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4051 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4052 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4053 lit_sym
= frag_now
->fr_symbol
;
4054 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4057 xtensa_restore_emit_state (&state
);
4063 xg_assemble_literal_space (/* const */ int size
, int slot
)
4066 /* We might have to do something about this alignment. It only
4067 takes effect if something is placed here. */
4068 offsetT litalign
= 2; /* 2^2 = 4 */
4069 fragS
*lit_saved_frag
;
4071 assert (size
% 4 == 0);
4073 xtensa_switch_to_literal_fragment (&state
);
4075 /* Force a 4-byte align here. */
4076 frag_align (litalign
, 0, 0);
4077 record_alignment (now_seg
, litalign
);
4079 xg_force_frag_space (size
);
4081 lit_saved_frag
= frag_now
;
4082 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4083 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4084 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4085 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4088 xtensa_restore_emit_state (&state
);
4089 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4093 /* Put in a fixup record based on the opcode.
4094 Return TRUE on success. */
4097 xg_add_opcode_fix (TInsn
*tinsn
,
4105 xtensa_opcode opcode
= tinsn
->opcode
;
4106 bfd_reloc_code_real_type reloc
;
4107 reloc_howto_type
*howto
;
4111 reloc
= BFD_RELOC_NONE
;
4113 /* First try the special cases for "alternate" relocs. */
4114 if (opcode
== xtensa_l32r_opcode
)
4116 if (fragP
->tc_frag_data
.use_absolute_literals
)
4117 reloc
= encode_alt_reloc (slot
);
4119 else if (opcode
== xtensa_const16_opcode
)
4121 if (expr
->X_op
== O_lo16
)
4123 reloc
= encode_reloc (slot
);
4124 expr
->X_op
= O_symbol
;
4126 else if (expr
->X_op
== O_hi16
)
4128 reloc
= encode_alt_reloc (slot
);
4129 expr
->X_op
= O_symbol
;
4133 if (opnum
!= get_relaxable_immed (opcode
))
4135 as_bad (_("invalid relocation for operand %i of '%s'"),
4136 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4140 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4141 into the symbol table where the generic portions of the assembler
4142 won't know what to do with them. */
4143 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4145 as_bad (_("invalid expression for operand %i of '%s'"),
4146 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4150 /* Next try the generic relocs. */
4151 if (reloc
== BFD_RELOC_NONE
)
4152 reloc
= encode_reloc (slot
);
4153 if (reloc
== BFD_RELOC_NONE
)
4155 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4159 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4162 as_bad (_("undefined symbol for opcode \"%s\""),
4163 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4167 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4168 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4169 howto
->pc_relative
, reloc
);
4170 the_fix
->fx_no_overflow
= 1;
4172 if (expr
->X_add_symbol
4173 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4174 || S_IS_WEAK (expr
->X_add_symbol
)))
4175 the_fix
->fx_plt
= TRUE
;
4177 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4178 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4179 the_fix
->tc_fix_data
.slot
= slot
;
4186 xg_emit_insn_to_buf (TInsn
*tinsn
,
4190 bfd_boolean build_fix
)
4192 static xtensa_insnbuf insnbuf
= NULL
;
4193 bfd_boolean has_symbolic_immed
= FALSE
;
4194 bfd_boolean ok
= TRUE
;
4197 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4199 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4200 if (has_symbolic_immed
&& build_fix
)
4203 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4204 int slot
= xg_get_single_slot (tinsn
->opcode
);
4205 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4206 expressionS
*exp
= &tinsn
->tok
[opnum
];
4208 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4211 fragP
->tc_frag_data
.is_insn
= TRUE
;
4212 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4213 (unsigned char *) buf
, 0);
4219 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4221 symbolS
*sym
= get_special_literal_symbol ();
4225 assert (insn
->insn_type
== ITYPE_INSN
);
4226 for (i
= 0; i
< insn
->ntok
; i
++)
4227 if (insn
->tok
[i
].X_add_symbol
== sym
)
4228 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4234 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4236 symbolS
*sym
= get_special_label_symbol ();
4238 /* assert (!insn->is_literal); */
4239 for (i
= 0; i
< insn
->ntok
; i
++)
4240 if (insn
->tok
[i
].X_add_symbol
== sym
)
4241 insn
->tok
[i
].X_add_symbol
= label_sym
;
4246 /* Return TRUE if the instruction can write to the specified
4247 integer register. */
4250 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4254 xtensa_isa isa
= xtensa_default_isa
;
4256 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4258 for (i
= 0; i
< num_ops
; i
++)
4261 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4262 if ((inout
== 'o' || inout
== 'm')
4263 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4265 xtensa_regfile opnd_rf
=
4266 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4267 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4269 if ((insn
->tok
[i
].X_op
== O_register
)
4270 && (insn
->tok
[i
].X_add_number
== regnum
))
4280 is_bad_loopend_opcode (const TInsn
*tinsn
)
4282 xtensa_opcode opcode
= tinsn
->opcode
;
4284 if (opcode
== XTENSA_UNDEFINED
)
4287 if (opcode
== xtensa_call0_opcode
4288 || opcode
== xtensa_callx0_opcode
4289 || opcode
== xtensa_call4_opcode
4290 || opcode
== xtensa_callx4_opcode
4291 || opcode
== xtensa_call8_opcode
4292 || opcode
== xtensa_callx8_opcode
4293 || opcode
== xtensa_call12_opcode
4294 || opcode
== xtensa_callx12_opcode
4295 || opcode
== xtensa_isync_opcode
4296 || opcode
== xtensa_ret_opcode
4297 || opcode
== xtensa_ret_n_opcode
4298 || opcode
== xtensa_retw_opcode
4299 || opcode
== xtensa_retw_n_opcode
4300 || opcode
== xtensa_waiti_opcode
4301 || opcode
== xtensa_rsr_lcount_opcode
)
4308 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4309 This allows the debugger to add unaligned labels.
4310 Also, the assembler generates stabs labels that need
4311 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4314 is_unaligned_label (symbolS
*sym
)
4316 const char *name
= S_GET_NAME (sym
);
4317 static size_t fake_size
= 0;
4321 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4324 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4326 fake_size
= strlen (FAKE_LABEL_NAME
);
4329 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4330 && (name
[fake_size
] == 'F'
4331 || name
[fake_size
] == 'L'
4332 || (name
[fake_size
] == 'e'
4333 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4341 next_non_empty_frag (const fragS
*fragP
)
4343 fragS
*next_fragP
= fragP
->fr_next
;
4345 /* Sometimes an empty will end up here due storage allocation issues.
4346 So we have to skip until we find something legit. */
4347 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4348 next_fragP
= next_fragP
->fr_next
;
4350 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4358 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4360 xtensa_opcode out_opcode
;
4361 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4363 if (next_fragP
== NULL
)
4366 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4367 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4369 *opcode
= out_opcode
;
4377 frag_format_size (const fragS
*fragP
)
4379 static xtensa_insnbuf insnbuf
= NULL
;
4380 xtensa_isa isa
= xtensa_default_isa
;
4385 insnbuf
= xtensa_insnbuf_alloc (isa
);
4388 return XTENSA_UNDEFINED
;
4390 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4391 (unsigned char *) fragP
->fr_literal
, 0);
4393 fmt
= xtensa_format_decode (isa
, insnbuf
);
4394 if (fmt
== XTENSA_UNDEFINED
)
4395 return XTENSA_UNDEFINED
;
4396 fmt_size
= xtensa_format_length (isa
, fmt
);
4398 /* If the next format won't be changing due to relaxation, just
4399 return the length of the first format. */
4400 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4403 /* If during relaxation we have to pull an instruction out of a
4404 multi-slot instruction, we will return the more conservative
4405 number. This works because alignment on bigger instructions
4406 is more restrictive than alignment on smaller instructions.
4407 This is more conservative than we would like, but it happens
4410 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4413 /* If we aren't doing one of our own relaxations or it isn't
4414 slot-based, then the insn size won't change. */
4415 if (fragP
->fr_type
!= rs_machine_dependent
)
4417 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4420 /* If an instruction is about to grow, return the longer size. */
4421 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4422 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4425 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4426 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4433 next_frag_format_size (const fragS
*fragP
)
4435 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4436 return frag_format_size (next_fragP
);
4440 /* If the next legit fragment is an end-of-loop marker,
4441 switch its state so it will instantiate a NOP. */
4444 update_next_frag_state (fragS
*fragP
)
4446 fragS
*next_fragP
= fragP
->fr_next
;
4447 fragS
*new_target
= NULL
;
4451 /* We are guaranteed there will be one of these... */
4452 while (!(next_fragP
->fr_type
== rs_machine_dependent
4453 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4454 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4455 next_fragP
= next_fragP
->fr_next
;
4457 assert (next_fragP
->fr_type
== rs_machine_dependent
4458 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4459 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4461 /* ...and one of these. */
4462 new_target
= next_fragP
->fr_next
;
4463 while (!(new_target
->fr_type
== rs_machine_dependent
4464 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4465 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4466 new_target
= new_target
->fr_next
;
4468 assert (new_target
->fr_type
== rs_machine_dependent
4469 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4470 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4473 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4475 if (next_fragP
->fr_type
== rs_machine_dependent
4476 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4478 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4482 next_fragP
= next_fragP
->fr_next
;
4488 next_frag_is_branch_target (const fragS
*fragP
)
4490 /* Sometimes an empty will end up here due to storage allocation issues,
4491 so we have to skip until we find something legit. */
4492 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4494 if (fragP
->tc_frag_data
.is_branch_target
)
4496 if (fragP
->fr_fix
!= 0)
4504 next_frag_is_loop_target (const fragS
*fragP
)
4506 /* Sometimes an empty will end up here due storage allocation issues.
4507 So we have to skip until we find something legit. */
4508 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4510 if (fragP
->tc_frag_data
.is_loop_target
)
4512 if (fragP
->fr_fix
!= 0)
4520 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4522 const fragS
*next_fragp
= fragp
->fr_next
;
4523 xtensa_opcode next_opcode
;
4525 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4528 /* Sometimes an empty will end up here due to storage allocation issues,
4529 so we have to skip until we find something legit. */
4530 while (next_fragp
->fr_fix
== 0)
4531 next_fragp
= next_fragp
->fr_next
;
4533 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4536 /* There is some implicit knowledge encoded in here.
4537 The LOOP instructions that are NOT RELAX_IMMED have
4538 been relaxed. Note that we can assume that the LOOP
4539 instruction is in slot 0 because loops aren't bundleable. */
4540 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4541 return get_expanded_loop_offset (next_opcode
);
4547 /* Mark a location where we can later insert literal frags. Update
4548 the section's literal_pool_loc, so subsequent literals can be
4549 placed nearest to their use. */
4552 xtensa_mark_literal_pool_location (void)
4554 /* Any labels pointing to the current location need
4555 to be adjusted to after the literal pool. */
4557 fragS
*pool_location
;
4559 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4562 frag_align (2, 0, 0);
4563 record_alignment (now_seg
, 2);
4565 /* We stash info in these frags so we can later move the literal's
4566 fixes into this frchain's fix list. */
4567 pool_location
= frag_now
;
4568 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4569 frag_variant (rs_machine_dependent
, 0, 0,
4570 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4571 xtensa_set_frag_assembly_state (frag_now
);
4572 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4573 frag_variant (rs_machine_dependent
, 0, 0,
4574 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4575 xtensa_set_frag_assembly_state (frag_now
);
4577 /* Now put a frag into the literal pool that points to this location. */
4578 set_literal_pool_location (now_seg
, pool_location
);
4579 xtensa_switch_to_non_abs_literal_fragment (&s
);
4580 frag_align (2, 0, 0);
4581 record_alignment (now_seg
, 2);
4583 /* Close whatever frag is there. */
4584 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4585 xtensa_set_frag_assembly_state (frag_now
);
4586 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4587 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4588 xtensa_restore_emit_state (&s
);
4589 xtensa_set_frag_assembly_state (frag_now
);
4593 /* Build a nop of the correct size into tinsn. */
4596 build_nop (TInsn
*tinsn
, int size
)
4602 tinsn
->opcode
= xtensa_nop_n_opcode
;
4604 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4605 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4609 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4611 tinsn
->opcode
= xtensa_or_opcode
;
4612 set_expr_const (&tinsn
->tok
[0], 1);
4613 set_expr_const (&tinsn
->tok
[1], 1);
4614 set_expr_const (&tinsn
->tok
[2], 1);
4618 tinsn
->opcode
= xtensa_nop_opcode
;
4620 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4625 /* Assemble a NOP of the requested size in the buffer. User must have
4626 allocated "buf" with at least "size" bytes. */
4629 assemble_nop (int size
, char *buf
)
4631 static xtensa_insnbuf insnbuf
= NULL
;
4634 build_nop (&tinsn
, size
);
4637 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4639 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4640 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4641 (unsigned char *) buf
, 0);
4645 /* Return the number of bytes for the offset of the expanded loop
4646 instruction. This should be incorporated into the relaxation
4647 specification but is hard-coded here. This is used to auto-align
4648 the loop instruction. It is invalid to call this function if the
4649 configuration does not have loops or if the opcode is not a loop
4653 get_expanded_loop_offset (xtensa_opcode opcode
)
4655 /* This is the OFFSET of the loop instruction in the expanded loop.
4656 This MUST correspond directly to the specification of the loop
4657 expansion. It will be validated on fragment conversion. */
4658 assert (opcode
!= XTENSA_UNDEFINED
);
4659 if (opcode
== xtensa_loop_opcode
)
4661 if (opcode
== xtensa_loopnez_opcode
)
4663 if (opcode
== xtensa_loopgtz_opcode
)
4665 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4671 get_literal_pool_location (segT seg
)
4673 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4678 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4680 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4684 /* Set frag assembly state should be called when a new frag is
4685 opened and after a frag has been closed. */
4688 xtensa_set_frag_assembly_state (fragS
*fragP
)
4690 if (!density_supported
)
4691 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4693 /* This function is called from subsegs_finish, which is called
4694 after xtensa_end, so we can't use "use_transform" or
4695 "use_schedule" here. */
4696 if (!directive_state
[directive_transform
])
4697 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4698 if (directive_state
[directive_longcalls
])
4699 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4700 fragP
->tc_frag_data
.use_absolute_literals
=
4701 directive_state
[directive_absolute_literals
];
4702 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4707 relaxable_section (asection
*sec
)
4709 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4714 xtensa_find_unmarked_state_frags (void)
4718 /* Walk over each fragment of all of the current segments. For each
4719 unmarked fragment, mark it with the same info as the previous
4721 for (seclist
= &stdoutput
->sections
;
4722 seclist
&& *seclist
;
4723 seclist
= &(*seclist
)->next
)
4725 segT sec
= *seclist
;
4726 segment_info_type
*seginfo
;
4729 flags
= bfd_get_section_flags (stdoutput
, sec
);
4730 if (flags
& SEC_DEBUGGING
)
4732 if (!(flags
& SEC_ALLOC
))
4735 seginfo
= seg_info (sec
);
4736 if (seginfo
&& seginfo
->frchainP
)
4738 fragS
*last_fragP
= 0;
4739 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4740 fragP
= fragP
->fr_next
)
4742 if (fragP
->fr_fix
!= 0
4743 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4745 if (last_fragP
== 0)
4747 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4748 _("assembly state not set for first frag in section %s"),
4753 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4754 fragP
->tc_frag_data
.is_no_density
=
4755 last_fragP
->tc_frag_data
.is_no_density
;
4756 fragP
->tc_frag_data
.is_no_transform
=
4757 last_fragP
->tc_frag_data
.is_no_transform
;
4758 fragP
->tc_frag_data
.use_longcalls
=
4759 last_fragP
->tc_frag_data
.use_longcalls
;
4760 fragP
->tc_frag_data
.use_absolute_literals
=
4761 last_fragP
->tc_frag_data
.use_absolute_literals
;
4764 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4773 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4775 void *unused ATTRIBUTE_UNUSED
)
4777 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4778 segment_info_type
*seginfo
= seg_info (sec
);
4779 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4781 if (flags
& SEC_CODE
)
4783 xtensa_isa isa
= xtensa_default_isa
;
4784 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4785 while (frag
!= NULL
)
4787 if (frag
->tc_frag_data
.is_branch_target
)
4790 addressT branch_align
, frag_addr
;
4793 xtensa_insnbuf_from_chars
4794 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4795 fmt
= xtensa_format_decode (isa
, insnbuf
);
4796 op_size
= xtensa_format_length (isa
, fmt
);
4797 branch_align
= 1 << branch_align_power (sec
);
4798 frag_addr
= frag
->fr_address
% branch_align
;
4799 if (frag_addr
+ op_size
> branch_align
)
4800 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4801 _("unaligned branch target: %d bytes at 0x%lx"),
4802 op_size
, (long) frag
->fr_address
);
4804 frag
= frag
->fr_next
;
4806 xtensa_insnbuf_free (isa
, insnbuf
);
4812 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4814 void *unused ATTRIBUTE_UNUSED
)
4816 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4817 segment_info_type
*seginfo
= seg_info (sec
);
4818 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4819 xtensa_isa isa
= xtensa_default_isa
;
4821 if (flags
& SEC_CODE
)
4823 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4824 while (frag
!= NULL
)
4826 if (frag
->tc_frag_data
.is_first_loop_insn
)
4832 xtensa_insnbuf_from_chars
4833 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4834 fmt
= xtensa_format_decode (isa
, insnbuf
);
4835 op_size
= xtensa_format_length (isa
, fmt
);
4836 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4838 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4839 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4840 _("unaligned loop: %d bytes at 0x%lx"),
4841 op_size
, (long) frag
->fr_address
);
4843 frag
= frag
->fr_next
;
4845 xtensa_insnbuf_free (isa
, insnbuf
);
4851 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4853 xtensa_isa isa
= xtensa_default_isa
;
4854 static xtensa_insnbuf insnbuf
= NULL
;
4855 static xtensa_insnbuf slotbuf
= NULL
;
4858 bfd_boolean alt_reloc
;
4859 xtensa_opcode opcode
;
4860 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4862 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4864 as_fatal (_("unexpected fix"));
4868 insnbuf
= xtensa_insnbuf_alloc (isa
);
4869 slotbuf
= xtensa_insnbuf_alloc (isa
);
4872 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4873 fmt
= xtensa_format_decode (isa
, insnbuf
);
4874 if (fmt
== XTENSA_UNDEFINED
)
4875 as_fatal (_("undecodable fix"));
4876 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4877 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4878 if (opcode
== XTENSA_UNDEFINED
)
4879 as_fatal (_("undecodable fix"));
4881 /* CONST16 immediates are not PC-relative, despite the fact that we
4882 reuse the normal PC-relative operand relocations for the low part
4883 of a CONST16 operand. */
4884 if (opcode
== xtensa_const16_opcode
)
4887 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4888 get_relaxable_immed (opcode
), val
,
4889 fixP
->fx_file
, fixP
->fx_line
);
4891 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4892 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4898 /* External Functions and Other GAS Hooks. */
4901 xtensa_target_format (void)
4903 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4908 xtensa_file_arch_init (bfd
*abfd
)
4910 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4915 md_number_to_chars (char *buf
, valueT val
, int n
)
4917 if (target_big_endian
)
4918 number_to_chars_bigendian (buf
, val
, n
);
4920 number_to_chars_littleendian (buf
, val
, n
);
4924 /* This function is called once, at assembler startup time. It should
4925 set up all the tables, etc. that the MD part of the assembler will
4931 segT current_section
= now_seg
;
4932 int current_subsec
= now_subseg
;
4935 xtensa_default_isa
= xtensa_isa_init (0, 0);
4936 isa
= xtensa_default_isa
;
4940 /* Set up the .literal, .fini.literal and .init.literal sections. */
4941 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4942 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4943 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4944 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4945 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4947 subseg_set (current_section
, current_subsec
);
4949 xg_init_vinsn (&cur_vinsn
);
4951 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4952 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4953 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4954 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4955 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4956 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4957 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4958 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4959 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4960 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4961 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4962 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4963 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4964 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4965 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4966 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4967 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4968 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4969 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4970 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4971 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4972 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4973 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4974 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4975 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4976 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4977 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4978 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4979 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4981 init_op_placement_info_table ();
4983 /* Set up the assembly state. */
4984 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4985 xtensa_set_frag_assembly_state (frag_now
);
4989 /* TC_INIT_FIX_DATA hook */
4992 xtensa_init_fix_data (fixS
*x
)
4994 x
->tc_fix_data
.slot
= 0;
4995 x
->tc_fix_data
.X_add_symbol
= NULL
;
4996 x
->tc_fix_data
.X_add_number
= 0;
5000 /* tc_frob_label hook */
5003 xtensa_frob_label (symbolS
*sym
)
5007 if (cur_vinsn
.inside_bundle
)
5009 as_bad (_("labels are not valid inside bundles"));
5013 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5015 /* Since the label was already attached to a frag associated with the
5016 previous basic block, it now needs to be reset to the current frag. */
5017 symbol_set_frag (sym
, frag_now
);
5018 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5020 if (generating_literals
)
5021 xtensa_add_literal_sym (sym
);
5023 xtensa_add_insn_label (sym
);
5025 if (symbol_get_tc (sym
)->is_loop_target
)
5027 if ((get_last_insn_flags (now_seg
, now_subseg
)
5028 & FLAG_IS_BAD_LOOPEND
) != 0)
5029 as_bad (_("invalid last instruction for a zero-overhead loop"));
5031 xtensa_set_frag_assembly_state (frag_now
);
5032 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5033 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5035 xtensa_set_frag_assembly_state (frag_now
);
5036 xtensa_move_labels (frag_now
, 0, TRUE
);
5039 /* No target aligning in the absolute section. */
5040 if (now_seg
!= absolute_section
5041 && do_align_targets ()
5042 && !is_unaligned_label (sym
)
5043 && !generating_literals
)
5045 xtensa_set_frag_assembly_state (frag_now
);
5047 frag_var (rs_machine_dependent
,
5049 RELAX_DESIRE_ALIGN_IF_TARGET
,
5050 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5051 xtensa_set_frag_assembly_state (frag_now
);
5052 xtensa_move_labels (frag_now
, 0, TRUE
);
5055 /* We need to mark the following properties even if we aren't aligning. */
5057 /* If the label is already known to be a branch target, i.e., a
5058 forward branch, mark the frag accordingly. Backward branches
5059 are handled by xg_add_branch_and_loop_targets. */
5060 if (symbol_get_tc (sym
)->is_branch_target
)
5061 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5063 /* Loops only go forward, so they can be identified here. */
5064 if (symbol_get_tc (sym
)->is_loop_target
)
5065 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5067 dwarf2_emit_label (sym
);
5071 /* tc_unrecognized_line hook */
5074 xtensa_unrecognized_line (int ch
)
5079 if (cur_vinsn
.inside_bundle
== 0)
5081 /* PR8110: Cannot emit line number info inside a FLIX bundle
5082 when using --gstabs. Temporarily disable debug info. */
5083 generate_lineno_debug ();
5084 if (debug_type
== DEBUG_STABS
)
5086 xt_saved_debug_type
= debug_type
;
5087 debug_type
= DEBUG_NONE
;
5090 cur_vinsn
.inside_bundle
= 1;
5094 as_bad (_("extra opening brace"));
5100 if (cur_vinsn
.inside_bundle
)
5101 finish_vinsn (&cur_vinsn
);
5104 as_bad (_("extra closing brace"));
5109 as_bad (_("syntax error"));
5116 /* md_flush_pending_output hook */
5119 xtensa_flush_pending_output (void)
5121 if (cur_vinsn
.inside_bundle
)
5122 as_bad (_("missing closing brace"));
5124 /* If there is a non-zero instruction fragment, close it. */
5125 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5127 frag_wane (frag_now
);
5129 xtensa_set_frag_assembly_state (frag_now
);
5131 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5133 xtensa_clear_insn_labels ();
5137 /* We had an error while parsing an instruction. The string might look
5138 like this: "insn arg1, arg2 }". If so, we need to see the closing
5139 brace and reset some fields. Otherwise, the vinsn never gets closed
5140 and the num_slots field will grow past the end of the array of slots,
5141 and bad things happen. */
5144 error_reset_cur_vinsn (void)
5146 if (cur_vinsn
.inside_bundle
)
5148 if (*input_line_pointer
== '}'
5149 || *(input_line_pointer
- 1) == '}'
5150 || *(input_line_pointer
- 2) == '}')
5151 xg_clear_vinsn (&cur_vinsn
);
5157 md_assemble (char *str
)
5159 xtensa_isa isa
= xtensa_default_isa
;
5160 char *opname
, *file_name
;
5162 bfd_boolean has_underbar
= FALSE
;
5163 char *arg_strings
[MAX_INSN_ARGS
];
5165 TInsn orig_insn
; /* Original instruction from the input. */
5167 tinsn_init (&orig_insn
);
5169 /* Split off the opcode. */
5170 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5171 opname
= xmalloc (opnamelen
+ 1);
5172 memcpy (opname
, str
, opnamelen
);
5173 opname
[opnamelen
] = '\0';
5175 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5178 as_bad (_("syntax error"));
5182 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5185 /* Check for an underbar prefix. */
5188 has_underbar
= TRUE
;
5192 orig_insn
.insn_type
= ITYPE_INSN
;
5194 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5196 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5197 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5199 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5200 if (fmt
== XTENSA_UNDEFINED
)
5202 as_bad (_("unknown opcode or format name '%s'"), opname
);
5203 error_reset_cur_vinsn ();
5206 if (!cur_vinsn
.inside_bundle
)
5208 as_bad (_("format names only valid inside bundles"));
5209 error_reset_cur_vinsn ();
5212 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5213 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5215 cur_vinsn
.format
= fmt
;
5216 free (has_underbar
? opname
- 1 : opname
);
5217 error_reset_cur_vinsn ();
5221 /* Parse the arguments. */
5222 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5224 as_bad (_("syntax error"));
5225 error_reset_cur_vinsn ();
5229 /* Free the opcode and argument strings, now that they've been parsed. */
5230 free (has_underbar
? opname
- 1 : opname
);
5232 while (num_args
-- > 0)
5233 free (arg_strings
[num_args
]);
5235 /* Get expressions for invisible operands. */
5236 if (get_invisible_operands (&orig_insn
))
5238 error_reset_cur_vinsn ();
5242 /* Check for the right number and type of arguments. */
5243 if (tinsn_check_arguments (&orig_insn
))
5245 error_reset_cur_vinsn ();
5249 /* A FLIX bundle may be spread across multiple input lines. We want to
5250 report the first such line in the debug information. Record the line
5251 number for each TInsn (assume the file name doesn't change), so the
5252 first line can be found later. */
5253 as_where (&file_name
, &orig_insn
.linenum
);
5255 xg_add_branch_and_loop_targets (&orig_insn
);
5257 /* Special-case for "entry" instruction. */
5258 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5260 /* Check that the third opcode (#2) is >= 16. */
5261 if (orig_insn
.ntok
>= 3)
5263 expressionS
*exp
= &orig_insn
.tok
[2];
5267 if (exp
->X_add_number
< 16)
5268 as_warn (_("entry instruction with stack decrement < 16"));
5272 as_warn (_("entry instruction with non-constant decrement"));
5278 assemble_tokens (opcode, tok, ntok);
5279 expand the tokens from the orig_insn into the
5280 stack of instructions that will not expand
5281 unless required at relaxation time. */
5283 if (!cur_vinsn
.inside_bundle
)
5284 emit_single_op (&orig_insn
);
5285 else /* We are inside a bundle. */
5287 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5288 cur_vinsn
.num_slots
++;
5289 if (*input_line_pointer
== '}'
5290 || *(input_line_pointer
- 1) == '}'
5291 || *(input_line_pointer
- 2) == '}')
5292 finish_vinsn (&cur_vinsn
);
5295 /* We've just emitted a new instruction so clear the list of labels. */
5296 xtensa_clear_insn_labels ();
5300 /* HANDLE_ALIGN hook */
5302 /* For a .align directive, we mark the previous block with the alignment
5303 information. This will be placed in the object file in the
5304 property section corresponding to this section. */
5307 xtensa_handle_align (fragS
*fragP
)
5310 && ! fragP
->tc_frag_data
.is_literal
5311 && (fragP
->fr_type
== rs_align
5312 || fragP
->fr_type
== rs_align_code
)
5313 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5314 && fragP
->fr_offset
> 0
5315 && now_seg
!= bss_section
)
5317 fragP
->tc_frag_data
.is_align
= TRUE
;
5318 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5321 if (fragP
->fr_type
== rs_align_test
)
5324 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5326 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5327 _("unaligned entry instruction"));
5332 /* TC_FRAG_INIT hook */
5335 xtensa_frag_init (fragS
*frag
)
5337 xtensa_set_frag_assembly_state (frag
);
5342 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5348 /* Round up a section size to the appropriate boundary. */
5351 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5353 return size
; /* Byte alignment is fine. */
5358 md_pcrel_from (fixS
*fixP
)
5361 static xtensa_insnbuf insnbuf
= NULL
;
5362 static xtensa_insnbuf slotbuf
= NULL
;
5365 xtensa_opcode opcode
;
5368 xtensa_isa isa
= xtensa_default_isa
;
5369 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5370 bfd_boolean alt_reloc
;
5372 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5377 insnbuf
= xtensa_insnbuf_alloc (isa
);
5378 slotbuf
= xtensa_insnbuf_alloc (isa
);
5381 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5382 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5383 fmt
= xtensa_format_decode (isa
, insnbuf
);
5385 if (fmt
== XTENSA_UNDEFINED
)
5386 as_fatal (_("bad instruction format"));
5388 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5389 as_fatal (_("invalid relocation"));
5391 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5392 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5394 /* Check for "alternate" relocations (operand not specified). None
5395 of the current uses for these are really PC-relative. */
5396 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5398 if (opcode
!= xtensa_l32r_opcode
5399 && opcode
!= xtensa_const16_opcode
)
5400 as_fatal (_("invalid relocation for '%s' instruction"),
5401 xtensa_opcode_name (isa
, opcode
));
5405 opnum
= get_relaxable_immed (opcode
);
5407 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5408 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5410 as_bad_where (fixP
->fx_file
,
5412 _("invalid relocation for operand %d of '%s'"),
5413 opnum
, xtensa_opcode_name (isa
, opcode
));
5416 return 0 - opnd_value
;
5420 /* TC_FORCE_RELOCATION hook */
5423 xtensa_force_relocation (fixS
*fix
)
5425 switch (fix
->fx_r_type
)
5427 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5428 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5429 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5430 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5431 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5440 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5441 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5442 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5448 if (linkrelax
&& fix
->fx_addsy
5449 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5452 return generic_force_reloc (fix
);
5456 /* TC_VALIDATE_FIX_SUB hook */
5459 xtensa_validate_fix_sub (fixS
*fix
)
5461 segT add_symbol_segment
, sub_symbol_segment
;
5463 /* The difference of two symbols should be resolved by the assembler when
5464 linkrelax is not set. If the linker may relax the section containing
5465 the symbols, then an Xtensa DIFF relocation must be generated so that
5466 the linker knows to adjust the difference value. */
5467 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5470 /* Make sure both symbols are in the same segment, and that segment is
5471 "normal" and relaxable. If the segment is not "normal", then the
5472 fix is not valid. If the segment is not "relaxable", then the fix
5473 should have been handled earlier. */
5474 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5475 if (! SEG_NORMAL (add_symbol_segment
) ||
5476 ! relaxable_section (add_symbol_segment
))
5478 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5479 return (sub_symbol_segment
== add_symbol_segment
);
5483 /* NO_PSEUDO_DOT hook */
5485 /* This function has nothing to do with pseudo dots, but this is the
5486 nearest macro to where the check needs to take place. FIXME: This
5490 xtensa_check_inside_bundle (void)
5492 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5493 as_bad (_("directives are not valid inside bundles"));
5495 /* This function must always return FALSE because it is called via a
5496 macro that has nothing to do with bundling. */
5501 /* md_elf_section_change_hook */
5504 xtensa_elf_section_change_hook (void)
5506 /* Set up the assembly state. */
5507 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5508 xtensa_set_frag_assembly_state (frag_now
);
5512 /* tc_fix_adjustable hook */
5515 xtensa_fix_adjustable (fixS
*fixP
)
5517 /* An offset is not allowed in combination with the difference of two
5518 symbols, but that cannot be easily detected after a local symbol
5519 has been adjusted to a (section+offset) form. Return 0 so that such
5520 an fix will not be adjusted. */
5521 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5522 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5525 /* We need the symbol name for the VTABLE entries. */
5526 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5527 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5535 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5537 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5540 switch (fixP
->fx_r_type
)
5545 if (linkrelax
&& fixP
->fx_subsy
)
5547 switch (fixP
->fx_r_type
)
5550 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5553 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5556 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5562 /* An offset is only allowed when it results from adjusting a
5563 local symbol into a section-relative offset. If the offset
5564 came from the original expression, tc_fix_adjustable will have
5565 prevented the fix from being converted to a section-relative
5566 form so that we can flag the error here. */
5567 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5569 _("cannot represent subtraction with an offset"));
5571 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5572 - S_GET_VALUE (fixP
->fx_subsy
));
5574 /* The difference value gets written out, and the DIFF reloc
5575 identifies the address of the subtracted symbol (i.e., the one
5576 with the lowest address). */
5578 fixP
->fx_offset
-= val
;
5579 fixP
->fx_subsy
= NULL
;
5581 else if (! fixP
->fx_addsy
)
5588 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5589 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5592 case BFD_RELOC_XTENSA_SLOT0_OP
:
5593 case BFD_RELOC_XTENSA_SLOT1_OP
:
5594 case BFD_RELOC_XTENSA_SLOT2_OP
:
5595 case BFD_RELOC_XTENSA_SLOT3_OP
:
5596 case BFD_RELOC_XTENSA_SLOT4_OP
:
5597 case BFD_RELOC_XTENSA_SLOT5_OP
:
5598 case BFD_RELOC_XTENSA_SLOT6_OP
:
5599 case BFD_RELOC_XTENSA_SLOT7_OP
:
5600 case BFD_RELOC_XTENSA_SLOT8_OP
:
5601 case BFD_RELOC_XTENSA_SLOT9_OP
:
5602 case BFD_RELOC_XTENSA_SLOT10_OP
:
5603 case BFD_RELOC_XTENSA_SLOT11_OP
:
5604 case BFD_RELOC_XTENSA_SLOT12_OP
:
5605 case BFD_RELOC_XTENSA_SLOT13_OP
:
5606 case BFD_RELOC_XTENSA_SLOT14_OP
:
5609 /* Write the tentative value of a PC-relative relocation to a
5610 local symbol into the instruction. The value will be ignored
5611 by the linker, and it makes the object file disassembly
5612 readable when all branch targets are encoded in relocations. */
5614 assert (fixP
->fx_addsy
);
5615 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5616 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5618 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5619 - md_pcrel_from (fixP
));
5620 (void) xg_apply_fix_value (fixP
, val
);
5623 else if (! fixP
->fx_addsy
)
5626 if (xg_apply_fix_value (fixP
, val
))
5631 case BFD_RELOC_XTENSA_PLT
:
5632 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5633 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5634 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5635 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5636 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5637 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5648 /* These all need to be resolved at link-time. Do nothing now. */
5651 case BFD_RELOC_VTABLE_INHERIT
:
5652 case BFD_RELOC_VTABLE_ENTRY
:
5657 as_bad (_("unhandled local relocation fix %s"),
5658 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5664 md_atof (int type
, char *litP
, int *sizeP
)
5667 LITTLENUM_TYPE words
[4];
5683 return "bad call to md_atof";
5686 t
= atof_ieee (input_line_pointer
, type
, words
);
5688 input_line_pointer
= t
;
5692 for (i
= prec
- 1; i
>= 0; i
--)
5695 if (target_big_endian
)
5696 idx
= (prec
- 1 - i
);
5698 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5707 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5709 return total_frag_text_expansion (fragP
);
5713 /* Translate internal representation of relocation info to BFD target
5717 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5721 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5722 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5723 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5724 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5726 /* Make sure none of our internal relocations make it this far.
5727 They'd better have been fully resolved by this point. */
5728 assert ((int) fixp
->fx_r_type
> 0);
5730 reloc
->addend
= fixp
->fx_offset
;
5732 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5733 if (reloc
->howto
== NULL
)
5735 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5736 _("cannot represent `%s' relocation in object file"),
5737 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5738 free (reloc
->sym_ptr_ptr
);
5743 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5744 as_fatal (_("internal error? cannot generate `%s' relocation"),
5745 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5751 /* Checks for resource conflicts between instructions. */
5753 /* The func unit stuff could be implemented as bit-vectors rather
5754 than the iterative approach here. If it ends up being too
5755 slow, we will switch it. */
5758 new_resource_table (void *data
,
5761 unit_num_copies_func uncf
,
5762 opcode_num_units_func onuf
,
5763 opcode_funcUnit_use_unit_func ouuf
,
5764 opcode_funcUnit_use_stage_func ousf
)
5767 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5769 rt
->cycles
= cycles
;
5770 rt
->allocated_cycles
= cycles
;
5772 rt
->unit_num_copies
= uncf
;
5773 rt
->opcode_num_units
= onuf
;
5774 rt
->opcode_unit_use
= ouuf
;
5775 rt
->opcode_unit_stage
= ousf
;
5777 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5778 for (i
= 0; i
< cycles
; i
++)
5779 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5786 clear_resource_table (resource_table
*rt
)
5789 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5790 for (j
= 0; j
< rt
->num_units
; j
++)
5791 rt
->units
[i
][j
] = 0;
5795 /* We never shrink it, just fake it into thinking so. */
5798 resize_resource_table (resource_table
*rt
, int cycles
)
5802 rt
->cycles
= cycles
;
5803 if (cycles
<= rt
->allocated_cycles
)
5806 old_cycles
= rt
->allocated_cycles
;
5807 rt
->allocated_cycles
= cycles
;
5809 rt
->units
= xrealloc (rt
->units
,
5810 rt
->allocated_cycles
* sizeof (unsigned char *));
5811 for (i
= 0; i
< old_cycles
; i
++)
5812 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5813 rt
->num_units
* sizeof (unsigned char));
5814 for (i
= old_cycles
; i
< cycles
; i
++)
5815 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5820 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5823 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5825 for (i
= 0; i
< uses
; i
++)
5827 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5828 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5829 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5830 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5831 if (copies_in_use
>= copies
)
5839 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5842 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5844 for (i
= 0; i
< uses
; i
++)
5846 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5847 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5848 /* Note that this allows resources to be oversubscribed. That's
5849 essential to the way the optional scheduler works.
5850 resources_available reports when a resource is over-subscribed,
5851 so it's easy to tell. */
5852 rt
->units
[stage
+ cycle
][unit
]++;
5858 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5861 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5863 for (i
= 0; i
< uses
; i
++)
5865 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5866 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5867 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5868 rt
->units
[stage
+ cycle
][unit
]--;
5873 /* Wrapper functions make parameterized resource reservation
5877 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5879 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5885 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5887 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5892 /* Note that this function does not check issue constraints, but
5893 solely whether the hardware is available to execute the given
5894 instructions together. It also doesn't check if the tinsns
5895 write the same state, or access the same tieports. That is
5896 checked by check_t1_t2_reads_and_writes. */
5899 resources_conflict (vliw_insn
*vinsn
)
5902 static resource_table
*rt
= NULL
;
5904 /* This is the most common case by far. Optimize it. */
5905 if (vinsn
->num_slots
== 1)
5910 xtensa_isa isa
= xtensa_default_isa
;
5911 rt
= new_resource_table
5912 (isa
, xtensa_isa_num_pipe_stages (isa
),
5913 xtensa_isa_num_funcUnits (isa
),
5914 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5915 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5916 opcode_funcUnit_use_unit
,
5917 opcode_funcUnit_use_stage
);
5920 clear_resource_table (rt
);
5922 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5924 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5926 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5933 /* finish_vinsn, emit_single_op and helper functions. */
5935 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5936 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5937 static void xg_assemble_vliw_tokens (vliw_insn
*);
5940 /* We have reached the end of a bundle; emit into the frag. */
5943 finish_vinsn (vliw_insn
*vinsn
)
5950 if (find_vinsn_conflicts (vinsn
))
5952 xg_clear_vinsn (vinsn
);
5956 /* First, find a format that works. */
5957 if (vinsn
->format
== XTENSA_UNDEFINED
)
5958 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5960 if (vinsn
->format
== XTENSA_UNDEFINED
)
5962 as_where (&file_name
, &line
);
5963 as_bad_where (file_name
, line
,
5964 _("couldn't find a valid instruction format"));
5965 fprintf (stderr
, _(" ops were: "));
5966 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5967 fprintf (stderr
, _(" %s;"),
5968 xtensa_opcode_name (xtensa_default_isa
,
5969 vinsn
->slots
[i
].opcode
));
5970 fprintf (stderr
, _("\n"));
5971 xg_clear_vinsn (vinsn
);
5975 if (vinsn
->num_slots
5976 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5978 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5979 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5980 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5982 xg_clear_vinsn (vinsn
);
5986 if (resources_conflict (vinsn
))
5988 as_where (&file_name
, &line
);
5989 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5990 fprintf (stderr
, " ops were: ");
5991 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5992 fprintf (stderr
, " %s;",
5993 xtensa_opcode_name (xtensa_default_isa
,
5994 vinsn
->slots
[i
].opcode
));
5995 fprintf (stderr
, "\n");
5996 xg_clear_vinsn (vinsn
);
6000 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6002 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6004 symbolS
*lit_sym
= NULL
;
6006 bfd_boolean e
= FALSE
;
6007 bfd_boolean saved_density
= density_supported
;
6009 /* We don't want to narrow ops inside multi-slot bundles. */
6010 if (vinsn
->num_slots
> 1)
6011 density_supported
= FALSE
;
6013 istack_init (&slotstack
);
6014 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6016 vinsn
->slots
[i
].opcode
=
6017 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6019 vinsn
->slots
[i
].ntok
= 0;
6022 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6028 density_supported
= saved_density
;
6032 xg_clear_vinsn (vinsn
);
6036 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6038 TInsn
*insn
= &slotstack
.insn
[j
];
6039 if (insn
->insn_type
== ITYPE_LITERAL
)
6041 assert (lit_sym
== NULL
);
6042 lit_sym
= xg_assemble_literal (insn
);
6046 assert (insn
->insn_type
== ITYPE_INSN
);
6048 xg_resolve_literals (insn
, lit_sym
);
6049 if (j
!= slotstack
.ninsn
- 1)
6050 emit_single_op (insn
);
6054 if (vinsn
->num_slots
> 1)
6056 if (opcode_fits_format_slot
6057 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6060 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6064 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6065 if (vinsn
->format
== XTENSA_UNDEFINED
)
6066 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6068 vinsn
->slots
[i
].opcode
6069 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6072 vinsn
->slots
[i
].ntok
= 0;
6077 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6078 vinsn
->format
= XTENSA_UNDEFINED
;
6083 /* Now check resource conflicts on the modified bundle. */
6084 if (resources_conflict (vinsn
))
6086 as_where (&file_name
, &line
);
6087 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6088 fprintf (stderr
, " ops were: ");
6089 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6090 fprintf (stderr
, " %s;",
6091 xtensa_opcode_name (xtensa_default_isa
,
6092 vinsn
->slots
[i
].opcode
));
6093 fprintf (stderr
, "\n");
6094 xg_clear_vinsn (vinsn
);
6098 /* First, find a format that works. */
6099 if (vinsn
->format
== XTENSA_UNDEFINED
)
6100 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6102 xg_assemble_vliw_tokens (vinsn
);
6104 xg_clear_vinsn (vinsn
);
6108 /* Given an vliw instruction, what conflicts are there in register
6109 usage and in writes to states and queues?
6111 This function does two things:
6112 1. Reports an error when a vinsn contains illegal combinations
6113 of writes to registers states or queues.
6114 2. Marks individual tinsns as not relaxable if the combination
6115 contains antidependencies.
6117 Job 2 handles things like swap semantics in instructions that need
6118 to be relaxed. For example,
6122 normally would be relaxed to
6127 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6129 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6131 then we can't relax it into
6134 { add a0, a1, a0 ; add a2, a0, a4 ; }
6136 because the value of a0 is trashed before the second add can read it. */
6138 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6141 find_vinsn_conflicts (vliw_insn
*vinsn
)
6145 xtensa_isa isa
= xtensa_default_isa
;
6147 assert (!past_xtensa_end
);
6149 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6151 TInsn
*op1
= &vinsn
->slots
[i
];
6152 if (op1
->is_specific_opcode
)
6153 op1
->keep_wide
= TRUE
;
6155 op1
->keep_wide
= FALSE
;
6158 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6160 TInsn
*op1
= &vinsn
->slots
[i
];
6162 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6165 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6169 TInsn
*op2
= &vinsn
->slots
[j
];
6170 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6171 switch (conflict_type
)
6174 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6175 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6176 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6179 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6180 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6181 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6184 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6185 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6186 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6189 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6190 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6191 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6194 /* Everything is OK. */
6197 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6198 || conflict_type
== 'a');
6205 as_bad (_("multiple branches or jumps in the same bundle"));
6213 /* Check how the state used by t1 and t2 relate.
6216 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6217 case B: no relationship between what is read and written (both could
6218 read the same reg though)
6219 case C: t1 writes a register t2 writes (a register conflict within a
6221 case D: t1 writes a state that t2 also writes
6222 case E: t1 writes a tie queue that t2 also writes
6223 case F: two volatile queue accesses
6227 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6229 xtensa_isa isa
= xtensa_default_isa
;
6230 xtensa_regfile t1_regfile
, t2_regfile
;
6232 int t1_base_reg
, t1_last_reg
;
6233 int t2_base_reg
, t2_last_reg
;
6234 char t1_inout
, t2_inout
;
6236 char conflict
= 'b';
6241 bfd_boolean t1_volatile
= FALSE
;
6242 bfd_boolean t2_volatile
= FALSE
;
6244 /* Check registers. */
6245 for (j
= 0; j
< t2
->ntok
; j
++)
6247 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6250 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6251 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6252 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6254 for (i
= 0; i
< t1
->ntok
; i
++)
6256 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6259 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6261 if (t1_regfile
!= t2_regfile
)
6264 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6265 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6267 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6268 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6270 if (t1_inout
== 'm' || t1_inout
== 'o'
6271 || t2_inout
== 'm' || t2_inout
== 'o')
6278 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6279 t1_last_reg
= (t1_base_reg
6280 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6282 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6284 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6286 if (t1_reg
!= t2_reg
)
6289 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6295 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6301 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6309 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6310 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6311 for (j
= 0; j
< t2_states
; j
++)
6313 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6314 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6315 for (i
= 0; i
< t1_states
; i
++)
6317 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6318 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6322 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6328 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6334 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6339 /* Check tieports. */
6340 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6341 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6342 for (j
= 0; j
< t2_interfaces
; j
++)
6344 xtensa_interface t2_int
6345 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6346 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6348 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6349 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6352 for (i
= 0; i
< t1_interfaces
; i
++)
6354 xtensa_interface t1_int
6355 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6356 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6358 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6359 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6362 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6365 if (t1_int
!= t2_int
)
6368 if (t2_inout
== 'i' && t1_inout
== 'o')
6374 if (t1_inout
== 'i' && t2_inout
== 'o')
6380 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6389 static xtensa_format
6390 xg_find_narrowest_format (vliw_insn
*vinsn
)
6392 /* Right now we assume that the ops within the vinsn are properly
6393 ordered for the slots that the programmer wanted them in. In
6394 other words, we don't rearrange the ops in hopes of finding a
6395 better format. The scheduler handles that. */
6397 xtensa_isa isa
= xtensa_default_isa
;
6398 xtensa_format format
;
6399 vliw_insn v_copy
= *vinsn
;
6400 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6402 if (vinsn
->num_slots
== 1)
6403 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6405 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6408 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6412 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6414 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6416 v_copy
.slots
[slot
].opcode
=
6417 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6418 v_copy
.slots
[slot
].ntok
= 0;
6421 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6424 else if (v_copy
.num_slots
> 1)
6427 /* Try the widened version. */
6428 if (!v_copy
.slots
[slot
].keep_wide
6429 && !v_copy
.slots
[slot
].is_specific_opcode
6430 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6432 && opcode_fits_format_slot (widened
.opcode
,
6435 v_copy
.slots
[slot
] = widened
;
6440 if (fit
== v_copy
.num_slots
)
6443 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6444 vinsn
->format
= format
;
6450 if (format
== xtensa_isa_num_formats (isa
))
6451 return XTENSA_UNDEFINED
;
6457 /* Return the additional space needed in a frag
6458 for possible relaxations of any ops in a VLIW insn.
6459 Also fill out the relaxations that might be required of
6460 each tinsn in the vinsn. */
6463 relaxation_requirements (vliw_insn
*vinsn
)
6465 int extra_space
= 0;
6468 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6470 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6471 if (!tinsn_has_symbolic_operands (tinsn
))
6473 /* A narrow instruction could be widened later to help
6474 alignment issues. */
6475 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6476 && !tinsn
->is_specific_opcode
6477 && vinsn
->num_slots
== 1)
6479 /* Difference in bytes between narrow and wide insns... */
6481 tinsn
->subtype
= RELAX_NARROW
;
6482 tinsn
->record_fix
= TRUE
;
6487 tinsn
->record_fix
= FALSE
;
6488 /* No extra_space needed. */
6493 if (workaround_b_j_loop_end
6494 && tinsn
->opcode
== xtensa_jx_opcode
6495 && use_transform ())
6497 /* Add 2 of these. */
6498 extra_space
+= 3; /* for the nop size */
6499 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6502 /* Need to assemble it with space for the relocation. */
6503 if (xg_is_relaxable_insn (tinsn
, 0)
6504 && !tinsn
->is_specific_opcode
)
6506 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6507 int max_literal_size
=
6508 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6510 tinsn
->literal_space
= max_literal_size
;
6512 tinsn
->subtype
= RELAX_IMMED
;
6513 tinsn
->record_fix
= FALSE
;
6514 extra_space
+= max_size
;
6518 tinsn
->record_fix
= TRUE
;
6519 /* No extra space needed. */
6528 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6530 xtensa_isa isa
= xtensa_default_isa
;
6531 int slot
, chosen_slot
;
6533 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6534 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6535 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6537 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6538 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6540 if (slot
== chosen_slot
)
6541 vinsn
->slots
[slot
] = *tinsn
;
6544 vinsn
->slots
[slot
].opcode
=
6545 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6546 vinsn
->slots
[slot
].ntok
= 0;
6547 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6554 emit_single_op (TInsn
*orig_insn
)
6557 IStack istack
; /* put instructions into here */
6558 symbolS
*lit_sym
= NULL
;
6559 symbolS
*label_sym
= NULL
;
6561 istack_init (&istack
);
6563 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6564 Because the scheduling and bundling characteristics of movi and
6565 l32r or const16 are so different, we can do much better if we relax
6566 it prior to scheduling and bundling, rather than after. */
6567 if ((orig_insn
->opcode
== xtensa_movi_opcode
6568 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6569 && !cur_vinsn
.inside_bundle
6570 && (orig_insn
->tok
[1].X_op
== O_symbol
6571 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6572 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6574 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6577 for (i
= 0; i
< istack
.ninsn
; i
++)
6579 TInsn
*insn
= &istack
.insn
[i
];
6580 switch (insn
->insn_type
)
6583 assert (lit_sym
== NULL
);
6584 lit_sym
= xg_assemble_literal (insn
);
6588 static int relaxed_sym_idx
= 0;
6589 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6590 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6592 assert (label_sym
== NULL
);
6593 label_sym
= symbol_find_or_make (label
);
6602 xg_resolve_literals (insn
, lit_sym
);
6604 xg_resolve_labels (insn
, label_sym
);
6606 bundle_tinsn (insn
, &v
);
6621 total_frag_text_expansion (fragS
*fragP
)
6624 int total_expansion
= 0;
6626 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6627 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6629 return total_expansion
;
6633 /* Emit a vliw instruction to the current fragment. */
6636 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6638 bfd_boolean finish_frag
= FALSE
;
6639 bfd_boolean is_jump
= FALSE
;
6640 bfd_boolean is_branch
= FALSE
;
6641 xtensa_isa isa
= xtensa_default_isa
;
6647 unsigned current_line
, best_linenum
;
6650 best_linenum
= UINT_MAX
;
6652 if (generating_literals
)
6654 static int reported
= 0;
6656 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6657 _("cannot assemble into a literal fragment"));
6664 if (frag_now_fix () != 0
6665 && (! frag_now
->tc_frag_data
.is_insn
6666 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6667 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6668 || (directive_state
[directive_longcalls
]
6669 != frag_now
->tc_frag_data
.use_longcalls
)
6670 || (directive_state
[directive_absolute_literals
]
6671 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6673 frag_wane (frag_now
);
6675 xtensa_set_frag_assembly_state (frag_now
);
6678 if (workaround_a0_b_retw
6679 && vinsn
->num_slots
== 1
6680 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6681 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6682 && use_transform ())
6684 has_a0_b_retw
= TRUE
;
6686 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6687 After the first assembly pass we will check all of them and
6688 add a nop if needed. */
6689 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6690 frag_var (rs_machine_dependent
, 4, 4,
6691 RELAX_ADD_NOP_IF_A0_B_RETW
,
6692 frag_now
->fr_symbol
,
6693 frag_now
->fr_offset
,
6695 xtensa_set_frag_assembly_state (frag_now
);
6696 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6697 frag_var (rs_machine_dependent
, 4, 4,
6698 RELAX_ADD_NOP_IF_A0_B_RETW
,
6699 frag_now
->fr_symbol
,
6700 frag_now
->fr_offset
,
6702 xtensa_set_frag_assembly_state (frag_now
);
6705 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6707 /* See if the instruction implies an aligned section. */
6708 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6709 record_alignment (now_seg
, 2);
6711 /* Also determine the best line number for debug info. */
6712 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6713 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6716 /* Special cases for instructions that force an alignment... */
6717 /* None of these opcodes are bundle-able. */
6718 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6722 xtensa_set_frag_assembly_state (frag_now
);
6723 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6725 max_fill
= get_text_align_max_fill_size
6726 (get_text_align_power (xtensa_fetch_width
),
6727 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6729 if (use_transform ())
6730 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6731 RELAX_ALIGN_NEXT_OPCODE
,
6732 frag_now
->fr_symbol
,
6733 frag_now
->fr_offset
,
6736 frag_var (rs_machine_dependent
, 0, 0,
6737 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6738 xtensa_set_frag_assembly_state (frag_now
);
6740 xtensa_move_labels (frag_now
, 0, FALSE
);
6743 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6744 && !vinsn
->slots
[0].is_specific_opcode
)
6746 xtensa_mark_literal_pool_location ();
6747 xtensa_move_labels (frag_now
, 0, TRUE
);
6748 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6751 if (vinsn
->num_slots
== 1)
6753 if (workaround_a0_b_retw
&& use_transform ())
6754 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6755 is_register_writer (&vinsn
->slots
[0], "a", 0));
6757 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6758 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6761 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6763 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6765 extra_space
= relaxation_requirements (vinsn
);
6767 /* vinsn_to_insnbuf will produce the error. */
6768 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6770 f
= frag_more (insn_size
+ extra_space
);
6771 xtensa_set_frag_assembly_state (frag_now
);
6772 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6775 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6776 if (vinsn
->format
== XTENSA_UNDEFINED
)
6779 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6781 /* Temporarily set the logical line number to the one we want to appear
6782 in the debug information. */
6783 as_where (¤t_file
, ¤t_line
);
6784 new_logical_line (current_file
, best_linenum
);
6785 dwarf2_emit_insn (insn_size
+ extra_space
);
6786 new_logical_line (current_file
, current_line
);
6788 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6790 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6791 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6792 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6793 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6794 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6795 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6796 if (tinsn
->literal_space
!= 0)
6797 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6799 if (tinsn
->subtype
== RELAX_NARROW
)
6800 assert (vinsn
->num_slots
== 1);
6801 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6803 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6806 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6807 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6811 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6812 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6816 frag_variant (rs_machine_dependent
,
6817 extra_space
, extra_space
, RELAX_SLOTS
,
6818 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6819 xtensa_set_frag_assembly_state (frag_now
);
6822 /* Special cases for loops:
6823 close_loop_end should be inserted AFTER short_loop.
6824 Make sure that CLOSE loops are processed BEFORE short_loops
6825 when converting them. */
6827 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6828 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6829 && !vinsn
->slots
[0].is_specific_opcode
)
6831 if (workaround_short_loop
&& use_transform ())
6833 maybe_has_short_loop
= TRUE
;
6834 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6835 frag_var (rs_machine_dependent
, 4, 4,
6836 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6837 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6838 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6839 frag_var (rs_machine_dependent
, 4, 4,
6840 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6841 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6844 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6845 loop at least 12 bytes away from another loop's end. */
6846 if (workaround_close_loop_end
&& use_transform ())
6848 maybe_has_close_loop_end
= TRUE
;
6849 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6850 frag_var (rs_machine_dependent
, 12, 12,
6851 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6852 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6856 if (use_transform ())
6860 assert (finish_frag
);
6861 frag_var (rs_machine_dependent
,
6862 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6864 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6865 xtensa_set_frag_assembly_state (frag_now
);
6867 else if (is_branch
&& do_align_targets ())
6869 assert (finish_frag
);
6870 frag_var (rs_machine_dependent
,
6871 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6872 RELAX_MAYBE_UNREACHABLE
,
6873 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6874 xtensa_set_frag_assembly_state (frag_now
);
6875 frag_var (rs_machine_dependent
,
6877 RELAX_MAYBE_DESIRE_ALIGN
,
6878 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6879 xtensa_set_frag_assembly_state (frag_now
);
6883 /* Now, if the original opcode was a call... */
6884 if (do_align_targets ()
6885 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6887 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6888 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6889 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6890 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6891 xtensa_set_frag_assembly_state (frag_now
);
6894 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6896 frag_wane (frag_now
);
6898 xtensa_set_frag_assembly_state (frag_now
);
6903 /* xtensa_end and helper functions. */
6905 static void xtensa_cleanup_align_frags (void);
6906 static void xtensa_fix_target_frags (void);
6907 static void xtensa_mark_narrow_branches (void);
6908 static void xtensa_mark_zcl_first_insns (void);
6909 static void xtensa_fix_a0_b_retw_frags (void);
6910 static void xtensa_fix_b_j_loop_end_frags (void);
6911 static void xtensa_fix_close_loop_end_frags (void);
6912 static void xtensa_fix_short_loop_frags (void);
6913 static void xtensa_sanity_check (void);
6918 directive_balance ();
6919 xtensa_flush_pending_output ();
6921 past_xtensa_end
= TRUE
;
6923 xtensa_move_literals ();
6925 xtensa_reorder_segments ();
6926 xtensa_cleanup_align_frags ();
6927 xtensa_fix_target_frags ();
6928 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6929 xtensa_fix_a0_b_retw_frags ();
6930 if (workaround_b_j_loop_end
)
6931 xtensa_fix_b_j_loop_end_frags ();
6933 /* "close_loop_end" should be processed BEFORE "short_loop". */
6934 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6935 xtensa_fix_close_loop_end_frags ();
6937 if (workaround_short_loop
&& maybe_has_short_loop
)
6938 xtensa_fix_short_loop_frags ();
6939 xtensa_mark_narrow_branches ();
6940 xtensa_mark_zcl_first_insns ();
6942 xtensa_sanity_check ();
6947 xtensa_cleanup_align_frags (void)
6951 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6954 /* Walk over all of the fragments in a subsection. */
6955 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6957 if ((fragP
->fr_type
== rs_align
6958 || fragP
->fr_type
== rs_align_code
6959 || (fragP
->fr_type
== rs_machine_dependent
6960 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6961 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6962 && fragP
->fr_fix
== 0)
6964 fragS
*next
= fragP
->fr_next
;
6967 && next
->fr_fix
== 0
6968 && next
->fr_type
== rs_machine_dependent
6969 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6972 next
= next
->fr_next
;
6975 /* If we don't widen branch targets, then they
6976 will be easier to align. */
6977 if (fragP
->tc_frag_data
.is_branch_target
6978 && fragP
->fr_opcode
== fragP
->fr_literal
6979 && fragP
->fr_type
== rs_machine_dependent
6980 && fragP
->fr_subtype
== RELAX_SLOTS
6981 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6983 if (fragP
->fr_type
== rs_machine_dependent
6984 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6985 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6991 /* Re-process all of the fragments looking to convert all of the
6992 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6993 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6994 Otherwise, convert to a .fill 0. */
6997 xtensa_fix_target_frags (void)
7001 /* When this routine is called, all of the subsections are still intact
7002 so we walk over subsections instead of sections. */
7003 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7007 /* Walk over all of the fragments in a subsection. */
7008 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7010 if (fragP
->fr_type
== rs_machine_dependent
7011 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7013 if (next_frag_is_branch_target (fragP
))
7014 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7023 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7026 xtensa_mark_narrow_branches (void)
7030 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7033 /* Walk over all of the fragments in a subsection. */
7034 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7036 if (fragP
->fr_type
== rs_machine_dependent
7037 && fragP
->fr_subtype
== RELAX_SLOTS
7038 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7041 const expressionS
*expr
;
7044 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7045 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7047 expr
= &vinsn
.slots
[0].tok
[1];
7048 symbolP
= expr
->X_add_symbol
;
7050 if (vinsn
.num_slots
== 1
7051 && xtensa_opcode_is_branch (xtensa_default_isa
,
7052 vinsn
.slots
[0].opcode
)
7053 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7054 && is_narrow_branch_guaranteed_in_range (fragP
,
7057 fragP
->fr_subtype
= RELAX_SLOTS
;
7058 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7059 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7067 /* A branch is typically widened only when its target is out of
7068 range. However, we would like to widen them to align a subsequent
7069 branch target when possible.
7071 Because the branch relaxation code is so convoluted, the optimal solution
7072 (combining the two cases) is difficult to get right in all circumstances.
7073 We therefore go with an "almost as good" solution, where we only
7074 use for alignment narrow branches that definitely will not expand to a
7075 jump and a branch. These functions find and mark these cases. */
7077 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7078 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7079 We start counting beginning with the frag after the 2-byte branch, so the
7080 maximum offset is (4 - 2) + 63 = 65. */
7081 #define MAX_IMMED6 65
7083 static offsetT
unrelaxed_frag_max_size (fragS
*);
7086 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7088 const expressionS
*expr
= &tinsn
->tok
[1];
7089 symbolS
*symbolP
= expr
->X_add_symbol
;
7090 fragS
*target_frag
= symbol_get_frag (symbolP
);
7091 offsetT max_distance
= expr
->X_add_number
;
7092 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7093 if (is_branch_jmp_to_next (tinsn
, fragP
))
7096 /* The branch doesn't branch over it's own frag,
7097 but over the subsequent ones. */
7098 fragP
= fragP
->fr_next
;
7099 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7101 max_distance
+= unrelaxed_frag_max_size (fragP
);
7102 fragP
= fragP
->fr_next
;
7104 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7111 xtensa_mark_zcl_first_insns (void)
7115 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7118 /* Walk over all of the fragments in a subsection. */
7119 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7121 if (fragP
->fr_type
== rs_machine_dependent
7122 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7123 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7125 /* Find the loop frag. */
7126 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7127 /* Find the first insn frag. */
7128 targ_frag
= next_non_empty_frag (targ_frag
);
7130 /* Of course, sometimes (mostly for toy test cases) a
7131 zero-cost loop instruction is the last in a section. */
7133 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7134 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7142 /* Re-process all of the fragments looking to convert all of the
7143 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7144 conditional branch or a retw/retw.n, convert this frag to one that
7145 will generate a NOP. In any case close it off with a .fill 0. */
7147 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7150 xtensa_fix_a0_b_retw_frags (void)
7154 /* When this routine is called, all of the subsections are still intact
7155 so we walk over subsections instead of sections. */
7156 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7160 /* Walk over all of the fragments in a subsection. */
7161 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7163 if (fragP
->fr_type
== rs_machine_dependent
7164 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7166 if (next_instrs_are_b_retw (fragP
))
7168 if (fragP
->tc_frag_data
.is_no_transform
)
7169 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7171 relax_frag_add_nop (fragP
);
7181 next_instrs_are_b_retw (fragS
*fragP
)
7183 xtensa_opcode opcode
;
7185 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7186 static xtensa_insnbuf insnbuf
= NULL
;
7187 static xtensa_insnbuf slotbuf
= NULL
;
7188 xtensa_isa isa
= xtensa_default_isa
;
7191 bfd_boolean branch_seen
= FALSE
;
7195 insnbuf
= xtensa_insnbuf_alloc (isa
);
7196 slotbuf
= xtensa_insnbuf_alloc (isa
);
7199 if (next_fragP
== NULL
)
7202 /* Check for the conditional branch. */
7203 xtensa_insnbuf_from_chars
7204 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7205 fmt
= xtensa_format_decode (isa
, insnbuf
);
7206 if (fmt
== XTENSA_UNDEFINED
)
7209 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7211 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7212 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7214 branch_seen
= (branch_seen
7215 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7221 offset
+= xtensa_format_length (isa
, fmt
);
7222 if (offset
== next_fragP
->fr_fix
)
7224 next_fragP
= next_non_empty_frag (next_fragP
);
7228 if (next_fragP
== NULL
)
7231 /* Check for the retw/retw.n. */
7232 xtensa_insnbuf_from_chars
7233 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7234 fmt
= xtensa_format_decode (isa
, insnbuf
);
7236 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7237 have no problems. */
7238 if (fmt
== XTENSA_UNDEFINED
7239 || xtensa_format_num_slots (isa
, fmt
) != 1)
7242 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7243 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7245 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7252 /* Re-process all of the fragments looking to convert all of the
7253 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7254 loop end label, convert this frag to one that will generate a NOP.
7255 In any case close it off with a .fill 0. */
7257 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7260 xtensa_fix_b_j_loop_end_frags (void)
7264 /* When this routine is called, all of the subsections are still intact
7265 so we walk over subsections instead of sections. */
7266 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7270 /* Walk over all of the fragments in a subsection. */
7271 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7273 if (fragP
->fr_type
== rs_machine_dependent
7274 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7276 if (next_instr_is_loop_end (fragP
))
7278 if (fragP
->tc_frag_data
.is_no_transform
)
7279 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7281 relax_frag_add_nop (fragP
);
7291 next_instr_is_loop_end (fragS
*fragP
)
7293 const fragS
*next_fragP
;
7295 if (next_frag_is_loop_target (fragP
))
7298 next_fragP
= next_non_empty_frag (fragP
);
7299 if (next_fragP
== NULL
)
7302 if (!next_frag_is_loop_target (next_fragP
))
7305 /* If the size is >= 3 then there is more than one instruction here.
7306 The hardware bug will not fire. */
7307 if (next_fragP
->fr_fix
> 3)
7314 /* Re-process all of the fragments looking to convert all of the
7315 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7316 not MY loop's loop end within 12 bytes, add enough nops here to
7317 make it at least 12 bytes away. In any case close it off with a
7320 static offsetT min_bytes_to_other_loop_end
7321 (fragS
*, fragS
*, offsetT
, offsetT
);
7324 xtensa_fix_close_loop_end_frags (void)
7328 /* When this routine is called, all of the subsections are still intact
7329 so we walk over subsections instead of sections. */
7330 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7334 fragS
*current_target
= NULL
;
7335 offsetT current_offset
= 0;
7337 /* Walk over all of the fragments in a subsection. */
7338 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7340 if (fragP
->fr_type
== rs_machine_dependent
7341 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7342 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7343 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7346 /* Read it. If the instruction is a loop, get the target. */
7348 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7349 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7350 t_insn
.opcode
) == 1)
7352 /* Get the current fragment target. */
7353 if (fragP
->tc_frag_data
.slot_symbols
[0])
7355 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7356 current_target
= symbol_get_frag (sym
);
7357 current_offset
= fragP
->fr_offset
;
7363 && fragP
->fr_type
== rs_machine_dependent
7364 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7367 int bytes_added
= 0;
7369 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7370 /* Max out at 12. */
7371 min_bytes
= min_bytes_to_other_loop_end
7372 (fragP
->fr_next
, current_target
, current_offset
,
7373 REQUIRED_LOOP_DIVIDING_BYTES
);
7375 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7377 if (fragP
->tc_frag_data
.is_no_transform
)
7378 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7381 while (min_bytes
+ bytes_added
7382 < REQUIRED_LOOP_DIVIDING_BYTES
)
7386 if (fragP
->fr_var
< length
)
7387 as_fatal (_("fr_var %lu < length %d"),
7388 (long) fragP
->fr_var
, length
);
7391 assemble_nop (length
,
7392 fragP
->fr_literal
+ fragP
->fr_fix
);
7393 fragP
->fr_fix
+= length
;
7394 fragP
->fr_var
-= length
;
7396 bytes_added
+= length
;
7402 assert (fragP
->fr_type
!= rs_machine_dependent
7403 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7409 static offsetT
unrelaxed_frag_min_size (fragS
*);
7412 min_bytes_to_other_loop_end (fragS
*fragP
,
7413 fragS
*current_target
,
7414 offsetT current_offset
,
7418 fragS
*current_fragP
;
7420 for (current_fragP
= fragP
;
7422 current_fragP
= current_fragP
->fr_next
)
7424 if (current_fragP
->tc_frag_data
.is_loop_target
7425 && current_fragP
!= current_target
)
7426 return offset
+ current_offset
;
7428 offset
+= unrelaxed_frag_min_size (current_fragP
);
7430 if (offset
+ current_offset
>= max_size
)
7438 unrelaxed_frag_min_size (fragS
*fragP
)
7440 offsetT size
= fragP
->fr_fix
;
7442 /* Add fill size. */
7443 if (fragP
->fr_type
== rs_fill
)
7444 size
+= fragP
->fr_offset
;
7451 unrelaxed_frag_max_size (fragS
*fragP
)
7453 offsetT size
= fragP
->fr_fix
;
7454 switch (fragP
->fr_type
)
7457 /* Empty frags created by the obstack allocation scheme
7458 end up with type 0. */
7463 size
+= fragP
->fr_offset
;
7471 /* No further adjustments needed. */
7473 case rs_machine_dependent
:
7474 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7475 size
+= fragP
->fr_var
;
7478 /* We had darn well better know how big it is. */
7487 /* Re-process all of the fragments looking to convert all
7488 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7491 1) the instruction size count to the loop end label
7492 is too short (<= 2 instructions),
7493 2) loop has a jump or branch in it
7496 1) workaround_all_short_loops is TRUE
7497 2) The generating loop was a 'loopgtz' or 'loopnez'
7498 3) the instruction size count to the loop end label is too short
7500 then convert this frag (and maybe the next one) to generate a NOP.
7501 In any case close it off with a .fill 0. */
7503 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7504 static bfd_boolean
branch_before_loop_end (fragS
*);
7507 xtensa_fix_short_loop_frags (void)
7511 /* When this routine is called, all of the subsections are still intact
7512 so we walk over subsections instead of sections. */
7513 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7516 fragS
*current_target
= NULL
;
7517 offsetT current_offset
= 0;
7518 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7520 /* Walk over all of the fragments in a subsection. */
7521 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7523 /* Check on the current loop. */
7524 if (fragP
->fr_type
== rs_machine_dependent
7525 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7526 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7527 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7532 /* Read it. If the instruction is a loop, get the target. */
7533 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7534 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7535 t_insn
.opcode
) == 1)
7537 /* Get the current fragment target. */
7538 if (fragP
->tc_frag_data
.slot_symbols
[0])
7540 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7541 current_target
= symbol_get_frag (sym
);
7542 current_offset
= fragP
->fr_offset
;
7543 current_opcode
= t_insn
.opcode
;
7548 if (fragP
->fr_type
== rs_machine_dependent
7549 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7551 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7552 && (branch_before_loop_end (fragP
->fr_next
)
7553 || (workaround_all_short_loops
7554 && current_opcode
!= XTENSA_UNDEFINED
7555 && current_opcode
!= xtensa_loop_opcode
)))
7557 if (fragP
->tc_frag_data
.is_no_transform
)
7558 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7560 relax_frag_add_nop (fragP
);
7569 static int unrelaxed_frag_min_insn_count (fragS
*);
7572 count_insns_to_loop_end (fragS
*base_fragP
,
7573 bfd_boolean count_relax_add
,
7576 fragS
*fragP
= NULL
;
7581 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7583 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7584 if (insn_count
>= max_count
)
7587 if (count_relax_add
)
7589 if (fragP
->fr_type
== rs_machine_dependent
7590 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7592 /* In order to add the appropriate number of
7593 NOPs, we count an instruction for downstream
7596 if (insn_count
>= max_count
)
7606 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7608 xtensa_isa isa
= xtensa_default_isa
;
7609 static xtensa_insnbuf insnbuf
= NULL
;
7613 if (!fragP
->tc_frag_data
.is_insn
)
7617 insnbuf
= xtensa_insnbuf_alloc (isa
);
7619 /* Decode the fixed instructions. */
7620 while (offset
< fragP
->fr_fix
)
7624 xtensa_insnbuf_from_chars
7625 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7626 fmt
= xtensa_format_decode (isa
, insnbuf
);
7628 if (fmt
== XTENSA_UNDEFINED
)
7630 as_fatal (_("undecodable instruction in instruction frag"));
7633 offset
+= xtensa_format_length (isa
, fmt
);
7641 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7644 branch_before_loop_end (fragS
*base_fragP
)
7648 for (fragP
= base_fragP
;
7649 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7650 fragP
= fragP
->fr_next
)
7652 if (unrelaxed_frag_has_b_j (fragP
))
7660 unrelaxed_frag_has_b_j (fragS
*fragP
)
7662 static xtensa_insnbuf insnbuf
= NULL
;
7663 xtensa_isa isa
= xtensa_default_isa
;
7666 if (!fragP
->tc_frag_data
.is_insn
)
7670 insnbuf
= xtensa_insnbuf_alloc (isa
);
7672 /* Decode the fixed instructions. */
7673 while (offset
< fragP
->fr_fix
)
7678 xtensa_insnbuf_from_chars
7679 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7680 fmt
= xtensa_format_decode (isa
, insnbuf
);
7681 if (fmt
== XTENSA_UNDEFINED
)
7684 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7686 xtensa_opcode opcode
=
7687 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7688 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7689 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7692 offset
+= xtensa_format_length (isa
, fmt
);
7698 /* Checks to be made after initial assembly but before relaxation. */
7700 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7701 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7704 xtensa_sanity_check (void)
7711 as_where (&file_name
, &line
);
7712 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7716 /* Walk over all of the fragments in a subsection. */
7717 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7719 /* Currently we only check for empty loops here. */
7720 if (fragP
->fr_type
== rs_machine_dependent
7721 && fragP
->fr_subtype
== RELAX_IMMED
)
7723 static xtensa_insnbuf insnbuf
= NULL
;
7726 if (fragP
->fr_opcode
!= NULL
)
7729 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7730 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7731 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7733 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7734 t_insn
.opcode
) == 1)
7736 if (is_empty_loop (&t_insn
, fragP
))
7738 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7739 as_bad (_("invalid empty loop"));
7741 if (!is_local_forward_loop (&t_insn
, fragP
))
7743 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7744 as_bad (_("loop target does not follow "
7745 "loop instruction in section"));
7752 new_logical_line (file_name
, line
);
7756 #define LOOP_IMMED_OPN 1
7758 /* Return TRUE if the loop target is the next non-zero fragment. */
7761 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7763 const expressionS
*expr
;
7767 if (insn
->insn_type
!= ITYPE_INSN
)
7770 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7773 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7776 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7778 if (expr
->X_op
!= O_symbol
)
7781 symbolP
= expr
->X_add_symbol
;
7785 if (symbol_get_frag (symbolP
) == NULL
)
7788 if (S_GET_VALUE (symbolP
) != 0)
7791 /* Walk through the zero-size fragments from this one. If we find
7792 the target fragment, then this is a zero-size loop. */
7794 for (next_fragP
= fragP
->fr_next
;
7796 next_fragP
= next_fragP
->fr_next
)
7798 if (next_fragP
== symbol_get_frag (symbolP
))
7800 if (next_fragP
->fr_fix
!= 0)
7808 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7810 const expressionS
*expr
;
7814 if (insn
->insn_type
!= ITYPE_INSN
)
7817 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7820 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7823 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7825 if (expr
->X_op
!= O_symbol
)
7828 symbolP
= expr
->X_add_symbol
;
7832 if (symbol_get_frag (symbolP
) == NULL
)
7835 /* Walk through fragments until we find the target.
7836 If we do not find the target, then this is an invalid loop. */
7838 for (next_fragP
= fragP
->fr_next
;
7840 next_fragP
= next_fragP
->fr_next
)
7842 if (next_fragP
== symbol_get_frag (symbolP
))
7850 /* Alignment Functions. */
7853 get_text_align_power (unsigned target_size
)
7858 assert (target_size
<= INT_MAX
);
7859 while (target_size
> power
)
7869 get_text_align_max_fill_size (int align_pow
,
7870 bfd_boolean use_nops
,
7871 bfd_boolean use_no_density
)
7874 return (1 << align_pow
);
7876 return 3 * (1 << align_pow
);
7878 return 1 + (1 << align_pow
);
7882 /* Calculate the minimum bytes of fill needed at "address" to align a
7883 target instruction of size "target_size" so that it does not cross a
7884 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7885 the fill can be an arbitrary number of bytes. Otherwise, the space must
7886 be filled by NOP instructions. */
7889 get_text_align_fill_size (addressT address
,
7892 bfd_boolean use_nops
,
7893 bfd_boolean use_no_density
)
7895 addressT alignment
, fill
, fill_limit
, fill_step
;
7896 bfd_boolean skip_one
= FALSE
;
7898 alignment
= (1 << align_pow
);
7899 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7903 fill_limit
= alignment
;
7906 else if (!use_no_density
)
7908 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7909 fill_limit
= alignment
* 2;
7915 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7916 fill_limit
= alignment
* 3;
7920 /* Try all fill sizes until finding one that works. */
7921 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7923 if (skip_one
&& fill
== 1)
7925 if ((address
+ fill
) >> align_pow
7926 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7935 branch_align_power (segT sec
)
7937 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7938 is aligned to at least an 8-byte boundary, then a branch target need
7939 only fit within an 8-byte aligned block of memory to avoid a stall.
7940 Otherwise, try to fit branch targets within 4-byte aligned blocks
7941 (which may be insufficient, e.g., if the section has no alignment, but
7942 it's good enough). */
7943 if (xtensa_fetch_width
== 8)
7945 if (get_recorded_alignment (sec
) >= 3)
7949 assert (xtensa_fetch_width
== 4);
7955 /* This will assert if it is not possible. */
7958 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7964 assert (fill_size
% 3 == 0);
7965 return (fill_size
/ 3);
7968 assert (fill_size
!= 1); /* Bad argument. */
7970 while (fill_size
> 1)
7973 if (fill_size
== 2 || fill_size
== 4)
7975 fill_size
-= insn_size
;
7978 assert (fill_size
!= 1); /* Bad algorithm. */
7984 get_text_align_nth_nop_size (offsetT fill_size
,
7986 bfd_boolean use_no_density
)
7993 assert (fill_size
!= 1); /* Bad argument. */
7995 while (fill_size
> 1)
7998 if (fill_size
== 2 || fill_size
== 4)
8000 fill_size
-= insn_size
;
8010 /* For the given fragment, find the appropriate address
8011 for it to begin at if we are using NOPs to align it. */
8014 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8016 /* The rule is: get next fragment's FIRST instruction. Find
8017 the smallest number of bytes that need to be added to
8018 ensure that the next fragment's FIRST instruction will fit
8021 E.G., 2 bytes : 0, 1, 2 mod 4
8024 If the FIRST instruction MIGHT be relaxed,
8025 assume that it will become a 3-byte instruction.
8027 Note again here that LOOP instructions are not bundleable,
8028 and this relaxation only applies to LOOP opcodes. */
8031 int first_insn_size
;
8033 addressT pre_opcode_bytes
;
8036 xtensa_opcode opcode
;
8037 bfd_boolean is_loop
;
8039 assert (fragP
->fr_type
== rs_machine_dependent
);
8040 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8042 /* Find the loop frag. */
8043 first_insn
= next_non_empty_frag (fragP
);
8044 /* Now find the first insn frag. */
8045 first_insn
= next_non_empty_frag (first_insn
);
8047 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8049 loop_insn_size
= xg_get_single_size (opcode
);
8051 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8052 pre_opcode_bytes
+= loop_insn_size
;
8054 /* For loops, the alignment depends on the size of the
8055 instruction following the loop, not the LOOP instruction. */
8057 if (first_insn
== NULL
)
8060 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8062 first_insn_size
= frag_format_size (first_insn
);
8064 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8065 first_insn_size
= 3; /* ISA specifies this */
8067 /* If it was 8, then we'll need a larger alignment for the section. */
8068 align_power
= get_text_align_power (first_insn_size
);
8069 record_alignment (now_seg
, align_power
);
8071 fill_size
= get_text_align_fill_size
8072 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8073 fragP
->tc_frag_data
.is_no_density
);
8075 return address
+ fill_size
;
8079 /* 3 mechanisms for relaxing an alignment:
8081 Align to a power of 2.
8082 Align so the next fragment's instruction does not cross a word boundary.
8083 Align the current instruction so that if the next instruction
8084 were 3 bytes, it would not cross a word boundary.
8088 zeros - This is easy; always insert zeros.
8089 nops - 3-byte and 2-byte instructions
8093 >=5 : 3-byte instruction + fn (n-3)
8094 widening - widen previous instructions. */
8097 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8099 addressT target_address
, loop_insn_offset
;
8101 xtensa_opcode loop_opcode
;
8102 bfd_boolean is_loop
;
8105 offsetT branch_align
;
8107 assert (fragP
->fr_type
== rs_machine_dependent
);
8108 switch (fragP
->fr_subtype
)
8110 case RELAX_DESIRE_ALIGN
:
8111 target_size
= next_frag_format_size (fragP
);
8112 if (target_size
== XTENSA_UNDEFINED
)
8114 align_power
= branch_align_power (now_seg
);
8115 branch_align
= 1 << align_power
;
8116 /* Don't count on the section alignment being as large as the target. */
8117 if (target_size
> branch_align
)
8118 target_size
= branch_align
;
8119 opt_diff
= get_text_align_fill_size (address
, align_power
,
8120 target_size
, FALSE
, FALSE
);
8122 *max_diff
= (opt_diff
+ branch_align
8123 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8124 assert (*max_diff
>= opt_diff
);
8127 case RELAX_ALIGN_NEXT_OPCODE
:
8128 target_size
= next_frag_format_size (fragP
);
8129 loop_insn_offset
= 0;
8130 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8133 /* If the loop has been expanded then the LOOP instruction
8134 could be at an offset from this fragment. */
8135 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8137 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8139 if (target_size
== 2)
8140 target_size
= 3; /* ISA specifies this */
8142 /* In an ideal world, which is what we are shooting for here,
8143 we wouldn't need to use any NOPs immediately prior to the
8144 LOOP instruction. If this approach fails, relax_frag_loop_align
8145 will call get_noop_aligned_address. */
8147 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8148 align_power
= get_text_align_power (target_size
),
8149 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8150 target_size
, FALSE
, FALSE
);
8152 *max_diff
= xtensa_fetch_width
8153 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8154 - target_size
+ opt_diff
;
8155 assert (*max_diff
>= opt_diff
);
8166 /* md_relax_frag Hook and Helper Functions. */
8168 static long relax_frag_loop_align (fragS
*, long);
8169 static long relax_frag_for_align (fragS
*, long);
8170 static long relax_frag_immed
8171 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8174 /* Return the number of bytes added to this fragment, given that the
8175 input has been stretched already by "stretch". */
8178 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8180 xtensa_isa isa
= xtensa_default_isa
;
8181 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8182 long new_stretch
= 0;
8186 static xtensa_insnbuf vbuf
= NULL
;
8187 int slot
, num_slots
;
8190 as_where (&file_name
, &line
);
8191 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8193 fragP
->tc_frag_data
.unreported_expansion
= 0;
8195 switch (fragP
->fr_subtype
)
8197 case RELAX_ALIGN_NEXT_OPCODE
:
8198 /* Always convert. */
8199 if (fragP
->tc_frag_data
.relax_seen
)
8200 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8203 case RELAX_LOOP_END
:
8207 case RELAX_LOOP_END_ADD_NOP
:
8208 /* Add a NOP and switch to .fill 0. */
8209 new_stretch
= relax_frag_add_nop (fragP
);
8213 case RELAX_DESIRE_ALIGN
:
8214 /* Do nothing. The narrowing before this frag will either align
8219 case RELAX_LITERAL_FINAL
:
8222 case RELAX_LITERAL_NR
:
8224 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8225 assert (unreported
== lit_size
);
8226 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8227 fragP
->fr_var
-= lit_size
;
8228 fragP
->fr_fix
+= lit_size
;
8234 vbuf
= xtensa_insnbuf_alloc (isa
);
8236 xtensa_insnbuf_from_chars
8237 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8238 fmt
= xtensa_format_decode (isa
, vbuf
);
8239 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8241 for (slot
= 0; slot
< num_slots
; slot
++)
8243 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8246 if (fragP
->tc_frag_data
.relax_seen
)
8247 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8251 case RELAX_IMMED_STEP1
:
8252 case RELAX_IMMED_STEP2
:
8253 /* Place the immediate. */
8254 new_stretch
+= relax_frag_immed
8255 (now_seg
, fragP
, stretch
,
8256 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8257 fmt
, slot
, stretched_p
, FALSE
);
8261 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8267 case RELAX_LITERAL_POOL_BEGIN
:
8268 case RELAX_LITERAL_POOL_END
:
8269 case RELAX_MAYBE_UNREACHABLE
:
8270 case RELAX_MAYBE_DESIRE_ALIGN
:
8271 /* No relaxation required. */
8274 case RELAX_FILL_NOP
:
8275 case RELAX_UNREACHABLE
:
8276 if (fragP
->tc_frag_data
.relax_seen
)
8277 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8281 as_bad (_("bad relaxation state"));
8284 /* Tell gas we need another relaxation pass. */
8285 if (! fragP
->tc_frag_data
.relax_seen
)
8287 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8291 new_logical_line (file_name
, line
);
8297 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8299 addressT old_address
, old_next_address
, old_size
;
8300 addressT new_address
, new_next_address
, new_size
;
8303 /* All the frags with relax_frag_for_alignment prior to this one in the
8304 section have been done, hopefully eliminating the need for a NOP here.
8305 But, this will put it in if necessary. */
8307 /* Calculate the old address of this fragment and the next fragment. */
8308 old_address
= fragP
->fr_address
- stretch
;
8309 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8310 fragP
->tc_frag_data
.text_expansion
[0]);
8311 old_size
= old_next_address
- old_address
;
8313 /* Calculate the new address of this fragment and the next fragment. */
8314 new_address
= fragP
->fr_address
;
8316 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8317 new_size
= new_next_address
- new_address
;
8319 growth
= new_size
- old_size
;
8321 /* Fix up the text_expansion field and return the new growth. */
8322 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8327 /* Add a NOP instruction. */
8330 relax_frag_add_nop (fragS
*fragP
)
8332 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8333 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8334 assemble_nop (length
, nop_buf
);
8335 fragP
->tc_frag_data
.is_insn
= TRUE
;
8337 if (fragP
->fr_var
< length
)
8339 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8343 fragP
->fr_fix
+= length
;
8344 fragP
->fr_var
-= length
;
8349 static long future_alignment_required (fragS
*, long);
8352 relax_frag_for_align (fragS
*fragP
, long stretch
)
8354 /* Overview of the relaxation procedure for alignment:
8355 We can widen with NOPs or by widening instructions or by filling
8356 bytes after jump instructions. Find the opportune places and widen
8357 them if necessary. */
8362 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8363 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8364 || (fragP
->fr_subtype
== RELAX_SLOTS
8365 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8367 stretch_me
= future_alignment_required (fragP
, stretch
);
8368 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8374 /* We expanded on a previous pass. Can we shrink now? */
8375 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8376 if (shrink
<= stretch
&& stretch
> 0)
8378 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8384 /* Below here, diff > 0. */
8385 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8391 /* Return the address of the next frag that should be aligned.
8393 By "address" we mean the address it _would_ be at if there
8394 is no action taken to align it between here and the target frag.
8395 In other words, if no narrows and no fill nops are used between
8396 here and the frag to align, _even_if_ some of the frags we use
8397 to align targets have already expanded on a previous relaxation
8400 Also, count each frag that may be used to help align the target.
8402 Return 0 if there are no frags left in the chain that need to be
8406 find_address_of_next_align_frag (fragS
**fragPP
,
8410 bfd_boolean
*paddable
)
8412 fragS
*fragP
= *fragPP
;
8413 addressT address
= fragP
->fr_address
;
8415 /* Do not reset the counts to 0. */
8419 /* Limit this to a small search. */
8420 if (*widens
>= (int) xtensa_fetch_width
)
8425 address
+= fragP
->fr_fix
;
8427 if (fragP
->fr_type
== rs_fill
)
8428 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8429 else if (fragP
->fr_type
== rs_machine_dependent
)
8431 switch (fragP
->fr_subtype
)
8433 case RELAX_UNREACHABLE
:
8437 case RELAX_FILL_NOP
:
8439 if (!fragP
->tc_frag_data
.is_no_density
)
8444 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8449 address
+= total_frag_text_expansion (fragP
);;
8453 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8456 case RELAX_ALIGN_NEXT_OPCODE
:
8457 case RELAX_DESIRE_ALIGN
:
8461 case RELAX_MAYBE_UNREACHABLE
:
8462 case RELAX_MAYBE_DESIRE_ALIGN
:
8467 /* Just punt if we don't know the type. */
8474 /* Just punt if we don't know the type. */
8478 fragP
= fragP
->fr_next
;
8486 static long bytes_to_stretch (fragS
*, int, int, int, int);
8489 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8491 fragS
*this_frag
= fragP
;
8495 int narrow_nops
= 0;
8496 bfd_boolean paddable
= FALSE
;
8497 offsetT local_opt_diff
;
8500 int stretch_amount
= 0;
8501 int local_stretch_amount
;
8502 int global_stretch_amount
;
8504 address
= find_address_of_next_align_frag
8505 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8509 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8510 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8512 frag_wane (this_frag
);
8516 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8517 opt_diff
= local_opt_diff
;
8518 assert (opt_diff
>= 0);
8519 assert (max_diff
>= opt_diff
);
8524 fragP
= fragP
->fr_next
;
8526 while (fragP
&& opt_diff
< max_diff
&& address
)
8528 /* We only use these to determine if we can exit early
8529 because there will be plenty of ways to align future
8531 int glob_widens
= 0;
8534 bfd_boolean glob_pad
= 0;
8535 address
= find_address_of_next_align_frag
8536 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8537 /* If there is a padable portion, then skip. */
8538 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8543 offsetT next_m_diff
;
8544 offsetT next_o_diff
;
8546 /* Downrange frags haven't had stretch added to them yet. */
8549 /* The address also includes any text expansion from this
8550 frag in a previous pass, but we don't want that. */
8551 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8553 /* Assume we are going to move at least opt_diff. In
8554 reality, we might not be able to, but assuming that
8555 we will helps catch cases where moving opt_diff pushes
8556 the next target from aligned to unaligned. */
8557 address
+= opt_diff
;
8559 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8561 /* Now cleanup for the adjustments to address. */
8562 next_o_diff
+= opt_diff
;
8563 next_m_diff
+= opt_diff
;
8564 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8565 opt_diff
= next_o_diff
;
8566 if (next_m_diff
< max_diff
)
8567 max_diff
= next_m_diff
;
8568 fragP
= fragP
->fr_next
;
8572 /* If there are enough wideners in between, do it. */
8575 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8577 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8582 local_stretch_amount
8583 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8584 num_widens
, local_opt_diff
);
8585 global_stretch_amount
8586 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8587 num_widens
, opt_diff
);
8588 /* If the condition below is true, then the frag couldn't
8589 stretch the correct amount for the global case, so we just
8590 optimize locally. We'll rely on the subsequent frags to get
8591 the correct alignment in the global case. */
8592 if (global_stretch_amount
< local_stretch_amount
)
8593 stretch_amount
= local_stretch_amount
;
8595 stretch_amount
= global_stretch_amount
;
8597 if (this_frag
->fr_subtype
== RELAX_SLOTS
8598 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8599 assert (stretch_amount
<= 1);
8600 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8602 if (this_frag
->tc_frag_data
.is_no_density
)
8603 assert (stretch_amount
== 3 || stretch_amount
== 0);
8605 assert (stretch_amount
<= 3);
8608 return stretch_amount
;
8612 /* The idea: widen everything you can to get a target or loop aligned,
8613 then start using NOPs.
8615 When we must have a NOP, here is a table of how we decide
8616 (so you don't have to fight through the control flow below):
8618 wide_nops = the number of wide NOPs available for aligning
8619 narrow_nops = the number of narrow NOPs available for aligning
8620 (a subset of wide_nops)
8621 widens = the number of narrow instructions that should be widened
8628 b 0 1 1 (case 3a makes this case unnecessary)
8631 c 0 1 2 (case 4a makes this case unnecessary)
8634 c 0 2 1 (case 5b makes this case unnecessary)
8637 c 0 1 4 (case 6b makes this case unneccesary)
8638 d 1 1 1 (case 6a makes this case unnecessary)
8639 e 0 2 2 (case 6a makes this case unnecessary)
8640 f 0 3 0 (case 6a makes this case unnecessary)
8643 c 1 1 2 (case 7b makes this case unnecessary)
8644 d 0 1 5 (case 7a makes this case unnecessary)
8645 e 0 2 3 (case 7b makes this case unnecessary)
8646 f 0 3 1 (case 7b makes this case unnecessary)
8647 g 1 2 1 (case 7b makes this case unnecessary)
8651 bytes_to_stretch (fragS
*this_frag
,
8657 int bytes_short
= desired_diff
- num_widens
;
8659 assert (desired_diff
>= 0 && desired_diff
< 8);
8660 if (desired_diff
== 0)
8663 assert (wide_nops
> 0 || num_widens
> 0);
8665 /* Always prefer widening to NOP-filling. */
8666 if (bytes_short
< 0)
8668 /* There are enough RELAX_NARROW frags after this one
8669 to align the target without widening this frag in any way. */
8673 if (bytes_short
== 0)
8675 /* Widen every narrow between here and the align target
8676 and the align target will be properly aligned. */
8677 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8683 /* From here we will need at least one NOP to get an alignment.
8684 However, we may not be able to align at all, in which case,
8686 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8688 switch (desired_diff
)
8693 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8694 return 2; /* case 2 */
8700 return 3; /* case 3a */
8702 if (num_widens
>= 1 && wide_nops
== 1)
8703 return 3; /* case 4a */
8704 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8705 return 2; /* case 4b */
8708 if (num_widens
>= 2 && wide_nops
== 1)
8709 return 3; /* case 5a */
8710 /* We will need two nops. Are there enough nops
8711 between here and the align target? */
8712 if (wide_nops
< 2 || narrow_nops
== 0)
8714 /* Are there other nops closer that can serve instead? */
8715 if (wide_nops
> 2 && narrow_nops
> 1)
8717 /* Take the density one first, because there might not be
8718 another density one available. */
8719 if (!this_frag
->tc_frag_data
.is_no_density
)
8720 return 2; /* case 5b narrow */
8722 return 3; /* case 5b wide */
8726 return 3; /* case 6a */
8727 else if (num_widens
>= 3 && wide_nops
== 1)
8728 return 3; /* case 6b */
8731 if (wide_nops
== 1 && num_widens
>= 4)
8732 return 3; /* case 7a */
8733 else if (wide_nops
== 2 && num_widens
>= 1)
8734 return 3; /* case 7b */
8742 /* We will need a NOP no matter what, but should we widen
8743 this instruction to help?
8745 This is a RELAX_FRAG_NARROW frag. */
8746 switch (desired_diff
)
8755 if (wide_nops
>= 1 && num_widens
== 1)
8756 return 1; /* case 4a */
8759 if (wide_nops
>= 1 && num_widens
== 2)
8760 return 1; /* case 5a */
8764 return 0; /* case 6a */
8765 else if (wide_nops
>= 1 && num_widens
== 3)
8766 return 1; /* case 6b */
8769 if (wide_nops
>= 1 && num_widens
== 4)
8770 return 1; /* case 7a */
8771 else if (wide_nops
>= 2 && num_widens
== 1)
8772 return 1; /* case 7b */
8785 relax_frag_immed (segT segP
,
8792 bfd_boolean estimate_only
)
8796 bfd_boolean negatable_branch
= FALSE
;
8797 bfd_boolean branch_jmp_to_next
= FALSE
;
8798 bfd_boolean wide_insn
= FALSE
;
8799 xtensa_isa isa
= xtensa_default_isa
;
8801 offsetT frag_offset
;
8804 int num_text_bytes
, num_literal_bytes
;
8805 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8807 assert (fragP
->fr_opcode
!= NULL
);
8809 xg_clear_vinsn (&cur_vinsn
);
8810 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8811 if (cur_vinsn
.num_slots
> 1)
8814 tinsn
= cur_vinsn
.slots
[slot
];
8815 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8817 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8820 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8821 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8823 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8825 old_size
= xtensa_format_length (isa
, fmt
);
8827 /* Special case: replace a branch to the next instruction with a NOP.
8828 This is required to work around a hardware bug in T1040.0 and also
8829 serves as an optimization. */
8831 if (branch_jmp_to_next
8832 && ((old_size
== 2) || (old_size
== 3))
8833 && !next_frag_is_loop_target (fragP
))
8836 /* Here is the fun stuff: Get the immediate field from this
8837 instruction. If it fits, we are done. If not, find the next
8838 instruction sequence that fits. */
8840 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8841 istack_init (&istack
);
8842 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8843 min_steps
, stretch
);
8844 if (num_steps
< min_steps
)
8846 as_fatal (_("internal error: relaxation failed"));
8850 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8852 as_fatal (_("internal error: relaxation requires too many steps"));
8856 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8858 /* Figure out the number of bytes needed. */
8860 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8862 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8864 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8866 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8869 num_text_bytes
+= old_size
;
8870 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8871 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8873 total_text_diff
= num_text_bytes
- old_size
;
8874 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8876 /* It MUST get larger. If not, we could get an infinite loop. */
8877 assert (num_text_bytes
>= 0);
8878 assert (literal_diff
>= 0);
8879 assert (total_text_diff
>= 0);
8881 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8882 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8883 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8884 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8886 /* Find the associated expandable literal for this. */
8887 if (literal_diff
!= 0)
8889 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8892 assert (literal_diff
== 4);
8893 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8895 /* We expect that the literal section state has NOT been
8897 assert (lit_fragP
->fr_type
== rs_machine_dependent
8898 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8899 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8901 /* We need to mark this section for another iteration
8907 if (negatable_branch
&& istack
.ninsn
> 1)
8908 update_next_frag_state (fragP
);
8910 return this_text_diff
;
8914 /* md_convert_frag Hook and Helper Functions. */
8916 static void convert_frag_align_next_opcode (fragS
*);
8917 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8918 static void convert_frag_fill_nop (fragS
*);
8919 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8922 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8924 static xtensa_insnbuf vbuf
= NULL
;
8925 xtensa_isa isa
= xtensa_default_isa
;
8932 as_where (&file_name
, &line
);
8933 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8935 switch (fragp
->fr_subtype
)
8937 case RELAX_ALIGN_NEXT_OPCODE
:
8938 /* Always convert. */
8939 convert_frag_align_next_opcode (fragp
);
8942 case RELAX_DESIRE_ALIGN
:
8943 /* Do nothing. If not aligned already, too bad. */
8947 case RELAX_LITERAL_FINAL
:
8952 vbuf
= xtensa_insnbuf_alloc (isa
);
8954 xtensa_insnbuf_from_chars
8955 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8956 fmt
= xtensa_format_decode (isa
, vbuf
);
8957 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8959 for (slot
= 0; slot
< num_slots
; slot
++)
8961 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8964 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8968 case RELAX_IMMED_STEP1
:
8969 case RELAX_IMMED_STEP2
:
8970 /* Place the immediate. */
8973 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8978 /* This is OK because some slots could have
8979 relaxations and others have none. */
8985 case RELAX_UNREACHABLE
:
8986 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8987 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8988 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8992 case RELAX_MAYBE_UNREACHABLE
:
8993 case RELAX_MAYBE_DESIRE_ALIGN
:
8997 case RELAX_FILL_NOP
:
8998 convert_frag_fill_nop (fragp
);
9001 case RELAX_LITERAL_NR
:
9002 if (use_literal_section
)
9004 /* This should have been handled during relaxation. When
9005 relaxing a code segment, literals sometimes need to be
9006 added to the corresponding literal segment. If that
9007 literal segment has already been relaxed, then we end up
9008 in this situation. Marking the literal segments as data
9009 would make this happen less often (since GAS always relaxes
9010 code before data), but we could still get into trouble if
9011 there are instructions in a segment that is not marked as
9012 containing code. Until we can implement a better solution,
9013 cheat and adjust the addresses of all the following frags.
9014 This could break subsequent alignments, but the linker's
9015 literal coalescing will do that anyway. */
9018 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9019 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9020 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9023 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9027 as_bad (_("invalid relaxation fragment result"));
9032 new_logical_line (file_name
, line
);
9037 convert_frag_align_next_opcode (fragS
*fragp
)
9039 char *nop_buf
; /* Location for Writing. */
9040 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9041 addressT aligned_address
;
9045 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9047 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9048 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9049 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9051 for (nop
= 0; nop
< nop_count
; nop
++)
9054 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9056 assemble_nop (nop_size
, nop_buf
);
9057 nop_buf
+= nop_size
;
9060 fragp
->fr_fix
+= fill_size
;
9061 fragp
->fr_var
-= fill_size
;
9066 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9068 TInsn tinsn
, single_target
;
9069 int size
, old_size
, diff
;
9070 offsetT frag_offset
;
9073 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9075 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9077 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9078 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9079 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9084 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9086 /* No conversion. */
9091 assert (fragP
->fr_opcode
!= NULL
);
9093 /* Frags in this relaxation state should only contain
9094 single instruction bundles. */
9095 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9097 /* Just convert it to a wide form.... */
9099 old_size
= xg_get_single_size (tinsn
.opcode
);
9101 tinsn_init (&single_target
);
9102 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9104 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9106 as_bad (_("unable to widen instruction"));
9110 size
= xg_get_single_size (single_target
.opcode
);
9111 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9114 diff
= size
- old_size
;
9116 assert (diff
<= fragP
->fr_var
);
9117 fragP
->fr_var
-= diff
;
9118 fragP
->fr_fix
+= diff
;
9126 convert_frag_fill_nop (fragS
*fragP
)
9128 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9129 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9130 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9131 - fragP
->fr_address
- fragP
->fr_fix
));
9134 /* No conversion. */
9138 assemble_nop (size
, loc
);
9139 fragP
->tc_frag_data
.is_insn
= TRUE
;
9140 fragP
->fr_var
-= size
;
9141 fragP
->fr_fix
+= size
;
9146 static fixS
*fix_new_exp_in_seg
9147 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9148 bfd_reloc_code_real_type
);
9149 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9152 convert_frag_immed (segT segP
,
9158 char *immed_instr
= fragP
->fr_opcode
;
9160 bfd_boolean expanded
= FALSE
;
9161 bfd_boolean branch_jmp_to_next
= FALSE
;
9162 char *fr_opcode
= fragP
->fr_opcode
;
9163 xtensa_isa isa
= xtensa_default_isa
;
9164 bfd_boolean wide_insn
= FALSE
;
9166 bfd_boolean is_loop
;
9168 assert (fr_opcode
!= NULL
);
9170 xg_clear_vinsn (&cur_vinsn
);
9172 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9173 if (cur_vinsn
.num_slots
> 1)
9176 orig_tinsn
= cur_vinsn
.slots
[slot
];
9177 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9179 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9181 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9182 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9184 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9186 /* Conversion just inserts a NOP and marks the fix as completed. */
9187 bytes
= xtensa_format_length (isa
, fmt
);
9190 cur_vinsn
.slots
[slot
].opcode
=
9191 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9192 cur_vinsn
.slots
[slot
].ntok
= 0;
9196 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9197 assert (bytes
== 2 || bytes
== 3);
9198 build_nop (&cur_vinsn
.slots
[0], bytes
);
9199 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9201 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, FALSE
);
9202 xtensa_insnbuf_to_chars
9203 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9208 /* Here is the fun stuff: Get the immediate field from this
9209 instruction. If it fits, we're done. If not, find the next
9210 instruction sequence that fits. */
9214 symbolS
*lit_sym
= NULL
;
9216 int target_offset
= 0;
9219 symbolS
*gen_label
= NULL
;
9220 offsetT frag_offset
;
9221 bfd_boolean first
= TRUE
;
9222 bfd_boolean last_is_jump
;
9224 /* It does not fit. Find something that does and
9225 convert immediately. */
9226 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9227 istack_init (&istack
);
9228 xg_assembly_relax (&istack
, &orig_tinsn
,
9229 segP
, fragP
, frag_offset
, min_steps
, 0);
9231 old_size
= xtensa_format_length (isa
, fmt
);
9233 /* Assemble this right inline. */
9235 /* First, create the mapping from a label name to the REAL label. */
9237 for (i
= 0; i
< istack
.ninsn
; i
++)
9239 TInsn
*tinsn
= &istack
.insn
[i
];
9242 switch (tinsn
->insn_type
)
9245 if (lit_sym
!= NULL
)
9246 as_bad (_("multiple literals in expansion"));
9247 /* First find the appropriate space in the literal pool. */
9248 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9249 if (lit_frag
== NULL
)
9250 as_bad (_("no registered fragment for literal"));
9251 if (tinsn
->ntok
!= 1)
9252 as_bad (_("number of literal tokens != 1"));
9254 /* Set the literal symbol and add a fixup. */
9255 lit_sym
= lit_frag
->fr_symbol
;
9259 if (align_targets
&& !is_loop
)
9261 fragS
*unreach
= fragP
->fr_next
;
9262 while (!(unreach
->fr_type
== rs_machine_dependent
9263 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9264 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9266 unreach
= unreach
->fr_next
;
9269 assert (unreach
->fr_type
== rs_machine_dependent
9270 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9271 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9273 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9275 assert (gen_label
== NULL
);
9276 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9277 fr_opcode
- fragP
->fr_literal
9278 + target_offset
, fragP
);
9282 if (first
&& wide_insn
)
9284 target_offset
+= xtensa_format_length (isa
, fmt
);
9286 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9287 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9290 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9297 last_is_jump
= FALSE
;
9298 for (i
= 0; i
< istack
.ninsn
; i
++)
9300 TInsn
*tinsn
= &istack
.insn
[i
];
9304 bfd_reloc_code_real_type reloc_type
;
9306 switch (tinsn
->insn_type
)
9309 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9310 /* Already checked. */
9311 assert (lit_frag
!= NULL
);
9312 assert (lit_sym
!= NULL
);
9313 assert (tinsn
->ntok
== 1);
9315 target_seg
= S_GET_SEGMENT (lit_sym
);
9316 assert (target_seg
);
9317 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9318 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9320 reloc_type
= BFD_RELOC_32
;
9321 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9322 &tinsn
->tok
[0], FALSE
, reloc_type
);
9329 xg_resolve_labels (tinsn
, gen_label
);
9330 xg_resolve_literals (tinsn
, lit_sym
);
9331 if (wide_insn
&& first
)
9334 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9336 tinsn
->record_fix
= TRUE
;
9337 cur_vinsn
.slots
[slot
] = *tinsn
;
9341 cur_vinsn
.slots
[slot
].opcode
=
9342 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9343 cur_vinsn
.slots
[slot
].ntok
= 0;
9344 cur_vinsn
.slots
[slot
].record_fix
= FALSE
;
9346 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9347 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9348 (unsigned char *) immed_instr
, 0);
9349 fragP
->tc_frag_data
.is_insn
= TRUE
;
9350 size
= xtensa_format_length (isa
, fmt
);
9351 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9354 (tinsn
, immed_instr
+ size
, fragP
,
9355 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9356 size
+= xg_get_single_size (tinsn
->opcode
);
9361 size
= xg_get_single_size (tinsn
->opcode
);
9362 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9363 immed_instr
- fragP
->fr_literal
, TRUE
);
9365 immed_instr
+= size
;
9371 diff
= total_size
- old_size
;
9375 assert (diff
<= fragP
->fr_var
);
9376 fragP
->fr_var
-= diff
;
9377 fragP
->fr_fix
+= diff
;
9380 /* Check for undefined immediates in LOOP instructions. */
9384 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9385 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9387 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9390 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9391 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9393 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9398 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9399 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9401 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9403 /* Add an expansion note on the expanded instruction. */
9404 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9405 &orig_tinsn
.tok
[0], TRUE
,
9406 BFD_RELOC_XTENSA_ASM_EXPAND
);
9411 /* Add a new fix expression into the desired segment. We have to
9412 switch to that segment to do this. */
9415 fix_new_exp_in_seg (segT new_seg
,
9422 bfd_reloc_code_real_type r_type
)
9426 subsegT subseg
= now_subseg
;
9428 assert (new_seg
!= 0);
9429 subseg_set (new_seg
, new_subseg
);
9431 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9432 subseg_set (seg
, subseg
);
9437 /* Relax a loop instruction so that it can span loop >256 bytes.
9443 addi as, as, lo8 (label-.L1)
9444 addmi as, as, mid8 (label-.L1)
9455 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9460 unsigned long target
;
9461 static xtensa_insnbuf insnbuf
= NULL
;
9462 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9463 xtensa_isa isa
= xtensa_default_isa
;
9464 addressT loop_offset
;
9465 addressT addi_offset
= 9;
9466 addressT addmi_offset
= 12;
9471 insnbuf
= xtensa_insnbuf_alloc (isa
);
9473 /* Get the loop offset. */
9474 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9476 /* Validate that there really is a LOOP at the loop_offset. Because
9477 loops are not bundleable, we can assume that the instruction will be
9479 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9480 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9482 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9483 addi_offset
+= loop_offset
;
9484 addmi_offset
+= loop_offset
;
9486 assert (tinsn
->ntok
== 2);
9487 if (tinsn
->tok
[1].X_op
== O_constant
)
9488 target
= tinsn
->tok
[1].X_add_number
;
9489 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9491 /* Find the fragment. */
9492 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9493 assert (S_GET_SEGMENT (sym
) == segP
9494 || S_GET_SEGMENT (sym
) == absolute_section
);
9495 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9499 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9504 know (symbolP
->sy_frag
);
9505 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9506 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9508 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9509 loop_length_hi
= loop_length
& ~0x0ff;
9510 loop_length_lo
= loop_length
& 0x0ff;
9511 if (loop_length_lo
>= 128)
9513 loop_length_lo
-= 256;
9514 loop_length_hi
+= 256;
9517 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9518 32512. If the loop is larger than that, then we just fail. */
9519 if (loop_length_hi
> 32512)
9520 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9521 _("loop too long for LOOP instruction"));
9523 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9524 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9526 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9527 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9529 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9530 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9532 fragP
->tc_frag_data
.is_insn
= TRUE
;
9533 xtensa_insnbuf_to_chars
9534 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9536 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9537 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9538 xtensa_insnbuf_to_chars
9539 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9541 /* Walk through all of the frags from here to the loop end
9542 and mark them as no_transform to keep them from being modified
9543 by the linker. If we ever have a relocation for the
9544 addi/addmi of the difference of two symbols we can remove this. */
9547 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9548 next_fragP
= next_fragP
->fr_next
)
9550 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9551 if (next_fragP
->tc_frag_data
.is_loop_target
)
9553 if (target_count
== 2)
9559 /* A map that keeps information on a per-subsegment basis. This is
9560 maintained during initial assembly, but is invalid once the
9561 subsegments are smashed together. I.E., it cannot be used during
9564 typedef struct subseg_map_struct
9572 float total_freq
; /* fall-through + branch target frequency */
9573 float target_freq
; /* branch target frequency alone */
9575 struct subseg_map_struct
*next
;
9579 static subseg_map
*sseg_map
= NULL
;
9582 get_subseg_info (segT seg
, subsegT subseg
)
9584 subseg_map
*subseg_e
;
9586 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9588 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9596 add_subseg_info (segT seg
, subsegT subseg
)
9598 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9599 memset (subseg_e
, 0, sizeof (subseg_map
));
9600 subseg_e
->seg
= seg
;
9601 subseg_e
->subseg
= subseg
;
9602 subseg_e
->flags
= 0;
9603 /* Start off considering every branch target very important. */
9604 subseg_e
->target_freq
= 1.0;
9605 subseg_e
->total_freq
= 1.0;
9606 subseg_e
->next
= sseg_map
;
9607 sseg_map
= subseg_e
;
9613 get_last_insn_flags (segT seg
, subsegT subseg
)
9615 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9617 return subseg_e
->flags
;
9623 set_last_insn_flags (segT seg
,
9628 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9630 subseg_e
= add_subseg_info (seg
, subseg
);
9632 subseg_e
->flags
|= fl
;
9634 subseg_e
->flags
&= ~fl
;
9639 get_subseg_total_freq (segT seg
, subsegT subseg
)
9641 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9643 return subseg_e
->total_freq
;
9649 get_subseg_target_freq (segT seg
, subsegT subseg
)
9651 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9653 return subseg_e
->target_freq
;
9659 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9661 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9663 subseg_e
= add_subseg_info (seg
, subseg
);
9664 subseg_e
->total_freq
= total_f
;
9665 subseg_e
->target_freq
= target_f
;
9669 /* Segment Lists and emit_state Stuff. */
9672 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9677 segT literal_section
= head
->seg
;
9679 /* Move the literal section to the front of the section list. */
9680 assert (literal_section
);
9681 if (literal_section
!= stdoutput
->sections
)
9683 bfd_section_list_remove (stdoutput
, literal_section
);
9684 bfd_section_list_prepend (stdoutput
, literal_section
);
9691 static void mark_literal_frags (seg_list
*);
9694 xtensa_move_literals (void)
9697 frchainS
*frchain_from
, *frchain_to
;
9698 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9699 fragS
**frag_splice
;
9702 fixS
*fix
, *next_fix
, **fix_splice
;
9705 mark_literal_frags (literal_head
->next
);
9706 mark_literal_frags (init_literal_head
->next
);
9707 mark_literal_frags (fini_literal_head
->next
);
9709 if (use_literal_section
)
9712 segment
= literal_head
->next
;
9715 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9716 search_frag
= frchain_from
->frch_root
;
9717 literal_pool
= NULL
;
9719 frag_splice
= &(frchain_from
->frch_root
);
9721 while (!search_frag
->tc_frag_data
.literal_frag
)
9723 assert (search_frag
->fr_fix
== 0
9724 || search_frag
->fr_type
== rs_align
);
9725 search_frag
= search_frag
->fr_next
;
9728 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9729 == RELAX_LITERAL_POOL_BEGIN
);
9730 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9732 /* Make sure that all the frags in this series are closed, and
9733 that there is at least one left over of zero-size. This
9734 prevents us from making a segment with an frchain without any
9736 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9737 xtensa_set_frag_assembly_state (frag_now
);
9738 last_frag
= frag_now
;
9739 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9740 xtensa_set_frag_assembly_state (frag_now
);
9742 while (search_frag
!= frag_now
)
9744 next_frag
= search_frag
->fr_next
;
9746 /* First, move the frag out of the literal section and
9747 to the appropriate place. */
9748 if (search_frag
->tc_frag_data
.literal_frag
)
9750 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9751 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9752 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9753 assert (frchain_to
);
9755 insert_after
= literal_pool
;
9757 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9758 insert_after
= insert_after
->fr_next
;
9760 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9762 *frag_splice
= next_frag
;
9763 search_frag
->fr_next
= insert_after
->fr_next
;
9764 insert_after
->fr_next
= search_frag
;
9765 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9767 /* Now move any fixups associated with this frag to the
9769 fix
= frchain_from
->fix_root
;
9770 fix_splice
= &(frchain_from
->fix_root
);
9773 next_fix
= fix
->fx_next
;
9774 if (fix
->fx_frag
== search_frag
)
9776 *fix_splice
= next_fix
;
9777 fix
->fx_next
= frchain_to
->fix_root
;
9778 frchain_to
->fix_root
= fix
;
9779 if (frchain_to
->fix_tail
== NULL
)
9780 frchain_to
->fix_tail
= fix
;
9783 fix_splice
= &(fix
->fx_next
);
9786 search_frag
= next_frag
;
9789 if (frchain_from
->fix_root
!= NULL
)
9791 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9792 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9794 assert (frchain_from
->fix_root
== NULL
);
9796 frchain_from
->fix_tail
= NULL
;
9797 xtensa_restore_emit_state (&state
);
9798 segment
= segment
->next
;
9801 /* Now fix up the SEGMENT value for all the literal symbols. */
9802 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9804 symbolS
*lit_sym
= lit
->sym
;
9805 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9807 S_SET_SEGMENT (lit_sym
, dest_seg
);
9812 /* Walk over all the frags for segments in a list and mark them as
9813 containing literals. As clunky as this is, we can't rely on frag_var
9814 and frag_variant to get called in all situations. */
9817 mark_literal_frags (seg_list
*segment
)
9819 frchainS
*frchain_from
;
9824 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9825 search_frag
= frchain_from
->frch_root
;
9828 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9829 search_frag
= search_frag
->fr_next
;
9831 segment
= segment
->next
;
9837 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9839 /* Move all of the sections in the section list to come
9840 after "after" in the gnu segment list. */
9845 segT literal_section
= head
->seg
;
9847 /* Move the literal section after "after". */
9848 assert (literal_section
);
9849 if (literal_section
!= after
)
9851 bfd_section_list_remove (stdoutput
, literal_section
);
9852 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9860 /* Push all the literal segments to the end of the gnu list. */
9863 xtensa_reorder_segments (void)
9870 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9876 /* Now that we have the last section, push all the literal
9877 sections to the end. */
9878 xtensa_reorder_seg_list (literal_head
, last_sec
);
9879 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9880 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9882 /* Now perform the final error check. */
9883 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9885 assert (new_count
== old_count
);
9889 /* Change the emit state (seg, subseg, and frag related stuff) to the
9890 correct location. Return a emit_state which can be passed to
9891 xtensa_restore_emit_state to return to current fragment. */
9894 xtensa_switch_to_literal_fragment (emit_state
*result
)
9896 if (directive_state
[directive_absolute_literals
])
9898 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9899 &default_lit_sections
.lit4_seg
, FALSE
);
9900 xtensa_switch_section_emit_state (result
,
9901 default_lit_sections
.lit4_seg
, 0);
9904 xtensa_switch_to_non_abs_literal_fragment (result
);
9906 /* Do a 4-byte align here. */
9907 frag_align (2, 0, 0);
9908 record_alignment (now_seg
, 2);
9913 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9915 /* When we mark a literal pool location, we want to put a frag in
9916 the literal pool that points to it. But to do that, we want to
9917 switch_to_literal_fragment. But literal sections don't have
9918 literal pools, so their location is always null, so we would
9919 recurse forever. This is kind of hacky, but it works. */
9921 static bfd_boolean recursive
= FALSE
;
9922 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9923 bfd_boolean is_init
=
9924 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9926 bfd_boolean is_fini
=
9927 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9929 if (pool_location
== NULL
9930 && !use_literal_section
9932 && !is_init
&& ! is_fini
)
9934 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9936 xtensa_mark_literal_pool_location ();
9940 /* Special case: If we are in the ".fini" or ".init" section, then
9941 we will ALWAYS be generating to the ".fini.literal" and
9942 ".init.literal" sections. */
9946 cache_literal_section (init_literal_head
,
9947 default_lit_sections
.init_lit_seg_name
,
9948 &default_lit_sections
.init_lit_seg
, TRUE
);
9949 xtensa_switch_section_emit_state (result
,
9950 default_lit_sections
.init_lit_seg
, 0);
9954 cache_literal_section (fini_literal_head
,
9955 default_lit_sections
.fini_lit_seg_name
,
9956 &default_lit_sections
.fini_lit_seg
, TRUE
);
9957 xtensa_switch_section_emit_state (result
,
9958 default_lit_sections
.fini_lit_seg
, 0);
9962 cache_literal_section (literal_head
,
9963 default_lit_sections
.lit_seg_name
,
9964 &default_lit_sections
.lit_seg
, TRUE
);
9965 xtensa_switch_section_emit_state (result
,
9966 default_lit_sections
.lit_seg
, 0);
9969 if (!use_literal_section
9970 && !is_init
&& !is_fini
9971 && get_literal_pool_location (now_seg
) != pool_location
)
9973 /* Close whatever frag is there. */
9974 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9975 xtensa_set_frag_assembly_state (frag_now
);
9976 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9977 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9978 xtensa_set_frag_assembly_state (frag_now
);
9983 /* Call this function before emitting data into the literal section.
9984 This is a helper function for xtensa_switch_to_literal_fragment.
9985 This is similar to a .section new_now_seg subseg. */
9988 xtensa_switch_section_emit_state (emit_state
*state
,
9990 subsegT new_now_subseg
)
9992 state
->name
= now_seg
->name
;
9993 state
->now_seg
= now_seg
;
9994 state
->now_subseg
= now_subseg
;
9995 state
->generating_literals
= generating_literals
;
9996 generating_literals
++;
9997 subseg_set (new_now_seg
, new_now_subseg
);
10001 /* Use to restore the emitting into the normal place. */
10004 xtensa_restore_emit_state (emit_state
*state
)
10006 generating_literals
= state
->generating_literals
;
10007 subseg_set (state
->now_seg
, state
->now_subseg
);
10011 /* Get a segment of a given name. If the segment is already
10012 present, return it; otherwise, create a new one. */
10015 cache_literal_section (seg_list
*head
,
10018 bfd_boolean is_code
)
10020 segT current_section
= now_seg
;
10021 int current_subsec
= now_subseg
;
10027 /* Check if the named section exists. */
10028 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10030 if (!strcmp (segment_name (seg
), name
))
10036 /* Create a new literal section. */
10037 seg
= subseg_new (name
, (subsegT
) 0);
10040 /* Add the newly created literal segment to the specified list. */
10041 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10043 n
->next
= head
->next
;
10046 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10047 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10048 | (is_code
? SEC_CODE
: SEC_DATA
));
10049 bfd_set_section_alignment (stdoutput
, seg
, 2);
10053 subseg_set (current_section
, current_subsec
);
10057 /* Property Tables Stuff. */
10059 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10060 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10061 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10063 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10064 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10066 static bfd_boolean
get_frag_is_literal (const fragS
*);
10067 static void xtensa_create_property_segments
10068 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10069 static void xtensa_create_xproperty_segments
10070 (frag_flags_fn
, const char *, xt_section_type
);
10071 static segment_info_type
*retrieve_segment_info (segT
);
10072 static segT
retrieve_xtensa_section (char *);
10073 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10074 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10075 static void add_xt_block_frags
10076 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10077 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10078 static void xtensa_frag_flags_init (frag_flags
*);
10079 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10080 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10081 static void add_xt_prop_frags
10082 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10084 /* Set up property tables after relaxation. */
10087 xtensa_post_relax_hook (void)
10089 xtensa_move_seg_list_to_beginning (literal_head
);
10090 xtensa_move_seg_list_to_beginning (init_literal_head
);
10091 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10093 xtensa_find_unmarked_state_frags ();
10095 if (use_literal_section
)
10096 xtensa_create_property_segments (get_frag_is_literal
,
10098 XTENSA_LIT_SEC_NAME
,
10100 xtensa_create_xproperty_segments (get_frag_property_flags
,
10101 XTENSA_PROP_SEC_NAME
,
10104 if (warn_unaligned_branch_targets
)
10105 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10106 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10110 /* This function is only meaningful after xtensa_move_literals. */
10113 get_frag_is_literal (const fragS
*fragP
)
10115 assert (fragP
!= NULL
);
10116 return fragP
->tc_frag_data
.is_literal
;
10121 xtensa_create_property_segments (frag_predicate property_function
,
10122 frag_predicate end_property_function
,
10123 const char *section_name_base
,
10124 xt_section_type sec_type
)
10128 /* Walk over all of the current segments.
10129 Walk over each fragment
10130 For each non-empty fragment,
10131 Build a property record (append where possible). */
10133 for (seclist
= &stdoutput
->sections
;
10134 seclist
&& *seclist
;
10135 seclist
= &(*seclist
)->next
)
10137 segT sec
= *seclist
;
10140 flags
= bfd_get_section_flags (stdoutput
, sec
);
10141 if (flags
& SEC_DEBUGGING
)
10143 if (!(flags
& SEC_ALLOC
))
10146 if (section_has_property (sec
, property_function
))
10148 char *property_section_name
=
10149 xtensa_get_property_section_name (sec
, section_name_base
);
10150 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10151 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10152 xtensa_block_info
**xt_blocks
=
10153 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10154 /* Walk over all of the frchains here and add new sections. */
10155 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10156 end_property_function
);
10160 /* Now we fill them out.... */
10162 for (seclist
= &stdoutput
->sections
;
10163 seclist
&& *seclist
;
10164 seclist
= &(*seclist
)->next
)
10166 segment_info_type
*seginfo
;
10167 xtensa_block_info
*block
;
10168 segT sec
= *seclist
;
10170 seginfo
= seg_info (sec
);
10171 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10175 xtensa_block_info
*cur_block
;
10176 /* This is a section with some data. */
10178 bfd_size_type rec_size
;
10180 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10183 rec_size
= num_recs
* 8;
10184 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10186 /* In order to make this work with the assembler, we have to
10187 build some frags and then build the "fixups" for it. It
10188 would be easier to just set the contents then set the
10193 /* Allocate a fragment and leak it. */
10195 bfd_size_type frag_size
;
10197 frchainS
*frchainP
;
10201 frag_size
= sizeof (fragS
) + rec_size
;
10202 fragP
= (fragS
*) xmalloc (frag_size
);
10204 memset (fragP
, 0, frag_size
);
10205 fragP
->fr_address
= 0;
10206 fragP
->fr_next
= NULL
;
10207 fragP
->fr_fix
= rec_size
;
10209 fragP
->fr_type
= rs_fill
;
10210 /* The rest are zeros. */
10212 frchainP
= seginfo
->frchainP
;
10213 frchainP
->frch_root
= fragP
;
10214 frchainP
->frch_last
= fragP
;
10216 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10217 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10219 seginfo
->fix_root
= fixes
;
10220 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10222 frag_data
= &fragP
->fr_literal
[0];
10223 for (i
= 0; i
< num_recs
; i
++)
10225 fixS
*fix
= &fixes
[i
];
10226 assert (cur_block
);
10228 /* Write the fixup. */
10229 if (i
!= num_recs
- 1)
10230 fix
->fx_next
= &fixes
[i
+ 1];
10232 fix
->fx_next
= NULL
;
10235 fix
->fx_frag
= fragP
;
10236 fix
->fx_where
= i
* 8;
10237 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10238 fix
->fx_offset
= cur_block
->offset
;
10239 fix
->fx_r_type
= BFD_RELOC_32
;
10240 fix
->fx_file
= "Internal Assembly";
10243 /* Write the length. */
10244 md_number_to_chars (&frag_data
[4 + 8 * i
],
10245 cur_block
->size
, 4);
10246 cur_block
= cur_block
->next
;
10255 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10256 const char *section_name_base
,
10257 xt_section_type sec_type
)
10261 /* Walk over all of the current segments.
10262 Walk over each fragment.
10263 For each fragment that has instructions,
10264 build an instruction record (append where possible). */
10266 for (seclist
= &stdoutput
->sections
;
10267 seclist
&& *seclist
;
10268 seclist
= &(*seclist
)->next
)
10270 segT sec
= *seclist
;
10273 flags
= bfd_get_section_flags (stdoutput
, sec
);
10274 if ((flags
& SEC_DEBUGGING
)
10275 || !(flags
& SEC_ALLOC
)
10276 || (flags
& SEC_MERGE
))
10279 if (section_has_xproperty (sec
, flag_fn
))
10281 char *property_section_name
=
10282 xtensa_get_property_section_name (sec
, section_name_base
);
10283 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10284 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10285 xtensa_block_info
**xt_blocks
=
10286 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10287 /* Walk over all of the frchains here and add new sections. */
10288 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10292 /* Now we fill them out.... */
10294 for (seclist
= &stdoutput
->sections
;
10295 seclist
&& *seclist
;
10296 seclist
= &(*seclist
)->next
)
10298 segment_info_type
*seginfo
;
10299 xtensa_block_info
*block
;
10300 segT sec
= *seclist
;
10302 seginfo
= seg_info (sec
);
10303 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10307 xtensa_block_info
*cur_block
;
10308 /* This is a section with some data. */
10310 bfd_size_type rec_size
;
10312 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10315 rec_size
= num_recs
* (8 + 4);
10316 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10318 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10320 /* In order to make this work with the assembler, we have to build
10321 some frags then build the "fixups" for it. It would be easier to
10322 just set the contents then set the arlents. */
10326 /* Allocate a fragment and (unfortunately) leak it. */
10328 bfd_size_type frag_size
;
10330 frchainS
*frchainP
;
10334 frag_size
= sizeof (fragS
) + rec_size
;
10335 fragP
= (fragS
*) xmalloc (frag_size
);
10337 memset (fragP
, 0, frag_size
);
10338 fragP
->fr_address
= 0;
10339 fragP
->fr_next
= NULL
;
10340 fragP
->fr_fix
= rec_size
;
10342 fragP
->fr_type
= rs_fill
;
10343 /* The rest are zeros. */
10345 frchainP
= seginfo
->frchainP
;
10346 frchainP
->frch_root
= fragP
;
10347 frchainP
->frch_last
= fragP
;
10349 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10350 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10352 seginfo
->fix_root
= fixes
;
10353 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10355 frag_data
= &fragP
->fr_literal
[0];
10356 for (i
= 0; i
< num_recs
; i
++)
10358 fixS
*fix
= &fixes
[i
];
10359 assert (cur_block
);
10361 /* Write the fixup. */
10362 if (i
!= num_recs
- 1)
10363 fix
->fx_next
= &fixes
[i
+ 1];
10365 fix
->fx_next
= NULL
;
10368 fix
->fx_frag
= fragP
;
10369 fix
->fx_where
= i
* (8 + 4);
10370 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10371 fix
->fx_offset
= cur_block
->offset
;
10372 fix
->fx_r_type
= BFD_RELOC_32
;
10373 fix
->fx_file
= "Internal Assembly";
10376 /* Write the length. */
10377 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10378 cur_block
->size
, 4);
10379 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10380 frag_flags_to_number (&cur_block
->flags
),
10382 cur_block
= cur_block
->next
;
10390 static segment_info_type
*
10391 retrieve_segment_info (segT seg
)
10393 segment_info_type
*seginfo
;
10394 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10397 frchainS
*frchainP
;
10399 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10400 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10401 seginfo
->fix_root
= NULL
;
10402 seginfo
->fix_tail
= NULL
;
10403 seginfo
->bfd_section
= seg
;
10405 /* We will not be dealing with these, only our special ones. */
10406 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10408 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10409 frchainP
->frch_root
= NULL
;
10410 frchainP
->frch_last
= NULL
;
10411 frchainP
->frch_next
= NULL
;
10412 frchainP
->frch_seg
= seg
;
10413 frchainP
->frch_subseg
= 0;
10414 frchainP
->fix_root
= NULL
;
10415 frchainP
->fix_tail
= NULL
;
10416 /* Do not init the objstack. */
10417 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10418 /* frchainP->frch_frag_now = fragP; */
10419 frchainP
->frch_frag_now
= NULL
;
10421 seginfo
->frchainP
= frchainP
;
10429 retrieve_xtensa_section (char *sec_name
)
10431 bfd
*abfd
= stdoutput
;
10432 flagword flags
, out_flags
, link_once_flags
;
10435 flags
= bfd_get_section_flags (abfd
, now_seg
);
10436 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10437 if (link_once_flags
)
10438 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10439 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10441 s
= bfd_make_section_old_way (abfd
, sec_name
);
10443 as_bad (_("could not create section %s"), sec_name
);
10444 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10445 as_bad (_("invalid flag combination on section %s"), sec_name
);
10452 section_has_property (segT sec
, frag_predicate property_function
)
10454 segment_info_type
*seginfo
= seg_info (sec
);
10457 if (seginfo
&& seginfo
->frchainP
)
10459 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10461 if (property_function (fragP
)
10462 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10471 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10473 segment_info_type
*seginfo
= seg_info (sec
);
10476 if (seginfo
&& seginfo
->frchainP
)
10478 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10480 frag_flags prop_flags
;
10481 property_function (fragP
, &prop_flags
);
10482 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10490 /* Two types of block sections exist right now: literal and insns. */
10493 add_xt_block_frags (segT sec
,
10495 xtensa_block_info
**xt_block
,
10496 frag_predicate property_function
,
10497 frag_predicate end_property_function
)
10499 segment_info_type
*seg_info
;
10500 segment_info_type
*xt_seg_info
;
10501 bfd_vma seg_offset
;
10504 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10505 seg_info
= retrieve_segment_info (sec
);
10507 /* Build it if needed. */
10508 while (*xt_block
!= NULL
)
10509 xt_block
= &(*xt_block
)->next
;
10510 /* We are either at NULL at the beginning or at the end. */
10512 /* Walk through the frags. */
10515 if (seg_info
->frchainP
)
10517 for (fragP
= seg_info
->frchainP
->frch_root
;
10519 fragP
= fragP
->fr_next
)
10521 if (property_function (fragP
)
10522 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10524 if (*xt_block
!= NULL
)
10526 if ((*xt_block
)->offset
+ (*xt_block
)->size
10527 == fragP
->fr_address
)
10528 (*xt_block
)->size
+= fragP
->fr_fix
;
10530 xt_block
= &((*xt_block
)->next
);
10532 if (*xt_block
== NULL
)
10534 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10535 xmalloc (sizeof (xtensa_block_info
));
10536 new_block
->sec
= sec
;
10537 new_block
->offset
= fragP
->fr_address
;
10538 new_block
->size
= fragP
->fr_fix
;
10539 new_block
->next
= NULL
;
10540 xtensa_frag_flags_init (&new_block
->flags
);
10541 *xt_block
= new_block
;
10543 if (end_property_function
10544 && end_property_function (fragP
))
10546 xt_block
= &((*xt_block
)->next
);
10554 /* Break the encapsulation of add_xt_prop_frags here. */
10557 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10559 if (prop_flags
->is_literal
10560 || prop_flags
->is_insn
10561 || prop_flags
->is_data
10562 || prop_flags
->is_unreachable
)
10569 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10571 memset (prop_flags
, 0, sizeof (frag_flags
));
10576 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10578 xtensa_frag_flags_init (prop_flags
);
10579 if (fragP
->tc_frag_data
.is_literal
)
10580 prop_flags
->is_literal
= TRUE
;
10581 if (fragP
->tc_frag_data
.is_unreachable
)
10582 prop_flags
->is_unreachable
= TRUE
;
10583 else if (fragP
->tc_frag_data
.is_insn
)
10585 prop_flags
->is_insn
= TRUE
;
10586 if (fragP
->tc_frag_data
.is_loop_target
)
10587 prop_flags
->insn
.is_loop_target
= TRUE
;
10588 if (fragP
->tc_frag_data
.is_branch_target
)
10589 prop_flags
->insn
.is_branch_target
= TRUE
;
10590 if (fragP
->tc_frag_data
.is_specific_opcode
10591 || fragP
->tc_frag_data
.is_no_transform
)
10592 prop_flags
->insn
.is_no_transform
= TRUE
;
10593 if (fragP
->tc_frag_data
.is_no_density
)
10594 prop_flags
->insn
.is_no_density
= TRUE
;
10595 if (fragP
->tc_frag_data
.use_absolute_literals
)
10596 prop_flags
->insn
.is_abslit
= TRUE
;
10598 if (fragP
->tc_frag_data
.is_align
)
10600 prop_flags
->is_align
= TRUE
;
10601 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10602 if (xtensa_frag_flags_is_empty (prop_flags
))
10603 prop_flags
->is_data
= TRUE
;
10609 frag_flags_to_number (const frag_flags
*prop_flags
)
10612 if (prop_flags
->is_literal
)
10613 num
|= XTENSA_PROP_LITERAL
;
10614 if (prop_flags
->is_insn
)
10615 num
|= XTENSA_PROP_INSN
;
10616 if (prop_flags
->is_data
)
10617 num
|= XTENSA_PROP_DATA
;
10618 if (prop_flags
->is_unreachable
)
10619 num
|= XTENSA_PROP_UNREACHABLE
;
10620 if (prop_flags
->insn
.is_loop_target
)
10621 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10622 if (prop_flags
->insn
.is_branch_target
)
10624 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10625 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10628 if (prop_flags
->insn
.is_no_density
)
10629 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10630 if (prop_flags
->insn
.is_no_transform
)
10631 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10632 if (prop_flags
->insn
.is_no_reorder
)
10633 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10634 if (prop_flags
->insn
.is_abslit
)
10635 num
|= XTENSA_PROP_INSN_ABSLIT
;
10637 if (prop_flags
->is_align
)
10639 num
|= XTENSA_PROP_ALIGN
;
10640 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10648 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10649 const frag_flags
*prop_flags_2
)
10651 /* Cannot combine with an end marker. */
10653 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10655 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10657 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10660 if (prop_flags_1
->is_insn
)
10662 /* Properties of the beginning of the frag. */
10663 if (prop_flags_2
->insn
.is_loop_target
)
10665 if (prop_flags_2
->insn
.is_branch_target
)
10667 if (prop_flags_1
->insn
.is_no_density
!=
10668 prop_flags_2
->insn
.is_no_density
)
10670 if (prop_flags_1
->insn
.is_no_transform
!=
10671 prop_flags_2
->insn
.is_no_transform
)
10673 if (prop_flags_1
->insn
.is_no_reorder
!=
10674 prop_flags_2
->insn
.is_no_reorder
)
10676 if (prop_flags_1
->insn
.is_abslit
!=
10677 prop_flags_2
->insn
.is_abslit
)
10681 if (prop_flags_1
->is_align
)
10689 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10692 unsigned align_bits
;
10694 if (!xt_block
->flags
.is_align
)
10695 return xt_block
->size
;
10697 end_addr
= xt_block
->offset
+ xt_block
->size
;
10698 align_bits
= xt_block
->flags
.alignment
;
10699 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10700 return end_addr
- xt_block
->offset
;
10705 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10706 const xtensa_block_info
*xt_block_2
)
10708 if (xt_block
->sec
!= xt_block_2
->sec
)
10710 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10711 != xt_block_2
->offset
)
10714 if (xt_block_2
->size
== 0
10715 && (!xt_block_2
->flags
.is_unreachable
10716 || xt_block
->flags
.is_unreachable
))
10718 if (xt_block_2
->flags
.is_align
10719 && xt_block
->flags
.is_align
)
10721 /* Nothing needed. */
10722 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10727 if (xt_block_2
->flags
.is_align
)
10729 /* Push alignment to previous entry. */
10730 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10731 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10736 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10737 &xt_block_2
->flags
))
10740 xt_block
->size
+= xt_block_2
->size
;
10742 if (xt_block_2
->flags
.is_align
)
10744 xt_block
->flags
.is_align
= TRUE
;
10745 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10753 add_xt_prop_frags (segT sec
,
10755 xtensa_block_info
**xt_block
,
10756 frag_flags_fn property_function
)
10758 segment_info_type
*seg_info
;
10759 segment_info_type
*xt_seg_info
;
10760 bfd_vma seg_offset
;
10763 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10764 seg_info
= retrieve_segment_info (sec
);
10765 /* Build it if needed. */
10766 while (*xt_block
!= NULL
)
10768 xt_block
= &(*xt_block
)->next
;
10770 /* We are either at NULL at the beginning or at the end. */
10772 /* Walk through the frags. */
10775 if (seg_info
->frchainP
)
10777 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10778 fragP
= fragP
->fr_next
)
10780 xtensa_block_info tmp_block
;
10781 tmp_block
.sec
= sec
;
10782 tmp_block
.offset
= fragP
->fr_address
;
10783 tmp_block
.size
= fragP
->fr_fix
;
10784 tmp_block
.next
= NULL
;
10785 property_function (fragP
, &tmp_block
.flags
);
10787 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10788 /* && fragP->fr_fix != 0) */
10790 if ((*xt_block
) == NULL
10791 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10793 xtensa_block_info
*new_block
;
10794 if ((*xt_block
) != NULL
)
10795 xt_block
= &(*xt_block
)->next
;
10796 new_block
= (xtensa_block_info
*)
10797 xmalloc (sizeof (xtensa_block_info
));
10798 *new_block
= tmp_block
;
10799 *xt_block
= new_block
;
10807 /* op_placement_info_table */
10809 /* op_placement_info makes it easier to determine which
10810 ops can go in which slots. */
10813 init_op_placement_info_table (void)
10815 xtensa_isa isa
= xtensa_default_isa
;
10816 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10817 xtensa_opcode opcode
;
10820 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10822 op_placement_table
= (op_placement_info_table
)
10823 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10824 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10826 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10828 op_placement_info
*opi
= &op_placement_table
[opcode
];
10829 /* FIXME: Make tinsn allocation dynamic. */
10830 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10831 as_fatal (_("too many operands in instruction"));
10832 opi
->narrowest
= XTENSA_UNDEFINED
;
10833 opi
->narrowest_size
= 0x7F;
10834 opi
->narrowest_slot
= 0;
10836 opi
->num_formats
= 0;
10838 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10840 opi
->slots
[fmt
] = 0;
10841 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10843 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10845 int fmt_length
= xtensa_format_length (isa
, fmt
);
10847 set_bit (fmt
, opi
->formats
);
10848 set_bit (slot
, opi
->slots
[fmt
]);
10849 /* opi->slot_count[fmt]++; */
10850 if (fmt_length
< opi
->narrowest_size
)
10852 opi
->narrowest
= fmt
;
10853 opi
->narrowest_size
= fmt_length
;
10854 opi
->narrowest_slot
= slot
;
10859 opi
->num_formats
++;
10862 xtensa_insnbuf_free (isa
, ibuf
);
10867 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10869 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10873 /* If the opcode is available in a single slot format, return its size. */
10876 xg_get_single_size (xtensa_opcode opcode
)
10878 return op_placement_table
[opcode
].narrowest_size
;
10882 static xtensa_format
10883 xg_get_single_format (xtensa_opcode opcode
)
10885 return op_placement_table
[opcode
].narrowest
;
10890 xg_get_single_slot (xtensa_opcode opcode
)
10892 return op_placement_table
[opcode
].narrowest_slot
;
10896 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10899 istack_init (IStack
*stack
)
10901 memset (stack
, 0, sizeof (IStack
));
10907 istack_empty (IStack
*stack
)
10909 return (stack
->ninsn
== 0);
10914 istack_full (IStack
*stack
)
10916 return (stack
->ninsn
== MAX_ISTACK
);
10920 /* Return a pointer to the top IStack entry.
10921 It is an error to call this if istack_empty () is TRUE. */
10924 istack_top (IStack
*stack
)
10926 int rec
= stack
->ninsn
- 1;
10927 assert (!istack_empty (stack
));
10928 return &stack
->insn
[rec
];
10932 /* Add a new TInsn to an IStack.
10933 It is an error to call this if istack_full () is TRUE. */
10936 istack_push (IStack
*stack
, TInsn
*insn
)
10938 int rec
= stack
->ninsn
;
10939 assert (!istack_full (stack
));
10940 stack
->insn
[rec
] = *insn
;
10945 /* Clear space for the next TInsn on the IStack and return a pointer
10946 to it. It is an error to call this if istack_full () is TRUE. */
10949 istack_push_space (IStack
*stack
)
10951 int rec
= stack
->ninsn
;
10953 assert (!istack_full (stack
));
10954 insn
= &stack
->insn
[rec
];
10955 memset (insn
, 0, sizeof (TInsn
));
10961 /* Remove the last pushed instruction. It is an error to call this if
10962 istack_empty () returns TRUE. */
10965 istack_pop (IStack
*stack
)
10967 int rec
= stack
->ninsn
- 1;
10968 assert (!istack_empty (stack
));
10970 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10974 /* TInsn functions. */
10977 tinsn_init (TInsn
*dst
)
10979 memset (dst
, 0, sizeof (TInsn
));
10983 /* Get the ``num''th token of the TInsn.
10984 It is illegal to call this if num > insn->ntoks. */
10987 tinsn_get_tok (TInsn
*insn
, int num
)
10989 assert (num
< insn
->ntok
);
10990 return &insn
->tok
[num
];
10994 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10997 tinsn_has_symbolic_operands (const TInsn
*insn
)
11000 int n
= insn
->ntok
;
11002 assert (insn
->insn_type
== ITYPE_INSN
);
11004 for (i
= 0; i
< n
; ++i
)
11006 switch (insn
->tok
[i
].X_op
)
11020 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11022 xtensa_isa isa
= xtensa_default_isa
;
11024 int n
= insn
->ntok
;
11026 assert (insn
->insn_type
== ITYPE_INSN
);
11028 for (i
= 0; i
< n
; ++i
)
11030 switch (insn
->tok
[i
].X_op
)
11038 /* Errors for these types are caught later. */
11043 /* Symbolic immediates are only allowed on the last immediate
11044 operand. At this time, CONST16 is the only opcode where we
11045 support non-PC-relative relocations. (It isn't necessary
11046 to complain about non-PC-relative relocations here, but
11047 otherwise, no error is reported until the relocations are
11048 generated, and the assembler won't get that far if there
11049 are any other errors. It's nice to see all the problems
11051 if (i
!= get_relaxable_immed (insn
->opcode
)
11052 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11053 && insn
->opcode
!= xtensa_const16_opcode
))
11055 as_bad (_("invalid symbolic operand %d on '%s'"),
11056 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11065 /* For assembly code with complex expressions (e.g. subtraction),
11066 we have to build them in the literal pool so that
11067 their results are calculated correctly after relaxation.
11068 The relaxation only handles expressions that
11069 boil down to SYMBOL + OFFSET. */
11072 tinsn_has_complex_operands (const TInsn
*insn
)
11075 int n
= insn
->ntok
;
11076 assert (insn
->insn_type
== ITYPE_INSN
);
11077 for (i
= 0; i
< n
; ++i
)
11079 switch (insn
->tok
[i
].X_op
)
11095 /* Encode a TInsn opcode and its constant operands into slotbuf.
11096 Return TRUE if there is a symbol in the immediate field. This
11097 function assumes that:
11098 1) The number of operands are correct.
11099 2) The insn_type is ITYPE_INSN.
11100 3) The opcode can be encoded in the specified format and slot.
11101 4) Operands are either O_constant or O_symbol, and all constants fit. */
11104 tinsn_to_slotbuf (xtensa_format fmt
,
11107 xtensa_insnbuf slotbuf
)
11109 xtensa_isa isa
= xtensa_default_isa
;
11110 xtensa_opcode opcode
= tinsn
->opcode
;
11111 bfd_boolean has_fixup
= FALSE
;
11112 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11115 assert (tinsn
->insn_type
== ITYPE_INSN
);
11116 if (noperands
!= tinsn
->ntok
)
11117 as_fatal (_("operand number mismatch"));
11119 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11121 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11122 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11126 for (i
= 0; i
< noperands
; i
++)
11128 expressionS
*expr
= &tinsn
->tok
[i
];
11134 switch (expr
->X_op
)
11137 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11139 /* The register number has already been checked in
11140 expression_maybe_register, so we don't need to check here. */
11141 opnd_value
= expr
->X_add_number
;
11142 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11143 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11146 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11150 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11152 as_where (&file_name
, &line
);
11153 /* It is a constant and we called this function
11154 then we have to try to fit it. */
11155 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11156 expr
->X_add_number
, file_name
, line
);
11169 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11170 into a multi-slot instruction, fill the other slots with NOPs.
11171 Return TRUE if there is a symbol in the immediate field. See also the
11172 assumptions listed for tinsn_to_slotbuf. */
11175 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11177 static xtensa_insnbuf slotbuf
= 0;
11178 static vliw_insn vinsn
;
11179 xtensa_isa isa
= xtensa_default_isa
;
11180 bfd_boolean has_fixup
= FALSE
;
11185 slotbuf
= xtensa_insnbuf_alloc (isa
);
11186 xg_init_vinsn (&vinsn
);
11189 xg_clear_vinsn (&vinsn
);
11191 bundle_tinsn (tinsn
, &vinsn
);
11193 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11195 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11197 /* Only one slot may have a fix-up because the rest contains NOPs. */
11199 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11200 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11207 /* Check the instruction arguments. Return TRUE on failure. */
11210 tinsn_check_arguments (const TInsn
*insn
)
11212 xtensa_isa isa
= xtensa_default_isa
;
11213 xtensa_opcode opcode
= insn
->opcode
;
11215 if (opcode
== XTENSA_UNDEFINED
)
11217 as_bad (_("invalid opcode"));
11221 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11223 as_bad (_("too few operands"));
11227 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11229 as_bad (_("too many operands"));
11236 /* Load an instruction from its encoded form. */
11239 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11243 xg_init_vinsn (&vinsn
);
11244 vinsn_from_chars (&vinsn
, f
);
11246 *tinsn
= vinsn
.slots
[slot
];
11247 xg_free_vinsn (&vinsn
);
11252 tinsn_from_insnbuf (TInsn
*tinsn
,
11253 xtensa_insnbuf slotbuf
,
11258 xtensa_isa isa
= xtensa_default_isa
;
11260 /* Find the immed. */
11261 tinsn_init (tinsn
);
11262 tinsn
->insn_type
= ITYPE_INSN
;
11263 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11264 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11265 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11266 for (i
= 0; i
< tinsn
->ntok
; i
++)
11268 set_expr_const (&tinsn
->tok
[i
],
11269 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11270 tinsn
->opcode
, i
));
11275 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11278 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11280 xtensa_opcode opcode
= tinsn
->opcode
;
11283 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11285 opnum
= get_relaxable_immed (opcode
);
11286 assert (opnum
>= 0);
11287 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11289 set_expr_symbol_offset_diff
11290 (&tinsn
->tok
[opnum
],
11291 fragP
->tc_frag_data
.slot_symbols
[slot
],
11292 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11293 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11297 set_expr_symbol_offset
11298 (&tinsn
->tok
[opnum
],
11299 fragP
->tc_frag_data
.slot_symbols
[slot
],
11300 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11307 get_num_stack_text_bytes (IStack
*istack
)
11310 int text_bytes
= 0;
11312 for (i
= 0; i
< istack
->ninsn
; i
++)
11314 TInsn
*tinsn
= &istack
->insn
[i
];
11315 if (tinsn
->insn_type
== ITYPE_INSN
)
11316 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11323 get_num_stack_literal_bytes (IStack
*istack
)
11328 for (i
= 0; i
< istack
->ninsn
; i
++)
11330 TInsn
*tinsn
= &istack
->insn
[i
];
11331 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11338 /* vliw_insn functions. */
11341 xg_init_vinsn (vliw_insn
*v
)
11344 xtensa_isa isa
= xtensa_default_isa
;
11346 xg_clear_vinsn (v
);
11348 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11349 if (v
->insnbuf
== NULL
)
11350 as_fatal (_("out of memory"));
11352 for (i
= 0; i
< MAX_SLOTS
; i
++)
11354 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11355 if (v
->slotbuf
[i
] == NULL
)
11356 as_fatal (_("out of memory"));
11362 xg_clear_vinsn (vliw_insn
*v
)
11366 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11368 v
->format
= XTENSA_UNDEFINED
;
11370 v
->inside_bundle
= FALSE
;
11372 if (xt_saved_debug_type
!= DEBUG_NONE
)
11373 debug_type
= xt_saved_debug_type
;
11375 for (i
= 0; i
< MAX_SLOTS
; i
++)
11376 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11381 vinsn_has_specific_opcodes (vliw_insn
*v
)
11385 for (i
= 0; i
< v
->num_slots
; i
++)
11387 if (v
->slots
[i
].is_specific_opcode
)
11395 xg_free_vinsn (vliw_insn
*v
)
11398 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11399 for (i
= 0; i
< MAX_SLOTS
; i
++)
11400 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11404 /* Before this is called, we should have
11405 filled out the following fields:
11407 1) the number of operands for each opcode are correct
11408 2) the tinsn in the slots are ITYPE_INSN
11409 3) ONLY the relaxable_ is built
11410 4) All operands are
11411 O_constant, O_symbol
11414 The return value tells whether there are any remaining O_symbols. */
11417 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11420 bfd_boolean record_fixup
)
11422 xtensa_isa isa
= xtensa_default_isa
;
11423 xtensa_format fmt
= vinsn
->format
;
11424 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11426 bfd_boolean has_fixup
= FALSE
;
11428 xtensa_format_encode (isa
, fmt
, insnbuf
);
11430 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11432 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11433 bfd_boolean tinsn_has_fixup
=
11434 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11435 vinsn
->slotbuf
[slot
]);
11437 xtensa_format_set_slot (isa
, fmt
, slot
,
11438 insnbuf
, vinsn
->slotbuf
[slot
]);
11439 /* tinsn_has_fixup tracks if there is a fixup at all.
11440 record_fixup controls globally. I.E., we use this
11441 function from several places, some of which are after
11442 fixups have already been recorded. Finally,
11443 tinsn->record_fixup controls based on the individual ops,
11444 which may or may not need it based on the relaxation
11446 if (tinsn_has_fixup
&& record_fixup
)
11449 xtensa_opcode opcode
= tinsn
->opcode
;
11450 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11453 for (i
= 0; i
< noperands
; i
++)
11455 expressionS
* expr
= &tinsn
->tok
[i
];
11456 switch (expr
->X_op
)
11461 if (get_relaxable_immed (opcode
) == i
)
11463 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11465 if (!xg_add_opcode_fix
11466 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11467 frag_offset
- fragP
->fr_literal
))
11468 as_bad (_("instruction with constant operands does not fit"));
11472 tinsn
->symbol
= expr
->X_add_symbol
;
11473 tinsn
->offset
= expr
->X_add_number
;
11477 as_bad (_("invalid operand %d on '%s'"),
11478 i
, xtensa_opcode_name (isa
, opcode
));
11486 if (get_relaxable_immed (opcode
) == i
)
11488 if (tinsn
->record_fix
)
11489 as_bad (_("invalid subtract operand"));
11492 tinsn
->symbol
= expr
->X_add_symbol
;
11493 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11494 tinsn
->offset
= expr
->X_add_number
;
11498 as_bad (_("invalid operand %d on '%s'"),
11499 i
, xtensa_opcode_name (isa
, opcode
));
11503 as_bad (_("invalid expression for operand %d on '%s'"),
11504 i
, xtensa_opcode_name (isa
, opcode
));
11516 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11518 static xtensa_insnbuf insnbuf
= NULL
;
11519 static xtensa_insnbuf slotbuf
= NULL
;
11522 xtensa_isa isa
= xtensa_default_isa
;
11526 insnbuf
= xtensa_insnbuf_alloc (isa
);
11527 slotbuf
= xtensa_insnbuf_alloc (isa
);
11530 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11531 fmt
= xtensa_format_decode (isa
, insnbuf
);
11532 if (fmt
== XTENSA_UNDEFINED
)
11533 as_fatal (_("cannot decode instruction format"));
11534 vinsn
->format
= fmt
;
11535 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11537 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11539 TInsn
*tinsn
= &vinsn
->slots
[i
];
11540 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11541 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11546 /* Expression utilities. */
11548 /* Return TRUE if the expression is an integer constant. */
11551 expr_is_const (const expressionS
*s
)
11553 return (s
->X_op
== O_constant
);
11557 /* Get the expression constant.
11558 Calling this is illegal if expr_is_const () returns TRUE. */
11561 get_expr_const (const expressionS
*s
)
11563 assert (expr_is_const (s
));
11564 return s
->X_add_number
;
11568 /* Set the expression to a constant value. */
11571 set_expr_const (expressionS
*s
, offsetT val
)
11573 s
->X_op
= O_constant
;
11574 s
->X_add_number
= val
;
11575 s
->X_add_symbol
= NULL
;
11576 s
->X_op_symbol
= NULL
;
11581 expr_is_register (const expressionS
*s
)
11583 return (s
->X_op
== O_register
);
11587 /* Get the expression constant.
11588 Calling this is illegal if expr_is_const () returns TRUE. */
11591 get_expr_register (const expressionS
*s
)
11593 assert (expr_is_register (s
));
11594 return s
->X_add_number
;
11598 /* Set the expression to a symbol + constant offset. */
11601 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11603 s
->X_op
= O_symbol
;
11604 s
->X_add_symbol
= sym
;
11605 s
->X_op_symbol
= NULL
; /* unused */
11606 s
->X_add_number
= offset
;
11610 /* Set the expression to symbol - minus_sym + offset. */
11613 set_expr_symbol_offset_diff (expressionS
*s
,
11615 symbolS
*minus_sym
,
11618 s
->X_op
= O_subtract
;
11619 s
->X_add_symbol
= sym
;
11620 s
->X_op_symbol
= minus_sym
; /* unused */
11621 s
->X_add_number
= offset
;
11625 /* Return TRUE if the two expressions are equal. */
11628 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11630 if (s1
->X_op
!= s2
->X_op
)
11632 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11634 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11636 if (s1
->X_add_number
!= s2
->X_add_number
)
11643 copy_expr (expressionS
*dst
, const expressionS
*src
)
11645 memcpy (dst
, src
, sizeof (expressionS
));
11649 /* Support for the "--rename-section" option. */
11651 struct rename_section_struct
11655 struct rename_section_struct
*next
;
11658 static struct rename_section_struct
*section_rename
;
11661 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11662 entries to the section_rename list. Note: Specifying multiple
11663 renamings separated by colons is not documented and is retained only
11664 for backward compatibility. */
11667 build_section_rename (const char *arg
)
11669 struct rename_section_struct
*r
;
11670 char *this_arg
= NULL
;
11671 char *next_arg
= NULL
;
11673 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11675 char *old_name
, *new_name
;
11679 next_arg
= strchr (this_arg
, ':');
11687 old_name
= this_arg
;
11688 new_name
= strchr (this_arg
, '=');
11690 if (*old_name
== '\0')
11692 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11695 if (!new_name
|| new_name
[1] == '\0')
11697 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11704 /* Check for invalid section renaming. */
11705 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11707 if (strcmp (r
->old_name
, old_name
) == 0)
11708 as_bad (_("section %s renamed multiple times"), old_name
);
11709 if (strcmp (r
->new_name
, new_name
) == 0)
11710 as_bad (_("multiple sections remapped to output section %s"),
11715 r
= (struct rename_section_struct
*)
11716 xmalloc (sizeof (struct rename_section_struct
));
11717 r
->old_name
= xstrdup (old_name
);
11718 r
->new_name
= xstrdup (new_name
);
11719 r
->next
= section_rename
;
11720 section_rename
= r
;
11726 xtensa_section_rename (char *name
)
11728 struct rename_section_struct
*r
= section_rename
;
11730 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11732 if (strcmp (r
->old_name
, name
) == 0)
11733 return r
->new_name
;