1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
274 /* is_specific_opcode implies no_transform. */
275 unsigned is_no_transform
: 1;
277 unsigned is_no_reorder
: 1;
279 /* Uses absolute literal addressing for l32r. */
280 unsigned is_abslit
: 1;
282 unsigned is_align
: 1;
283 unsigned alignment
: 5;
287 /* Structure for saving information about a block of property data
288 for frags that have the same flags. */
289 struct xtensa_block_info_struct
295 struct xtensa_block_info_struct
*next
;
299 /* Structure for saving the current state before emitting literals. */
300 typedef struct emit_state_struct
305 int generating_literals
;
309 /* Opcode placement information */
311 typedef unsigned long long bitfield
;
312 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
313 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
314 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
316 #define MAX_FORMATS 32
318 typedef struct op_placement_info_struct
321 /* A number describing how restrictive the issue is for this
322 opcode. For example, an opcode that fits lots of different
323 formats has a high freedom, as does an opcode that fits
324 only one format but many slots in that format. The most
325 restrictive is the opcode that fits only one slot in one
328 xtensa_format narrowest
;
332 /* formats is a bitfield with the Nth bit set
333 if the opcode fits in the Nth xtensa_format. */
336 /* slots[N]'s Mth bit is set if the op fits in the
337 Mth slot of the Nth xtensa_format. */
338 bitfield slots
[MAX_FORMATS
];
340 /* A count of the number of slots in a given format
341 an op can fit (i.e., the bitcount of the slot field above). */
342 char slots_in_format
[MAX_FORMATS
];
344 } op_placement_info
, *op_placement_info_table
;
346 op_placement_info_table op_placement_table
;
349 /* Extra expression types. */
351 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
352 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
353 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 struct suffix_reloc_map
359 bfd_reloc_code_real_type reloc
;
360 unsigned char operator;
363 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
365 static struct suffix_reloc_map suffix_relocs
[] =
367 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
368 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
369 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
370 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
384 directive_literal_prefix
,
386 directive_absolute_literals
,
387 directive_last_directive
393 bfd_boolean can_be_negated
;
396 const directive_infoS directive_info
[] =
399 { "literal", FALSE
},
401 { "transform", TRUE
},
402 { "freeregs", FALSE
},
403 { "longcalls", TRUE
},
404 { "literal_prefix", FALSE
},
405 { "schedule", TRUE
},
406 { "absolute-literals", TRUE
}
409 bfd_boolean directive_state
[] =
413 #if !XCHAL_HAVE_DENSITY
418 TRUE
, /* transform */
419 FALSE
, /* freeregs */
420 FALSE
, /* longcalls */
421 FALSE
, /* literal_prefix */
422 FALSE
, /* schedule */
423 #if XSHAL_USE_ABSOLUTE_LITERALS
424 TRUE
/* absolute_literals */
426 FALSE
/* absolute_literals */
431 /* Directive functions. */
433 static void xtensa_begin_directive (int);
434 static void xtensa_end_directive (int);
435 static void xtensa_literal_prefix (void);
436 static void xtensa_literal_position (int);
437 static void xtensa_literal_pseudo (int);
438 static void xtensa_frequency_pseudo (int);
439 static void xtensa_elf_cons (int);
441 /* Parsing and Idiom Translation. */
443 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
445 /* Various Other Internal Functions. */
447 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
448 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
449 static void xtensa_mark_literal_pool_location (void);
450 static addressT
get_expanded_loop_offset (xtensa_opcode
);
451 static fragS
*get_literal_pool_location (segT
);
452 static void set_literal_pool_location (segT
, fragS
*);
453 static void xtensa_set_frag_assembly_state (fragS
*);
454 static void finish_vinsn (vliw_insn
*);
455 static bfd_boolean
emit_single_op (TInsn
*);
456 static int total_frag_text_expansion (fragS
*);
458 /* Alignment Functions. */
460 static int get_text_align_power (unsigned);
461 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
462 static int branch_align_power (segT
);
464 /* Helpers for xtensa_relax_frag(). */
466 static long relax_frag_add_nop (fragS
*);
468 /* Accessors for additional per-subsegment information. */
470 static unsigned get_last_insn_flags (segT
, subsegT
);
471 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
472 static float get_subseg_total_freq (segT
, subsegT
);
473 static float get_subseg_target_freq (segT
, subsegT
);
474 static void set_subseg_freq (segT
, subsegT
, float, float);
476 /* Segment list functions. */
478 static void xtensa_move_literals (void);
479 static void xtensa_reorder_segments (void);
480 static void xtensa_switch_to_literal_fragment (emit_state
*);
481 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
482 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
483 static void xtensa_restore_emit_state (emit_state
*);
484 static segT
cache_literal_section (bfd_boolean
);
486 /* Import from elf32-xtensa.c in BFD library. */
488 extern asection
*xtensa_get_property_section (asection
*, const char *);
490 /* op_placement_info functions. */
492 static void init_op_placement_info_table (void);
493 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
494 static int xg_get_single_size (xtensa_opcode
);
495 static xtensa_format
xg_get_single_format (xtensa_opcode
);
496 static int xg_get_single_slot (xtensa_opcode
);
498 /* TInsn and IStack functions. */
500 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
501 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
502 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
503 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
504 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
505 static void tinsn_from_chars (TInsn
*, char *, int);
506 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
507 static int get_num_stack_text_bytes (IStack
*);
508 static int get_num_stack_literal_bytes (IStack
*);
510 /* vliw_insn functions. */
512 static void xg_init_vinsn (vliw_insn
*);
513 static void xg_clear_vinsn (vliw_insn
*);
514 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
515 static void xg_free_vinsn (vliw_insn
*);
516 static bfd_boolean vinsn_to_insnbuf
517 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
518 static void vinsn_from_chars (vliw_insn
*, char *);
520 /* Expression Utilities. */
522 bfd_boolean
expr_is_const (const expressionS
*);
523 offsetT
get_expr_const (const expressionS
*);
524 void set_expr_const (expressionS
*, offsetT
);
525 bfd_boolean
expr_is_register (const expressionS
*);
526 offsetT
get_expr_register (const expressionS
*);
527 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
528 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
529 static void copy_expr (expressionS
*, const expressionS
*);
531 /* Section renaming. */
533 static void build_section_rename (const char *);
536 /* ISA imported from bfd. */
537 extern xtensa_isa xtensa_default_isa
;
539 extern int target_big_endian
;
541 static xtensa_opcode xtensa_addi_opcode
;
542 static xtensa_opcode xtensa_addmi_opcode
;
543 static xtensa_opcode xtensa_call0_opcode
;
544 static xtensa_opcode xtensa_call4_opcode
;
545 static xtensa_opcode xtensa_call8_opcode
;
546 static xtensa_opcode xtensa_call12_opcode
;
547 static xtensa_opcode xtensa_callx0_opcode
;
548 static xtensa_opcode xtensa_callx4_opcode
;
549 static xtensa_opcode xtensa_callx8_opcode
;
550 static xtensa_opcode xtensa_callx12_opcode
;
551 static xtensa_opcode xtensa_const16_opcode
;
552 static xtensa_opcode xtensa_entry_opcode
;
553 static xtensa_opcode xtensa_movi_opcode
;
554 static xtensa_opcode xtensa_movi_n_opcode
;
555 static xtensa_opcode xtensa_isync_opcode
;
556 static xtensa_opcode xtensa_jx_opcode
;
557 static xtensa_opcode xtensa_l32r_opcode
;
558 static xtensa_opcode xtensa_loop_opcode
;
559 static xtensa_opcode xtensa_loopnez_opcode
;
560 static xtensa_opcode xtensa_loopgtz_opcode
;
561 static xtensa_opcode xtensa_nop_opcode
;
562 static xtensa_opcode xtensa_nop_n_opcode
;
563 static xtensa_opcode xtensa_or_opcode
;
564 static xtensa_opcode xtensa_ret_opcode
;
565 static xtensa_opcode xtensa_ret_n_opcode
;
566 static xtensa_opcode xtensa_retw_opcode
;
567 static xtensa_opcode xtensa_retw_n_opcode
;
568 static xtensa_opcode xtensa_rsr_lcount_opcode
;
569 static xtensa_opcode xtensa_waiti_opcode
;
572 /* Command-line Options. */
574 bfd_boolean use_literal_section
= TRUE
;
575 static bfd_boolean align_targets
= TRUE
;
576 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
577 static bfd_boolean has_a0_b_retw
= FALSE
;
578 static bfd_boolean workaround_a0_b_retw
= FALSE
;
579 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
580 static bfd_boolean workaround_short_loop
= FALSE
;
581 static bfd_boolean maybe_has_short_loop
= FALSE
;
582 static bfd_boolean workaround_close_loop_end
= FALSE
;
583 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
584 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
586 /* When workaround_short_loops is TRUE, all loops with early exits must
587 have at least 3 instructions. workaround_all_short_loops is a modifier
588 to the workaround_short_loop flag. In addition to the
589 workaround_short_loop actions, all straightline loopgtz and loopnez
590 must have at least 3 instructions. */
592 static bfd_boolean workaround_all_short_loops
= FALSE
;
596 xtensa_setup_hw_workarounds (int earliest
, int latest
)
598 if (earliest
> latest
)
599 as_fatal (_("illegal range of target hardware versions"));
601 /* Enable all workarounds for pre-T1050.0 hardware. */
602 if (earliest
< 105000 || latest
< 105000)
604 workaround_a0_b_retw
|= TRUE
;
605 workaround_b_j_loop_end
|= TRUE
;
606 workaround_short_loop
|= TRUE
;
607 workaround_close_loop_end
|= TRUE
;
608 workaround_all_short_loops
|= TRUE
;
609 enforce_three_byte_loop_align
= TRUE
;
616 option_density
= OPTION_MD_BASE
,
623 option_no_link_relax
,
631 option_text_section_literals
,
632 option_no_text_section_literals
,
634 option_absolute_literals
,
635 option_no_absolute_literals
,
637 option_align_targets
,
638 option_no_align_targets
,
640 option_warn_unaligned_targets
,
645 option_workaround_a0_b_retw
,
646 option_no_workaround_a0_b_retw
,
648 option_workaround_b_j_loop_end
,
649 option_no_workaround_b_j_loop_end
,
651 option_workaround_short_loop
,
652 option_no_workaround_short_loop
,
654 option_workaround_all_short_loops
,
655 option_no_workaround_all_short_loops
,
657 option_workaround_close_loop_end
,
658 option_no_workaround_close_loop_end
,
660 option_no_workarounds
,
662 option_rename_section_name
,
665 option_prefer_const16
,
667 option_target_hardware
670 const char *md_shortopts
= "";
672 struct option md_longopts
[] =
674 { "density", no_argument
, NULL
, option_density
},
675 { "no-density", no_argument
, NULL
, option_no_density
},
677 /* Both "relax" and "generics" are deprecated and treated as equivalent
678 to the "transform" option. */
679 { "relax", no_argument
, NULL
, option_relax
},
680 { "no-relax", no_argument
, NULL
, option_no_relax
},
681 { "generics", no_argument
, NULL
, option_generics
},
682 { "no-generics", no_argument
, NULL
, option_no_generics
},
684 { "transform", no_argument
, NULL
, option_transform
},
685 { "no-transform", no_argument
, NULL
, option_no_transform
},
686 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
687 { "no-text-section-literals", no_argument
, NULL
,
688 option_no_text_section_literals
},
689 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
690 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
691 /* This option was changed from -align-target to -target-align
692 because it conflicted with the "-al" option. */
693 { "target-align", no_argument
, NULL
, option_align_targets
},
694 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
695 { "warn-unaligned-targets", no_argument
, NULL
,
696 option_warn_unaligned_targets
},
697 { "longcalls", no_argument
, NULL
, option_longcalls
},
698 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
700 { "no-workaround-a0-b-retw", no_argument
, NULL
,
701 option_no_workaround_a0_b_retw
},
702 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
704 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
705 option_no_workaround_b_j_loop_end
},
706 { "workaround-b-j-loop-end", no_argument
, NULL
,
707 option_workaround_b_j_loop_end
},
709 { "no-workaround-short-loops", no_argument
, NULL
,
710 option_no_workaround_short_loop
},
711 { "workaround-short-loops", no_argument
, NULL
,
712 option_workaround_short_loop
},
714 { "no-workaround-all-short-loops", no_argument
, NULL
,
715 option_no_workaround_all_short_loops
},
716 { "workaround-all-short-loop", no_argument
, NULL
,
717 option_workaround_all_short_loops
},
719 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
720 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
722 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
724 { "no-workaround-close-loop-end", no_argument
, NULL
,
725 option_no_workaround_close_loop_end
},
726 { "workaround-close-loop-end", no_argument
, NULL
,
727 option_workaround_close_loop_end
},
729 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
731 { "link-relax", no_argument
, NULL
, option_link_relax
},
732 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
734 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
736 { NULL
, no_argument
, NULL
, 0 }
739 size_t md_longopts_size
= sizeof md_longopts
;
743 md_parse_option (int c
, char *arg
)
748 as_warn (_("--density option is ignored"));
750 case option_no_density
:
751 as_warn (_("--no-density option is ignored"));
753 case option_link_relax
:
756 case option_no_link_relax
:
759 case option_generics
:
760 as_warn (_("--generics is deprecated; use --transform instead"));
761 return md_parse_option (option_transform
, arg
);
762 case option_no_generics
:
763 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
764 return md_parse_option (option_no_transform
, arg
);
766 as_warn (_("--relax is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_relax
:
769 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
771 case option_longcalls
:
772 directive_state
[directive_longcalls
] = TRUE
;
774 case option_no_longcalls
:
775 directive_state
[directive_longcalls
] = FALSE
;
777 case option_text_section_literals
:
778 use_literal_section
= FALSE
;
780 case option_no_text_section_literals
:
781 use_literal_section
= TRUE
;
783 case option_absolute_literals
:
784 if (!absolute_literals_supported
)
786 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
789 directive_state
[directive_absolute_literals
] = TRUE
;
791 case option_no_absolute_literals
:
792 directive_state
[directive_absolute_literals
] = FALSE
;
795 case option_workaround_a0_b_retw
:
796 workaround_a0_b_retw
= TRUE
;
798 case option_no_workaround_a0_b_retw
:
799 workaround_a0_b_retw
= FALSE
;
801 case option_workaround_b_j_loop_end
:
802 workaround_b_j_loop_end
= TRUE
;
804 case option_no_workaround_b_j_loop_end
:
805 workaround_b_j_loop_end
= FALSE
;
808 case option_workaround_short_loop
:
809 workaround_short_loop
= TRUE
;
811 case option_no_workaround_short_loop
:
812 workaround_short_loop
= FALSE
;
815 case option_workaround_all_short_loops
:
816 workaround_all_short_loops
= TRUE
;
818 case option_no_workaround_all_short_loops
:
819 workaround_all_short_loops
= FALSE
;
822 case option_workaround_close_loop_end
:
823 workaround_close_loop_end
= TRUE
;
825 case option_no_workaround_close_loop_end
:
826 workaround_close_loop_end
= FALSE
;
829 case option_no_workarounds
:
830 workaround_a0_b_retw
= FALSE
;
831 workaround_b_j_loop_end
= FALSE
;
832 workaround_short_loop
= FALSE
;
833 workaround_all_short_loops
= FALSE
;
834 workaround_close_loop_end
= FALSE
;
837 case option_align_targets
:
838 align_targets
= TRUE
;
840 case option_no_align_targets
:
841 align_targets
= FALSE
;
844 case option_warn_unaligned_targets
:
845 warn_unaligned_branch_targets
= TRUE
;
848 case option_rename_section_name
:
849 build_section_rename (arg
);
853 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
854 should be emitted or not. FIXME: Not implemented. */
857 case option_prefer_l32r
:
859 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
863 case option_prefer_const16
:
865 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
869 case option_target_hardware
:
871 int earliest
, latest
= 0;
872 if (*arg
== 0 || *arg
== '-')
873 as_fatal (_("invalid target hardware version"));
875 earliest
= strtol (arg
, &arg
, 0);
879 else if (*arg
== '-')
882 as_fatal (_("invalid target hardware version"));
883 latest
= strtol (arg
, &arg
, 0);
886 as_fatal (_("invalid target hardware version"));
888 xtensa_setup_hw_workarounds (earliest
, latest
);
892 case option_transform
:
893 /* This option has no affect other than to use the defaults,
894 which are already set. */
897 case option_no_transform
:
898 /* This option turns off all transformations of any kind.
899 However, because we want to preserve the state of other
900 directives, we only change its own field. Thus, before
901 you perform any transformation, always check if transform
902 is available. If you use the functions we provide for this
903 purpose, you will be ok. */
904 directive_state
[directive_transform
] = FALSE
;
914 md_show_usage (FILE *stream
)
918 --[no-]text-section-literals\n\
919 [Do not] put literals in the text section\n\
920 --[no-]absolute-literals\n\
921 [Do not] default to use non-PC-relative literals\n\
922 --[no-]target-align [Do not] try to align branch targets\n\
923 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
924 --[no-]transform [Do not] transform instructions\n\
925 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
929 /* Functions related to the list of current label symbols. */
932 xtensa_add_insn_label (symbolS
*sym
)
936 if (!free_insn_labels
)
937 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
940 l
= free_insn_labels
;
941 free_insn_labels
= l
->next
;
945 l
->next
= insn_labels
;
951 xtensa_clear_insn_labels (void)
955 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
962 /* The "loops_ok" argument is provided to allow ignoring labels that
963 define loop ends. This fixes a bug where the NOPs to align a
964 loop opcode were included in a previous zero-cost loop:
983 This argument is used to prevent moving the NOP to before the
984 loop-end label, which is what you want in this special case. */
987 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
991 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
993 symbolS
*lit_sym
= lit
->sym
;
994 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
996 S_SET_VALUE (lit_sym
, new_offset
);
997 symbol_set_frag (lit_sym
, new_frag
);
1003 /* Directive data and functions. */
1005 typedef struct state_stackS_struct
1007 directiveE directive
;
1008 bfd_boolean negated
;
1009 bfd_boolean old_state
;
1013 struct state_stackS_struct
*prev
;
1016 state_stackS
*directive_state_stack
;
1018 const pseudo_typeS md_pseudo_table
[] =
1020 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1021 { "literal_position", xtensa_literal_position
, 0 },
1022 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1023 { "long", xtensa_elf_cons
, 4 },
1024 { "word", xtensa_elf_cons
, 4 },
1025 { "short", xtensa_elf_cons
, 2 },
1026 { "begin", xtensa_begin_directive
, 0 },
1027 { "end", xtensa_end_directive
, 0 },
1028 { "literal", xtensa_literal_pseudo
, 0 },
1029 { "frequency", xtensa_frequency_pseudo
, 0 },
1035 use_transform (void)
1037 /* After md_end, you should be checking frag by frag, rather
1038 than state directives. */
1039 assert (!past_xtensa_end
);
1040 return directive_state
[directive_transform
];
1045 do_align_targets (void)
1047 /* Do not use this function after md_end; just look at align_targets
1048 instead. There is no target-align directive, so alignment is either
1049 enabled for all frags or not done at all. */
1050 assert (!past_xtensa_end
);
1051 return align_targets
&& use_transform ();
1056 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1060 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1062 as_where (&file
, &line
);
1064 stack
->directive
= directive
;
1065 stack
->negated
= negated
;
1066 stack
->old_state
= directive_state
[directive
];
1069 stack
->datum
= datum
;
1070 stack
->prev
= directive_state_stack
;
1071 directive_state_stack
= stack
;
1073 directive_state
[directive
] = !negated
;
1078 directive_pop (directiveE
*directive
,
1079 bfd_boolean
*negated
,
1084 state_stackS
*top
= directive_state_stack
;
1086 if (!directive_state_stack
)
1088 as_bad (_("unmatched end directive"));
1089 *directive
= directive_none
;
1093 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1094 *directive
= top
->directive
;
1095 *negated
= top
->negated
;
1098 *datum
= top
->datum
;
1099 directive_state_stack
= top
->prev
;
1105 directive_balance (void)
1107 while (directive_state_stack
)
1109 directiveE directive
;
1110 bfd_boolean negated
;
1115 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1116 as_warn_where ((char *) file
, line
,
1117 _(".begin directive with no matching .end directive"));
1123 inside_directive (directiveE dir
)
1125 state_stackS
*top
= directive_state_stack
;
1127 while (top
&& top
->directive
!= dir
)
1130 return (top
!= NULL
);
1135 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1139 char *directive_string
;
1141 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1146 input_line_pointer
+= 3;
1149 len
= strspn (input_line_pointer
,
1150 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1152 /* This code is a hack to make .begin [no-][generics|relax] exactly
1153 equivalent to .begin [no-]transform. We should remove it when
1154 we stop accepting those options. */
1156 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1158 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1159 directive_string
= "transform";
1161 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1163 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1164 directive_string
= "transform";
1167 directive_string
= input_line_pointer
;
1169 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1171 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1173 input_line_pointer
+= len
;
1174 *directive
= (directiveE
) i
;
1175 if (*negated
&& !directive_info
[i
].can_be_negated
)
1176 as_bad (_("directive %s cannot be negated"),
1177 directive_info
[i
].name
);
1182 as_bad (_("unknown directive"));
1183 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1188 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1190 directiveE directive
;
1191 bfd_boolean negated
;
1195 get_directive (&directive
, &negated
);
1196 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1198 discard_rest_of_line ();
1202 if (cur_vinsn
.inside_bundle
)
1203 as_bad (_("directives are not valid inside bundles"));
1207 case directive_literal
:
1208 if (!inside_directive (directive_literal
))
1210 /* Previous labels go with whatever follows this directive, not with
1211 the literal, so save them now. */
1212 saved_insn_labels
= insn_labels
;
1215 as_warn (_(".begin literal is deprecated; use .literal instead"));
1216 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1217 xtensa_switch_to_literal_fragment (state
);
1218 directive_push (directive_literal
, negated
, state
);
1221 case directive_literal_prefix
:
1222 /* Have to flush pending output because a movi relaxed to an l32r
1223 might produce a literal. */
1224 md_flush_pending_output ();
1225 /* Check to see if the current fragment is a literal
1226 fragment. If it is, then this operation is not allowed. */
1227 if (generating_literals
)
1229 as_bad (_("cannot set literal_prefix inside literal fragment"));
1233 /* Allocate the literal state for this section and push
1234 onto the directive stack. */
1235 ls
= xmalloc (sizeof (lit_state
));
1238 *ls
= default_lit_sections
;
1239 directive_push (directive_literal_prefix
, negated
, ls
);
1241 /* Process the new prefix. */
1242 xtensa_literal_prefix ();
1245 case directive_freeregs
:
1246 /* This information is currently unused, but we'll accept the statement
1247 and just discard the rest of the line. This won't check the syntax,
1248 but it will accept every correct freeregs directive. */
1249 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1250 directive_push (directive_freeregs
, negated
, 0);
1253 case directive_schedule
:
1254 md_flush_pending_output ();
1255 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1256 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1257 directive_push (directive_schedule
, negated
, 0);
1258 xtensa_set_frag_assembly_state (frag_now
);
1261 case directive_density
:
1262 as_warn (_(".begin [no-]density is ignored"));
1265 case directive_absolute_literals
:
1266 md_flush_pending_output ();
1267 if (!absolute_literals_supported
&& !negated
)
1269 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 md_flush_pending_output ();
1278 xtensa_set_frag_assembly_state (frag_now
);
1279 directive_push (directive
, negated
, 0);
1283 demand_empty_rest_of_line ();
1288 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1290 directiveE begin_directive
, end_directive
;
1291 bfd_boolean begin_negated
, end_negated
;
1295 emit_state
**state_ptr
;
1298 if (cur_vinsn
.inside_bundle
)
1299 as_bad (_("directives are not valid inside bundles"));
1301 get_directive (&end_directive
, &end_negated
);
1303 md_flush_pending_output ();
1305 switch (end_directive
)
1307 case (directiveE
) XTENSA_UNDEFINED
:
1308 discard_rest_of_line ();
1311 case directive_density
:
1312 as_warn (_(".end [no-]density is ignored"));
1313 demand_empty_rest_of_line ();
1316 case directive_absolute_literals
:
1317 if (!absolute_literals_supported
&& !end_negated
)
1319 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1320 demand_empty_rest_of_line ();
1329 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1330 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1331 (const void **) state_ptr
);
1333 if (begin_directive
!= directive_none
)
1335 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1337 as_bad (_("does not match begin %s%s at %s:%d"),
1338 begin_negated
? "no-" : "",
1339 directive_info
[begin_directive
].name
, file
, line
);
1343 switch (end_directive
)
1345 case directive_literal
:
1346 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1347 xtensa_restore_emit_state (state
);
1348 xtensa_set_frag_assembly_state (frag_now
);
1350 if (!inside_directive (directive_literal
))
1352 /* Restore the list of current labels. */
1353 xtensa_clear_insn_labels ();
1354 insn_labels
= saved_insn_labels
;
1358 case directive_literal_prefix
:
1359 /* Restore the default collection sections from saved state. */
1360 s
= (lit_state
*) state
;
1362 default_lit_sections
= *s
;
1364 /* Free the state storage. */
1365 free (s
->lit_prefix
);
1369 case directive_schedule
:
1370 case directive_freeregs
:
1374 xtensa_set_frag_assembly_state (frag_now
);
1380 demand_empty_rest_of_line ();
1384 /* Place an aligned literal fragment at the current location. */
1387 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1389 md_flush_pending_output ();
1391 if (inside_directive (directive_literal
))
1392 as_warn (_(".literal_position inside literal directive; ignoring"));
1393 xtensa_mark_literal_pool_location ();
1395 demand_empty_rest_of_line ();
1396 xtensa_clear_insn_labels ();
1400 /* Support .literal label, expr, ... */
1403 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1406 char *p
, *base_name
;
1410 if (inside_directive (directive_literal
))
1412 as_bad (_(".literal not allowed inside .begin literal region"));
1413 ignore_rest_of_line ();
1417 md_flush_pending_output ();
1419 /* Previous labels go with whatever follows this directive, not with
1420 the literal, so save them now. */
1421 saved_insn_labels
= insn_labels
;
1424 /* If we are using text-section literals, then this is the right value... */
1427 base_name
= input_line_pointer
;
1429 xtensa_switch_to_literal_fragment (&state
);
1431 /* ...but if we aren't using text-section-literals, then we
1432 need to put them in the section we just switched to. */
1433 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1436 /* All literals are aligned to four-byte boundaries. */
1437 frag_align (2, 0, 0);
1438 record_alignment (now_seg
, 2);
1440 c
= get_symbol_end ();
1441 /* Just after name is now '\0'. */
1442 p
= input_line_pointer
;
1446 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1448 as_bad (_("expected comma or colon after symbol name; "
1449 "rest of line ignored"));
1450 ignore_rest_of_line ();
1451 xtensa_restore_emit_state (&state
);
1459 input_line_pointer
++; /* skip ',' or ':' */
1461 xtensa_elf_cons (4);
1463 xtensa_restore_emit_state (&state
);
1465 /* Restore the list of current labels. */
1466 xtensa_clear_insn_labels ();
1467 insn_labels
= saved_insn_labels
;
1472 xtensa_literal_prefix (void)
1477 /* Parse the new prefix from the input_line_pointer. */
1479 len
= strspn (input_line_pointer
,
1480 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1481 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1483 /* Get a null-terminated copy of the name. */
1484 name
= xmalloc (len
+ 1);
1486 strncpy (name
, input_line_pointer
, len
);
1489 /* Skip the name in the input line. */
1490 input_line_pointer
+= len
;
1492 default_lit_sections
.lit_prefix
= name
;
1494 /* Clear cached literal sections, since the prefix has changed. */
1495 default_lit_sections
.lit_seg
= NULL
;
1496 default_lit_sections
.lit4_seg
= NULL
;
1500 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1503 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1505 float fall_through_f
, target_f
;
1507 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1508 if (fall_through_f
< 0)
1510 as_bad (_("fall through frequency must be greater than 0"));
1511 ignore_rest_of_line ();
1515 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1518 as_bad (_("branch target frequency must be greater than 0"));
1519 ignore_rest_of_line ();
1523 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1525 demand_empty_rest_of_line ();
1529 /* Like normal .long/.short/.word, except support @plt, etc.
1530 Clobbers input_line_pointer, checks end-of-line. */
1533 xtensa_elf_cons (int nbytes
)
1536 bfd_reloc_code_real_type reloc
;
1538 md_flush_pending_output ();
1540 if (cur_vinsn
.inside_bundle
)
1541 as_bad (_("directives are not valid inside bundles"));
1543 if (is_it_end_of_statement ())
1545 demand_empty_rest_of_line ();
1552 if (exp
.X_op
== O_symbol
1553 && *input_line_pointer
== '@'
1554 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1557 reloc_howto_type
*reloc_howto
=
1558 bfd_reloc_type_lookup (stdoutput
, reloc
);
1560 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1561 as_bad (_("unsupported relocation"));
1562 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1563 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1564 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1565 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1566 as_bad (_("opcode-specific %s relocation used outside "
1567 "an instruction"), reloc_howto
->name
);
1568 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1569 as_bad (_("%s relocations do not fit in %d bytes"),
1570 reloc_howto
->name
, nbytes
);
1573 char *p
= frag_more ((int) nbytes
);
1574 xtensa_set_frag_assembly_state (frag_now
);
1575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1576 nbytes
, &exp
, 0, reloc
);
1580 emit_expr (&exp
, (unsigned int) nbytes
);
1582 while (*input_line_pointer
++ == ',');
1584 input_line_pointer
--; /* Put terminator back into stream. */
1585 demand_empty_rest_of_line ();
1589 /* Parsing and Idiom Translation. */
1591 /* Parse @plt, etc. and return the desired relocation. */
1592 static bfd_reloc_code_real_type
1593 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1600 struct suffix_reloc_map
*ptr
;
1603 return BFD_RELOC_NONE
;
1605 for (ch
= *str
, str2
= ident
;
1606 (str2
< ident
+ sizeof (ident
) - 1
1607 && (ISALNUM (ch
) || ch
== '@'));
1610 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1617 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1618 if (ch
== ptr
->suffix
[0]
1619 && len
== ptr
->length
1620 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1622 /* Now check for "identifier@suffix+constant". */
1623 if (*str
== '-' || *str
== '+')
1625 char *orig_line
= input_line_pointer
;
1626 expressionS new_exp
;
1628 input_line_pointer
= str
;
1629 expression (&new_exp
);
1630 if (new_exp
.X_op
== O_constant
)
1632 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1633 str
= input_line_pointer
;
1636 if (&input_line_pointer
!= str_p
)
1637 input_line_pointer
= orig_line
;
1644 return BFD_RELOC_UNUSED
;
1648 /* Find the matching operator type. */
1649 static unsigned char
1650 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1652 struct suffix_reloc_map
*sfx
;
1653 unsigned char operator = (unsigned char) -1;
1655 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1657 if (sfx
->reloc
== reloc
)
1659 operator = sfx
->operator;
1663 assert (operator != (unsigned char) -1);
1668 /* Find the matching reloc type. */
1669 static bfd_reloc_code_real_type
1670 map_operator_to_reloc (unsigned char operator)
1672 struct suffix_reloc_map
*sfx
;
1673 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1675 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1677 if (sfx
->operator == operator)
1684 if (reloc
== BFD_RELOC_UNUSED
)
1685 return BFD_RELOC_32
;
1692 expression_end (const char *name
)
1715 #define ERROR_REG_NUM ((unsigned) -1)
1718 tc_get_register (const char *prefix
)
1721 const char *next_expr
;
1722 const char *old_line_pointer
;
1725 old_line_pointer
= input_line_pointer
;
1727 if (*input_line_pointer
== '$')
1728 ++input_line_pointer
;
1730 /* Accept "sp" as a synonym for "a1". */
1731 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1732 && expression_end (input_line_pointer
+ 2))
1734 input_line_pointer
+= 2;
1735 return 1; /* AR[1] */
1738 while (*input_line_pointer
++ == *prefix
++)
1740 --input_line_pointer
;
1745 as_bad (_("bad register name: %s"), old_line_pointer
);
1746 return ERROR_REG_NUM
;
1749 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1751 as_bad (_("bad register number: %s"), input_line_pointer
);
1752 return ERROR_REG_NUM
;
1757 while (ISDIGIT ((int) *input_line_pointer
))
1758 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1760 if (!(next_expr
= expression_end (input_line_pointer
)))
1762 as_bad (_("bad register name: %s"), old_line_pointer
);
1763 return ERROR_REG_NUM
;
1766 input_line_pointer
= (char *) next_expr
;
1773 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1775 xtensa_isa isa
= xtensa_default_isa
;
1777 /* Check if this is an immediate operand. */
1778 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1780 bfd_reloc_code_real_type reloc
;
1781 segT t
= expression (tok
);
1782 if (t
== absolute_section
1783 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1785 assert (tok
->X_op
== O_constant
);
1786 tok
->X_op
= O_symbol
;
1787 tok
->X_add_symbol
= &abs_symbol
;
1790 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1791 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1794 if (reloc
== BFD_RELOC_UNUSED
)
1796 as_bad (_("unsupported relocation"));
1800 if (tok
->X_op
== O_constant
)
1804 case BFD_RELOC_LO16
:
1805 tok
->X_add_number
&= 0xffff;
1808 case BFD_RELOC_HI16
:
1809 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1816 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1821 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1822 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1824 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1827 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1828 as_bad (_("register number out of range"));
1831 tok
->X_op
= O_register
;
1832 tok
->X_add_symbol
= 0;
1833 tok
->X_add_number
= reg
;
1838 /* Split up the arguments for an opcode or pseudo-op. */
1841 tokenize_arguments (char **args
, char *str
)
1843 char *old_input_line_pointer
;
1844 bfd_boolean saw_comma
= FALSE
;
1845 bfd_boolean saw_arg
= FALSE
;
1846 bfd_boolean saw_colon
= FALSE
;
1848 char *arg_end
, *arg
;
1851 /* Save and restore input_line_pointer around this function. */
1852 old_input_line_pointer
= input_line_pointer
;
1853 input_line_pointer
= str
;
1855 while (*input_line_pointer
)
1858 switch (*input_line_pointer
)
1865 input_line_pointer
++;
1866 if (saw_comma
|| saw_colon
|| !saw_arg
)
1872 input_line_pointer
++;
1873 if (saw_comma
|| saw_colon
|| !saw_arg
)
1879 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1882 arg_end
= input_line_pointer
+ 1;
1883 while (!expression_end (arg_end
))
1886 arg_len
= arg_end
- input_line_pointer
;
1887 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1888 args
[num_args
] = arg
;
1892 strncpy (arg
, input_line_pointer
, arg_len
);
1893 arg
[arg_len
] = '\0';
1895 input_line_pointer
= arg_end
;
1905 if (saw_comma
|| saw_colon
)
1907 input_line_pointer
= old_input_line_pointer
;
1912 as_bad (_("extra comma"));
1914 as_bad (_("extra colon"));
1916 as_bad (_("missing argument"));
1918 as_bad (_("missing comma or colon"));
1919 input_line_pointer
= old_input_line_pointer
;
1924 /* Parse the arguments to an opcode. Return TRUE on error. */
1927 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1929 expressionS
*tok
, *last_tok
;
1930 xtensa_opcode opcode
= insn
->opcode
;
1931 bfd_boolean had_error
= TRUE
;
1932 xtensa_isa isa
= xtensa_default_isa
;
1933 int n
, num_regs
= 0;
1934 int opcode_operand_count
;
1935 int opnd_cnt
, last_opnd_cnt
;
1936 unsigned int next_reg
= 0;
1937 char *old_input_line_pointer
;
1939 if (insn
->insn_type
== ITYPE_LITERAL
)
1940 opcode_operand_count
= 1;
1942 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1945 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1947 /* Save and restore input_line_pointer around this function. */
1948 old_input_line_pointer
= input_line_pointer
;
1954 /* Skip invisible operands. */
1955 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1961 for (n
= 0; n
< num_args
; n
++)
1963 input_line_pointer
= arg_strings
[n
];
1964 if (*input_line_pointer
== ':')
1966 xtensa_regfile opnd_rf
;
1967 input_line_pointer
++;
1970 assert (opnd_cnt
> 0);
1972 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1974 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1975 as_warn (_("incorrect register number, ignoring"));
1980 if (opnd_cnt
>= opcode_operand_count
)
1982 as_warn (_("too many arguments"));
1985 assert (opnd_cnt
< MAX_INSN_ARGS
);
1987 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1988 next_reg
= tok
->X_add_number
+ 1;
1990 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1992 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1994 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1995 /* minus 1 because we are seeing one right now */
2001 last_opnd_cnt
= opnd_cnt
;
2008 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2012 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2015 insn
->ntok
= tok
- insn
->tok
;
2019 input_line_pointer
= old_input_line_pointer
;
2025 get_invisible_operands (TInsn
*insn
)
2027 xtensa_isa isa
= xtensa_default_isa
;
2028 static xtensa_insnbuf slotbuf
= NULL
;
2030 xtensa_opcode opc
= insn
->opcode
;
2031 int slot
, opnd
, fmt_found
;
2035 slotbuf
= xtensa_insnbuf_alloc (isa
);
2037 /* Find format/slot where this can be encoded. */
2040 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2042 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2044 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2050 if (fmt_found
) break;
2055 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2059 /* First encode all the visible operands
2060 (to deal with shared field operands). */
2061 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2063 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2064 && (insn
->tok
[opnd
].X_op
== O_register
2065 || insn
->tok
[opnd
].X_op
== O_constant
))
2067 val
= insn
->tok
[opnd
].X_add_number
;
2068 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2069 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2073 /* Then pull out the values for the invisible ones. */
2074 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2076 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2078 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2079 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2080 insn
->tok
[opnd
].X_add_number
= val
;
2081 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2082 insn
->tok
[opnd
].X_op
= O_register
;
2084 insn
->tok
[opnd
].X_op
= O_constant
;
2093 xg_reverse_shift_count (char **cnt_argp
)
2095 char *cnt_arg
, *new_arg
;
2096 cnt_arg
= *cnt_argp
;
2098 /* replace the argument with "31-(argument)" */
2099 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2100 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2103 *cnt_argp
= new_arg
;
2107 /* If "arg" is a constant expression, return non-zero with the value
2111 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2114 char *save_ptr
= input_line_pointer
;
2116 input_line_pointer
= arg
;
2118 input_line_pointer
= save_ptr
;
2120 if (exp
.X_op
== O_constant
)
2122 *valp
= exp
.X_add_number
;
2131 xg_replace_opname (char **popname
, char *newop
)
2134 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2135 strcpy (*popname
, newop
);
2140 xg_check_num_args (int *pnum_args
,
2145 int num_args
= *pnum_args
;
2147 if (num_args
< expected_num
)
2149 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2150 num_args
, opname
, expected_num
);
2154 if (num_args
> expected_num
)
2156 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2157 num_args
, opname
, expected_num
);
2158 while (num_args
-- > expected_num
)
2160 free (arg_strings
[num_args
]);
2161 arg_strings
[num_args
] = 0;
2163 *pnum_args
= expected_num
;
2171 /* If the register is not specified as part of the opcode,
2172 then get it from the operand and move it to the opcode. */
2175 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2177 xtensa_isa isa
= xtensa_default_isa
;
2179 char *opname
, *new_opname
;
2180 const char *sr_name
;
2181 int is_user
, is_write
;
2186 is_user
= (opname
[1] == 'u');
2187 is_write
= (opname
[0] == 'w');
2189 /* Opname == [rw]ur or [rwx]sr... */
2191 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2194 /* Check if the argument is a symbolic register name. */
2195 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2196 /* Handle WSR to "INTSET" as a special case. */
2197 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2198 && !strcasecmp (arg_strings
[1], "intset"))
2199 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2200 if (sr
== XTENSA_UNDEFINED
2201 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2203 /* Maybe it's a register number.... */
2205 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2207 as_bad (_("invalid register '%s' for '%s' instruction"),
2208 arg_strings
[1], opname
);
2211 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2212 if (sr
== XTENSA_UNDEFINED
)
2214 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2215 (long) val
, opname
);
2220 /* Remove the last argument, which is now part of the opcode. */
2221 free (arg_strings
[1]);
2225 /* Translate the opcode. */
2226 sr_name
= xtensa_sysreg_name (isa
, sr
);
2227 /* Another special case for "WSR.INTSET".... */
2228 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2230 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2231 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2233 *popname
= new_opname
;
2240 xtensa_translate_old_userreg_ops (char **popname
)
2242 xtensa_isa isa
= xtensa_default_isa
;
2244 char *opname
, *new_opname
;
2245 const char *sr_name
;
2246 bfd_boolean has_underbar
= FALSE
;
2249 if (opname
[0] == '_')
2251 has_underbar
= TRUE
;
2255 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2256 if (sr
!= XTENSA_UNDEFINED
)
2258 /* The new default name ("nnn") is different from the old default
2259 name ("URnnn"). The old default is handled below, and we don't
2260 want to recognize [RW]nnn, so do nothing if the name is the (new)
2262 static char namebuf
[10];
2263 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2264 if (strcmp (namebuf
, opname
+ 1) == 0)
2272 /* Only continue if the reg name is "URnnn". */
2273 if (opname
[1] != 'u' || opname
[2] != 'r')
2275 val
= strtoul (opname
+ 3, &end
, 10);
2279 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2280 if (sr
== XTENSA_UNDEFINED
)
2282 as_bad (_("invalid register number (%ld) for '%s'"),
2283 (long) val
, opname
);
2288 /* Translate the opcode. */
2289 sr_name
= xtensa_sysreg_name (isa
, sr
);
2290 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2291 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2292 opname
[0], sr_name
);
2294 *popname
= new_opname
;
2301 xtensa_translate_zero_immed (char *old_op
,
2311 assert (opname
[0] != '_');
2313 if (strcmp (opname
, old_op
) != 0)
2316 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2318 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2320 xg_replace_opname (popname
, new_op
);
2321 free (arg_strings
[1]);
2322 arg_strings
[1] = arg_strings
[2];
2331 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2332 Returns non-zero if an error was found. */
2335 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2337 char *opname
= *popname
;
2338 bfd_boolean has_underbar
= FALSE
;
2342 has_underbar
= TRUE
;
2346 if (strcmp (opname
, "mov") == 0)
2348 if (use_transform () && !has_underbar
&& density_supported
)
2349 xg_replace_opname (popname
, "mov.n");
2352 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2354 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2355 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2356 strcpy (arg_strings
[2], arg_strings
[1]);
2362 if (strcmp (opname
, "bbsi.l") == 0)
2364 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2366 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2367 if (target_big_endian
)
2368 xg_reverse_shift_count (&arg_strings
[1]);
2372 if (strcmp (opname
, "bbci.l") == 0)
2374 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2376 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2377 if (target_big_endian
)
2378 xg_reverse_shift_count (&arg_strings
[1]);
2382 /* Don't do anything special with NOPs inside FLIX instructions. They
2383 are handled elsewhere. Real NOP instructions are always available
2384 in configurations with FLIX, so this should never be an issue but
2385 check for it anyway. */
2386 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2387 && strcmp (opname
, "nop") == 0)
2389 if (use_transform () && !has_underbar
&& density_supported
)
2390 xg_replace_opname (popname
, "nop.n");
2393 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2395 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2396 arg_strings
[0] = (char *) xmalloc (3);
2397 arg_strings
[1] = (char *) xmalloc (3);
2398 arg_strings
[2] = (char *) xmalloc (3);
2399 strcpy (arg_strings
[0], "a1");
2400 strcpy (arg_strings
[1], "a1");
2401 strcpy (arg_strings
[2], "a1");
2407 /* Recognize [RW]UR and [RWX]SR. */
2408 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2409 && (opname
[1] == 'u' || opname
[1] == 's'))
2410 || (opname
[0] == 'x' && opname
[1] == 's'))
2412 && opname
[3] == '\0')
2413 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2415 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2416 [RW]<name> if <name> is the non-default name of a user register. */
2417 if ((opname
[0] == 'r' || opname
[0] == 'w')
2418 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2419 return xtensa_translate_old_userreg_ops (popname
);
2421 /* Relax branches that don't allow comparisons against an immediate value
2422 of zero to the corresponding branches with implicit zero immediates. */
2423 if (!has_underbar
&& use_transform ())
2425 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2426 pnum_args
, arg_strings
))
2429 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2430 pnum_args
, arg_strings
))
2433 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2434 pnum_args
, arg_strings
))
2437 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2438 pnum_args
, arg_strings
))
2446 /* Functions for dealing with the Xtensa ISA. */
2448 /* Currently the assembler only allows us to use a single target per
2449 fragment. Because of this, only one operand for a given
2450 instruction may be symbolic. If there is a PC-relative operand,
2451 the last one is chosen. Otherwise, the result is the number of the
2452 last immediate operand, and if there are none of those, we fail and
2456 get_relaxable_immed (xtensa_opcode opcode
)
2458 int last_immed
= -1;
2461 if (opcode
== XTENSA_UNDEFINED
)
2464 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2465 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2467 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2469 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2471 if (last_immed
== -1
2472 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2479 static xtensa_opcode
2480 get_opcode_from_buf (const char *buf
, int slot
)
2482 static xtensa_insnbuf insnbuf
= NULL
;
2483 static xtensa_insnbuf slotbuf
= NULL
;
2484 xtensa_isa isa
= xtensa_default_isa
;
2489 insnbuf
= xtensa_insnbuf_alloc (isa
);
2490 slotbuf
= xtensa_insnbuf_alloc (isa
);
2493 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2494 fmt
= xtensa_format_decode (isa
, insnbuf
);
2495 if (fmt
== XTENSA_UNDEFINED
)
2496 return XTENSA_UNDEFINED
;
2498 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2499 return XTENSA_UNDEFINED
;
2501 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2502 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2506 #ifdef TENSILICA_DEBUG
2508 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2511 xtensa_print_insn_table (void)
2513 int num_opcodes
, num_operands
;
2514 xtensa_opcode opcode
;
2515 xtensa_isa isa
= xtensa_default_isa
;
2517 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2518 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2521 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2522 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2523 for (opn
= 0; opn
< num_operands
; opn
++)
2525 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2527 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2529 xtensa_regfile opnd_rf
=
2530 xtensa_operand_regfile (isa
, opcode
, opn
);
2531 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2533 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2534 fputs ("[lLr] ", stderr
);
2536 fputs ("i ", stderr
);
2538 fprintf (stderr
, "\n");
2544 print_vliw_insn (xtensa_insnbuf vbuf
)
2546 xtensa_isa isa
= xtensa_default_isa
;
2547 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2548 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2551 fprintf (stderr
, "format = %d\n", f
);
2553 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2555 xtensa_opcode opcode
;
2559 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2560 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2561 opname
= xtensa_opcode_name (isa
, opcode
);
2563 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2564 fprintf (stderr
, " operands = ");
2566 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2570 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2572 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2573 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2574 fprintf (stderr
, "%d ", val
);
2576 fprintf (stderr
, "\n");
2578 xtensa_insnbuf_free (isa
, sbuf
);
2581 #endif /* TENSILICA_DEBUG */
2585 is_direct_call_opcode (xtensa_opcode opcode
)
2587 xtensa_isa isa
= xtensa_default_isa
;
2588 int n
, num_operands
;
2590 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2593 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2594 for (n
= 0; n
< num_operands
; n
++)
2596 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2597 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2604 /* Convert from BFD relocation type code to slot and operand number.
2605 Returns non-zero on failure. */
2608 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2610 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2611 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2613 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2616 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2617 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2619 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2629 /* Convert from slot number to BFD relocation type code for the
2630 standard PC-relative relocations. Return BFD_RELOC_NONE on
2633 static bfd_reloc_code_real_type
2634 encode_reloc (int slot
)
2636 if (slot
< 0 || slot
> 14)
2637 return BFD_RELOC_NONE
;
2639 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2643 /* Convert from slot numbers to BFD relocation type code for the
2644 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2646 static bfd_reloc_code_real_type
2647 encode_alt_reloc (int slot
)
2649 if (slot
< 0 || slot
> 14)
2650 return BFD_RELOC_NONE
;
2652 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2657 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2660 xtensa_opcode opcode
,
2666 uint32 valbuf
= value
;
2668 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2670 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2672 as_bad_where ((char *) file
, line
,
2673 _("operand %d of '%s' has out of range value '%u'"),
2675 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2678 as_bad_where ((char *) file
, line
,
2679 _("operand %d of '%s' has invalid value '%u'"),
2681 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2686 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2692 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2695 xtensa_opcode opcode
,
2699 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2700 fmt
, slot
, slotbuf
, &val
);
2701 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2706 /* Checks for rules from xtensa-relax tables. */
2708 /* The routine xg_instruction_matches_option_term must return TRUE
2709 when a given option term is true. The meaning of all of the option
2710 terms is given interpretation by this function. This is needed when
2711 an option depends on the state of a directive, but there are no such
2712 options in use right now. */
2715 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2716 const ReqOrOption
*option
)
2718 if (strcmp (option
->option_name
, "realnop") == 0
2719 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2721 /* These conditions were evaluated statically when building the
2722 relaxation table. There's no need to reevaluate them now. */
2727 as_fatal (_("internal error: unknown option name '%s'"),
2728 option
->option_name
);
2734 xg_instruction_matches_or_options (TInsn
*insn
,
2735 const ReqOrOptionList
*or_option
)
2737 const ReqOrOption
*option
;
2738 /* Must match each of the AND terms. */
2739 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2741 if (xg_instruction_matches_option_term (insn
, option
))
2749 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2751 const ReqOption
*req_options
;
2752 /* Must match each of the AND terms. */
2753 for (req_options
= options
;
2754 req_options
!= NULL
;
2755 req_options
= req_options
->next
)
2757 /* Must match one of the OR clauses. */
2758 if (!xg_instruction_matches_or_options (insn
,
2759 req_options
->or_option_terms
))
2766 /* Return the transition rule that matches or NULL if none matches. */
2769 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2771 PreconditionList
*condition_l
;
2773 if (rule
->opcode
!= insn
->opcode
)
2776 for (condition_l
= rule
->conditions
;
2777 condition_l
!= NULL
;
2778 condition_l
= condition_l
->next
)
2782 Precondition
*cond
= condition_l
->precond
;
2787 /* The expression must be the constant. */
2788 assert (cond
->op_num
< insn
->ntok
);
2789 exp1
= &insn
->tok
[cond
->op_num
];
2790 if (expr_is_const (exp1
))
2795 if (get_expr_const (exp1
) != cond
->op_data
)
2799 if (get_expr_const (exp1
) == cond
->op_data
)
2806 else if (expr_is_register (exp1
))
2811 if (get_expr_register (exp1
) != cond
->op_data
)
2815 if (get_expr_register (exp1
) == cond
->op_data
)
2827 assert (cond
->op_num
< insn
->ntok
);
2828 assert (cond
->op_data
< insn
->ntok
);
2829 exp1
= &insn
->tok
[cond
->op_num
];
2830 exp2
= &insn
->tok
[cond
->op_data
];
2835 if (!expr_is_equal (exp1
, exp2
))
2839 if (expr_is_equal (exp1
, exp2
))
2851 if (!xg_instruction_matches_options (insn
, rule
->options
))
2859 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2861 bfd_boolean a_greater
= FALSE
;
2862 bfd_boolean b_greater
= FALSE
;
2864 ReqOptionList
*l_a
= a
->options
;
2865 ReqOptionList
*l_b
= b
->options
;
2867 /* We only care if they both are the same except for
2868 a const16 vs. an l32r. */
2870 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2872 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2873 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2874 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2876 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2878 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2880 /* This is the case we care about. */
2881 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2882 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2889 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2890 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2900 l_or_a
= l_or_a
->next
;
2901 l_or_b
= l_or_b
->next
;
2903 if (l_or_a
|| l_or_b
)
2912 /* Incomparable if the substitution was used differently in two cases. */
2913 if (a_greater
&& b_greater
)
2925 static TransitionRule
*
2926 xg_instruction_match (TInsn
*insn
)
2928 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2930 assert (insn
->opcode
< table
->num_opcodes
);
2932 /* Walk through all of the possible transitions. */
2933 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2935 TransitionRule
*rule
= l
->rule
;
2936 if (xg_instruction_matches_rule (insn
, rule
))
2943 /* Various Other Internal Functions. */
2946 is_unique_insn_expansion (TransitionRule
*r
)
2948 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2950 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2956 /* Check if there is exactly one relaxation for INSN that converts it to
2957 another instruction of equal or larger size. If so, and if TARG is
2958 non-null, go ahead and generate the relaxed instruction into TARG. If
2959 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2960 instruction, i.e., ignore relaxations that convert to an instruction of
2961 equal size. In some contexts where this function is used, only
2962 a single widening is allowed and the NARROW_ONLY argument is used to
2963 exclude cases like ADDI being "widened" to an ADDMI, which may
2964 later be relaxed to an ADDMI/ADDI pair. */
2967 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2969 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2971 TransitionRule
*match
= 0;
2973 assert (insn
->insn_type
== ITYPE_INSN
);
2974 assert (insn
->opcode
< table
->num_opcodes
);
2976 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2978 TransitionRule
*rule
= l
->rule
;
2980 if (xg_instruction_matches_rule (insn
, rule
)
2981 && is_unique_insn_expansion (rule
)
2982 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2983 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2994 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2999 /* Return the maximum number of bytes this opcode can expand to. */
3002 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3004 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3006 int max_size
= xg_get_single_size (opcode
);
3008 assert (opcode
< table
->num_opcodes
);
3010 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3012 TransitionRule
*rule
= l
->rule
;
3013 BuildInstr
*build_list
;
3018 build_list
= rule
->to_instr
;
3019 if (is_unique_insn_expansion (rule
))
3021 assert (build_list
->typ
== INSTR_INSTR
);
3022 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3025 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3027 switch (build_list
->typ
)
3030 this_size
+= xg_get_single_size (build_list
->opcode
);
3032 case INSTR_LITERAL_DEF
:
3033 case INSTR_LABEL_DEF
:
3038 if (this_size
> max_size
)
3039 max_size
= this_size
;
3045 /* Return the maximum number of literal bytes this opcode can generate. */
3048 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3050 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 assert (opcode
< table
->num_opcodes
);
3056 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3058 TransitionRule
*rule
= l
->rule
;
3059 BuildInstr
*build_list
;
3064 build_list
= rule
->to_instr
;
3065 if (is_unique_insn_expansion (rule
))
3067 assert (build_list
->typ
== INSTR_INSTR
);
3068 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3071 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3073 switch (build_list
->typ
)
3075 case INSTR_LITERAL_DEF
:
3076 /* Hard-coded 4-byte literal. */
3080 case INSTR_LABEL_DEF
:
3085 if (this_size
> max_size
)
3086 max_size
= this_size
;
3093 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3095 int steps_taken
= 0;
3096 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3099 assert (insn
->insn_type
== ITYPE_INSN
);
3100 assert (insn
->opcode
< table
->num_opcodes
);
3102 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3104 TransitionRule
*rule
= l
->rule
;
3106 if (xg_instruction_matches_rule (insn
, rule
))
3108 if (steps_taken
== lateral_steps
)
3118 get_special_literal_symbol (void)
3120 static symbolS
*sym
= NULL
;
3123 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3129 get_special_label_symbol (void)
3131 static symbolS
*sym
= NULL
;
3134 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3140 xg_valid_literal_expression (const expressionS
*exp
)
3157 /* This will check to see if the value can be converted into the
3158 operand type. It will return TRUE if it does not fit. */
3161 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3163 uint32 valbuf
= value
;
3164 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3170 /* Assumes: All immeds are constants. Check that all constants fit
3171 into their immeds; return FALSE if not. */
3174 xg_immeds_fit (const TInsn
*insn
)
3176 xtensa_isa isa
= xtensa_default_isa
;
3180 assert (insn
->insn_type
== ITYPE_INSN
);
3181 for (i
= 0; i
< n
; ++i
)
3183 const expressionS
*expr
= &insn
->tok
[i
];
3184 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3191 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3196 /* The symbol should have a fixup associated with it. */
3205 /* This should only be called after we have an initial
3206 estimate of the addresses. */
3209 xg_symbolic_immeds_fit (const TInsn
*insn
,
3215 xtensa_isa isa
= xtensa_default_isa
;
3223 assert (insn
->insn_type
== ITYPE_INSN
);
3225 for (i
= 0; i
< n
; ++i
)
3227 const expressionS
*expr
= &insn
->tok
[i
];
3228 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3235 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3241 /* Check for the worst case. */
3242 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3247 /* We only allow symbols for PC-relative references.
3248 If pc_frag == 0, then we don't have frag locations yet. */
3250 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3253 /* If it is a weak symbol, then assume it won't reach. */
3254 if (S_IS_WEAK (expr
->X_add_symbol
))
3257 if (is_direct_call_opcode (insn
->opcode
)
3258 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3260 /* If callee is undefined or in a different segment, be
3261 optimistic and assume it will be in range. */
3262 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3266 /* Only references within a segment can be known to fit in the
3267 operands at assembly time. */
3268 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3271 symbolP
= expr
->X_add_symbol
;
3272 sym_frag
= symbol_get_frag (symbolP
);
3273 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3274 pc
= pc_frag
->fr_address
+ pc_offset
;
3276 /* If frag has yet to be reached on this pass, assume it
3277 will move by STRETCH just as we did. If this is not so,
3278 it will be because some frag between grows, and that will
3279 force another pass. Beware zero-length frags. There
3280 should be a faster way to do this. */
3283 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3284 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3289 new_offset
= target
;
3290 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3291 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3296 /* The symbol should have a fixup associated with it. */
3305 /* Return TRUE on success. */
3308 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3314 targ
->linenum
= insn
->linenum
;
3319 targ
->opcode
= bi
->opcode
;
3320 targ
->insn_type
= ITYPE_INSN
;
3321 targ
->is_specific_opcode
= FALSE
;
3323 for (; op
!= NULL
; op
= op
->next
)
3325 int op_num
= op
->op_num
;
3326 int op_data
= op
->op_data
;
3328 assert (op
->op_num
< MAX_INSN_ARGS
);
3330 if (targ
->ntok
<= op_num
)
3331 targ
->ntok
= op_num
+ 1;
3336 set_expr_const (&targ
->tok
[op_num
], op_data
);
3339 assert (op_data
< insn
->ntok
);
3340 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3343 sym
= get_special_literal_symbol ();
3344 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3347 sym
= get_special_label_symbol ();
3348 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3350 case OP_OPERAND_HI16U
:
3351 case OP_OPERAND_LOW16U
:
3352 assert (op_data
< insn
->ntok
);
3353 if (expr_is_const (&insn
->tok
[op_data
]))
3356 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3357 val
= xg_apply_userdef_op_fn (op
->typ
,
3360 targ
->tok
[op_num
].X_add_number
= val
;
3364 /* For const16 we can create relocations for these. */
3365 if (targ
->opcode
== XTENSA_UNDEFINED
3366 || (targ
->opcode
!= xtensa_const16_opcode
))
3368 assert (op_data
< insn
->ntok
);
3369 /* Need to build a O_lo16 or O_hi16. */
3370 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3371 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3373 if (op
->typ
== OP_OPERAND_HI16U
)
3374 targ
->tok
[op_num
].X_op
= O_hi16
;
3375 else if (op
->typ
== OP_OPERAND_LOW16U
)
3376 targ
->tok
[op_num
].X_op
= O_lo16
;
3383 /* currently handles:
3386 OP_OPERAND_F32MINUS */
3387 if (xg_has_userdef_op_fn (op
->typ
))
3389 assert (op_data
< insn
->ntok
);
3390 if (expr_is_const (&insn
->tok
[op_data
]))
3393 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3394 val
= xg_apply_userdef_op_fn (op
->typ
,
3397 targ
->tok
[op_num
].X_add_number
= val
;
3400 return FALSE
; /* We cannot use a relocation for this. */
3409 case INSTR_LITERAL_DEF
:
3411 targ
->opcode
= XTENSA_UNDEFINED
;
3412 targ
->insn_type
= ITYPE_LITERAL
;
3413 targ
->is_specific_opcode
= FALSE
;
3414 for (; op
!= NULL
; op
= op
->next
)
3416 int op_num
= op
->op_num
;
3417 int op_data
= op
->op_data
;
3418 assert (op
->op_num
< MAX_INSN_ARGS
);
3420 if (targ
->ntok
<= op_num
)
3421 targ
->ntok
= op_num
+ 1;
3426 assert (op_data
< insn
->ntok
);
3427 /* We can only pass resolvable literals through. */
3428 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3430 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3442 case INSTR_LABEL_DEF
:
3444 targ
->opcode
= XTENSA_UNDEFINED
;
3445 targ
->insn_type
= ITYPE_LABEL
;
3446 targ
->is_specific_opcode
= FALSE
;
3447 /* Literal with no ops is a label? */
3448 assert (op
== NULL
);
3459 /* Return TRUE on success. */
3462 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3464 for (; bi
!= NULL
; bi
= bi
->next
)
3466 TInsn
*next_insn
= istack_push_space (istack
);
3468 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3475 /* Return TRUE on valid expansion. */
3478 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3480 int stack_size
= istack
->ninsn
;
3481 int steps_taken
= 0;
3482 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3485 assert (insn
->insn_type
== ITYPE_INSN
);
3486 assert (insn
->opcode
< table
->num_opcodes
);
3488 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3490 TransitionRule
*rule
= l
->rule
;
3492 if (xg_instruction_matches_rule (insn
, rule
))
3494 if (lateral_steps
== steps_taken
)
3498 /* This is it. Expand the rule to the stack. */
3499 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3502 /* Check to see if it fits. */
3503 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3505 TInsn
*insn
= &istack
->insn
[i
];
3507 if (insn
->insn_type
== ITYPE_INSN
3508 && !tinsn_has_symbolic_operands (insn
)
3509 && !xg_immeds_fit (insn
))
3511 istack
->ninsn
= stack_size
;
3524 /* Relax the assembly instruction at least "min_steps".
3525 Return the number of steps taken. */
3528 xg_assembly_relax (IStack
*istack
,
3531 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3532 offsetT pc_offset
, /* offset in fragment */
3533 int min_steps
, /* minimum conversion steps */
3534 long stretch
) /* number of bytes stretched so far */
3536 int steps_taken
= 0;
3538 /* assert (has no symbolic operands)
3539 Some of its immeds don't fit.
3540 Try to build a relaxed version.
3541 This may go through a couple of stages
3542 of single instruction transformations before
3545 TInsn single_target
;
3547 int lateral_steps
= 0;
3548 int istack_size
= istack
->ninsn
;
3550 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3551 && steps_taken
>= min_steps
)
3553 istack_push (istack
, insn
);
3556 current_insn
= *insn
;
3558 /* Walk through all of the single instruction expansions. */
3559 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3562 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3565 if (steps_taken
>= min_steps
)
3567 istack_push (istack
, &single_target
);
3571 current_insn
= single_target
;
3574 /* Now check for a multi-instruction expansion. */
3575 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3577 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3580 if (steps_taken
>= min_steps
)
3582 istack_push (istack
, ¤t_insn
);
3587 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3589 if (steps_taken
>= min_steps
)
3593 istack
->ninsn
= istack_size
;
3596 /* It's not going to work -- use the original. */
3597 istack_push (istack
, insn
);
3603 xg_force_frag_space (int size
)
3605 /* This may have the side effect of creating a new fragment for the
3606 space to go into. I just do not like the name of the "frag"
3613 xg_finish_frag (char *last_insn
,
3614 enum xtensa_relax_statesE frag_state
,
3615 enum xtensa_relax_statesE slot0_state
,
3617 bfd_boolean is_insn
)
3619 /* Finish off this fragment so that it has at LEAST the desired
3620 max_growth. If it doesn't fit in this fragment, close this one
3621 and start a new one. In either case, return a pointer to the
3622 beginning of the growth area. */
3626 xg_force_frag_space (max_growth
);
3628 old_frag
= frag_now
;
3630 frag_now
->fr_opcode
= last_insn
;
3632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3634 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3635 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3637 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3638 xtensa_set_frag_assembly_state (frag_now
);
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag
->fr_next
== frag_now
);
3645 /* Return TRUE if the target frag is one of the next non-empty frags. */
3648 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3653 for (; fragP
; fragP
= fragP
->fr_next
)
3655 if (fragP
== target
)
3657 if (fragP
->fr_fix
!= 0)
3659 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3661 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3662 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3664 if (fragP
->fr_type
== rs_space
)
3672 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3674 xtensa_isa isa
= xtensa_default_isa
;
3676 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3681 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3682 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3685 for (i
= 0; i
< num_ops
; i
++)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3693 if (target_op
== -1)
3696 if (insn
->ntok
<= target_op
)
3699 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3702 sym
= insn
->tok
[target_op
].X_add_symbol
;
3706 if (insn
->tok
[target_op
].X_add_number
!= 0)
3709 target_frag
= symbol_get_frag (sym
);
3710 if (target_frag
== NULL
)
3713 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3714 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3722 xg_add_branch_and_loop_targets (TInsn
*insn
)
3724 xtensa_isa isa
= xtensa_default_isa
;
3725 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3727 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3730 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3731 && insn
->tok
[i
].X_op
== O_symbol
)
3732 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3736 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3737 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3741 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3746 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3747 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3748 if (S_IS_DEFINED (sym
))
3749 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3756 /* Return FALSE if no error. */
3759 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3764 switch (instr_spec
->typ
)
3767 new_insn
->insn_type
= ITYPE_INSN
;
3768 new_insn
->opcode
= instr_spec
->opcode
;
3769 new_insn
->is_specific_opcode
= FALSE
;
3770 new_insn
->linenum
= old_insn
->linenum
;
3772 case INSTR_LITERAL_DEF
:
3773 new_insn
->insn_type
= ITYPE_LITERAL
;
3774 new_insn
->opcode
= XTENSA_UNDEFINED
;
3775 new_insn
->is_specific_opcode
= FALSE
;
3776 new_insn
->linenum
= old_insn
->linenum
;
3778 case INSTR_LABEL_DEF
:
3779 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3783 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3786 const expressionS
*src_exp
;
3792 /* The expression must be the constant. */
3793 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3794 exp
= &new_insn
->tok
[b_op
->op_num
];
3795 set_expr_const (exp
, b_op
->op_data
);
3799 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3800 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3801 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3802 exp
= &new_insn
->tok
[b_op
->op_num
];
3803 copy_expr (exp
, src_exp
);
3808 as_bad (_("can't handle generation of literal/labels yet"));
3812 as_bad (_("can't handle undefined OP TYPE"));
3817 new_insn
->ntok
= num_ops
;
3822 /* Return TRUE if it was simplified. */
3825 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3827 TransitionRule
*rule
;
3828 BuildInstr
*insn_spec
;
3830 if (old_insn
->is_specific_opcode
|| !density_supported
)
3833 rule
= xg_instruction_match (old_insn
);
3837 insn_spec
= rule
->to_instr
;
3838 /* There should only be one. */
3839 assert (insn_spec
!= NULL
);
3840 assert (insn_spec
->next
== NULL
);
3841 if (insn_spec
->next
!= NULL
)
3844 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3850 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3851 l32i.n. (2) Check the number of operands. (3) Place the instruction
3852 tokens into the stack or relax it and place multiple
3853 instructions/literals onto the stack. Return FALSE if no error. */
3856 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3860 bfd_boolean do_expand
;
3862 tinsn_init (&new_insn
);
3864 /* Narrow it if we can. xg_simplify_insn now does all the
3865 appropriate checking (e.g., for the density option). */
3866 if (xg_simplify_insn (orig_insn
, &new_insn
))
3867 orig_insn
= &new_insn
;
3869 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3871 if (orig_insn
->ntok
< noperands
)
3873 as_bad (_("found %d operands for '%s': Expected %d"),
3875 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3879 if (orig_insn
->ntok
> noperands
)
3880 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3882 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3885 /* If there are not enough operands, we will assert above. If there
3886 are too many, just cut out the extras here. */
3887 orig_insn
->ntok
= noperands
;
3889 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3892 /* If the instruction will definitely need to be relaxed, it is better
3893 to expand it now for better scheduling. Decide whether to expand
3895 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3897 /* Calls should be expanded to longcalls only in the backend relaxation
3898 so that the assembly scheduler will keep the L32R/CALLX instructions
3900 if (is_direct_call_opcode (orig_insn
->opcode
))
3903 if (tinsn_has_symbolic_operands (orig_insn
))
3905 /* The values of symbolic operands are not known yet, so only expand
3906 now if an operand is "complex" (e.g., difference of symbols) and
3907 will have to be stored as a literal regardless of the value. */
3908 if (!tinsn_has_complex_operands (orig_insn
))
3911 else if (xg_immeds_fit (orig_insn
))
3915 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3917 istack_push (istack
, orig_insn
);
3923 /* Return TRUE if the section flags are marked linkonce
3924 or the name is .gnu.linkonce.*. */
3926 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3929 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3931 flagword flags
, link_once_flags
;
3933 flags
= bfd_get_section_flags (abfd
, sec
);
3934 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3936 /* Flags might not be set yet. */
3937 if (!link_once_flags
3938 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3939 link_once_flags
= SEC_LINK_ONCE
;
3941 return (link_once_flags
!= 0);
3946 xtensa_add_literal_sym (symbolS
*sym
)
3950 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3952 l
->next
= literal_syms
;
3958 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3960 static int lit_num
= 0;
3961 static char name
[256];
3964 sprintf (name
, ".L_lit_sym%d", lit_num
);
3966 /* Create a local symbol. If it is in a linkonce section, we have to
3967 be careful to make sure that if it is used in a relocation that the
3968 symbol will be in the output file. */
3969 if (get_is_linkonce_section (stdoutput
, sec
))
3971 symbolP
= symbol_new (name
, sec
, 0, frag
);
3972 S_CLEAR_EXTERNAL (symbolP
);
3973 /* symbolP->local = 1; */
3976 symbolP
= symbol_new (name
, sec
, 0, frag
);
3978 xtensa_add_literal_sym (symbolP
);
3985 /* Currently all literals that are generated here are 32-bit L32R targets. */
3988 xg_assemble_literal (/* const */ TInsn
*insn
)
3991 symbolS
*lit_sym
= NULL
;
3992 bfd_reloc_code_real_type reloc
;
3995 /* size = 4 for L32R. It could easily be larger when we move to
3996 larger constants. Add a parameter later. */
3997 offsetT litsize
= 4;
3998 offsetT litalign
= 2; /* 2^2 = 4 */
3999 expressionS saved_loc
;
4000 expressionS
* emit_val
;
4002 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4004 assert (insn
->insn_type
== ITYPE_LITERAL
);
4005 assert (insn
->ntok
== 1); /* must be only one token here */
4007 xtensa_switch_to_literal_fragment (&state
);
4009 emit_val
= &insn
->tok
[0];
4010 if (emit_val
->X_op
== O_big
)
4012 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4015 /* This happens when someone writes a "movi a2, big_number". */
4016 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4017 _("invalid immediate"));
4018 xtensa_restore_emit_state (&state
);
4023 /* Force a 4-byte align here. Note that this opens a new frag, so all
4024 literals done with this function have a frag to themselves. That's
4025 important for the way text section literals work. */
4026 frag_align (litalign
, 0, 0);
4027 record_alignment (now_seg
, litalign
);
4029 switch (emit_val
->X_op
)
4032 p
= frag_more (litsize
);
4033 xtensa_set_frag_assembly_state (frag_now
);
4034 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4035 if (emit_val
->X_add_symbol
)
4036 emit_val
->X_op
= O_symbol
;
4038 emit_val
->X_op
= O_constant
;
4039 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4040 litsize
, emit_val
, 0, reloc
);
4044 emit_expr (emit_val
, litsize
);
4048 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4049 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4050 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4051 lit_sym
= frag_now
->fr_symbol
;
4054 xtensa_restore_emit_state (&state
);
4060 xg_assemble_literal_space (/* const */ int size
, int slot
)
4063 /* We might have to do something about this alignment. It only
4064 takes effect if something is placed here. */
4065 offsetT litalign
= 2; /* 2^2 = 4 */
4066 fragS
*lit_saved_frag
;
4068 assert (size
% 4 == 0);
4070 xtensa_switch_to_literal_fragment (&state
);
4072 /* Force a 4-byte align here. */
4073 frag_align (litalign
, 0, 0);
4074 record_alignment (now_seg
, litalign
);
4076 xg_force_frag_space (size
);
4078 lit_saved_frag
= frag_now
;
4079 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4080 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4081 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4084 xtensa_restore_emit_state (&state
);
4085 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4089 /* Put in a fixup record based on the opcode.
4090 Return TRUE on success. */
4093 xg_add_opcode_fix (TInsn
*tinsn
,
4101 xtensa_opcode opcode
= tinsn
->opcode
;
4102 bfd_reloc_code_real_type reloc
;
4103 reloc_howto_type
*howto
;
4107 reloc
= BFD_RELOC_NONE
;
4109 /* First try the special cases for "alternate" relocs. */
4110 if (opcode
== xtensa_l32r_opcode
)
4112 if (fragP
->tc_frag_data
.use_absolute_literals
)
4113 reloc
= encode_alt_reloc (slot
);
4115 else if (opcode
== xtensa_const16_opcode
)
4117 if (expr
->X_op
== O_lo16
)
4119 reloc
= encode_reloc (slot
);
4120 expr
->X_op
= O_symbol
;
4122 else if (expr
->X_op
== O_hi16
)
4124 reloc
= encode_alt_reloc (slot
);
4125 expr
->X_op
= O_symbol
;
4129 if (opnum
!= get_relaxable_immed (opcode
))
4131 as_bad (_("invalid relocation for operand %i of '%s'"),
4132 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4136 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4137 into the symbol table where the generic portions of the assembler
4138 won't know what to do with them. */
4139 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4141 as_bad (_("invalid expression for operand %i of '%s'"),
4142 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4146 /* Next try the generic relocs. */
4147 if (reloc
== BFD_RELOC_NONE
)
4148 reloc
= encode_reloc (slot
);
4149 if (reloc
== BFD_RELOC_NONE
)
4151 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4155 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4158 as_bad (_("undefined symbol for opcode \"%s\""),
4159 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4163 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4164 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4165 howto
->pc_relative
, reloc
);
4166 the_fix
->fx_no_overflow
= 1;
4167 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4168 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4169 the_fix
->tc_fix_data
.slot
= slot
;
4176 xg_emit_insn_to_buf (TInsn
*tinsn
,
4180 bfd_boolean build_fix
)
4182 static xtensa_insnbuf insnbuf
= NULL
;
4183 bfd_boolean has_symbolic_immed
= FALSE
;
4184 bfd_boolean ok
= TRUE
;
4187 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4189 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4190 if (has_symbolic_immed
&& build_fix
)
4193 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4194 int slot
= xg_get_single_slot (tinsn
->opcode
);
4195 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4196 expressionS
*exp
= &tinsn
->tok
[opnum
];
4198 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4201 fragP
->tc_frag_data
.is_insn
= TRUE
;
4202 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4203 (unsigned char *) buf
, 0);
4209 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4211 symbolS
*sym
= get_special_literal_symbol ();
4215 assert (insn
->insn_type
== ITYPE_INSN
);
4216 for (i
= 0; i
< insn
->ntok
; i
++)
4217 if (insn
->tok
[i
].X_add_symbol
== sym
)
4218 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4224 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4226 symbolS
*sym
= get_special_label_symbol ();
4228 for (i
= 0; i
< insn
->ntok
; i
++)
4229 if (insn
->tok
[i
].X_add_symbol
== sym
)
4230 insn
->tok
[i
].X_add_symbol
= label_sym
;
4235 /* Return TRUE if the instruction can write to the specified
4236 integer register. */
4239 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4243 xtensa_isa isa
= xtensa_default_isa
;
4245 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4247 for (i
= 0; i
< num_ops
; i
++)
4250 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4251 if ((inout
== 'o' || inout
== 'm')
4252 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4254 xtensa_regfile opnd_rf
=
4255 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4256 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4258 if ((insn
->tok
[i
].X_op
== O_register
)
4259 && (insn
->tok
[i
].X_add_number
== regnum
))
4269 is_bad_loopend_opcode (const TInsn
*tinsn
)
4271 xtensa_opcode opcode
= tinsn
->opcode
;
4273 if (opcode
== XTENSA_UNDEFINED
)
4276 if (opcode
== xtensa_call0_opcode
4277 || opcode
== xtensa_callx0_opcode
4278 || opcode
== xtensa_call4_opcode
4279 || opcode
== xtensa_callx4_opcode
4280 || opcode
== xtensa_call8_opcode
4281 || opcode
== xtensa_callx8_opcode
4282 || opcode
== xtensa_call12_opcode
4283 || opcode
== xtensa_callx12_opcode
4284 || opcode
== xtensa_isync_opcode
4285 || opcode
== xtensa_ret_opcode
4286 || opcode
== xtensa_ret_n_opcode
4287 || opcode
== xtensa_retw_opcode
4288 || opcode
== xtensa_retw_n_opcode
4289 || opcode
== xtensa_waiti_opcode
4290 || opcode
== xtensa_rsr_lcount_opcode
)
4297 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4298 This allows the debugger to add unaligned labels.
4299 Also, the assembler generates stabs labels that need
4300 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4303 is_unaligned_label (symbolS
*sym
)
4305 const char *name
= S_GET_NAME (sym
);
4306 static size_t fake_size
= 0;
4310 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4313 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4315 fake_size
= strlen (FAKE_LABEL_NAME
);
4318 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4319 && (name
[fake_size
] == 'F'
4320 || name
[fake_size
] == 'L'
4321 || (name
[fake_size
] == 'e'
4322 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4330 next_non_empty_frag (const fragS
*fragP
)
4332 fragS
*next_fragP
= fragP
->fr_next
;
4334 /* Sometimes an empty will end up here due storage allocation issues.
4335 So we have to skip until we find something legit. */
4336 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4337 next_fragP
= next_fragP
->fr_next
;
4339 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4347 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4349 xtensa_opcode out_opcode
;
4350 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4352 if (next_fragP
== NULL
)
4355 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4356 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4358 *opcode
= out_opcode
;
4366 frag_format_size (const fragS
*fragP
)
4368 static xtensa_insnbuf insnbuf
= NULL
;
4369 xtensa_isa isa
= xtensa_default_isa
;
4374 insnbuf
= xtensa_insnbuf_alloc (isa
);
4377 return XTENSA_UNDEFINED
;
4379 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4380 (unsigned char *) fragP
->fr_literal
, 0);
4382 fmt
= xtensa_format_decode (isa
, insnbuf
);
4383 if (fmt
== XTENSA_UNDEFINED
)
4384 return XTENSA_UNDEFINED
;
4385 fmt_size
= xtensa_format_length (isa
, fmt
);
4387 /* If the next format won't be changing due to relaxation, just
4388 return the length of the first format. */
4389 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4392 /* If during relaxation we have to pull an instruction out of a
4393 multi-slot instruction, we will return the more conservative
4394 number. This works because alignment on bigger instructions
4395 is more restrictive than alignment on smaller instructions.
4396 This is more conservative than we would like, but it happens
4399 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4402 /* If we aren't doing one of our own relaxations or it isn't
4403 slot-based, then the insn size won't change. */
4404 if (fragP
->fr_type
!= rs_machine_dependent
)
4406 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4409 /* If an instruction is about to grow, return the longer size. */
4410 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4411 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4414 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4415 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4422 next_frag_format_size (const fragS
*fragP
)
4424 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4425 return frag_format_size (next_fragP
);
4429 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4430 required two-byte instructions to be treated as three-byte instructions
4431 for loop instruction alignment. This restriction was removed beginning
4432 with Xtensa LX. Now the only requirement on loop instruction alignment
4433 is that the first instruction of the loop must appear at an address that
4434 does not cross a fetch boundary. */
4437 get_loop_align_size (int insn_size
)
4439 if (insn_size
== XTENSA_UNDEFINED
)
4440 return xtensa_fetch_width
;
4442 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4449 /* If the next legit fragment is an end-of-loop marker,
4450 switch its state so it will instantiate a NOP. */
4453 update_next_frag_state (fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4456 fragS
*new_target
= NULL
;
4460 /* We are guaranteed there will be one of these... */
4461 while (!(next_fragP
->fr_type
== rs_machine_dependent
4462 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4463 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4464 next_fragP
= next_fragP
->fr_next
;
4466 assert (next_fragP
->fr_type
== rs_machine_dependent
4467 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4468 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4470 /* ...and one of these. */
4471 new_target
= next_fragP
->fr_next
;
4472 while (!(new_target
->fr_type
== rs_machine_dependent
4473 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4474 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4475 new_target
= new_target
->fr_next
;
4477 assert (new_target
->fr_type
== rs_machine_dependent
4478 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4479 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4482 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4484 if (next_fragP
->fr_type
== rs_machine_dependent
4485 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4487 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4491 next_fragP
= next_fragP
->fr_next
;
4497 next_frag_is_branch_target (const fragS
*fragP
)
4499 /* Sometimes an empty will end up here due to storage allocation issues,
4500 so we have to skip until we find something legit. */
4501 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4503 if (fragP
->tc_frag_data
.is_branch_target
)
4505 if (fragP
->fr_fix
!= 0)
4513 next_frag_is_loop_target (const fragS
*fragP
)
4515 /* Sometimes an empty will end up here due storage allocation issues.
4516 So we have to skip until we find something legit. */
4517 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4519 if (fragP
->tc_frag_data
.is_loop_target
)
4521 if (fragP
->fr_fix
!= 0)
4529 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4531 const fragS
*next_fragp
= fragp
->fr_next
;
4532 xtensa_opcode next_opcode
;
4534 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4537 /* Sometimes an empty will end up here due to storage allocation issues,
4538 so we have to skip until we find something legit. */
4539 while (next_fragp
->fr_fix
== 0)
4540 next_fragp
= next_fragp
->fr_next
;
4542 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4545 /* There is some implicit knowledge encoded in here.
4546 The LOOP instructions that are NOT RELAX_IMMED have
4547 been relaxed. Note that we can assume that the LOOP
4548 instruction is in slot 0 because loops aren't bundleable. */
4549 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4550 return get_expanded_loop_offset (next_opcode
);
4556 /* Mark a location where we can later insert literal frags. Update
4557 the section's literal_pool_loc, so subsequent literals can be
4558 placed nearest to their use. */
4561 xtensa_mark_literal_pool_location (void)
4563 /* Any labels pointing to the current location need
4564 to be adjusted to after the literal pool. */
4566 fragS
*pool_location
;
4568 if (use_literal_section
)
4571 /* We stash info in these frags so we can later move the literal's
4572 fixes into this frchain's fix list. */
4573 pool_location
= frag_now
;
4574 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4575 frag_variant (rs_machine_dependent
, 0, 0,
4576 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4577 xtensa_set_frag_assembly_state (frag_now
);
4578 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4579 frag_variant (rs_machine_dependent
, 0, 0,
4580 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4581 xtensa_set_frag_assembly_state (frag_now
);
4583 /* Now put a frag into the literal pool that points to this location. */
4584 set_literal_pool_location (now_seg
, pool_location
);
4585 xtensa_switch_to_non_abs_literal_fragment (&s
);
4586 frag_align (2, 0, 0);
4587 record_alignment (now_seg
, 2);
4589 /* Close whatever frag is there. */
4590 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4591 xtensa_set_frag_assembly_state (frag_now
);
4592 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4593 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4594 xtensa_restore_emit_state (&s
);
4595 xtensa_set_frag_assembly_state (frag_now
);
4599 /* Build a nop of the correct size into tinsn. */
4602 build_nop (TInsn
*tinsn
, int size
)
4608 tinsn
->opcode
= xtensa_nop_n_opcode
;
4610 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4611 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4615 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4617 tinsn
->opcode
= xtensa_or_opcode
;
4618 set_expr_const (&tinsn
->tok
[0], 1);
4619 set_expr_const (&tinsn
->tok
[1], 1);
4620 set_expr_const (&tinsn
->tok
[2], 1);
4624 tinsn
->opcode
= xtensa_nop_opcode
;
4626 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4631 /* Assemble a NOP of the requested size in the buffer. User must have
4632 allocated "buf" with at least "size" bytes. */
4635 assemble_nop (int size
, char *buf
)
4637 static xtensa_insnbuf insnbuf
= NULL
;
4640 build_nop (&tinsn
, size
);
4643 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4645 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4646 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4647 (unsigned char *) buf
, 0);
4651 /* Return the number of bytes for the offset of the expanded loop
4652 instruction. This should be incorporated into the relaxation
4653 specification but is hard-coded here. This is used to auto-align
4654 the loop instruction. It is invalid to call this function if the
4655 configuration does not have loops or if the opcode is not a loop
4659 get_expanded_loop_offset (xtensa_opcode opcode
)
4661 /* This is the OFFSET of the loop instruction in the expanded loop.
4662 This MUST correspond directly to the specification of the loop
4663 expansion. It will be validated on fragment conversion. */
4664 assert (opcode
!= XTENSA_UNDEFINED
);
4665 if (opcode
== xtensa_loop_opcode
)
4667 if (opcode
== xtensa_loopnez_opcode
)
4669 if (opcode
== xtensa_loopgtz_opcode
)
4671 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4677 get_literal_pool_location (segT seg
)
4679 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4684 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4686 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4690 /* Set frag assembly state should be called when a new frag is
4691 opened and after a frag has been closed. */
4694 xtensa_set_frag_assembly_state (fragS
*fragP
)
4696 if (!density_supported
)
4697 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4699 /* This function is called from subsegs_finish, which is called
4700 after xtensa_end, so we can't use "use_transform" or
4701 "use_schedule" here. */
4702 if (!directive_state
[directive_transform
])
4703 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4704 if (directive_state
[directive_longcalls
])
4705 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4706 fragP
->tc_frag_data
.use_absolute_literals
=
4707 directive_state
[directive_absolute_literals
];
4708 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4713 relaxable_section (asection
*sec
)
4715 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4720 xtensa_find_unmarked_state_frags (void)
4724 /* Walk over each fragment of all of the current segments. For each
4725 unmarked fragment, mark it with the same info as the previous
4727 for (seclist
= &stdoutput
->sections
;
4728 seclist
&& *seclist
;
4729 seclist
= &(*seclist
)->next
)
4731 segT sec
= *seclist
;
4732 segment_info_type
*seginfo
;
4735 flags
= bfd_get_section_flags (stdoutput
, sec
);
4736 if (flags
& SEC_DEBUGGING
)
4738 if (!(flags
& SEC_ALLOC
))
4741 seginfo
= seg_info (sec
);
4742 if (seginfo
&& seginfo
->frchainP
)
4744 fragS
*last_fragP
= 0;
4745 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4746 fragP
= fragP
->fr_next
)
4748 if (fragP
->fr_fix
!= 0
4749 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4751 if (last_fragP
== 0)
4753 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4754 _("assembly state not set for first frag in section %s"),
4759 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4760 fragP
->tc_frag_data
.is_no_density
=
4761 last_fragP
->tc_frag_data
.is_no_density
;
4762 fragP
->tc_frag_data
.is_no_transform
=
4763 last_fragP
->tc_frag_data
.is_no_transform
;
4764 fragP
->tc_frag_data
.use_longcalls
=
4765 last_fragP
->tc_frag_data
.use_longcalls
;
4766 fragP
->tc_frag_data
.use_absolute_literals
=
4767 last_fragP
->tc_frag_data
.use_absolute_literals
;
4770 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4779 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4781 void *unused ATTRIBUTE_UNUSED
)
4783 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4784 segment_info_type
*seginfo
= seg_info (sec
);
4785 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4787 if (flags
& SEC_CODE
)
4789 xtensa_isa isa
= xtensa_default_isa
;
4790 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4791 while (frag
!= NULL
)
4793 if (frag
->tc_frag_data
.is_branch_target
)
4796 addressT branch_align
, frag_addr
;
4799 xtensa_insnbuf_from_chars
4800 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4801 fmt
= xtensa_format_decode (isa
, insnbuf
);
4802 op_size
= xtensa_format_length (isa
, fmt
);
4803 branch_align
= 1 << branch_align_power (sec
);
4804 frag_addr
= frag
->fr_address
% branch_align
;
4805 if (frag_addr
+ op_size
> branch_align
)
4806 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4807 _("unaligned branch target: %d bytes at 0x%lx"),
4808 op_size
, (long) frag
->fr_address
);
4810 frag
= frag
->fr_next
;
4812 xtensa_insnbuf_free (isa
, insnbuf
);
4818 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4820 void *unused ATTRIBUTE_UNUSED
)
4822 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4823 segment_info_type
*seginfo
= seg_info (sec
);
4824 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4825 xtensa_isa isa
= xtensa_default_isa
;
4827 if (flags
& SEC_CODE
)
4829 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4830 while (frag
!= NULL
)
4832 if (frag
->tc_frag_data
.is_first_loop_insn
)
4838 xtensa_insnbuf_from_chars
4839 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4840 fmt
= xtensa_format_decode (isa
, insnbuf
);
4841 op_size
= xtensa_format_length (isa
, fmt
);
4842 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4844 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4845 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4846 _("unaligned loop: %d bytes at 0x%lx"),
4847 op_size
, (long) frag
->fr_address
);
4849 frag
= frag
->fr_next
;
4851 xtensa_insnbuf_free (isa
, insnbuf
);
4857 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4859 xtensa_isa isa
= xtensa_default_isa
;
4860 static xtensa_insnbuf insnbuf
= NULL
;
4861 static xtensa_insnbuf slotbuf
= NULL
;
4864 bfd_boolean alt_reloc
;
4865 xtensa_opcode opcode
;
4866 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4868 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4870 as_fatal (_("unexpected fix"));
4874 insnbuf
= xtensa_insnbuf_alloc (isa
);
4875 slotbuf
= xtensa_insnbuf_alloc (isa
);
4878 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4879 fmt
= xtensa_format_decode (isa
, insnbuf
);
4880 if (fmt
== XTENSA_UNDEFINED
)
4881 as_fatal (_("undecodable fix"));
4882 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4883 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4884 if (opcode
== XTENSA_UNDEFINED
)
4885 as_fatal (_("undecodable fix"));
4887 /* CONST16 immediates are not PC-relative, despite the fact that we
4888 reuse the normal PC-relative operand relocations for the low part
4889 of a CONST16 operand. */
4890 if (opcode
== xtensa_const16_opcode
)
4893 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4894 get_relaxable_immed (opcode
), val
,
4895 fixP
->fx_file
, fixP
->fx_line
);
4897 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4898 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4904 /* External Functions and Other GAS Hooks. */
4907 xtensa_target_format (void)
4909 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4914 xtensa_file_arch_init (bfd
*abfd
)
4916 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4921 md_number_to_chars (char *buf
, valueT val
, int n
)
4923 if (target_big_endian
)
4924 number_to_chars_bigendian (buf
, val
, n
);
4926 number_to_chars_littleendian (buf
, val
, n
);
4930 /* This function is called once, at assembler startup time. It should
4931 set up all the tables, etc. that the MD part of the assembler will
4937 segT current_section
= now_seg
;
4938 int current_subsec
= now_subseg
;
4941 xtensa_default_isa
= xtensa_isa_init (0, 0);
4942 isa
= xtensa_default_isa
;
4946 /* Set up the literal sections. */
4947 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4949 subseg_set (current_section
, current_subsec
);
4951 xg_init_vinsn (&cur_vinsn
);
4953 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4954 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4955 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4956 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4957 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4958 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4959 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4960 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4961 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4962 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4963 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4964 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4965 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4966 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4967 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4968 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4969 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4970 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4971 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4972 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4973 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4974 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4975 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4976 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4977 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4978 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4979 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4980 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4981 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4983 init_op_placement_info_table ();
4985 /* Set up the assembly state. */
4986 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4987 xtensa_set_frag_assembly_state (frag_now
);
4991 /* TC_INIT_FIX_DATA hook */
4994 xtensa_init_fix_data (fixS
*x
)
4996 x
->tc_fix_data
.slot
= 0;
4997 x
->tc_fix_data
.X_add_symbol
= NULL
;
4998 x
->tc_fix_data
.X_add_number
= 0;
5002 /* tc_frob_label hook */
5005 xtensa_frob_label (symbolS
*sym
)
5009 if (cur_vinsn
.inside_bundle
)
5011 as_bad (_("labels are not valid inside bundles"));
5015 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5017 /* Since the label was already attached to a frag associated with the
5018 previous basic block, it now needs to be reset to the current frag. */
5019 symbol_set_frag (sym
, frag_now
);
5020 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5022 if (generating_literals
)
5023 xtensa_add_literal_sym (sym
);
5025 xtensa_add_insn_label (sym
);
5027 if (symbol_get_tc (sym
)->is_loop_target
)
5029 if ((get_last_insn_flags (now_seg
, now_subseg
)
5030 & FLAG_IS_BAD_LOOPEND
) != 0)
5031 as_bad (_("invalid last instruction for a zero-overhead loop"));
5033 xtensa_set_frag_assembly_state (frag_now
);
5034 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5035 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5037 xtensa_set_frag_assembly_state (frag_now
);
5038 xtensa_move_labels (frag_now
, 0, TRUE
);
5041 /* No target aligning in the absolute section. */
5042 if (now_seg
!= absolute_section
5043 && do_align_targets ()
5044 && !is_unaligned_label (sym
)
5045 && !generating_literals
)
5047 xtensa_set_frag_assembly_state (frag_now
);
5049 frag_var (rs_machine_dependent
,
5051 RELAX_DESIRE_ALIGN_IF_TARGET
,
5052 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5053 xtensa_set_frag_assembly_state (frag_now
);
5054 xtensa_move_labels (frag_now
, 0, TRUE
);
5057 /* We need to mark the following properties even if we aren't aligning. */
5059 /* If the label is already known to be a branch target, i.e., a
5060 forward branch, mark the frag accordingly. Backward branches
5061 are handled by xg_add_branch_and_loop_targets. */
5062 if (symbol_get_tc (sym
)->is_branch_target
)
5063 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5065 /* Loops only go forward, so they can be identified here. */
5066 if (symbol_get_tc (sym
)->is_loop_target
)
5067 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5069 dwarf2_emit_label (sym
);
5073 /* tc_unrecognized_line hook */
5076 xtensa_unrecognized_line (int ch
)
5081 if (cur_vinsn
.inside_bundle
== 0)
5083 /* PR8110: Cannot emit line number info inside a FLIX bundle
5084 when using --gstabs. Temporarily disable debug info. */
5085 generate_lineno_debug ();
5086 if (debug_type
== DEBUG_STABS
)
5088 xt_saved_debug_type
= debug_type
;
5089 debug_type
= DEBUG_NONE
;
5092 cur_vinsn
.inside_bundle
= 1;
5096 as_bad (_("extra opening brace"));
5102 if (cur_vinsn
.inside_bundle
)
5103 finish_vinsn (&cur_vinsn
);
5106 as_bad (_("extra closing brace"));
5111 as_bad (_("syntax error"));
5118 /* md_flush_pending_output hook */
5121 xtensa_flush_pending_output (void)
5123 if (cur_vinsn
.inside_bundle
)
5124 as_bad (_("missing closing brace"));
5126 /* If there is a non-zero instruction fragment, close it. */
5127 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5129 frag_wane (frag_now
);
5131 xtensa_set_frag_assembly_state (frag_now
);
5133 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5135 xtensa_clear_insn_labels ();
5139 /* We had an error while parsing an instruction. The string might look
5140 like this: "insn arg1, arg2 }". If so, we need to see the closing
5141 brace and reset some fields. Otherwise, the vinsn never gets closed
5142 and the num_slots field will grow past the end of the array of slots,
5143 and bad things happen. */
5146 error_reset_cur_vinsn (void)
5148 if (cur_vinsn
.inside_bundle
)
5150 if (*input_line_pointer
== '}'
5151 || *(input_line_pointer
- 1) == '}'
5152 || *(input_line_pointer
- 2) == '}')
5153 xg_clear_vinsn (&cur_vinsn
);
5159 md_assemble (char *str
)
5161 xtensa_isa isa
= xtensa_default_isa
;
5162 char *opname
, *file_name
;
5164 bfd_boolean has_underbar
= FALSE
;
5165 char *arg_strings
[MAX_INSN_ARGS
];
5167 TInsn orig_insn
; /* Original instruction from the input. */
5169 tinsn_init (&orig_insn
);
5171 /* Split off the opcode. */
5172 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5173 opname
= xmalloc (opnamelen
+ 1);
5174 memcpy (opname
, str
, opnamelen
);
5175 opname
[opnamelen
] = '\0';
5177 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5180 as_bad (_("syntax error"));
5184 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5187 /* Check for an underbar prefix. */
5190 has_underbar
= TRUE
;
5194 orig_insn
.insn_type
= ITYPE_INSN
;
5196 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5198 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5199 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5201 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5202 if (fmt
== XTENSA_UNDEFINED
)
5204 as_bad (_("unknown opcode or format name '%s'"), opname
);
5205 error_reset_cur_vinsn ();
5208 if (!cur_vinsn
.inside_bundle
)
5210 as_bad (_("format names only valid inside bundles"));
5211 error_reset_cur_vinsn ();
5214 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5215 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5217 cur_vinsn
.format
= fmt
;
5218 free (has_underbar
? opname
- 1 : opname
);
5219 error_reset_cur_vinsn ();
5223 /* Parse the arguments. */
5224 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5226 as_bad (_("syntax error"));
5227 error_reset_cur_vinsn ();
5231 /* Free the opcode and argument strings, now that they've been parsed. */
5232 free (has_underbar
? opname
- 1 : opname
);
5234 while (num_args
-- > 0)
5235 free (arg_strings
[num_args
]);
5237 /* Get expressions for invisible operands. */
5238 if (get_invisible_operands (&orig_insn
))
5240 error_reset_cur_vinsn ();
5244 /* Check for the right number and type of arguments. */
5245 if (tinsn_check_arguments (&orig_insn
))
5247 error_reset_cur_vinsn ();
5251 /* A FLIX bundle may be spread across multiple input lines. We want to
5252 report the first such line in the debug information. Record the line
5253 number for each TInsn (assume the file name doesn't change), so the
5254 first line can be found later. */
5255 as_where (&file_name
, &orig_insn
.linenum
);
5257 xg_add_branch_and_loop_targets (&orig_insn
);
5259 /* Check that immediate value for ENTRY is >= 16. */
5260 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5262 expressionS
*exp
= &orig_insn
.tok
[2];
5263 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5264 as_warn (_("entry instruction with stack decrement < 16"));
5268 assemble_tokens (opcode, tok, ntok);
5269 expand the tokens from the orig_insn into the
5270 stack of instructions that will not expand
5271 unless required at relaxation time. */
5273 if (!cur_vinsn
.inside_bundle
)
5274 emit_single_op (&orig_insn
);
5275 else /* We are inside a bundle. */
5277 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5278 cur_vinsn
.num_slots
++;
5279 if (*input_line_pointer
== '}'
5280 || *(input_line_pointer
- 1) == '}'
5281 || *(input_line_pointer
- 2) == '}')
5282 finish_vinsn (&cur_vinsn
);
5285 /* We've just emitted a new instruction so clear the list of labels. */
5286 xtensa_clear_insn_labels ();
5290 /* HANDLE_ALIGN hook */
5292 /* For a .align directive, we mark the previous block with the alignment
5293 information. This will be placed in the object file in the
5294 property section corresponding to this section. */
5297 xtensa_handle_align (fragS
*fragP
)
5300 && ! fragP
->tc_frag_data
.is_literal
5301 && (fragP
->fr_type
== rs_align
5302 || fragP
->fr_type
== rs_align_code
)
5303 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5304 && fragP
->fr_offset
> 0
5305 && now_seg
!= bss_section
)
5307 fragP
->tc_frag_data
.is_align
= TRUE
;
5308 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5311 if (fragP
->fr_type
== rs_align_test
)
5314 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5316 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5317 _("unaligned entry instruction"));
5322 /* TC_FRAG_INIT hook */
5325 xtensa_frag_init (fragS
*frag
)
5327 xtensa_set_frag_assembly_state (frag
);
5332 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5338 /* Round up a section size to the appropriate boundary. */
5341 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5343 return size
; /* Byte alignment is fine. */
5348 md_pcrel_from (fixS
*fixP
)
5351 static xtensa_insnbuf insnbuf
= NULL
;
5352 static xtensa_insnbuf slotbuf
= NULL
;
5355 xtensa_opcode opcode
;
5358 xtensa_isa isa
= xtensa_default_isa
;
5359 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5360 bfd_boolean alt_reloc
;
5362 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5367 insnbuf
= xtensa_insnbuf_alloc (isa
);
5368 slotbuf
= xtensa_insnbuf_alloc (isa
);
5371 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5372 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5373 fmt
= xtensa_format_decode (isa
, insnbuf
);
5375 if (fmt
== XTENSA_UNDEFINED
)
5376 as_fatal (_("bad instruction format"));
5378 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5379 as_fatal (_("invalid relocation"));
5381 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5382 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5384 /* Check for "alternate" relocations (operand not specified). None
5385 of the current uses for these are really PC-relative. */
5386 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5388 if (opcode
!= xtensa_l32r_opcode
5389 && opcode
!= xtensa_const16_opcode
)
5390 as_fatal (_("invalid relocation for '%s' instruction"),
5391 xtensa_opcode_name (isa
, opcode
));
5395 opnum
= get_relaxable_immed (opcode
);
5397 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5398 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5400 as_bad_where (fixP
->fx_file
,
5402 _("invalid relocation for operand %d of '%s'"),
5403 opnum
, xtensa_opcode_name (isa
, opcode
));
5406 return 0 - opnd_value
;
5410 /* TC_FORCE_RELOCATION hook */
5413 xtensa_force_relocation (fixS
*fix
)
5415 switch (fix
->fx_r_type
)
5417 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5418 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5419 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5420 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5421 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5422 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5423 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5424 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5425 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5426 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5427 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5428 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5429 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5430 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5431 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5438 if (linkrelax
&& fix
->fx_addsy
5439 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5442 return generic_force_reloc (fix
);
5446 /* TC_VALIDATE_FIX_SUB hook */
5449 xtensa_validate_fix_sub (fixS
*fix
)
5451 segT add_symbol_segment
, sub_symbol_segment
;
5453 /* The difference of two symbols should be resolved by the assembler when
5454 linkrelax is not set. If the linker may relax the section containing
5455 the symbols, then an Xtensa DIFF relocation must be generated so that
5456 the linker knows to adjust the difference value. */
5457 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5460 /* Make sure both symbols are in the same segment, and that segment is
5461 "normal" and relaxable. If the segment is not "normal", then the
5462 fix is not valid. If the segment is not "relaxable", then the fix
5463 should have been handled earlier. */
5464 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5465 if (! SEG_NORMAL (add_symbol_segment
) ||
5466 ! relaxable_section (add_symbol_segment
))
5468 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5469 return (sub_symbol_segment
== add_symbol_segment
);
5473 /* NO_PSEUDO_DOT hook */
5475 /* This function has nothing to do with pseudo dots, but this is the
5476 nearest macro to where the check needs to take place. FIXME: This
5480 xtensa_check_inside_bundle (void)
5482 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5483 as_bad (_("directives are not valid inside bundles"));
5485 /* This function must always return FALSE because it is called via a
5486 macro that has nothing to do with bundling. */
5491 /* md_elf_section_change_hook */
5494 xtensa_elf_section_change_hook (void)
5496 /* Set up the assembly state. */
5497 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5498 xtensa_set_frag_assembly_state (frag_now
);
5502 /* tc_fix_adjustable hook */
5505 xtensa_fix_adjustable (fixS
*fixP
)
5507 /* An offset is not allowed in combination with the difference of two
5508 symbols, but that cannot be easily detected after a local symbol
5509 has been adjusted to a (section+offset) form. Return 0 so that such
5510 an fix will not be adjusted. */
5511 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5512 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5515 /* We need the symbol name for the VTABLE entries. */
5516 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5517 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5525 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5527 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5530 /* Subtracted symbols are only allowed for a few relocation types, and
5531 unless linkrelax is enabled, they should not make it to this point. */
5532 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5533 || fixP
->fx_r_type
== BFD_RELOC_16
5534 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5535 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5537 switch (fixP
->fx_r_type
)
5544 switch (fixP
->fx_r_type
)
5547 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5550 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5553 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5559 /* An offset is only allowed when it results from adjusting a
5560 local symbol into a section-relative offset. If the offset
5561 came from the original expression, tc_fix_adjustable will have
5562 prevented the fix from being converted to a section-relative
5563 form so that we can flag the error here. */
5564 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5566 _("cannot represent subtraction with an offset"));
5568 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5569 - S_GET_VALUE (fixP
->fx_subsy
));
5571 /* The difference value gets written out, and the DIFF reloc
5572 identifies the address of the subtracted symbol (i.e., the one
5573 with the lowest address). */
5575 fixP
->fx_offset
-= val
;
5576 fixP
->fx_subsy
= NULL
;
5578 else if (! fixP
->fx_addsy
)
5585 case BFD_RELOC_XTENSA_PLT
:
5586 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5587 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5590 case BFD_RELOC_XTENSA_SLOT0_OP
:
5591 case BFD_RELOC_XTENSA_SLOT1_OP
:
5592 case BFD_RELOC_XTENSA_SLOT2_OP
:
5593 case BFD_RELOC_XTENSA_SLOT3_OP
:
5594 case BFD_RELOC_XTENSA_SLOT4_OP
:
5595 case BFD_RELOC_XTENSA_SLOT5_OP
:
5596 case BFD_RELOC_XTENSA_SLOT6_OP
:
5597 case BFD_RELOC_XTENSA_SLOT7_OP
:
5598 case BFD_RELOC_XTENSA_SLOT8_OP
:
5599 case BFD_RELOC_XTENSA_SLOT9_OP
:
5600 case BFD_RELOC_XTENSA_SLOT10_OP
:
5601 case BFD_RELOC_XTENSA_SLOT11_OP
:
5602 case BFD_RELOC_XTENSA_SLOT12_OP
:
5603 case BFD_RELOC_XTENSA_SLOT13_OP
:
5604 case BFD_RELOC_XTENSA_SLOT14_OP
:
5607 /* Write the tentative value of a PC-relative relocation to a
5608 local symbol into the instruction. The value will be ignored
5609 by the linker, and it makes the object file disassembly
5610 readable when all branch targets are encoded in relocations. */
5612 assert (fixP
->fx_addsy
);
5613 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5614 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5616 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5617 - md_pcrel_from (fixP
));
5618 (void) xg_apply_fix_value (fixP
, val
);
5621 else if (! fixP
->fx_addsy
)
5624 if (xg_apply_fix_value (fixP
, val
))
5629 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5630 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5631 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5632 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5633 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5634 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5635 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5636 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5637 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5645 /* These all need to be resolved at link-time. Do nothing now. */
5648 case BFD_RELOC_VTABLE_INHERIT
:
5649 case BFD_RELOC_VTABLE_ENTRY
:
5654 as_bad (_("unhandled local relocation fix %s"),
5655 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5661 md_atof (int type
, char *litP
, int *sizeP
)
5664 LITTLENUM_TYPE words
[4];
5680 return "bad call to md_atof";
5683 t
= atof_ieee (input_line_pointer
, type
, words
);
5685 input_line_pointer
= t
;
5689 for (i
= prec
- 1; i
>= 0; i
--)
5692 if (target_big_endian
)
5693 idx
= (prec
- 1 - i
);
5695 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5704 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5706 return total_frag_text_expansion (fragP
);
5710 /* Translate internal representation of relocation info to BFD target
5714 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5718 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5719 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5720 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5721 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5723 /* Make sure none of our internal relocations make it this far.
5724 They'd better have been fully resolved by this point. */
5725 assert ((int) fixp
->fx_r_type
> 0);
5727 reloc
->addend
= fixp
->fx_offset
;
5729 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5730 if (reloc
->howto
== NULL
)
5732 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5733 _("cannot represent `%s' relocation in object file"),
5734 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5735 free (reloc
->sym_ptr_ptr
);
5740 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5741 as_fatal (_("internal error? cannot generate `%s' relocation"),
5742 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5748 /* Checks for resource conflicts between instructions. */
5750 /* The func unit stuff could be implemented as bit-vectors rather
5751 than the iterative approach here. If it ends up being too
5752 slow, we will switch it. */
5755 new_resource_table (void *data
,
5758 unit_num_copies_func uncf
,
5759 opcode_num_units_func onuf
,
5760 opcode_funcUnit_use_unit_func ouuf
,
5761 opcode_funcUnit_use_stage_func ousf
)
5764 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5766 rt
->cycles
= cycles
;
5767 rt
->allocated_cycles
= cycles
;
5769 rt
->unit_num_copies
= uncf
;
5770 rt
->opcode_num_units
= onuf
;
5771 rt
->opcode_unit_use
= ouuf
;
5772 rt
->opcode_unit_stage
= ousf
;
5774 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5775 for (i
= 0; i
< cycles
; i
++)
5776 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5783 clear_resource_table (resource_table
*rt
)
5786 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5787 for (j
= 0; j
< rt
->num_units
; j
++)
5788 rt
->units
[i
][j
] = 0;
5792 /* We never shrink it, just fake it into thinking so. */
5795 resize_resource_table (resource_table
*rt
, int cycles
)
5799 rt
->cycles
= cycles
;
5800 if (cycles
<= rt
->allocated_cycles
)
5803 old_cycles
= rt
->allocated_cycles
;
5804 rt
->allocated_cycles
= cycles
;
5806 rt
->units
= xrealloc (rt
->units
,
5807 rt
->allocated_cycles
* sizeof (unsigned char *));
5808 for (i
= 0; i
< old_cycles
; i
++)
5809 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5810 rt
->num_units
* sizeof (unsigned char));
5811 for (i
= old_cycles
; i
< cycles
; i
++)
5812 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5817 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5820 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5822 for (i
= 0; i
< uses
; i
++)
5824 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5825 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5826 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5827 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5828 if (copies_in_use
>= copies
)
5836 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5839 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5841 for (i
= 0; i
< uses
; i
++)
5843 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5844 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5845 /* Note that this allows resources to be oversubscribed. That's
5846 essential to the way the optional scheduler works.
5847 resources_available reports when a resource is over-subscribed,
5848 so it's easy to tell. */
5849 rt
->units
[stage
+ cycle
][unit
]++;
5855 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5858 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5860 for (i
= 0; i
< uses
; i
++)
5862 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5863 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5864 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5865 rt
->units
[stage
+ cycle
][unit
]--;
5870 /* Wrapper functions make parameterized resource reservation
5874 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5876 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5882 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5884 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5889 /* Note that this function does not check issue constraints, but
5890 solely whether the hardware is available to execute the given
5891 instructions together. It also doesn't check if the tinsns
5892 write the same state, or access the same tieports. That is
5893 checked by check_t1_t2_reads_and_writes. */
5896 resources_conflict (vliw_insn
*vinsn
)
5899 static resource_table
*rt
= NULL
;
5901 /* This is the most common case by far. Optimize it. */
5902 if (vinsn
->num_slots
== 1)
5907 xtensa_isa isa
= xtensa_default_isa
;
5908 rt
= new_resource_table
5909 (isa
, xtensa_isa_num_pipe_stages (isa
),
5910 xtensa_isa_num_funcUnits (isa
),
5911 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5912 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5913 opcode_funcUnit_use_unit
,
5914 opcode_funcUnit_use_stage
);
5917 clear_resource_table (rt
);
5919 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5921 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5923 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5930 /* finish_vinsn, emit_single_op and helper functions. */
5932 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5933 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5934 static void xg_assemble_vliw_tokens (vliw_insn
*);
5937 /* We have reached the end of a bundle; emit into the frag. */
5940 finish_vinsn (vliw_insn
*vinsn
)
5947 if (find_vinsn_conflicts (vinsn
))
5949 xg_clear_vinsn (vinsn
);
5953 /* First, find a format that works. */
5954 if (vinsn
->format
== XTENSA_UNDEFINED
)
5955 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5957 if (vinsn
->format
== XTENSA_UNDEFINED
)
5959 as_where (&file_name
, &line
);
5960 as_bad_where (file_name
, line
,
5961 _("couldn't find a valid instruction format"));
5962 fprintf (stderr
, _(" ops were: "));
5963 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5964 fprintf (stderr
, _(" %s;"),
5965 xtensa_opcode_name (xtensa_default_isa
,
5966 vinsn
->slots
[i
].opcode
));
5967 fprintf (stderr
, _("\n"));
5968 xg_clear_vinsn (vinsn
);
5972 if (vinsn
->num_slots
5973 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5975 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5976 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5977 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5979 xg_clear_vinsn (vinsn
);
5983 if (resources_conflict (vinsn
))
5985 as_where (&file_name
, &line
);
5986 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5987 fprintf (stderr
, " ops were: ");
5988 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5989 fprintf (stderr
, " %s;",
5990 xtensa_opcode_name (xtensa_default_isa
,
5991 vinsn
->slots
[i
].opcode
));
5992 fprintf (stderr
, "\n");
5993 xg_clear_vinsn (vinsn
);
5997 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5999 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6001 symbolS
*lit_sym
= NULL
;
6003 bfd_boolean e
= FALSE
;
6004 bfd_boolean saved_density
= density_supported
;
6006 /* We don't want to narrow ops inside multi-slot bundles. */
6007 if (vinsn
->num_slots
> 1)
6008 density_supported
= FALSE
;
6010 istack_init (&slotstack
);
6011 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6013 vinsn
->slots
[i
].opcode
=
6014 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6016 vinsn
->slots
[i
].ntok
= 0;
6019 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6025 density_supported
= saved_density
;
6029 xg_clear_vinsn (vinsn
);
6033 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6035 TInsn
*insn
= &slotstack
.insn
[j
];
6036 if (insn
->insn_type
== ITYPE_LITERAL
)
6038 assert (lit_sym
== NULL
);
6039 lit_sym
= xg_assemble_literal (insn
);
6043 assert (insn
->insn_type
== ITYPE_INSN
);
6045 xg_resolve_literals (insn
, lit_sym
);
6046 if (j
!= slotstack
.ninsn
- 1)
6047 emit_single_op (insn
);
6051 if (vinsn
->num_slots
> 1)
6053 if (opcode_fits_format_slot
6054 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6057 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6061 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6062 if (vinsn
->format
== XTENSA_UNDEFINED
)
6063 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6065 vinsn
->slots
[i
].opcode
6066 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6069 vinsn
->slots
[i
].ntok
= 0;
6074 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6075 vinsn
->format
= XTENSA_UNDEFINED
;
6080 /* Now check resource conflicts on the modified bundle. */
6081 if (resources_conflict (vinsn
))
6083 as_where (&file_name
, &line
);
6084 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6085 fprintf (stderr
, " ops were: ");
6086 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6087 fprintf (stderr
, " %s;",
6088 xtensa_opcode_name (xtensa_default_isa
,
6089 vinsn
->slots
[i
].opcode
));
6090 fprintf (stderr
, "\n");
6091 xg_clear_vinsn (vinsn
);
6095 /* First, find a format that works. */
6096 if (vinsn
->format
== XTENSA_UNDEFINED
)
6097 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6099 xg_assemble_vliw_tokens (vinsn
);
6101 xg_clear_vinsn (vinsn
);
6105 /* Given an vliw instruction, what conflicts are there in register
6106 usage and in writes to states and queues?
6108 This function does two things:
6109 1. Reports an error when a vinsn contains illegal combinations
6110 of writes to registers states or queues.
6111 2. Marks individual tinsns as not relaxable if the combination
6112 contains antidependencies.
6114 Job 2 handles things like swap semantics in instructions that need
6115 to be relaxed. For example,
6119 normally would be relaxed to
6124 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6126 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6128 then we can't relax it into
6131 { add a0, a1, a0 ; add a2, a0, a4 ; }
6133 because the value of a0 is trashed before the second add can read it. */
6135 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6138 find_vinsn_conflicts (vliw_insn
*vinsn
)
6142 xtensa_isa isa
= xtensa_default_isa
;
6144 assert (!past_xtensa_end
);
6146 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6148 TInsn
*op1
= &vinsn
->slots
[i
];
6149 if (op1
->is_specific_opcode
)
6150 op1
->keep_wide
= TRUE
;
6152 op1
->keep_wide
= FALSE
;
6155 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6157 TInsn
*op1
= &vinsn
->slots
[i
];
6159 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6162 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6166 TInsn
*op2
= &vinsn
->slots
[j
];
6167 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6168 switch (conflict_type
)
6171 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6172 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6173 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6176 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6177 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6178 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6181 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6182 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6183 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6186 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6187 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6188 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6191 /* Everything is OK. */
6194 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6195 || conflict_type
== 'a');
6202 as_bad (_("multiple branches or jumps in the same bundle"));
6210 /* Check how the state used by t1 and t2 relate.
6213 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6214 case B: no relationship between what is read and written (both could
6215 read the same reg though)
6216 case C: t1 writes a register t2 writes (a register conflict within a
6218 case D: t1 writes a state that t2 also writes
6219 case E: t1 writes a tie queue that t2 also writes
6220 case F: two volatile queue accesses
6224 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6226 xtensa_isa isa
= xtensa_default_isa
;
6227 xtensa_regfile t1_regfile
, t2_regfile
;
6229 int t1_base_reg
, t1_last_reg
;
6230 int t2_base_reg
, t2_last_reg
;
6231 char t1_inout
, t2_inout
;
6233 char conflict
= 'b';
6238 bfd_boolean t1_volatile
= FALSE
;
6239 bfd_boolean t2_volatile
= FALSE
;
6241 /* Check registers. */
6242 for (j
= 0; j
< t2
->ntok
; j
++)
6244 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6247 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6248 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6249 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6251 for (i
= 0; i
< t1
->ntok
; i
++)
6253 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6256 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6258 if (t1_regfile
!= t2_regfile
)
6261 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6262 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6264 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6265 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6267 if (t1_inout
== 'm' || t1_inout
== 'o'
6268 || t2_inout
== 'm' || t2_inout
== 'o')
6275 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6276 t1_last_reg
= (t1_base_reg
6277 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6279 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6281 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6283 if (t1_reg
!= t2_reg
)
6286 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6292 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6298 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6306 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6307 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6308 for (j
= 0; j
< t2_states
; j
++)
6310 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6311 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6312 for (i
= 0; i
< t1_states
; i
++)
6314 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6315 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6319 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6325 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6331 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6336 /* Check tieports. */
6337 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6338 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6339 for (j
= 0; j
< t2_interfaces
; j
++)
6341 xtensa_interface t2_int
6342 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6343 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6345 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6346 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6349 for (i
= 0; i
< t1_interfaces
; i
++)
6351 xtensa_interface t1_int
6352 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6353 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6355 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6356 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6359 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6362 if (t1_int
!= t2_int
)
6365 if (t2_inout
== 'i' && t1_inout
== 'o')
6371 if (t1_inout
== 'i' && t2_inout
== 'o')
6377 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6386 static xtensa_format
6387 xg_find_narrowest_format (vliw_insn
*vinsn
)
6389 /* Right now we assume that the ops within the vinsn are properly
6390 ordered for the slots that the programmer wanted them in. In
6391 other words, we don't rearrange the ops in hopes of finding a
6392 better format. The scheduler handles that. */
6394 xtensa_isa isa
= xtensa_default_isa
;
6395 xtensa_format format
;
6396 vliw_insn v_copy
= *vinsn
;
6397 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6399 if (vinsn
->num_slots
== 1)
6400 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6402 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6405 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6409 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6411 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6413 v_copy
.slots
[slot
].opcode
=
6414 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6415 v_copy
.slots
[slot
].ntok
= 0;
6418 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6421 else if (v_copy
.num_slots
> 1)
6424 /* Try the widened version. */
6425 if (!v_copy
.slots
[slot
].keep_wide
6426 && !v_copy
.slots
[slot
].is_specific_opcode
6427 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6429 && opcode_fits_format_slot (widened
.opcode
,
6432 v_copy
.slots
[slot
] = widened
;
6437 if (fit
== v_copy
.num_slots
)
6440 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6441 vinsn
->format
= format
;
6447 if (format
== xtensa_isa_num_formats (isa
))
6448 return XTENSA_UNDEFINED
;
6454 /* Return the additional space needed in a frag
6455 for possible relaxations of any ops in a VLIW insn.
6456 Also fill out the relaxations that might be required of
6457 each tinsn in the vinsn. */
6460 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6462 bfd_boolean finish_frag
= FALSE
;
6463 int extra_space
= 0;
6466 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6468 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6469 if (!tinsn_has_symbolic_operands (tinsn
))
6471 /* A narrow instruction could be widened later to help
6472 alignment issues. */
6473 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6474 && !tinsn
->is_specific_opcode
6475 && vinsn
->num_slots
== 1)
6477 /* Difference in bytes between narrow and wide insns... */
6479 tinsn
->subtype
= RELAX_NARROW
;
6484 if (workaround_b_j_loop_end
6485 && tinsn
->opcode
== xtensa_jx_opcode
6486 && use_transform ())
6488 /* Add 2 of these. */
6489 extra_space
+= 3; /* for the nop size */
6490 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6493 /* Need to assemble it with space for the relocation. */
6494 if (xg_is_relaxable_insn (tinsn
, 0)
6495 && !tinsn
->is_specific_opcode
)
6497 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6498 int max_literal_size
=
6499 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6501 tinsn
->literal_space
= max_literal_size
;
6503 tinsn
->subtype
= RELAX_IMMED
;
6504 extra_space
+= max_size
;
6508 /* A fix record will be added for this instruction prior
6509 to relaxation, so make it end the frag. */
6514 *pfinish_frag
= finish_frag
;
6520 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6522 xtensa_isa isa
= xtensa_default_isa
;
6523 int slot
, chosen_slot
;
6525 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6526 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6527 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6529 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6530 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6532 if (slot
== chosen_slot
)
6533 vinsn
->slots
[slot
] = *tinsn
;
6536 vinsn
->slots
[slot
].opcode
=
6537 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6538 vinsn
->slots
[slot
].ntok
= 0;
6539 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6546 emit_single_op (TInsn
*orig_insn
)
6549 IStack istack
; /* put instructions into here */
6550 symbolS
*lit_sym
= NULL
;
6551 symbolS
*label_sym
= NULL
;
6553 istack_init (&istack
);
6555 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6556 Because the scheduling and bundling characteristics of movi and
6557 l32r or const16 are so different, we can do much better if we relax
6558 it prior to scheduling and bundling, rather than after. */
6559 if ((orig_insn
->opcode
== xtensa_movi_opcode
6560 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6561 && !cur_vinsn
.inside_bundle
6562 && (orig_insn
->tok
[1].X_op
== O_symbol
6563 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6564 && !orig_insn
->is_specific_opcode
&& use_transform ())
6565 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6567 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6570 for (i
= 0; i
< istack
.ninsn
; i
++)
6572 TInsn
*insn
= &istack
.insn
[i
];
6573 switch (insn
->insn_type
)
6576 assert (lit_sym
== NULL
);
6577 lit_sym
= xg_assemble_literal (insn
);
6581 static int relaxed_sym_idx
= 0;
6582 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6583 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6585 assert (label_sym
== NULL
);
6586 label_sym
= symbol_find_or_make (label
);
6595 xg_resolve_literals (insn
, lit_sym
);
6597 xg_resolve_labels (insn
, label_sym
);
6599 bundle_tinsn (insn
, &v
);
6614 total_frag_text_expansion (fragS
*fragP
)
6617 int total_expansion
= 0;
6619 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6620 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6622 return total_expansion
;
6626 /* Emit a vliw instruction to the current fragment. */
6629 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6631 bfd_boolean finish_frag
;
6632 bfd_boolean is_jump
= FALSE
;
6633 bfd_boolean is_branch
= FALSE
;
6634 xtensa_isa isa
= xtensa_default_isa
;
6640 unsigned current_line
, best_linenum
;
6643 best_linenum
= UINT_MAX
;
6645 if (generating_literals
)
6647 static int reported
= 0;
6649 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6650 _("cannot assemble into a literal fragment"));
6657 if (frag_now_fix () != 0
6658 && (! frag_now
->tc_frag_data
.is_insn
6659 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6660 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6661 || (directive_state
[directive_longcalls
]
6662 != frag_now
->tc_frag_data
.use_longcalls
)
6663 || (directive_state
[directive_absolute_literals
]
6664 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6666 frag_wane (frag_now
);
6668 xtensa_set_frag_assembly_state (frag_now
);
6671 if (workaround_a0_b_retw
6672 && vinsn
->num_slots
== 1
6673 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6674 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6675 && use_transform ())
6677 has_a0_b_retw
= TRUE
;
6679 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6680 After the first assembly pass we will check all of them and
6681 add a nop if needed. */
6682 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6683 frag_var (rs_machine_dependent
, 4, 4,
6684 RELAX_ADD_NOP_IF_A0_B_RETW
,
6685 frag_now
->fr_symbol
,
6686 frag_now
->fr_offset
,
6688 xtensa_set_frag_assembly_state (frag_now
);
6689 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6690 frag_var (rs_machine_dependent
, 4, 4,
6691 RELAX_ADD_NOP_IF_A0_B_RETW
,
6692 frag_now
->fr_symbol
,
6693 frag_now
->fr_offset
,
6695 xtensa_set_frag_assembly_state (frag_now
);
6698 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6700 /* See if the instruction implies an aligned section. */
6701 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6702 record_alignment (now_seg
, 2);
6704 /* Also determine the best line number for debug info. */
6705 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6706 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6709 /* Special cases for instructions that force an alignment... */
6710 /* None of these opcodes are bundle-able. */
6711 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6715 /* Remember the symbol that marks the end of the loop in the frag
6716 that marks the start of the loop. This way we can easily find
6717 the end of the loop at the beginning, without adding special code
6718 to mark the loop instructions themselves. */
6719 symbolS
*target_sym
= NULL
;
6720 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6721 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6723 xtensa_set_frag_assembly_state (frag_now
);
6724 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6726 max_fill
= get_text_align_max_fill_size
6727 (get_text_align_power (xtensa_fetch_width
),
6728 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6730 if (use_transform ())
6731 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6732 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6734 frag_var (rs_machine_dependent
, 0, 0,
6735 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6736 xtensa_set_frag_assembly_state (frag_now
);
6738 xtensa_move_labels (frag_now
, 0, FALSE
);
6741 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6742 && !vinsn
->slots
[0].is_specific_opcode
)
6744 xtensa_mark_literal_pool_location ();
6745 xtensa_move_labels (frag_now
, 0, TRUE
);
6746 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6749 if (vinsn
->num_slots
== 1)
6751 if (workaround_a0_b_retw
&& use_transform ())
6752 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6753 is_register_writer (&vinsn
->slots
[0], "a", 0));
6755 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6756 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6759 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6761 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6763 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6765 /* vinsn_to_insnbuf will produce the error. */
6766 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6768 f
= frag_more (insn_size
+ extra_space
);
6769 xtensa_set_frag_assembly_state (frag_now
);
6770 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6773 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6774 if (vinsn
->format
== XTENSA_UNDEFINED
)
6777 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6779 /* Temporarily set the logical line number to the one we want to appear
6780 in the debug information. */
6781 as_where (¤t_file
, ¤t_line
);
6782 new_logical_line (current_file
, best_linenum
);
6783 dwarf2_emit_insn (insn_size
+ extra_space
);
6784 new_logical_line (current_file
, current_line
);
6786 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6788 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6789 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6790 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6791 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6792 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6793 if (tinsn
->literal_space
!= 0)
6794 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6796 if (tinsn
->subtype
== RELAX_NARROW
)
6797 assert (vinsn
->num_slots
== 1);
6798 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6800 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6803 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6804 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6808 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6809 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6813 frag_variant (rs_machine_dependent
,
6814 extra_space
, extra_space
, RELAX_SLOTS
,
6815 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6816 xtensa_set_frag_assembly_state (frag_now
);
6819 /* Special cases for loops:
6820 close_loop_end should be inserted AFTER short_loop.
6821 Make sure that CLOSE loops are processed BEFORE short_loops
6822 when converting them. */
6824 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6825 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6826 && !vinsn
->slots
[0].is_specific_opcode
)
6828 if (workaround_short_loop
&& use_transform ())
6830 maybe_has_short_loop
= TRUE
;
6831 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6832 frag_var (rs_machine_dependent
, 4, 4,
6833 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6834 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6835 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6836 frag_var (rs_machine_dependent
, 4, 4,
6837 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6838 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6841 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6842 loop at least 12 bytes away from another loop's end. */
6843 if (workaround_close_loop_end
&& use_transform ())
6845 maybe_has_close_loop_end
= TRUE
;
6846 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6847 frag_var (rs_machine_dependent
, 12, 12,
6848 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6849 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6853 if (use_transform ())
6857 assert (finish_frag
);
6858 frag_var (rs_machine_dependent
,
6859 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6861 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6862 xtensa_set_frag_assembly_state (frag_now
);
6864 else if (is_branch
&& do_align_targets ())
6866 assert (finish_frag
);
6867 frag_var (rs_machine_dependent
,
6868 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6869 RELAX_MAYBE_UNREACHABLE
,
6870 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6871 xtensa_set_frag_assembly_state (frag_now
);
6872 frag_var (rs_machine_dependent
,
6874 RELAX_MAYBE_DESIRE_ALIGN
,
6875 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6876 xtensa_set_frag_assembly_state (frag_now
);
6880 /* Now, if the original opcode was a call... */
6881 if (do_align_targets ()
6882 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6884 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6885 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6886 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6887 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6888 xtensa_set_frag_assembly_state (frag_now
);
6891 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6893 frag_wane (frag_now
);
6895 xtensa_set_frag_assembly_state (frag_now
);
6900 /* xtensa_end and helper functions. */
6902 static void xtensa_cleanup_align_frags (void);
6903 static void xtensa_fix_target_frags (void);
6904 static void xtensa_mark_narrow_branches (void);
6905 static void xtensa_mark_zcl_first_insns (void);
6906 static void xtensa_fix_a0_b_retw_frags (void);
6907 static void xtensa_fix_b_j_loop_end_frags (void);
6908 static void xtensa_fix_close_loop_end_frags (void);
6909 static void xtensa_fix_short_loop_frags (void);
6910 static void xtensa_sanity_check (void);
6911 static void xtensa_add_config_info (void);
6916 directive_balance ();
6917 xtensa_flush_pending_output ();
6919 past_xtensa_end
= TRUE
;
6921 xtensa_move_literals ();
6923 xtensa_reorder_segments ();
6924 xtensa_cleanup_align_frags ();
6925 xtensa_fix_target_frags ();
6926 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6927 xtensa_fix_a0_b_retw_frags ();
6928 if (workaround_b_j_loop_end
)
6929 xtensa_fix_b_j_loop_end_frags ();
6931 /* "close_loop_end" should be processed BEFORE "short_loop". */
6932 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6933 xtensa_fix_close_loop_end_frags ();
6935 if (workaround_short_loop
&& maybe_has_short_loop
)
6936 xtensa_fix_short_loop_frags ();
6938 xtensa_mark_narrow_branches ();
6939 xtensa_mark_zcl_first_insns ();
6941 xtensa_sanity_check ();
6943 xtensa_add_config_info ();
6948 xtensa_cleanup_align_frags (void)
6953 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6954 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6957 /* Walk over all of the fragments in a subsection. */
6958 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6960 if ((fragP
->fr_type
== rs_align
6961 || fragP
->fr_type
== rs_align_code
6962 || (fragP
->fr_type
== rs_machine_dependent
6963 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6964 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6965 && fragP
->fr_fix
== 0)
6967 fragS
*next
= fragP
->fr_next
;
6970 && next
->fr_fix
== 0
6971 && next
->fr_type
== rs_machine_dependent
6972 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6975 next
= next
->fr_next
;
6978 /* If we don't widen branch targets, then they
6979 will be easier to align. */
6980 if (fragP
->tc_frag_data
.is_branch_target
6981 && fragP
->fr_opcode
== fragP
->fr_literal
6982 && fragP
->fr_type
== rs_machine_dependent
6983 && fragP
->fr_subtype
== RELAX_SLOTS
6984 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6986 if (fragP
->fr_type
== rs_machine_dependent
6987 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6988 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6994 /* Re-process all of the fragments looking to convert all of the
6995 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6996 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6997 Otherwise, convert to a .fill 0. */
7000 xtensa_fix_target_frags (void)
7005 /* When this routine is called, all of the subsections are still intact
7006 so we walk over subsections instead of sections. */
7007 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7008 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7012 /* Walk over all of the fragments in a subsection. */
7013 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7015 if (fragP
->fr_type
== rs_machine_dependent
7016 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7018 if (next_frag_is_branch_target (fragP
))
7019 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7028 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7031 xtensa_mark_narrow_branches (void)
7036 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7037 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7040 /* Walk over all of the fragments in a subsection. */
7041 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7043 if (fragP
->fr_type
== rs_machine_dependent
7044 && fragP
->fr_subtype
== RELAX_SLOTS
7045 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7049 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7050 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7052 if (vinsn
.num_slots
== 1
7053 && xtensa_opcode_is_branch (xtensa_default_isa
,
7054 vinsn
.slots
[0].opcode
) == 1
7055 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7056 && is_narrow_branch_guaranteed_in_range (fragP
,
7059 fragP
->fr_subtype
= RELAX_SLOTS
;
7060 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7061 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7069 /* A branch is typically widened only when its target is out of
7070 range. However, we would like to widen them to align a subsequent
7071 branch target when possible.
7073 Because the branch relaxation code is so convoluted, the optimal solution
7074 (combining the two cases) is difficult to get right in all circumstances.
7075 We therefore go with an "almost as good" solution, where we only
7076 use for alignment narrow branches that definitely will not expand to a
7077 jump and a branch. These functions find and mark these cases. */
7079 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7080 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7081 We start counting beginning with the frag after the 2-byte branch, so the
7082 maximum offset is (4 - 2) + 63 = 65. */
7083 #define MAX_IMMED6 65
7085 static offsetT
unrelaxed_frag_max_size (fragS
*);
7088 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7090 const expressionS
*expr
= &tinsn
->tok
[1];
7091 symbolS
*symbolP
= expr
->X_add_symbol
;
7092 offsetT max_distance
= expr
->X_add_number
;
7095 if (expr
->X_op
!= O_symbol
)
7098 target_frag
= symbol_get_frag (symbolP
);
7100 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7101 if (is_branch_jmp_to_next (tinsn
, fragP
))
7104 /* The branch doesn't branch over it's own frag,
7105 but over the subsequent ones. */
7106 fragP
= fragP
->fr_next
;
7107 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7109 max_distance
+= unrelaxed_frag_max_size (fragP
);
7110 fragP
= fragP
->fr_next
;
7112 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7119 xtensa_mark_zcl_first_insns (void)
7124 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7125 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7128 /* Walk over all of the fragments in a subsection. */
7129 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7131 if (fragP
->fr_type
== rs_machine_dependent
7132 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7133 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7135 /* Find the loop frag. */
7136 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7137 /* Find the first insn frag. */
7138 targ_frag
= next_non_empty_frag (targ_frag
);
7140 /* Of course, sometimes (mostly for toy test cases) a
7141 zero-cost loop instruction is the last in a section. */
7144 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7145 /* Do not widen a frag that is the first instruction of a
7146 zero-cost loop. It makes that loop harder to align. */
7147 if (targ_frag
->fr_type
== rs_machine_dependent
7148 && targ_frag
->fr_subtype
== RELAX_SLOTS
7149 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7152 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7153 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7156 frag_wane (targ_frag
);
7157 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7161 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7169 /* Re-process all of the fragments looking to convert all of the
7170 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7171 conditional branch or a retw/retw.n, convert this frag to one that
7172 will generate a NOP. In any case close it off with a .fill 0. */
7174 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7177 xtensa_fix_a0_b_retw_frags (void)
7182 /* When this routine is called, all of the subsections are still intact
7183 so we walk over subsections instead of sections. */
7184 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7185 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7189 /* Walk over all of the fragments in a subsection. */
7190 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7192 if (fragP
->fr_type
== rs_machine_dependent
7193 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7195 if (next_instrs_are_b_retw (fragP
))
7197 if (fragP
->tc_frag_data
.is_no_transform
)
7198 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7200 relax_frag_add_nop (fragP
);
7210 next_instrs_are_b_retw (fragS
*fragP
)
7212 xtensa_opcode opcode
;
7214 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7215 static xtensa_insnbuf insnbuf
= NULL
;
7216 static xtensa_insnbuf slotbuf
= NULL
;
7217 xtensa_isa isa
= xtensa_default_isa
;
7220 bfd_boolean branch_seen
= FALSE
;
7224 insnbuf
= xtensa_insnbuf_alloc (isa
);
7225 slotbuf
= xtensa_insnbuf_alloc (isa
);
7228 if (next_fragP
== NULL
)
7231 /* Check for the conditional branch. */
7232 xtensa_insnbuf_from_chars
7233 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7234 fmt
= xtensa_format_decode (isa
, insnbuf
);
7235 if (fmt
== XTENSA_UNDEFINED
)
7238 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7240 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7241 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7243 branch_seen
= (branch_seen
7244 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7250 offset
+= xtensa_format_length (isa
, fmt
);
7251 if (offset
== next_fragP
->fr_fix
)
7253 next_fragP
= next_non_empty_frag (next_fragP
);
7257 if (next_fragP
== NULL
)
7260 /* Check for the retw/retw.n. */
7261 xtensa_insnbuf_from_chars
7262 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7263 fmt
= xtensa_format_decode (isa
, insnbuf
);
7265 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7266 have no problems. */
7267 if (fmt
== XTENSA_UNDEFINED
7268 || xtensa_format_num_slots (isa
, fmt
) != 1)
7271 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7272 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7274 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7281 /* Re-process all of the fragments looking to convert all of the
7282 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7283 loop end label, convert this frag to one that will generate a NOP.
7284 In any case close it off with a .fill 0. */
7286 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7289 xtensa_fix_b_j_loop_end_frags (void)
7294 /* When this routine is called, all of the subsections are still intact
7295 so we walk over subsections instead of sections. */
7296 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7297 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7301 /* Walk over all of the fragments in a subsection. */
7302 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7304 if (fragP
->fr_type
== rs_machine_dependent
7305 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7307 if (next_instr_is_loop_end (fragP
))
7309 if (fragP
->tc_frag_data
.is_no_transform
)
7310 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7312 relax_frag_add_nop (fragP
);
7322 next_instr_is_loop_end (fragS
*fragP
)
7324 const fragS
*next_fragP
;
7326 if (next_frag_is_loop_target (fragP
))
7329 next_fragP
= next_non_empty_frag (fragP
);
7330 if (next_fragP
== NULL
)
7333 if (!next_frag_is_loop_target (next_fragP
))
7336 /* If the size is >= 3 then there is more than one instruction here.
7337 The hardware bug will not fire. */
7338 if (next_fragP
->fr_fix
> 3)
7345 /* Re-process all of the fragments looking to convert all of the
7346 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7347 not MY loop's loop end within 12 bytes, add enough nops here to
7348 make it at least 12 bytes away. In any case close it off with a
7351 static offsetT min_bytes_to_other_loop_end
7352 (fragS
*, fragS
*, offsetT
);
7355 xtensa_fix_close_loop_end_frags (void)
7360 /* When this routine is called, all of the subsections are still intact
7361 so we walk over subsections instead of sections. */
7362 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7363 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7367 fragS
*current_target
= NULL
;
7369 /* Walk over all of the fragments in a subsection. */
7370 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7372 if (fragP
->fr_type
== rs_machine_dependent
7373 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7374 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7375 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7378 && fragP
->fr_type
== rs_machine_dependent
7379 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7382 int bytes_added
= 0;
7384 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7385 /* Max out at 12. */
7386 min_bytes
= min_bytes_to_other_loop_end
7387 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7389 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7391 if (fragP
->tc_frag_data
.is_no_transform
)
7392 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7395 while (min_bytes
+ bytes_added
7396 < REQUIRED_LOOP_DIVIDING_BYTES
)
7400 if (fragP
->fr_var
< length
)
7401 as_fatal (_("fr_var %lu < length %d"),
7402 (long) fragP
->fr_var
, length
);
7405 assemble_nop (length
,
7406 fragP
->fr_literal
+ fragP
->fr_fix
);
7407 fragP
->fr_fix
+= length
;
7408 fragP
->fr_var
-= length
;
7410 bytes_added
+= length
;
7416 assert (fragP
->fr_type
!= rs_machine_dependent
7417 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7423 static offsetT
unrelaxed_frag_min_size (fragS
*);
7426 min_bytes_to_other_loop_end (fragS
*fragP
,
7427 fragS
*current_target
,
7431 fragS
*current_fragP
;
7433 for (current_fragP
= fragP
;
7435 current_fragP
= current_fragP
->fr_next
)
7437 if (current_fragP
->tc_frag_data
.is_loop_target
7438 && current_fragP
!= current_target
)
7441 offset
+= unrelaxed_frag_min_size (current_fragP
);
7443 if (offset
>= max_size
)
7451 unrelaxed_frag_min_size (fragS
*fragP
)
7453 offsetT size
= fragP
->fr_fix
;
7455 /* Add fill size. */
7456 if (fragP
->fr_type
== rs_fill
)
7457 size
+= fragP
->fr_offset
;
7464 unrelaxed_frag_max_size (fragS
*fragP
)
7466 offsetT size
= fragP
->fr_fix
;
7467 switch (fragP
->fr_type
)
7470 /* Empty frags created by the obstack allocation scheme
7471 end up with type 0. */
7476 size
+= fragP
->fr_offset
;
7484 /* No further adjustments needed. */
7486 case rs_machine_dependent
:
7487 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7488 size
+= fragP
->fr_var
;
7491 /* We had darn well better know how big it is. */
7500 /* Re-process all of the fragments looking to convert all
7501 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7504 1) the instruction size count to the loop end label
7505 is too short (<= 2 instructions),
7506 2) loop has a jump or branch in it
7509 1) workaround_all_short_loops is TRUE
7510 2) The generating loop was a 'loopgtz' or 'loopnez'
7511 3) the instruction size count to the loop end label is too short
7513 then convert this frag (and maybe the next one) to generate a NOP.
7514 In any case close it off with a .fill 0. */
7516 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7517 static bfd_boolean
branch_before_loop_end (fragS
*);
7520 xtensa_fix_short_loop_frags (void)
7525 /* When this routine is called, all of the subsections are still intact
7526 so we walk over subsections instead of sections. */
7527 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7528 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7531 fragS
*current_target
= NULL
;
7532 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7534 /* Walk over all of the fragments in a subsection. */
7535 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7537 if (fragP
->fr_type
== rs_machine_dependent
7538 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7539 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7542 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7543 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7544 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7545 current_opcode
= t_insn
.opcode
;
7546 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7547 current_opcode
) == 1);
7550 if (fragP
->fr_type
== rs_machine_dependent
7551 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7553 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7554 && (branch_before_loop_end (fragP
->fr_next
)
7555 || (workaround_all_short_loops
7556 && current_opcode
!= XTENSA_UNDEFINED
7557 && current_opcode
!= xtensa_loop_opcode
)))
7559 if (fragP
->tc_frag_data
.is_no_transform
)
7560 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7562 relax_frag_add_nop (fragP
);
7571 static int unrelaxed_frag_min_insn_count (fragS
*);
7574 count_insns_to_loop_end (fragS
*base_fragP
,
7575 bfd_boolean count_relax_add
,
7578 fragS
*fragP
= NULL
;
7583 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7585 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7586 if (insn_count
>= max_count
)
7589 if (count_relax_add
)
7591 if (fragP
->fr_type
== rs_machine_dependent
7592 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7594 /* In order to add the appropriate number of
7595 NOPs, we count an instruction for downstream
7598 if (insn_count
>= max_count
)
7608 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7610 xtensa_isa isa
= xtensa_default_isa
;
7611 static xtensa_insnbuf insnbuf
= NULL
;
7615 if (!fragP
->tc_frag_data
.is_insn
)
7619 insnbuf
= xtensa_insnbuf_alloc (isa
);
7621 /* Decode the fixed instructions. */
7622 while (offset
< fragP
->fr_fix
)
7626 xtensa_insnbuf_from_chars
7627 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7628 fmt
= xtensa_format_decode (isa
, insnbuf
);
7630 if (fmt
== XTENSA_UNDEFINED
)
7632 as_fatal (_("undecodable instruction in instruction frag"));
7635 offset
+= xtensa_format_length (isa
, fmt
);
7643 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7646 branch_before_loop_end (fragS
*base_fragP
)
7650 for (fragP
= base_fragP
;
7651 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7652 fragP
= fragP
->fr_next
)
7654 if (unrelaxed_frag_has_b_j (fragP
))
7662 unrelaxed_frag_has_b_j (fragS
*fragP
)
7664 static xtensa_insnbuf insnbuf
= NULL
;
7665 xtensa_isa isa
= xtensa_default_isa
;
7668 if (!fragP
->tc_frag_data
.is_insn
)
7672 insnbuf
= xtensa_insnbuf_alloc (isa
);
7674 /* Decode the fixed instructions. */
7675 while (offset
< fragP
->fr_fix
)
7680 xtensa_insnbuf_from_chars
7681 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7682 fmt
= xtensa_format_decode (isa
, insnbuf
);
7683 if (fmt
== XTENSA_UNDEFINED
)
7686 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7688 xtensa_opcode opcode
=
7689 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7690 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7691 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7694 offset
+= xtensa_format_length (isa
, fmt
);
7700 /* Checks to be made after initial assembly but before relaxation. */
7702 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7703 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7706 xtensa_sanity_check (void)
7713 as_where (&file_name
, &line
);
7714 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7715 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7719 /* Walk over all of the fragments in a subsection. */
7720 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7722 if (fragP
->fr_type
== rs_machine_dependent
7723 && fragP
->fr_subtype
== RELAX_SLOTS
7724 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7726 static xtensa_insnbuf insnbuf
= NULL
;
7729 if (fragP
->fr_opcode
!= NULL
)
7732 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7733 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7734 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7736 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7737 t_insn
.opcode
) == 1)
7739 if (is_empty_loop (&t_insn
, fragP
))
7741 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7742 as_bad (_("invalid empty loop"));
7744 if (!is_local_forward_loop (&t_insn
, fragP
))
7746 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7747 as_bad (_("loop target does not follow "
7748 "loop instruction in section"));
7755 new_logical_line (file_name
, line
);
7759 #define LOOP_IMMED_OPN 1
7761 /* Return TRUE if the loop target is the next non-zero fragment. */
7764 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7766 const expressionS
*expr
;
7770 if (insn
->insn_type
!= ITYPE_INSN
)
7773 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7776 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7779 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7781 if (expr
->X_op
!= O_symbol
)
7784 symbolP
= expr
->X_add_symbol
;
7788 if (symbol_get_frag (symbolP
) == NULL
)
7791 if (S_GET_VALUE (symbolP
) != 0)
7794 /* Walk through the zero-size fragments from this one. If we find
7795 the target fragment, then this is a zero-size loop. */
7797 for (next_fragP
= fragP
->fr_next
;
7799 next_fragP
= next_fragP
->fr_next
)
7801 if (next_fragP
== symbol_get_frag (symbolP
))
7803 if (next_fragP
->fr_fix
!= 0)
7811 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7813 const expressionS
*expr
;
7817 if (insn
->insn_type
!= ITYPE_INSN
)
7820 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7823 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7826 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7828 if (expr
->X_op
!= O_symbol
)
7831 symbolP
= expr
->X_add_symbol
;
7835 if (symbol_get_frag (symbolP
) == NULL
)
7838 /* Walk through fragments until we find the target.
7839 If we do not find the target, then this is an invalid loop. */
7841 for (next_fragP
= fragP
->fr_next
;
7843 next_fragP
= next_fragP
->fr_next
)
7845 if (next_fragP
== symbol_get_frag (symbolP
))
7853 #define XTINFO_NAME "Xtensa_Info"
7854 #define XTINFO_NAMESZ 12
7855 #define XTINFO_TYPE 1
7858 xtensa_add_config_info (void)
7864 info_sec
= subseg_new (".xtensa.info", 0);
7865 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7867 data
= xmalloc (100);
7868 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7869 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7870 sz
= strlen (data
) + 1;
7872 /* Add enough null terminators to pad to a word boundary. */
7875 while ((sz
& 3) != 0);
7877 /* Follow the standard note section layout:
7878 First write the length of the name string. */
7880 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7882 /* Next comes the length of the "descriptor", i.e., the actual data. */
7884 md_number_to_chars (p
, (valueT
) sz
, 4);
7886 /* Write the note type. */
7888 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7890 /* Write the name field. */
7891 p
= frag_more (XTINFO_NAMESZ
);
7892 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7894 /* Finally, write the descriptor. */
7896 memcpy (p
, data
, sz
);
7902 /* Alignment Functions. */
7905 get_text_align_power (unsigned target_size
)
7907 if (target_size
<= 4)
7909 assert (target_size
== 8);
7915 get_text_align_max_fill_size (int align_pow
,
7916 bfd_boolean use_nops
,
7917 bfd_boolean use_no_density
)
7920 return (1 << align_pow
);
7922 return 3 * (1 << align_pow
);
7924 return 1 + (1 << align_pow
);
7928 /* Calculate the minimum bytes of fill needed at "address" to align a
7929 target instruction of size "target_size" so that it does not cross a
7930 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7931 the fill can be an arbitrary number of bytes. Otherwise, the space must
7932 be filled by NOP instructions. */
7935 get_text_align_fill_size (addressT address
,
7938 bfd_boolean use_nops
,
7939 bfd_boolean use_no_density
)
7941 addressT alignment
, fill
, fill_limit
, fill_step
;
7942 bfd_boolean skip_one
= FALSE
;
7944 alignment
= (1 << align_pow
);
7945 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7949 fill_limit
= alignment
;
7952 else if (!use_no_density
)
7954 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7955 fill_limit
= alignment
* 2;
7961 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7962 fill_limit
= alignment
* 3;
7966 /* Try all fill sizes until finding one that works. */
7967 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7969 if (skip_one
&& fill
== 1)
7971 if ((address
+ fill
) >> align_pow
7972 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7981 branch_align_power (segT sec
)
7983 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7984 is aligned to at least an 8-byte boundary, then a branch target need
7985 only fit within an 8-byte aligned block of memory to avoid a stall.
7986 Otherwise, try to fit branch targets within 4-byte aligned blocks
7987 (which may be insufficient, e.g., if the section has no alignment, but
7988 it's good enough). */
7989 if (xtensa_fetch_width
== 8)
7991 if (get_recorded_alignment (sec
) >= 3)
7995 assert (xtensa_fetch_width
== 4);
8001 /* This will assert if it is not possible. */
8004 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8010 assert (fill_size
% 3 == 0);
8011 return (fill_size
/ 3);
8014 assert (fill_size
!= 1); /* Bad argument. */
8016 while (fill_size
> 1)
8019 if (fill_size
== 2 || fill_size
== 4)
8021 fill_size
-= insn_size
;
8024 assert (fill_size
!= 1); /* Bad algorithm. */
8030 get_text_align_nth_nop_size (offsetT fill_size
,
8032 bfd_boolean use_no_density
)
8039 assert (fill_size
!= 1); /* Bad argument. */
8041 while (fill_size
> 1)
8044 if (fill_size
== 2 || fill_size
== 4)
8046 fill_size
-= insn_size
;
8056 /* For the given fragment, find the appropriate address
8057 for it to begin at if we are using NOPs to align it. */
8060 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8062 /* The rule is: get next fragment's FIRST instruction. Find
8063 the smallest number of bytes that need to be added to
8064 ensure that the next fragment's FIRST instruction will fit
8067 E.G., 2 bytes : 0, 1, 2 mod 4
8070 If the FIRST instruction MIGHT be relaxed,
8071 assume that it will become a 3-byte instruction.
8073 Note again here that LOOP instructions are not bundleable,
8074 and this relaxation only applies to LOOP opcodes. */
8077 int first_insn_size
;
8079 addressT pre_opcode_bytes
;
8082 xtensa_opcode opcode
;
8083 bfd_boolean is_loop
;
8085 assert (fragP
->fr_type
== rs_machine_dependent
);
8086 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8088 /* Find the loop frag. */
8089 first_insn
= next_non_empty_frag (fragP
);
8090 /* Now find the first insn frag. */
8091 first_insn
= next_non_empty_frag (first_insn
);
8093 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8095 loop_insn_size
= xg_get_single_size (opcode
);
8097 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8098 pre_opcode_bytes
+= loop_insn_size
;
8100 /* For loops, the alignment depends on the size of the
8101 instruction following the loop, not the LOOP instruction. */
8103 if (first_insn
== NULL
)
8104 first_insn_size
= xtensa_fetch_width
;
8106 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8108 /* If it was 8, then we'll need a larger alignment for the section. */
8109 align_power
= get_text_align_power (first_insn_size
);
8110 record_alignment (now_seg
, align_power
);
8112 fill_size
= get_text_align_fill_size
8113 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8114 fragP
->tc_frag_data
.is_no_density
);
8116 return address
+ fill_size
;
8120 /* 3 mechanisms for relaxing an alignment:
8122 Align to a power of 2.
8123 Align so the next fragment's instruction does not cross a word boundary.
8124 Align the current instruction so that if the next instruction
8125 were 3 bytes, it would not cross a word boundary.
8129 zeros - This is easy; always insert zeros.
8130 nops - 3-byte and 2-byte instructions
8134 >=5 : 3-byte instruction + fn (n-3)
8135 widening - widen previous instructions. */
8138 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8140 addressT target_address
, loop_insn_offset
;
8142 xtensa_opcode loop_opcode
;
8143 bfd_boolean is_loop
;
8146 offsetT branch_align
;
8148 assert (fragP
->fr_type
== rs_machine_dependent
);
8149 switch (fragP
->fr_subtype
)
8151 case RELAX_DESIRE_ALIGN
:
8152 target_size
= next_frag_format_size (fragP
);
8153 if (target_size
== XTENSA_UNDEFINED
)
8155 align_power
= branch_align_power (now_seg
);
8156 branch_align
= 1 << align_power
;
8157 /* Don't count on the section alignment being as large as the target. */
8158 if (target_size
> branch_align
)
8159 target_size
= branch_align
;
8160 opt_diff
= get_text_align_fill_size (address
, align_power
,
8161 target_size
, FALSE
, FALSE
);
8163 *max_diff
= (opt_diff
+ branch_align
8164 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8165 assert (*max_diff
>= opt_diff
);
8168 case RELAX_ALIGN_NEXT_OPCODE
:
8169 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8170 loop_insn_offset
= 0;
8171 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8174 /* If the loop has been expanded then the LOOP instruction
8175 could be at an offset from this fragment. */
8176 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8178 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8180 /* In an ideal world, which is what we are shooting for here,
8181 we wouldn't need to use any NOPs immediately prior to the
8182 LOOP instruction. If this approach fails, relax_frag_loop_align
8183 will call get_noop_aligned_address. */
8185 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8186 align_power
= get_text_align_power (target_size
),
8187 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8188 target_size
, FALSE
, FALSE
);
8190 *max_diff
= xtensa_fetch_width
8191 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8192 - target_size
+ opt_diff
;
8193 assert (*max_diff
>= opt_diff
);
8204 /* md_relax_frag Hook and Helper Functions. */
8206 static long relax_frag_loop_align (fragS
*, long);
8207 static long relax_frag_for_align (fragS
*, long);
8208 static long relax_frag_immed
8209 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8212 /* Return the number of bytes added to this fragment, given that the
8213 input has been stretched already by "stretch". */
8216 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8218 xtensa_isa isa
= xtensa_default_isa
;
8219 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8220 long new_stretch
= 0;
8224 static xtensa_insnbuf vbuf
= NULL
;
8225 int slot
, num_slots
;
8228 as_where (&file_name
, &line
);
8229 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8231 fragP
->tc_frag_data
.unreported_expansion
= 0;
8233 switch (fragP
->fr_subtype
)
8235 case RELAX_ALIGN_NEXT_OPCODE
:
8236 /* Always convert. */
8237 if (fragP
->tc_frag_data
.relax_seen
)
8238 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8241 case RELAX_LOOP_END
:
8245 case RELAX_LOOP_END_ADD_NOP
:
8246 /* Add a NOP and switch to .fill 0. */
8247 new_stretch
= relax_frag_add_nop (fragP
);
8251 case RELAX_DESIRE_ALIGN
:
8252 /* Do nothing. The narrowing before this frag will either align
8257 case RELAX_LITERAL_FINAL
:
8260 case RELAX_LITERAL_NR
:
8262 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8263 assert (unreported
== lit_size
);
8264 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8265 fragP
->fr_var
-= lit_size
;
8266 fragP
->fr_fix
+= lit_size
;
8272 vbuf
= xtensa_insnbuf_alloc (isa
);
8274 xtensa_insnbuf_from_chars
8275 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8276 fmt
= xtensa_format_decode (isa
, vbuf
);
8277 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8279 for (slot
= 0; slot
< num_slots
; slot
++)
8281 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8284 if (fragP
->tc_frag_data
.relax_seen
)
8285 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8289 case RELAX_IMMED_STEP1
:
8290 case RELAX_IMMED_STEP2
:
8291 /* Place the immediate. */
8292 new_stretch
+= relax_frag_immed
8293 (now_seg
, fragP
, stretch
,
8294 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8295 fmt
, slot
, stretched_p
, FALSE
);
8299 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8305 case RELAX_LITERAL_POOL_BEGIN
:
8306 case RELAX_LITERAL_POOL_END
:
8307 case RELAX_MAYBE_UNREACHABLE
:
8308 case RELAX_MAYBE_DESIRE_ALIGN
:
8309 /* No relaxation required. */
8312 case RELAX_FILL_NOP
:
8313 case RELAX_UNREACHABLE
:
8314 if (fragP
->tc_frag_data
.relax_seen
)
8315 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8319 as_bad (_("bad relaxation state"));
8322 /* Tell gas we need another relaxation pass. */
8323 if (! fragP
->tc_frag_data
.relax_seen
)
8325 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8329 new_logical_line (file_name
, line
);
8335 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8337 addressT old_address
, old_next_address
, old_size
;
8338 addressT new_address
, new_next_address
, new_size
;
8341 /* All the frags with relax_frag_for_alignment prior to this one in the
8342 section have been done, hopefully eliminating the need for a NOP here.
8343 But, this will put it in if necessary. */
8345 /* Calculate the old address of this fragment and the next fragment. */
8346 old_address
= fragP
->fr_address
- stretch
;
8347 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8348 fragP
->tc_frag_data
.text_expansion
[0]);
8349 old_size
= old_next_address
- old_address
;
8351 /* Calculate the new address of this fragment and the next fragment. */
8352 new_address
= fragP
->fr_address
;
8354 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8355 new_size
= new_next_address
- new_address
;
8357 growth
= new_size
- old_size
;
8359 /* Fix up the text_expansion field and return the new growth. */
8360 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8365 /* Add a NOP instruction. */
8368 relax_frag_add_nop (fragS
*fragP
)
8370 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8371 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8372 assemble_nop (length
, nop_buf
);
8373 fragP
->tc_frag_data
.is_insn
= TRUE
;
8375 if (fragP
->fr_var
< length
)
8377 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8381 fragP
->fr_fix
+= length
;
8382 fragP
->fr_var
-= length
;
8387 static long future_alignment_required (fragS
*, long);
8390 relax_frag_for_align (fragS
*fragP
, long stretch
)
8392 /* Overview of the relaxation procedure for alignment:
8393 We can widen with NOPs or by widening instructions or by filling
8394 bytes after jump instructions. Find the opportune places and widen
8395 them if necessary. */
8400 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8401 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8402 || (fragP
->fr_subtype
== RELAX_SLOTS
8403 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8405 stretch_me
= future_alignment_required (fragP
, stretch
);
8406 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8412 /* We expanded on a previous pass. Can we shrink now? */
8413 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8414 if (shrink
<= stretch
&& stretch
> 0)
8416 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8422 /* Below here, diff > 0. */
8423 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8429 /* Return the address of the next frag that should be aligned.
8431 By "address" we mean the address it _would_ be at if there
8432 is no action taken to align it between here and the target frag.
8433 In other words, if no narrows and no fill nops are used between
8434 here and the frag to align, _even_if_ some of the frags we use
8435 to align targets have already expanded on a previous relaxation
8438 Also, count each frag that may be used to help align the target.
8440 Return 0 if there are no frags left in the chain that need to be
8444 find_address_of_next_align_frag (fragS
**fragPP
,
8448 bfd_boolean
*paddable
)
8450 fragS
*fragP
= *fragPP
;
8451 addressT address
= fragP
->fr_address
;
8453 /* Do not reset the counts to 0. */
8457 /* Limit this to a small search. */
8458 if (*widens
>= (int) xtensa_fetch_width
)
8463 address
+= fragP
->fr_fix
;
8465 if (fragP
->fr_type
== rs_fill
)
8466 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8467 else if (fragP
->fr_type
== rs_machine_dependent
)
8469 switch (fragP
->fr_subtype
)
8471 case RELAX_UNREACHABLE
:
8475 case RELAX_FILL_NOP
:
8477 if (!fragP
->tc_frag_data
.is_no_density
)
8482 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8487 address
+= total_frag_text_expansion (fragP
);;
8491 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8494 case RELAX_ALIGN_NEXT_OPCODE
:
8495 case RELAX_DESIRE_ALIGN
:
8499 case RELAX_MAYBE_UNREACHABLE
:
8500 case RELAX_MAYBE_DESIRE_ALIGN
:
8505 /* Just punt if we don't know the type. */
8512 /* Just punt if we don't know the type. */
8516 fragP
= fragP
->fr_next
;
8524 static long bytes_to_stretch (fragS
*, int, int, int, int);
8527 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8529 fragS
*this_frag
= fragP
;
8533 int narrow_nops
= 0;
8534 bfd_boolean paddable
= FALSE
;
8535 offsetT local_opt_diff
;
8538 int stretch_amount
= 0;
8539 int local_stretch_amount
;
8540 int global_stretch_amount
;
8542 address
= find_address_of_next_align_frag
8543 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8547 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8548 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8550 frag_wane (this_frag
);
8554 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8555 opt_diff
= local_opt_diff
;
8556 assert (opt_diff
>= 0);
8557 assert (max_diff
>= opt_diff
);
8562 fragP
= fragP
->fr_next
;
8564 while (fragP
&& opt_diff
< max_diff
&& address
)
8566 /* We only use these to determine if we can exit early
8567 because there will be plenty of ways to align future
8569 int glob_widens
= 0;
8572 bfd_boolean glob_pad
= 0;
8573 address
= find_address_of_next_align_frag
8574 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8575 /* If there is a padable portion, then skip. */
8576 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8581 offsetT next_m_diff
;
8582 offsetT next_o_diff
;
8584 /* Downrange frags haven't had stretch added to them yet. */
8587 /* The address also includes any text expansion from this
8588 frag in a previous pass, but we don't want that. */
8589 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8591 /* Assume we are going to move at least opt_diff. In
8592 reality, we might not be able to, but assuming that
8593 we will helps catch cases where moving opt_diff pushes
8594 the next target from aligned to unaligned. */
8595 address
+= opt_diff
;
8597 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8599 /* Now cleanup for the adjustments to address. */
8600 next_o_diff
+= opt_diff
;
8601 next_m_diff
+= opt_diff
;
8602 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8603 opt_diff
= next_o_diff
;
8604 if (next_m_diff
< max_diff
)
8605 max_diff
= next_m_diff
;
8606 fragP
= fragP
->fr_next
;
8610 /* If there are enough wideners in between, do it. */
8613 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8615 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8620 local_stretch_amount
8621 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8622 num_widens
, local_opt_diff
);
8623 global_stretch_amount
8624 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8625 num_widens
, opt_diff
);
8626 /* If the condition below is true, then the frag couldn't
8627 stretch the correct amount for the global case, so we just
8628 optimize locally. We'll rely on the subsequent frags to get
8629 the correct alignment in the global case. */
8630 if (global_stretch_amount
< local_stretch_amount
)
8631 stretch_amount
= local_stretch_amount
;
8633 stretch_amount
= global_stretch_amount
;
8635 if (this_frag
->fr_subtype
== RELAX_SLOTS
8636 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8637 assert (stretch_amount
<= 1);
8638 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8640 if (this_frag
->tc_frag_data
.is_no_density
)
8641 assert (stretch_amount
== 3 || stretch_amount
== 0);
8643 assert (stretch_amount
<= 3);
8646 return stretch_amount
;
8650 /* The idea: widen everything you can to get a target or loop aligned,
8651 then start using NOPs.
8653 When we must have a NOP, here is a table of how we decide
8654 (so you don't have to fight through the control flow below):
8656 wide_nops = the number of wide NOPs available for aligning
8657 narrow_nops = the number of narrow NOPs available for aligning
8658 (a subset of wide_nops)
8659 widens = the number of narrow instructions that should be widened
8666 b 0 1 1 (case 3a makes this case unnecessary)
8669 c 0 1 2 (case 4a makes this case unnecessary)
8672 c 0 2 1 (case 5b makes this case unnecessary)
8675 c 0 1 4 (case 6b makes this case unnecessary)
8676 d 1 1 1 (case 6a makes this case unnecessary)
8677 e 0 2 2 (case 6a makes this case unnecessary)
8678 f 0 3 0 (case 6a makes this case unnecessary)
8681 c 1 1 2 (case 7b makes this case unnecessary)
8682 d 0 1 5 (case 7a makes this case unnecessary)
8683 e 0 2 3 (case 7b makes this case unnecessary)
8684 f 0 3 1 (case 7b makes this case unnecessary)
8685 g 1 2 1 (case 7b makes this case unnecessary)
8689 bytes_to_stretch (fragS
*this_frag
,
8695 int bytes_short
= desired_diff
- num_widens
;
8697 assert (desired_diff
>= 0 && desired_diff
< 8);
8698 if (desired_diff
== 0)
8701 assert (wide_nops
> 0 || num_widens
> 0);
8703 /* Always prefer widening to NOP-filling. */
8704 if (bytes_short
< 0)
8706 /* There are enough RELAX_NARROW frags after this one
8707 to align the target without widening this frag in any way. */
8711 if (bytes_short
== 0)
8713 /* Widen every narrow between here and the align target
8714 and the align target will be properly aligned. */
8715 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8721 /* From here we will need at least one NOP to get an alignment.
8722 However, we may not be able to align at all, in which case,
8724 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8726 switch (desired_diff
)
8731 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8732 return 2; /* case 2 */
8738 return 3; /* case 3a */
8740 if (num_widens
>= 1 && wide_nops
== 1)
8741 return 3; /* case 4a */
8742 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8743 return 2; /* case 4b */
8746 if (num_widens
>= 2 && wide_nops
== 1)
8747 return 3; /* case 5a */
8748 /* We will need two nops. Are there enough nops
8749 between here and the align target? */
8750 if (wide_nops
< 2 || narrow_nops
== 0)
8752 /* Are there other nops closer that can serve instead? */
8753 if (wide_nops
> 2 && narrow_nops
> 1)
8755 /* Take the density one first, because there might not be
8756 another density one available. */
8757 if (!this_frag
->tc_frag_data
.is_no_density
)
8758 return 2; /* case 5b narrow */
8760 return 3; /* case 5b wide */
8764 return 3; /* case 6a */
8765 else if (num_widens
>= 3 && wide_nops
== 1)
8766 return 3; /* case 6b */
8769 if (wide_nops
== 1 && num_widens
>= 4)
8770 return 3; /* case 7a */
8771 else if (wide_nops
== 2 && num_widens
>= 1)
8772 return 3; /* case 7b */
8780 /* We will need a NOP no matter what, but should we widen
8781 this instruction to help?
8783 This is a RELAX_NARROW frag. */
8784 switch (desired_diff
)
8793 if (wide_nops
>= 1 && num_widens
== 1)
8794 return 1; /* case 4a */
8797 if (wide_nops
>= 1 && num_widens
== 2)
8798 return 1; /* case 5a */
8802 return 0; /* case 6a */
8803 else if (wide_nops
>= 1 && num_widens
== 3)
8804 return 1; /* case 6b */
8807 if (wide_nops
>= 1 && num_widens
== 4)
8808 return 1; /* case 7a */
8809 else if (wide_nops
>= 2 && num_widens
== 1)
8810 return 1; /* case 7b */
8823 relax_frag_immed (segT segP
,
8830 bfd_boolean estimate_only
)
8834 bfd_boolean negatable_branch
= FALSE
;
8835 bfd_boolean branch_jmp_to_next
= FALSE
;
8836 bfd_boolean wide_insn
= FALSE
;
8837 xtensa_isa isa
= xtensa_default_isa
;
8839 offsetT frag_offset
;
8842 int num_text_bytes
, num_literal_bytes
;
8843 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8845 assert (fragP
->fr_opcode
!= NULL
);
8847 xg_clear_vinsn (&cur_vinsn
);
8848 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8849 if (cur_vinsn
.num_slots
> 1)
8852 tinsn
= cur_vinsn
.slots
[slot
];
8853 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8855 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8858 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8859 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8861 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8863 old_size
= xtensa_format_length (isa
, fmt
);
8865 /* Special case: replace a branch to the next instruction with a NOP.
8866 This is required to work around a hardware bug in T1040.0 and also
8867 serves as an optimization. */
8869 if (branch_jmp_to_next
8870 && ((old_size
== 2) || (old_size
== 3))
8871 && !next_frag_is_loop_target (fragP
))
8874 /* Here is the fun stuff: Get the immediate field from this
8875 instruction. If it fits, we are done. If not, find the next
8876 instruction sequence that fits. */
8878 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8879 istack_init (&istack
);
8880 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8881 min_steps
, stretch
);
8882 if (num_steps
< min_steps
)
8884 as_fatal (_("internal error: relaxation failed"));
8888 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8890 as_fatal (_("internal error: relaxation requires too many steps"));
8894 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8896 /* Figure out the number of bytes needed. */
8898 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8900 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8902 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8904 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8907 num_text_bytes
+= old_size
;
8908 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8909 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8911 total_text_diff
= num_text_bytes
- old_size
;
8912 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8914 /* It MUST get larger. If not, we could get an infinite loop. */
8915 assert (num_text_bytes
>= 0);
8916 assert (literal_diff
>= 0);
8917 assert (total_text_diff
>= 0);
8919 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8920 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8921 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8922 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8924 /* Find the associated expandable literal for this. */
8925 if (literal_diff
!= 0)
8927 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8930 assert (literal_diff
== 4);
8931 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8933 /* We expect that the literal section state has NOT been
8935 assert (lit_fragP
->fr_type
== rs_machine_dependent
8936 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8937 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8939 /* We need to mark this section for another iteration
8945 if (negatable_branch
&& istack
.ninsn
> 1)
8946 update_next_frag_state (fragP
);
8948 return this_text_diff
;
8952 /* md_convert_frag Hook and Helper Functions. */
8954 static void convert_frag_align_next_opcode (fragS
*);
8955 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8956 static void convert_frag_fill_nop (fragS
*);
8957 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8960 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8962 static xtensa_insnbuf vbuf
= NULL
;
8963 xtensa_isa isa
= xtensa_default_isa
;
8970 as_where (&file_name
, &line
);
8971 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8973 switch (fragp
->fr_subtype
)
8975 case RELAX_ALIGN_NEXT_OPCODE
:
8976 /* Always convert. */
8977 convert_frag_align_next_opcode (fragp
);
8980 case RELAX_DESIRE_ALIGN
:
8981 /* Do nothing. If not aligned already, too bad. */
8985 case RELAX_LITERAL_FINAL
:
8990 vbuf
= xtensa_insnbuf_alloc (isa
);
8992 xtensa_insnbuf_from_chars
8993 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8994 fmt
= xtensa_format_decode (isa
, vbuf
);
8995 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8997 for (slot
= 0; slot
< num_slots
; slot
++)
8999 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9002 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9006 case RELAX_IMMED_STEP1
:
9007 case RELAX_IMMED_STEP2
:
9008 /* Place the immediate. */
9011 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9016 /* This is OK because some slots could have
9017 relaxations and others have none. */
9023 case RELAX_UNREACHABLE
:
9024 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9025 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9026 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9030 case RELAX_MAYBE_UNREACHABLE
:
9031 case RELAX_MAYBE_DESIRE_ALIGN
:
9035 case RELAX_FILL_NOP
:
9036 convert_frag_fill_nop (fragp
);
9039 case RELAX_LITERAL_NR
:
9040 if (use_literal_section
)
9042 /* This should have been handled during relaxation. When
9043 relaxing a code segment, literals sometimes need to be
9044 added to the corresponding literal segment. If that
9045 literal segment has already been relaxed, then we end up
9046 in this situation. Marking the literal segments as data
9047 would make this happen less often (since GAS always relaxes
9048 code before data), but we could still get into trouble if
9049 there are instructions in a segment that is not marked as
9050 containing code. Until we can implement a better solution,
9051 cheat and adjust the addresses of all the following frags.
9052 This could break subsequent alignments, but the linker's
9053 literal coalescing will do that anyway. */
9056 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9057 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9058 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9061 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9065 as_bad (_("invalid relaxation fragment result"));
9070 new_logical_line (file_name
, line
);
9075 convert_frag_align_next_opcode (fragS
*fragp
)
9077 char *nop_buf
; /* Location for Writing. */
9078 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9079 addressT aligned_address
;
9083 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9085 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9086 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9087 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9089 for (nop
= 0; nop
< nop_count
; nop
++)
9092 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9094 assemble_nop (nop_size
, nop_buf
);
9095 nop_buf
+= nop_size
;
9098 fragp
->fr_fix
+= fill_size
;
9099 fragp
->fr_var
-= fill_size
;
9104 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9106 TInsn tinsn
, single_target
;
9107 int size
, old_size
, diff
;
9108 offsetT frag_offset
;
9111 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9113 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9115 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9116 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9117 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9122 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9124 /* No conversion. */
9129 assert (fragP
->fr_opcode
!= NULL
);
9131 /* Frags in this relaxation state should only contain
9132 single instruction bundles. */
9133 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9135 /* Just convert it to a wide form.... */
9137 old_size
= xg_get_single_size (tinsn
.opcode
);
9139 tinsn_init (&single_target
);
9140 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9142 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9144 as_bad (_("unable to widen instruction"));
9148 size
= xg_get_single_size (single_target
.opcode
);
9149 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9152 diff
= size
- old_size
;
9154 assert (diff
<= fragP
->fr_var
);
9155 fragP
->fr_var
-= diff
;
9156 fragP
->fr_fix
+= diff
;
9164 convert_frag_fill_nop (fragS
*fragP
)
9166 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9167 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9168 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9169 - fragP
->fr_address
- fragP
->fr_fix
));
9172 /* No conversion. */
9176 assemble_nop (size
, loc
);
9177 fragP
->tc_frag_data
.is_insn
= TRUE
;
9178 fragP
->fr_var
-= size
;
9179 fragP
->fr_fix
+= size
;
9184 static fixS
*fix_new_exp_in_seg
9185 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9186 bfd_reloc_code_real_type
);
9187 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9190 convert_frag_immed (segT segP
,
9196 char *immed_instr
= fragP
->fr_opcode
;
9198 bfd_boolean expanded
= FALSE
;
9199 bfd_boolean branch_jmp_to_next
= FALSE
;
9200 char *fr_opcode
= fragP
->fr_opcode
;
9201 xtensa_isa isa
= xtensa_default_isa
;
9202 bfd_boolean wide_insn
= FALSE
;
9204 bfd_boolean is_loop
;
9206 assert (fr_opcode
!= NULL
);
9208 xg_clear_vinsn (&cur_vinsn
);
9210 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9211 if (cur_vinsn
.num_slots
> 1)
9214 orig_tinsn
= cur_vinsn
.slots
[slot
];
9215 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9217 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9219 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9220 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9222 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9224 /* Conversion just inserts a NOP and marks the fix as completed. */
9225 bytes
= xtensa_format_length (isa
, fmt
);
9228 cur_vinsn
.slots
[slot
].opcode
=
9229 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9230 cur_vinsn
.slots
[slot
].ntok
= 0;
9234 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9235 assert (bytes
== 2 || bytes
== 3);
9236 build_nop (&cur_vinsn
.slots
[0], bytes
);
9237 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9239 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9240 xtensa_insnbuf_to_chars
9241 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9246 /* Here is the fun stuff: Get the immediate field from this
9247 instruction. If it fits, we're done. If not, find the next
9248 instruction sequence that fits. */
9252 symbolS
*lit_sym
= NULL
;
9254 int target_offset
= 0;
9257 symbolS
*gen_label
= NULL
;
9258 offsetT frag_offset
;
9259 bfd_boolean first
= TRUE
;
9260 bfd_boolean last_is_jump
;
9262 /* It does not fit. Find something that does and
9263 convert immediately. */
9264 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9265 istack_init (&istack
);
9266 xg_assembly_relax (&istack
, &orig_tinsn
,
9267 segP
, fragP
, frag_offset
, min_steps
, 0);
9269 old_size
= xtensa_format_length (isa
, fmt
);
9271 /* Assemble this right inline. */
9273 /* First, create the mapping from a label name to the REAL label. */
9275 for (i
= 0; i
< istack
.ninsn
; i
++)
9277 TInsn
*tinsn
= &istack
.insn
[i
];
9280 switch (tinsn
->insn_type
)
9283 if (lit_sym
!= NULL
)
9284 as_bad (_("multiple literals in expansion"));
9285 /* First find the appropriate space in the literal pool. */
9286 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9287 if (lit_frag
== NULL
)
9288 as_bad (_("no registered fragment for literal"));
9289 if (tinsn
->ntok
!= 1)
9290 as_bad (_("number of literal tokens != 1"));
9292 /* Set the literal symbol and add a fixup. */
9293 lit_sym
= lit_frag
->fr_symbol
;
9297 if (align_targets
&& !is_loop
)
9299 fragS
*unreach
= fragP
->fr_next
;
9300 while (!(unreach
->fr_type
== rs_machine_dependent
9301 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9302 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9304 unreach
= unreach
->fr_next
;
9307 assert (unreach
->fr_type
== rs_machine_dependent
9308 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9309 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9311 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9313 assert (gen_label
== NULL
);
9314 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9315 fr_opcode
- fragP
->fr_literal
9316 + target_offset
, fragP
);
9320 if (first
&& wide_insn
)
9322 target_offset
+= xtensa_format_length (isa
, fmt
);
9324 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9325 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9328 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9335 last_is_jump
= FALSE
;
9336 for (i
= 0; i
< istack
.ninsn
; i
++)
9338 TInsn
*tinsn
= &istack
.insn
[i
];
9342 bfd_reloc_code_real_type reloc_type
;
9344 switch (tinsn
->insn_type
)
9347 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9348 /* Already checked. */
9349 assert (lit_frag
!= NULL
);
9350 assert (lit_sym
!= NULL
);
9351 assert (tinsn
->ntok
== 1);
9353 target_seg
= S_GET_SEGMENT (lit_sym
);
9354 assert (target_seg
);
9355 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9356 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9357 &tinsn
->tok
[0], FALSE
, reloc_type
);
9364 xg_resolve_labels (tinsn
, gen_label
);
9365 xg_resolve_literals (tinsn
, lit_sym
);
9366 if (wide_insn
&& first
)
9369 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9371 cur_vinsn
.slots
[slot
] = *tinsn
;
9375 cur_vinsn
.slots
[slot
].opcode
=
9376 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9377 cur_vinsn
.slots
[slot
].ntok
= 0;
9379 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9380 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9381 (unsigned char *) immed_instr
, 0);
9382 fragP
->tc_frag_data
.is_insn
= TRUE
;
9383 size
= xtensa_format_length (isa
, fmt
);
9384 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9387 (tinsn
, immed_instr
+ size
, fragP
,
9388 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9389 size
+= xg_get_single_size (tinsn
->opcode
);
9394 size
= xg_get_single_size (tinsn
->opcode
);
9395 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9396 immed_instr
- fragP
->fr_literal
, TRUE
);
9398 immed_instr
+= size
;
9404 diff
= total_size
- old_size
;
9408 assert (diff
<= fragP
->fr_var
);
9409 fragP
->fr_var
-= diff
;
9410 fragP
->fr_fix
+= diff
;
9413 /* Check for undefined immediates in LOOP instructions. */
9417 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9418 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9420 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9423 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9424 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9426 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9431 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9432 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9434 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9436 /* Add an expansion note on the expanded instruction. */
9437 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9438 &orig_tinsn
.tok
[0], TRUE
,
9439 BFD_RELOC_XTENSA_ASM_EXPAND
);
9444 /* Add a new fix expression into the desired segment. We have to
9445 switch to that segment to do this. */
9448 fix_new_exp_in_seg (segT new_seg
,
9455 bfd_reloc_code_real_type r_type
)
9459 subsegT subseg
= now_subseg
;
9461 assert (new_seg
!= 0);
9462 subseg_set (new_seg
, new_subseg
);
9464 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9465 subseg_set (seg
, subseg
);
9470 /* Relax a loop instruction so that it can span loop >256 bytes.
9476 addi as, as, lo8 (label-.L1)
9477 addmi as, as, mid8 (label-.L1)
9488 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9493 unsigned long target
;
9494 static xtensa_insnbuf insnbuf
= NULL
;
9495 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9496 xtensa_isa isa
= xtensa_default_isa
;
9497 addressT loop_offset
;
9498 addressT addi_offset
= 9;
9499 addressT addmi_offset
= 12;
9504 insnbuf
= xtensa_insnbuf_alloc (isa
);
9506 /* Get the loop offset. */
9507 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9509 /* Validate that there really is a LOOP at the loop_offset. Because
9510 loops are not bundleable, we can assume that the instruction will be
9512 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9513 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9515 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9516 addi_offset
+= loop_offset
;
9517 addmi_offset
+= loop_offset
;
9519 assert (tinsn
->ntok
== 2);
9520 if (tinsn
->tok
[1].X_op
== O_constant
)
9521 target
= tinsn
->tok
[1].X_add_number
;
9522 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9524 /* Find the fragment. */
9525 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9526 assert (S_GET_SEGMENT (sym
) == segP
9527 || S_GET_SEGMENT (sym
) == absolute_section
);
9528 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9532 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9537 know (symbolP
->sy_frag
);
9538 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9539 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9541 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9542 loop_length_hi
= loop_length
& ~0x0ff;
9543 loop_length_lo
= loop_length
& 0x0ff;
9544 if (loop_length_lo
>= 128)
9546 loop_length_lo
-= 256;
9547 loop_length_hi
+= 256;
9550 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9551 32512. If the loop is larger than that, then we just fail. */
9552 if (loop_length_hi
> 32512)
9553 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9554 _("loop too long for LOOP instruction"));
9556 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9557 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9559 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9560 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9562 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9563 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9565 fragP
->tc_frag_data
.is_insn
= TRUE
;
9566 xtensa_insnbuf_to_chars
9567 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9569 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9570 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9571 xtensa_insnbuf_to_chars
9572 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9574 /* Walk through all of the frags from here to the loop end
9575 and mark them as no_transform to keep them from being modified
9576 by the linker. If we ever have a relocation for the
9577 addi/addmi of the difference of two symbols we can remove this. */
9580 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9581 next_fragP
= next_fragP
->fr_next
)
9583 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9584 if (next_fragP
->tc_frag_data
.is_loop_target
)
9586 if (target_count
== 2)
9592 /* A map that keeps information on a per-subsegment basis. This is
9593 maintained during initial assembly, but is invalid once the
9594 subsegments are smashed together. I.E., it cannot be used during
9597 typedef struct subseg_map_struct
9605 float total_freq
; /* fall-through + branch target frequency */
9606 float target_freq
; /* branch target frequency alone */
9608 struct subseg_map_struct
*next
;
9612 static subseg_map
*sseg_map
= NULL
;
9615 get_subseg_info (segT seg
, subsegT subseg
)
9617 subseg_map
*subseg_e
;
9619 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9621 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9629 add_subseg_info (segT seg
, subsegT subseg
)
9631 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9632 memset (subseg_e
, 0, sizeof (subseg_map
));
9633 subseg_e
->seg
= seg
;
9634 subseg_e
->subseg
= subseg
;
9635 subseg_e
->flags
= 0;
9636 /* Start off considering every branch target very important. */
9637 subseg_e
->target_freq
= 1.0;
9638 subseg_e
->total_freq
= 1.0;
9639 subseg_e
->next
= sseg_map
;
9640 sseg_map
= subseg_e
;
9646 get_last_insn_flags (segT seg
, subsegT subseg
)
9648 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9650 return subseg_e
->flags
;
9656 set_last_insn_flags (segT seg
,
9661 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9663 subseg_e
= add_subseg_info (seg
, subseg
);
9665 subseg_e
->flags
|= fl
;
9667 subseg_e
->flags
&= ~fl
;
9672 get_subseg_total_freq (segT seg
, subsegT subseg
)
9674 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9676 return subseg_e
->total_freq
;
9682 get_subseg_target_freq (segT seg
, subsegT subseg
)
9684 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9686 return subseg_e
->target_freq
;
9692 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9694 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9696 subseg_e
= add_subseg_info (seg
, subseg
);
9697 subseg_e
->total_freq
= total_f
;
9698 subseg_e
->target_freq
= target_f
;
9702 /* Segment Lists and emit_state Stuff. */
9705 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9710 segT literal_section
= head
->seg
;
9712 /* Move the literal section to the front of the section list. */
9713 assert (literal_section
);
9714 if (literal_section
!= stdoutput
->sections
)
9716 bfd_section_list_remove (stdoutput
, literal_section
);
9717 bfd_section_list_prepend (stdoutput
, literal_section
);
9724 static void mark_literal_frags (seg_list
*);
9727 xtensa_move_literals (void)
9730 frchainS
*frchain_from
, *frchain_to
;
9731 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9732 fragS
**frag_splice
;
9735 fixS
*fix
, *next_fix
, **fix_splice
;
9738 mark_literal_frags (literal_head
->next
);
9740 if (use_literal_section
)
9743 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9745 /* Keep the literals for .init and .fini in separate sections. */
9746 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9747 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9750 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9751 search_frag
= frchain_from
->frch_root
;
9752 literal_pool
= NULL
;
9754 frag_splice
= &(frchain_from
->frch_root
);
9756 while (!search_frag
->tc_frag_data
.literal_frag
)
9758 assert (search_frag
->fr_fix
== 0
9759 || search_frag
->fr_type
== rs_align
);
9760 search_frag
= search_frag
->fr_next
;
9763 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9764 == RELAX_LITERAL_POOL_BEGIN
);
9765 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9767 /* Make sure that all the frags in this series are closed, and
9768 that there is at least one left over of zero-size. This
9769 prevents us from making a segment with an frchain without any
9771 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9772 xtensa_set_frag_assembly_state (frag_now
);
9773 last_frag
= frag_now
;
9774 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9775 xtensa_set_frag_assembly_state (frag_now
);
9777 while (search_frag
!= frag_now
)
9779 next_frag
= search_frag
->fr_next
;
9781 /* First, move the frag out of the literal section and
9782 to the appropriate place. */
9783 if (search_frag
->tc_frag_data
.literal_frag
)
9785 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9786 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9787 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9788 assert (frchain_to
);
9790 insert_after
= literal_pool
;
9792 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9793 insert_after
= insert_after
->fr_next
;
9795 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9797 *frag_splice
= next_frag
;
9798 search_frag
->fr_next
= insert_after
->fr_next
;
9799 insert_after
->fr_next
= search_frag
;
9800 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9802 /* Now move any fixups associated with this frag to the
9804 fix
= frchain_from
->fix_root
;
9805 fix_splice
= &(frchain_from
->fix_root
);
9808 next_fix
= fix
->fx_next
;
9809 if (fix
->fx_frag
== search_frag
)
9811 *fix_splice
= next_fix
;
9812 fix
->fx_next
= frchain_to
->fix_root
;
9813 frchain_to
->fix_root
= fix
;
9814 if (frchain_to
->fix_tail
== NULL
)
9815 frchain_to
->fix_tail
= fix
;
9818 fix_splice
= &(fix
->fx_next
);
9821 search_frag
= next_frag
;
9824 if (frchain_from
->fix_root
!= NULL
)
9826 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9827 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9829 assert (frchain_from
->fix_root
== NULL
);
9831 frchain_from
->fix_tail
= NULL
;
9832 xtensa_restore_emit_state (&state
);
9835 /* Now fix up the SEGMENT value for all the literal symbols. */
9836 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9838 symbolS
*lit_sym
= lit
->sym
;
9839 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9841 S_SET_SEGMENT (lit_sym
, dest_seg
);
9846 /* Walk over all the frags for segments in a list and mark them as
9847 containing literals. As clunky as this is, we can't rely on frag_var
9848 and frag_variant to get called in all situations. */
9851 mark_literal_frags (seg_list
*segment
)
9853 frchainS
*frchain_from
;
9858 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9859 search_frag
= frchain_from
->frch_root
;
9862 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9863 search_frag
= search_frag
->fr_next
;
9865 segment
= segment
->next
;
9871 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9873 /* Move all of the sections in the section list to come
9874 after "after" in the gnu segment list. */
9879 segT literal_section
= head
->seg
;
9881 /* Move the literal section after "after". */
9882 assert (literal_section
);
9883 if (literal_section
!= after
)
9885 bfd_section_list_remove (stdoutput
, literal_section
);
9886 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9894 /* Push all the literal segments to the end of the gnu list. */
9897 xtensa_reorder_segments (void)
9904 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9910 /* Now that we have the last section, push all the literal
9911 sections to the end. */
9912 xtensa_reorder_seg_list (literal_head
, last_sec
);
9914 /* Now perform the final error check. */
9915 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9917 assert (new_count
== old_count
);
9921 /* Change the emit state (seg, subseg, and frag related stuff) to the
9922 correct location. Return a emit_state which can be passed to
9923 xtensa_restore_emit_state to return to current fragment. */
9926 xtensa_switch_to_literal_fragment (emit_state
*result
)
9928 if (directive_state
[directive_absolute_literals
])
9930 segT lit4_seg
= cache_literal_section (TRUE
);
9931 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9934 xtensa_switch_to_non_abs_literal_fragment (result
);
9936 /* Do a 4-byte align here. */
9937 frag_align (2, 0, 0);
9938 record_alignment (now_seg
, 2);
9943 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9945 static bfd_boolean recursive
= FALSE
;
9946 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9948 bfd_boolean is_init
=
9949 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9950 bfd_boolean is_fini
=
9951 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9953 if (pool_location
== NULL
9954 && !use_literal_section
9956 && !is_init
&& ! is_fini
)
9958 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9960 /* When we mark a literal pool location, we want to put a frag in
9961 the literal pool that points to it. But to do that, we want to
9962 switch_to_literal_fragment. But literal sections don't have
9963 literal pools, so their location is always null, so we would
9964 recurse forever. This is kind of hacky, but it works. */
9967 xtensa_mark_literal_pool_location ();
9971 lit_seg
= cache_literal_section (FALSE
);
9972 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
9974 if (!use_literal_section
9975 && !is_init
&& !is_fini
9976 && get_literal_pool_location (now_seg
) != pool_location
)
9978 /* Close whatever frag is there. */
9979 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9980 xtensa_set_frag_assembly_state (frag_now
);
9981 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9982 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9983 xtensa_set_frag_assembly_state (frag_now
);
9988 /* Call this function before emitting data into the literal section.
9989 This is a helper function for xtensa_switch_to_literal_fragment.
9990 This is similar to a .section new_now_seg subseg. */
9993 xtensa_switch_section_emit_state (emit_state
*state
,
9995 subsegT new_now_subseg
)
9997 state
->name
= now_seg
->name
;
9998 state
->now_seg
= now_seg
;
9999 state
->now_subseg
= now_subseg
;
10000 state
->generating_literals
= generating_literals
;
10001 generating_literals
++;
10002 subseg_set (new_now_seg
, new_now_subseg
);
10006 /* Use to restore the emitting into the normal place. */
10009 xtensa_restore_emit_state (emit_state
*state
)
10011 generating_literals
= state
->generating_literals
;
10012 subseg_set (state
->now_seg
, state
->now_subseg
);
10016 /* Predicate function used to look up a section in a particular group. */
10019 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10021 const char *gname
= inf
;
10022 const char *group_name
= elf_group_name (sec
);
10024 return (group_name
== gname
10025 || (group_name
!= NULL
10027 && strcmp (group_name
, gname
) == 0));
10031 /* Get the literal section to be used for the current text section.
10032 The result may be cached in the default_lit_sections structure. */
10035 cache_literal_section (bfd_boolean use_abs_literals
)
10037 const char *text_name
, *group_name
= 0;
10038 char *base_name
, *name
, *suffix
;
10040 segT seg
, current_section
;
10041 int current_subsec
;
10042 bfd_boolean linkonce
= FALSE
;
10044 /* Save the current section/subsection. */
10045 current_section
= now_seg
;
10046 current_subsec
= now_subseg
;
10048 /* Clear the cached values if they are no longer valid. */
10049 if (now_seg
!= default_lit_sections
.current_text_seg
)
10051 default_lit_sections
.current_text_seg
= now_seg
;
10052 default_lit_sections
.lit_seg
= NULL
;
10053 default_lit_sections
.lit4_seg
= NULL
;
10056 /* Check if the literal section is already cached. */
10057 if (use_abs_literals
)
10058 pcached
= &default_lit_sections
.lit4_seg
;
10060 pcached
= &default_lit_sections
.lit_seg
;
10065 text_name
= default_lit_sections
.lit_prefix
;
10066 if (! text_name
|| ! *text_name
)
10068 text_name
= segment_name (current_section
);
10069 group_name
= elf_group_name (current_section
);
10070 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10073 base_name
= use_abs_literals
? ".lit4" : ".literal";
10076 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10077 sprintf (name
, "%s.%s", base_name
, group_name
);
10079 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10081 suffix
= strchr (text_name
+ linkonce_len
, '.');
10083 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10084 + (suffix
? strlen (suffix
) : 0));
10085 strcpy (name
, ".gnu.linkonce");
10086 strcat (name
, base_name
);
10088 strcat (name
, suffix
);
10093 /* If the section name ends with ".text", then replace that suffix
10094 instead of appending an additional suffix. */
10095 size_t len
= strlen (text_name
);
10096 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10099 name
= xmalloc (len
+ strlen (base_name
) + 1);
10100 strcpy (name
, text_name
);
10101 strcpy (name
+ len
, base_name
);
10104 /* Canonicalize section names to allow renaming literal sections.
10105 The group name, if any, came from the current text section and
10106 has already been canonicalized. */
10107 name
= tc_canonicalize_symbol_name (name
);
10109 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10110 (void *) group_name
);
10115 seg
= subseg_force_new (name
, 0);
10117 if (! use_abs_literals
)
10119 /* Add the newly created literal segment to the list. */
10120 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10122 n
->next
= literal_head
->next
;
10123 literal_head
->next
= n
;
10126 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10127 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10128 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10130 elf_group_name (seg
) = group_name
;
10132 bfd_set_section_flags (stdoutput
, seg
, flags
);
10133 bfd_set_section_alignment (stdoutput
, seg
, 2);
10137 subseg_set (current_section
, current_subsec
);
10142 /* Property Tables Stuff. */
10144 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10145 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10146 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10148 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10149 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10151 static bfd_boolean
get_frag_is_literal (const fragS
*);
10152 static void xtensa_create_property_segments
10153 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10154 static void xtensa_create_xproperty_segments
10155 (frag_flags_fn
, const char *, xt_section_type
);
10156 static segment_info_type
*retrieve_segment_info (segT
);
10157 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10158 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10159 static void add_xt_block_frags
10160 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10161 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10162 static void xtensa_frag_flags_init (frag_flags
*);
10163 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10164 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10165 static void add_xt_prop_frags
10166 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10168 /* Set up property tables after relaxation. */
10171 xtensa_post_relax_hook (void)
10173 xtensa_move_seg_list_to_beginning (literal_head
);
10175 xtensa_find_unmarked_state_frags ();
10177 xtensa_create_property_segments (get_frag_is_literal
,
10179 XTENSA_LIT_SEC_NAME
,
10181 xtensa_create_xproperty_segments (get_frag_property_flags
,
10182 XTENSA_PROP_SEC_NAME
,
10185 if (warn_unaligned_branch_targets
)
10186 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10187 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10191 /* This function is only meaningful after xtensa_move_literals. */
10194 get_frag_is_literal (const fragS
*fragP
)
10196 assert (fragP
!= NULL
);
10197 return fragP
->tc_frag_data
.is_literal
;
10202 xtensa_create_property_segments (frag_predicate property_function
,
10203 frag_predicate end_property_function
,
10204 const char *section_name_base
,
10205 xt_section_type sec_type
)
10209 /* Walk over all of the current segments.
10210 Walk over each fragment
10211 For each non-empty fragment,
10212 Build a property record (append where possible). */
10214 for (seclist
= &stdoutput
->sections
;
10215 seclist
&& *seclist
;
10216 seclist
= &(*seclist
)->next
)
10218 segT sec
= *seclist
;
10221 flags
= bfd_get_section_flags (stdoutput
, sec
);
10222 if (flags
& SEC_DEBUGGING
)
10224 if (!(flags
& SEC_ALLOC
))
10227 if (section_has_property (sec
, property_function
))
10230 xtensa_get_property_section (sec
, section_name_base
);
10231 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10232 xtensa_block_info
**xt_blocks
=
10233 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10234 /* Walk over all of the frchains here and add new sections. */
10235 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10236 end_property_function
);
10240 /* Now we fill them out.... */
10242 for (seclist
= &stdoutput
->sections
;
10243 seclist
&& *seclist
;
10244 seclist
= &(*seclist
)->next
)
10246 segment_info_type
*seginfo
;
10247 xtensa_block_info
*block
;
10248 segT sec
= *seclist
;
10250 seginfo
= seg_info (sec
);
10251 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10255 xtensa_block_info
*cur_block
;
10256 /* This is a section with some data. */
10258 bfd_size_type rec_size
;
10260 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10263 rec_size
= num_recs
* 8;
10264 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10266 /* In order to make this work with the assembler, we have to
10267 build some frags and then build the "fixups" for it. It
10268 would be easier to just set the contents then set the
10273 /* Allocate a fragment and leak it. */
10275 bfd_size_type frag_size
;
10277 frchainS
*frchainP
;
10281 frag_size
= sizeof (fragS
) + rec_size
;
10282 fragP
= (fragS
*) xmalloc (frag_size
);
10284 memset (fragP
, 0, frag_size
);
10285 fragP
->fr_address
= 0;
10286 fragP
->fr_next
= NULL
;
10287 fragP
->fr_fix
= rec_size
;
10289 fragP
->fr_type
= rs_fill
;
10290 /* The rest are zeros. */
10292 frchainP
= seginfo
->frchainP
;
10293 frchainP
->frch_root
= fragP
;
10294 frchainP
->frch_last
= fragP
;
10296 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10297 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10299 seginfo
->fix_root
= fixes
;
10300 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10302 frag_data
= &fragP
->fr_literal
[0];
10303 for (i
= 0; i
< num_recs
; i
++)
10305 fixS
*fix
= &fixes
[i
];
10306 assert (cur_block
);
10308 /* Write the fixup. */
10309 if (i
!= num_recs
- 1)
10310 fix
->fx_next
= &fixes
[i
+ 1];
10312 fix
->fx_next
= NULL
;
10315 fix
->fx_frag
= fragP
;
10316 fix
->fx_where
= i
* 8;
10317 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10318 fix
->fx_offset
= cur_block
->offset
;
10319 fix
->fx_r_type
= BFD_RELOC_32
;
10320 fix
->fx_file
= "Internal Assembly";
10323 /* Write the length. */
10324 md_number_to_chars (&frag_data
[4 + 8 * i
],
10325 cur_block
->size
, 4);
10326 cur_block
= cur_block
->next
;
10335 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10336 const char *section_name_base
,
10337 xt_section_type sec_type
)
10341 /* Walk over all of the current segments.
10342 Walk over each fragment.
10343 For each fragment that has instructions,
10344 build an instruction record (append where possible). */
10346 for (seclist
= &stdoutput
->sections
;
10347 seclist
&& *seclist
;
10348 seclist
= &(*seclist
)->next
)
10350 segT sec
= *seclist
;
10353 flags
= bfd_get_section_flags (stdoutput
, sec
);
10354 if ((flags
& SEC_DEBUGGING
)
10355 || !(flags
& SEC_ALLOC
)
10356 || (flags
& SEC_MERGE
))
10359 if (section_has_xproperty (sec
, flag_fn
))
10362 xtensa_get_property_section (sec
, section_name_base
);
10363 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10364 xtensa_block_info
**xt_blocks
=
10365 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10366 /* Walk over all of the frchains here and add new sections. */
10367 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10371 /* Now we fill them out.... */
10373 for (seclist
= &stdoutput
->sections
;
10374 seclist
&& *seclist
;
10375 seclist
= &(*seclist
)->next
)
10377 segment_info_type
*seginfo
;
10378 xtensa_block_info
*block
;
10379 segT sec
= *seclist
;
10381 seginfo
= seg_info (sec
);
10382 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10386 xtensa_block_info
*cur_block
;
10387 /* This is a section with some data. */
10389 bfd_size_type rec_size
;
10391 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10394 rec_size
= num_recs
* (8 + 4);
10395 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10397 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10399 /* In order to make this work with the assembler, we have to build
10400 some frags then build the "fixups" for it. It would be easier to
10401 just set the contents then set the arlents. */
10405 /* Allocate a fragment and (unfortunately) leak it. */
10407 bfd_size_type frag_size
;
10409 frchainS
*frchainP
;
10413 frag_size
= sizeof (fragS
) + rec_size
;
10414 fragP
= (fragS
*) xmalloc (frag_size
);
10416 memset (fragP
, 0, frag_size
);
10417 fragP
->fr_address
= 0;
10418 fragP
->fr_next
= NULL
;
10419 fragP
->fr_fix
= rec_size
;
10421 fragP
->fr_type
= rs_fill
;
10422 /* The rest are zeros. */
10424 frchainP
= seginfo
->frchainP
;
10425 frchainP
->frch_root
= fragP
;
10426 frchainP
->frch_last
= fragP
;
10428 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10429 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10431 seginfo
->fix_root
= fixes
;
10432 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10434 frag_data
= &fragP
->fr_literal
[0];
10435 for (i
= 0; i
< num_recs
; i
++)
10437 fixS
*fix
= &fixes
[i
];
10438 assert (cur_block
);
10440 /* Write the fixup. */
10441 if (i
!= num_recs
- 1)
10442 fix
->fx_next
= &fixes
[i
+ 1];
10444 fix
->fx_next
= NULL
;
10447 fix
->fx_frag
= fragP
;
10448 fix
->fx_where
= i
* (8 + 4);
10449 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10450 fix
->fx_offset
= cur_block
->offset
;
10451 fix
->fx_r_type
= BFD_RELOC_32
;
10452 fix
->fx_file
= "Internal Assembly";
10455 /* Write the length. */
10456 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10457 cur_block
->size
, 4);
10458 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10459 frag_flags_to_number (&cur_block
->flags
),
10461 cur_block
= cur_block
->next
;
10469 static segment_info_type
*
10470 retrieve_segment_info (segT seg
)
10472 segment_info_type
*seginfo
;
10473 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10476 frchainS
*frchainP
;
10478 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10479 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10480 seginfo
->fix_root
= NULL
;
10481 seginfo
->fix_tail
= NULL
;
10482 seginfo
->bfd_section
= seg
;
10484 /* We will not be dealing with these, only our special ones. */
10485 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10487 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10488 frchainP
->frch_root
= NULL
;
10489 frchainP
->frch_last
= NULL
;
10490 frchainP
->frch_next
= NULL
;
10491 frchainP
->frch_subseg
= 0;
10492 frchainP
->fix_root
= NULL
;
10493 frchainP
->fix_tail
= NULL
;
10494 /* Do not init the objstack. */
10495 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10496 /* frchainP->frch_frag_now = fragP; */
10497 frchainP
->frch_frag_now
= NULL
;
10499 seginfo
->frchainP
= frchainP
;
10507 section_has_property (segT sec
, frag_predicate property_function
)
10509 segment_info_type
*seginfo
= seg_info (sec
);
10512 if (seginfo
&& seginfo
->frchainP
)
10514 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10516 if (property_function (fragP
)
10517 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10526 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10528 segment_info_type
*seginfo
= seg_info (sec
);
10531 if (seginfo
&& seginfo
->frchainP
)
10533 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10535 frag_flags prop_flags
;
10536 property_function (fragP
, &prop_flags
);
10537 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10545 /* Two types of block sections exist right now: literal and insns. */
10548 add_xt_block_frags (segT sec
,
10550 xtensa_block_info
**xt_block
,
10551 frag_predicate property_function
,
10552 frag_predicate end_property_function
)
10554 segment_info_type
*seg_info
;
10555 segment_info_type
*xt_seg_info
;
10556 bfd_vma seg_offset
;
10559 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10560 seg_info
= retrieve_segment_info (sec
);
10562 /* Build it if needed. */
10563 while (*xt_block
!= NULL
)
10564 xt_block
= &(*xt_block
)->next
;
10565 /* We are either at NULL at the beginning or at the end. */
10567 /* Walk through the frags. */
10570 if (seg_info
->frchainP
)
10572 for (fragP
= seg_info
->frchainP
->frch_root
;
10574 fragP
= fragP
->fr_next
)
10576 if (property_function (fragP
)
10577 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10579 if (*xt_block
!= NULL
)
10581 if ((*xt_block
)->offset
+ (*xt_block
)->size
10582 == fragP
->fr_address
)
10583 (*xt_block
)->size
+= fragP
->fr_fix
;
10585 xt_block
= &((*xt_block
)->next
);
10587 if (*xt_block
== NULL
)
10589 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10590 xmalloc (sizeof (xtensa_block_info
));
10591 new_block
->sec
= sec
;
10592 new_block
->offset
= fragP
->fr_address
;
10593 new_block
->size
= fragP
->fr_fix
;
10594 new_block
->next
= NULL
;
10595 xtensa_frag_flags_init (&new_block
->flags
);
10596 *xt_block
= new_block
;
10598 if (end_property_function
10599 && end_property_function (fragP
))
10601 xt_block
= &((*xt_block
)->next
);
10609 /* Break the encapsulation of add_xt_prop_frags here. */
10612 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10614 if (prop_flags
->is_literal
10615 || prop_flags
->is_insn
10616 || prop_flags
->is_data
10617 || prop_flags
->is_unreachable
)
10624 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10626 memset (prop_flags
, 0, sizeof (frag_flags
));
10631 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10633 xtensa_frag_flags_init (prop_flags
);
10634 if (fragP
->tc_frag_data
.is_literal
)
10635 prop_flags
->is_literal
= TRUE
;
10636 if (fragP
->tc_frag_data
.is_unreachable
)
10637 prop_flags
->is_unreachable
= TRUE
;
10638 else if (fragP
->tc_frag_data
.is_insn
)
10640 prop_flags
->is_insn
= TRUE
;
10641 if (fragP
->tc_frag_data
.is_loop_target
)
10642 prop_flags
->insn
.is_loop_target
= TRUE
;
10643 if (fragP
->tc_frag_data
.is_branch_target
)
10644 prop_flags
->insn
.is_branch_target
= TRUE
;
10645 if (fragP
->tc_frag_data
.is_specific_opcode
10646 || fragP
->tc_frag_data
.is_no_transform
)
10647 prop_flags
->insn
.is_no_transform
= TRUE
;
10648 if (fragP
->tc_frag_data
.is_no_density
)
10649 prop_flags
->insn
.is_no_density
= TRUE
;
10650 if (fragP
->tc_frag_data
.use_absolute_literals
)
10651 prop_flags
->insn
.is_abslit
= TRUE
;
10653 if (fragP
->tc_frag_data
.is_align
)
10655 prop_flags
->is_align
= TRUE
;
10656 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10657 if (xtensa_frag_flags_is_empty (prop_flags
))
10658 prop_flags
->is_data
= TRUE
;
10664 frag_flags_to_number (const frag_flags
*prop_flags
)
10667 if (prop_flags
->is_literal
)
10668 num
|= XTENSA_PROP_LITERAL
;
10669 if (prop_flags
->is_insn
)
10670 num
|= XTENSA_PROP_INSN
;
10671 if (prop_flags
->is_data
)
10672 num
|= XTENSA_PROP_DATA
;
10673 if (prop_flags
->is_unreachable
)
10674 num
|= XTENSA_PROP_UNREACHABLE
;
10675 if (prop_flags
->insn
.is_loop_target
)
10676 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10677 if (prop_flags
->insn
.is_branch_target
)
10679 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10680 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10683 if (prop_flags
->insn
.is_no_density
)
10684 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10685 if (prop_flags
->insn
.is_no_transform
)
10686 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10687 if (prop_flags
->insn
.is_no_reorder
)
10688 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10689 if (prop_flags
->insn
.is_abslit
)
10690 num
|= XTENSA_PROP_INSN_ABSLIT
;
10692 if (prop_flags
->is_align
)
10694 num
|= XTENSA_PROP_ALIGN
;
10695 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10703 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10704 const frag_flags
*prop_flags_2
)
10706 /* Cannot combine with an end marker. */
10708 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10710 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10712 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10715 if (prop_flags_1
->is_insn
)
10717 /* Properties of the beginning of the frag. */
10718 if (prop_flags_2
->insn
.is_loop_target
)
10720 if (prop_flags_2
->insn
.is_branch_target
)
10722 if (prop_flags_1
->insn
.is_no_density
!=
10723 prop_flags_2
->insn
.is_no_density
)
10725 if (prop_flags_1
->insn
.is_no_transform
!=
10726 prop_flags_2
->insn
.is_no_transform
)
10728 if (prop_flags_1
->insn
.is_no_reorder
!=
10729 prop_flags_2
->insn
.is_no_reorder
)
10731 if (prop_flags_1
->insn
.is_abslit
!=
10732 prop_flags_2
->insn
.is_abslit
)
10736 if (prop_flags_1
->is_align
)
10744 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10747 unsigned align_bits
;
10749 if (!xt_block
->flags
.is_align
)
10750 return xt_block
->size
;
10752 end_addr
= xt_block
->offset
+ xt_block
->size
;
10753 align_bits
= xt_block
->flags
.alignment
;
10754 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10755 return end_addr
- xt_block
->offset
;
10760 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10761 const xtensa_block_info
*xt_block_2
)
10763 if (xt_block
->sec
!= xt_block_2
->sec
)
10765 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10766 != xt_block_2
->offset
)
10769 if (xt_block_2
->size
== 0
10770 && (!xt_block_2
->flags
.is_unreachable
10771 || xt_block
->flags
.is_unreachable
))
10773 if (xt_block_2
->flags
.is_align
10774 && xt_block
->flags
.is_align
)
10776 /* Nothing needed. */
10777 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10782 if (xt_block_2
->flags
.is_align
)
10784 /* Push alignment to previous entry. */
10785 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10786 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10791 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10792 &xt_block_2
->flags
))
10795 xt_block
->size
+= xt_block_2
->size
;
10797 if (xt_block_2
->flags
.is_align
)
10799 xt_block
->flags
.is_align
= TRUE
;
10800 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10808 add_xt_prop_frags (segT sec
,
10810 xtensa_block_info
**xt_block
,
10811 frag_flags_fn property_function
)
10813 segment_info_type
*seg_info
;
10814 segment_info_type
*xt_seg_info
;
10815 bfd_vma seg_offset
;
10818 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10819 seg_info
= retrieve_segment_info (sec
);
10820 /* Build it if needed. */
10821 while (*xt_block
!= NULL
)
10823 xt_block
= &(*xt_block
)->next
;
10825 /* We are either at NULL at the beginning or at the end. */
10827 /* Walk through the frags. */
10830 if (seg_info
->frchainP
)
10832 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10833 fragP
= fragP
->fr_next
)
10835 xtensa_block_info tmp_block
;
10836 tmp_block
.sec
= sec
;
10837 tmp_block
.offset
= fragP
->fr_address
;
10838 tmp_block
.size
= fragP
->fr_fix
;
10839 tmp_block
.next
= NULL
;
10840 property_function (fragP
, &tmp_block
.flags
);
10842 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10843 /* && fragP->fr_fix != 0) */
10845 if ((*xt_block
) == NULL
10846 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10848 xtensa_block_info
*new_block
;
10849 if ((*xt_block
) != NULL
)
10850 xt_block
= &(*xt_block
)->next
;
10851 new_block
= (xtensa_block_info
*)
10852 xmalloc (sizeof (xtensa_block_info
));
10853 *new_block
= tmp_block
;
10854 *xt_block
= new_block
;
10862 /* op_placement_info_table */
10864 /* op_placement_info makes it easier to determine which
10865 ops can go in which slots. */
10868 init_op_placement_info_table (void)
10870 xtensa_isa isa
= xtensa_default_isa
;
10871 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10872 xtensa_opcode opcode
;
10875 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10877 op_placement_table
= (op_placement_info_table
)
10878 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10879 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10881 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10883 op_placement_info
*opi
= &op_placement_table
[opcode
];
10884 /* FIXME: Make tinsn allocation dynamic. */
10885 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10886 as_fatal (_("too many operands in instruction"));
10887 opi
->narrowest
= XTENSA_UNDEFINED
;
10888 opi
->narrowest_size
= 0x7F;
10889 opi
->narrowest_slot
= 0;
10891 opi
->num_formats
= 0;
10893 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10895 opi
->slots
[fmt
] = 0;
10896 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10898 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10900 int fmt_length
= xtensa_format_length (isa
, fmt
);
10902 set_bit (fmt
, opi
->formats
);
10903 set_bit (slot
, opi
->slots
[fmt
]);
10904 if (fmt_length
< opi
->narrowest_size
10905 || (fmt_length
== opi
->narrowest_size
10906 && (xtensa_format_num_slots (isa
, fmt
)
10907 < xtensa_format_num_slots (isa
,
10910 opi
->narrowest
= fmt
;
10911 opi
->narrowest_size
= fmt_length
;
10912 opi
->narrowest_slot
= slot
;
10917 opi
->num_formats
++;
10920 xtensa_insnbuf_free (isa
, ibuf
);
10925 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10927 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10931 /* If the opcode is available in a single slot format, return its size. */
10934 xg_get_single_size (xtensa_opcode opcode
)
10936 return op_placement_table
[opcode
].narrowest_size
;
10940 static xtensa_format
10941 xg_get_single_format (xtensa_opcode opcode
)
10943 return op_placement_table
[opcode
].narrowest
;
10948 xg_get_single_slot (xtensa_opcode opcode
)
10950 return op_placement_table
[opcode
].narrowest_slot
;
10954 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10957 istack_init (IStack
*stack
)
10959 memset (stack
, 0, sizeof (IStack
));
10965 istack_empty (IStack
*stack
)
10967 return (stack
->ninsn
== 0);
10972 istack_full (IStack
*stack
)
10974 return (stack
->ninsn
== MAX_ISTACK
);
10978 /* Return a pointer to the top IStack entry.
10979 It is an error to call this if istack_empty () is TRUE. */
10982 istack_top (IStack
*stack
)
10984 int rec
= stack
->ninsn
- 1;
10985 assert (!istack_empty (stack
));
10986 return &stack
->insn
[rec
];
10990 /* Add a new TInsn to an IStack.
10991 It is an error to call this if istack_full () is TRUE. */
10994 istack_push (IStack
*stack
, TInsn
*insn
)
10996 int rec
= stack
->ninsn
;
10997 assert (!istack_full (stack
));
10998 stack
->insn
[rec
] = *insn
;
11003 /* Clear space for the next TInsn on the IStack and return a pointer
11004 to it. It is an error to call this if istack_full () is TRUE. */
11007 istack_push_space (IStack
*stack
)
11009 int rec
= stack
->ninsn
;
11011 assert (!istack_full (stack
));
11012 insn
= &stack
->insn
[rec
];
11019 /* Remove the last pushed instruction. It is an error to call this if
11020 istack_empty () returns TRUE. */
11023 istack_pop (IStack
*stack
)
11025 int rec
= stack
->ninsn
- 1;
11026 assert (!istack_empty (stack
));
11028 tinsn_init (&stack
->insn
[rec
]);
11032 /* TInsn functions. */
11035 tinsn_init (TInsn
*dst
)
11037 memset (dst
, 0, sizeof (TInsn
));
11041 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11044 tinsn_has_symbolic_operands (const TInsn
*insn
)
11047 int n
= insn
->ntok
;
11049 assert (insn
->insn_type
== ITYPE_INSN
);
11051 for (i
= 0; i
< n
; ++i
)
11053 switch (insn
->tok
[i
].X_op
)
11067 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11069 xtensa_isa isa
= xtensa_default_isa
;
11071 int n
= insn
->ntok
;
11073 assert (insn
->insn_type
== ITYPE_INSN
);
11075 for (i
= 0; i
< n
; ++i
)
11077 switch (insn
->tok
[i
].X_op
)
11085 /* Errors for these types are caught later. */
11090 /* Symbolic immediates are only allowed on the last immediate
11091 operand. At this time, CONST16 is the only opcode where we
11092 support non-PC-relative relocations. */
11093 if (i
!= get_relaxable_immed (insn
->opcode
)
11094 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11095 && insn
->opcode
!= xtensa_const16_opcode
))
11097 as_bad (_("invalid symbolic operand"));
11106 /* For assembly code with complex expressions (e.g. subtraction),
11107 we have to build them in the literal pool so that
11108 their results are calculated correctly after relaxation.
11109 The relaxation only handles expressions that
11110 boil down to SYMBOL + OFFSET. */
11113 tinsn_has_complex_operands (const TInsn
*insn
)
11116 int n
= insn
->ntok
;
11117 assert (insn
->insn_type
== ITYPE_INSN
);
11118 for (i
= 0; i
< n
; ++i
)
11120 switch (insn
->tok
[i
].X_op
)
11136 /* Encode a TInsn opcode and its constant operands into slotbuf.
11137 Return TRUE if there is a symbol in the immediate field. This
11138 function assumes that:
11139 1) The number of operands are correct.
11140 2) The insn_type is ITYPE_INSN.
11141 3) The opcode can be encoded in the specified format and slot.
11142 4) Operands are either O_constant or O_symbol, and all constants fit. */
11145 tinsn_to_slotbuf (xtensa_format fmt
,
11148 xtensa_insnbuf slotbuf
)
11150 xtensa_isa isa
= xtensa_default_isa
;
11151 xtensa_opcode opcode
= tinsn
->opcode
;
11152 bfd_boolean has_fixup
= FALSE
;
11153 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11156 assert (tinsn
->insn_type
== ITYPE_INSN
);
11157 if (noperands
!= tinsn
->ntok
)
11158 as_fatal (_("operand number mismatch"));
11160 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11162 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11163 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11167 for (i
= 0; i
< noperands
; i
++)
11169 expressionS
*expr
= &tinsn
->tok
[i
];
11175 switch (expr
->X_op
)
11178 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11180 /* The register number has already been checked in
11181 expression_maybe_register, so we don't need to check here. */
11182 opnd_value
= expr
->X_add_number
;
11183 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11184 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11187 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11191 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11193 as_where (&file_name
, &line
);
11194 /* It is a constant and we called this function
11195 then we have to try to fit it. */
11196 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11197 expr
->X_add_number
, file_name
, line
);
11210 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11211 into a multi-slot instruction, fill the other slots with NOPs.
11212 Return TRUE if there is a symbol in the immediate field. See also the
11213 assumptions listed for tinsn_to_slotbuf. */
11216 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11218 static xtensa_insnbuf slotbuf
= 0;
11219 static vliw_insn vinsn
;
11220 xtensa_isa isa
= xtensa_default_isa
;
11221 bfd_boolean has_fixup
= FALSE
;
11226 slotbuf
= xtensa_insnbuf_alloc (isa
);
11227 xg_init_vinsn (&vinsn
);
11230 xg_clear_vinsn (&vinsn
);
11232 bundle_tinsn (tinsn
, &vinsn
);
11234 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11236 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11238 /* Only one slot may have a fix-up because the rest contains NOPs. */
11240 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11241 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11248 /* Check the instruction arguments. Return TRUE on failure. */
11251 tinsn_check_arguments (const TInsn
*insn
)
11253 xtensa_isa isa
= xtensa_default_isa
;
11254 xtensa_opcode opcode
= insn
->opcode
;
11256 if (opcode
== XTENSA_UNDEFINED
)
11258 as_bad (_("invalid opcode"));
11262 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11264 as_bad (_("too few operands"));
11268 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11270 as_bad (_("too many operands"));
11277 /* Load an instruction from its encoded form. */
11280 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11284 xg_init_vinsn (&vinsn
);
11285 vinsn_from_chars (&vinsn
, f
);
11287 *tinsn
= vinsn
.slots
[slot
];
11288 xg_free_vinsn (&vinsn
);
11293 tinsn_from_insnbuf (TInsn
*tinsn
,
11294 xtensa_insnbuf slotbuf
,
11299 xtensa_isa isa
= xtensa_default_isa
;
11301 /* Find the immed. */
11302 tinsn_init (tinsn
);
11303 tinsn
->insn_type
= ITYPE_INSN
;
11304 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11305 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11306 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11307 for (i
= 0; i
< tinsn
->ntok
; i
++)
11309 set_expr_const (&tinsn
->tok
[i
],
11310 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11311 tinsn
->opcode
, i
));
11316 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11319 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11321 xtensa_opcode opcode
= tinsn
->opcode
;
11324 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11326 opnum
= get_relaxable_immed (opcode
);
11327 assert (opnum
>= 0);
11328 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11329 fragP
->tc_frag_data
.slot_symbols
[slot
],
11330 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11336 get_num_stack_text_bytes (IStack
*istack
)
11339 int text_bytes
= 0;
11341 for (i
= 0; i
< istack
->ninsn
; i
++)
11343 TInsn
*tinsn
= &istack
->insn
[i
];
11344 if (tinsn
->insn_type
== ITYPE_INSN
)
11345 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11352 get_num_stack_literal_bytes (IStack
*istack
)
11357 for (i
= 0; i
< istack
->ninsn
; i
++)
11359 TInsn
*tinsn
= &istack
->insn
[i
];
11360 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11367 /* vliw_insn functions. */
11370 xg_init_vinsn (vliw_insn
*v
)
11373 xtensa_isa isa
= xtensa_default_isa
;
11375 xg_clear_vinsn (v
);
11377 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11378 if (v
->insnbuf
== NULL
)
11379 as_fatal (_("out of memory"));
11381 for (i
= 0; i
< MAX_SLOTS
; i
++)
11383 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11384 if (v
->slotbuf
[i
] == NULL
)
11385 as_fatal (_("out of memory"));
11391 xg_clear_vinsn (vliw_insn
*v
)
11395 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11397 v
->format
= XTENSA_UNDEFINED
;
11399 v
->inside_bundle
= FALSE
;
11401 if (xt_saved_debug_type
!= DEBUG_NONE
)
11402 debug_type
= xt_saved_debug_type
;
11404 for (i
= 0; i
< MAX_SLOTS
; i
++)
11405 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11410 vinsn_has_specific_opcodes (vliw_insn
*v
)
11414 for (i
= 0; i
< v
->num_slots
; i
++)
11416 if (v
->slots
[i
].is_specific_opcode
)
11424 xg_free_vinsn (vliw_insn
*v
)
11427 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11428 for (i
= 0; i
< MAX_SLOTS
; i
++)
11429 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11433 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11434 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11437 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11440 bfd_boolean record_fixup
)
11442 xtensa_isa isa
= xtensa_default_isa
;
11443 xtensa_format fmt
= vinsn
->format
;
11444 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11446 bfd_boolean has_fixup
= FALSE
;
11448 xtensa_format_encode (isa
, fmt
, insnbuf
);
11450 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11452 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11453 bfd_boolean tinsn_has_fixup
=
11454 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11455 vinsn
->slotbuf
[slot
]);
11457 xtensa_format_set_slot (isa
, fmt
, slot
,
11458 insnbuf
, vinsn
->slotbuf
[slot
]);
11459 if (tinsn_has_fixup
)
11462 xtensa_opcode opcode
= tinsn
->opcode
;
11463 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11466 for (i
= 0; i
< noperands
; i
++)
11468 expressionS
* expr
= &tinsn
->tok
[i
];
11469 switch (expr
->X_op
)
11474 if (get_relaxable_immed (opcode
) == i
)
11476 /* Add a fix record for the instruction, except if this
11477 function is being called prior to relaxation, i.e.,
11478 if record_fixup is false, and the instruction might
11479 be relaxed later. */
11481 || tinsn
->is_specific_opcode
11482 || !xg_is_relaxable_insn (tinsn
, 0))
11484 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11485 frag_offset
- fragP
->fr_literal
);
11489 if (expr
->X_op
!= O_symbol
)
11490 as_bad (_("invalid operand"));
11491 tinsn
->symbol
= expr
->X_add_symbol
;
11492 tinsn
->offset
= expr
->X_add_number
;
11496 as_bad (_("symbolic operand not allowed"));
11504 as_bad (_("expression too complex"));
11516 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11518 static xtensa_insnbuf insnbuf
= NULL
;
11519 static xtensa_insnbuf slotbuf
= NULL
;
11522 xtensa_isa isa
= xtensa_default_isa
;
11526 insnbuf
= xtensa_insnbuf_alloc (isa
);
11527 slotbuf
= xtensa_insnbuf_alloc (isa
);
11530 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11531 fmt
= xtensa_format_decode (isa
, insnbuf
);
11532 if (fmt
== XTENSA_UNDEFINED
)
11533 as_fatal (_("cannot decode instruction format"));
11534 vinsn
->format
= fmt
;
11535 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11537 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11539 TInsn
*tinsn
= &vinsn
->slots
[i
];
11540 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11541 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11546 /* Expression utilities. */
11548 /* Return TRUE if the expression is an integer constant. */
11551 expr_is_const (const expressionS
*s
)
11553 return (s
->X_op
== O_constant
);
11557 /* Get the expression constant.
11558 Calling this is illegal if expr_is_const () returns TRUE. */
11561 get_expr_const (const expressionS
*s
)
11563 assert (expr_is_const (s
));
11564 return s
->X_add_number
;
11568 /* Set the expression to a constant value. */
11571 set_expr_const (expressionS
*s
, offsetT val
)
11573 s
->X_op
= O_constant
;
11574 s
->X_add_number
= val
;
11575 s
->X_add_symbol
= NULL
;
11576 s
->X_op_symbol
= NULL
;
11581 expr_is_register (const expressionS
*s
)
11583 return (s
->X_op
== O_register
);
11587 /* Get the expression constant.
11588 Calling this is illegal if expr_is_const () returns TRUE. */
11591 get_expr_register (const expressionS
*s
)
11593 assert (expr_is_register (s
));
11594 return s
->X_add_number
;
11598 /* Set the expression to a symbol + constant offset. */
11601 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11603 s
->X_op
= O_symbol
;
11604 s
->X_add_symbol
= sym
;
11605 s
->X_op_symbol
= NULL
; /* unused */
11606 s
->X_add_number
= offset
;
11610 /* Return TRUE if the two expressions are equal. */
11613 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11615 if (s1
->X_op
!= s2
->X_op
)
11617 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11619 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11621 if (s1
->X_add_number
!= s2
->X_add_number
)
11628 copy_expr (expressionS
*dst
, const expressionS
*src
)
11630 memcpy (dst
, src
, sizeof (expressionS
));
11634 /* Support for the "--rename-section" option. */
11636 struct rename_section_struct
11640 struct rename_section_struct
*next
;
11643 static struct rename_section_struct
*section_rename
;
11646 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11647 entries to the section_rename list. Note: Specifying multiple
11648 renamings separated by colons is not documented and is retained only
11649 for backward compatibility. */
11652 build_section_rename (const char *arg
)
11654 struct rename_section_struct
*r
;
11655 char *this_arg
= NULL
;
11656 char *next_arg
= NULL
;
11658 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11660 char *old_name
, *new_name
;
11664 next_arg
= strchr (this_arg
, ':');
11672 old_name
= this_arg
;
11673 new_name
= strchr (this_arg
, '=');
11675 if (*old_name
== '\0')
11677 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11680 if (!new_name
|| new_name
[1] == '\0')
11682 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11689 /* Check for invalid section renaming. */
11690 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11692 if (strcmp (r
->old_name
, old_name
) == 0)
11693 as_bad (_("section %s renamed multiple times"), old_name
);
11694 if (strcmp (r
->new_name
, new_name
) == 0)
11695 as_bad (_("multiple sections remapped to output section %s"),
11700 r
= (struct rename_section_struct
*)
11701 xmalloc (sizeof (struct rename_section_struct
));
11702 r
->old_name
= xstrdup (old_name
);
11703 r
->new_name
= xstrdup (new_name
);
11704 r
->next
= section_rename
;
11705 section_rename
= r
;
11711 xtensa_section_rename (char *name
)
11713 struct rename_section_struct
*r
= section_rename
;
11715 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11717 if (strcmp (r
->old_name
, name
) == 0)
11718 return r
->new_name
;