gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{cortex-a73},
  63 @code{exynos-m1},
  64 @code{falkor},
  65 @code{qdf24xx},
  66 @code{thunderx},
  67 @code{vulcan},
  68 @code{xgene1}
  69 and
  70 @code{xgene2}.
  71 The special name @code{all} may be used to allow the assembler to accept
  72 instructions valid for any supported processor, including all optional
  73 extensions.
  74
  75 In addition to the basic instruction set, the assembler can be told to
  76 accept, or restrict, various extension mnemonics that extend the
  77 processor.  @xref{AArch64 Extensions}.
  78
  79 If some implementations of a particular processor can have an
  80 extension, then then those extensions are automatically enabled.
  81 Consequently, you will not normally have to specify any additional
  82 extensions.
  83
  84 @cindex @option{-march=} command line option, AArch64
  85 @item -march=@var{architecture}[+@var{extension}@dots{}]
  86 This option specifies the target architecture.  The assembler will
  87 issue an error message if an attempt is made to assemble an
  88 instruction which will not execute on the target architecture.  The
  89 following architecture names are recognized: @code{armv8-a},
  90 @code{armv8.1-a}, @code{armv8.2-a} and @code{armv8.3-a}.
  91
  92 If both @option{-mcpu} and @option{-march} are specified, the
  93 assembler will use the setting for @option{-mcpu}.  If neither are
  94 specified, the assembler will default to @option{-mcpu=all}.
  95
  96 The architecture option can be extended with the same instruction set
  97 extension options as the @option{-mcpu} option.  Unlike
  98 @option{-mcpu}, extensions are not always enabled by default,
  99 @xref{AArch64 Extensions}.
 100
 101 @cindex @code{-mverbose-error} command line option, AArch64
 102 @item -mverbose-error
 103 This option enables verbose error messages for AArch64 gas.  This option
 104 is enabled by default.
 105
 106 @cindex @code{-mno-verbose-error} command line option, AArch64
 107 @item -mno-verbose-error
 108 This option disables verbose error messages in AArch64 gas.
 109
 110 @end table
 111 @c man end
 112
 113 @node AArch64 Extensions
 114 @section Architecture Extensions
 115
 116 The table below lists the permitted architecture extensions that are
 117 supported by the assembler and the conditions under which they are
 118 automatically enabled.
 119
 120 Multiple extensions may be specified, separated by a @code{+}.
 121 Extension mnemonics may also be removed from those the assembler
 122 accepts.  This is done by prepending @code{no} to the option that adds
 123 the extension.  Extensions that are removed must be listed after all
 124 extensions that have been added.
 125
 126 Enabling an extension that requires other extensions will
 127 automatically cause those extensions to be enabled.  Similarly,
 128 disabling an extension that is required by other extensions will
 129 automatically cause those extensions to be disabled.
 130
 131 @multitable @columnfractions .12 .17 .17 .54
 132 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 133  @tab Description
 134 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 135  @tab Enable the complex number SIMD extensions.  This implies
 136  @code{fp16} and @code{simd}.
 137 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 138  @tab Enable CRC instructions.
 139 @item @code{crypto} @tab ARMv8-A @tab No
 140  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 141 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 142  @tab Enable floating-point extensions.
 143 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 144  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 145  @code{fp}.
 146 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 147  @tab Enable Limited Ordering Regions extensions.
 148 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 149  @tab Enable Large System extensions.
 150 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 151  @tab Enable Privileged Access Never support.
 152 @item @code{profile} @tab ARMv8.2-A @tab No
 153  @tab Enable statistical profiling extensions.
 154 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 155  @tab Enable the Reliability, Availability and Serviceability
 156  extension.
 157 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 158  @tab Enable the weak release consistency extension.
 159 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 160  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 161 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 162  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 163 @item @code{sve} @tab ARMv8.2-A @tab No
 164  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 165  @code{simd} and @code{compnum}.
 166 @end multitable
 167
 168 @node AArch64 Syntax
 169 @section Syntax
 170 @menu
 171 * AArch64-Chars::                Special Characters
 172 * AArch64-Regs::                 Register Names
 173 * AArch64-Relocations::      Relocations
 174 @end menu
 175
 176 @node AArch64-Chars
 177 @subsection Special Characters
 178
 179 @cindex line comment character, AArch64
 180 @cindex AArch64 line comment character
 181 The presence of a @samp{//} on a line indicates the start of a comment
 182 that extends to the end of the current line.  If a @samp{#} appears as
 183 the first character of a line, the whole line is treated as a comment.
 184
 185 @cindex line separator, AArch64
 186 @cindex statement separator, AArch64
 187 @cindex AArch64 line separator
 188 The @samp{;} character can be used instead of a newline to separate
 189 statements.
 190
 191 @cindex immediate character, AArch64
 192 @cindex AArch64 immediate character
 193 The @samp{#} can be optionally used to indicate immediate operands.
 194
 195 @node AArch64-Regs
 196 @subsection Register Names
 197
 198 @cindex AArch64 register names
 199 @cindex register names, AArch64
 200 Please refer to the section @samp{4.4 Register Names} of
 201 @samp{ARMv8 Instruction Set Overview}, which is available at
 202 @uref{http://infocenter.arm.com}.
 203
 204 @node AArch64-Relocations
 205 @subsection Relocations
 206
 207 @cindex relocations, AArch64
 208 @cindex AArch64 relocations
 209 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 210 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 211 by prefixing the label with @samp{#:abs_g2:} etc.
 212 For example to load the 48-bit absolute address of @var{foo} into x0:
 213
 214 @smallexample
 215         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 216         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 217         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 218 @end smallexample
 219
 220 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 221 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 222 instructions can be generated by prefixing the label with
 223 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 224
 225 For example to use 33-bit (+/-4GB) pc-relative addressing to
 226 load the address of @var{foo} into x0:
 227
 228 @smallexample
 229         adrp x0, :pg_hi21:foo
 230         add  x0, x0, #:lo12:foo
 231 @end smallexample
 232
 233 Or to load the value of @var{foo} into x0:
 234
 235 @smallexample
 236         adrp x0, :pg_hi21:foo
 237         ldr  x0, [x0, #:lo12:foo]
 238 @end smallexample
 239
 240 Note that @samp{:pg_hi21:} is optional.
 241
 242 @smallexample
 243         adrp x0, foo
 244 @end smallexample
 245
 246 is equivalent to
 247
 248 @smallexample
 249         adrp x0, :pg_hi21:foo
 250 @end smallexample
 251
 252 @node AArch64 Floating Point
 253 @section Floating Point
 254
 255 @cindex floating point, AArch64 (@sc{ieee})
 256 @cindex AArch64 floating point (@sc{ieee})
 257 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 258
 259 @node AArch64 Directives
 260 @section AArch64 Machine Directives
 261
 262 @cindex machine directives, AArch64
 263 @cindex AArch64 machine directives
 264 @table @code
 265
 266 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 267
 268 @cindex @code{.arch} directive, AArch64
 269 @item .arch @var{name}
 270 Select the target architecture.  Valid values for @var{name} are the same as
 271 for the @option{-march} commandline option.
 272
 273 Specifying @code{.arch} clears any previously selected architecture
 274 extensions.
 275
 276 @cindex @code{.arch_extension} directive, AArch64
 277 @item .arch_extension @var{name}
 278 Add or remove an architecture extension to the target architecture.  Valid
 279 values for @var{name} are the same as those accepted as architectural
 280 extensions by the @option{-mcpu} commandline option.
 281
 282 @code{.arch_extension} may be used multiple times to add or remove extensions
 283 incrementally to the architecture being compiled for.
 284
 285 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 286
 287 @cindex @code{.bss} directive, AArch64
 288 @item .bss
 289 This directive switches to the @code{.bss} section.
 290
 291 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 292
 293 @cindex @code{.cpu} directive, AArch64
 294 @item .cpu @var{name}
 295 Set the target processor.  Valid values for @var{name} are the same as
 296 those accepted by the @option{-mcpu=} command line option.
 297
 298 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 299
 300 @cindex @code{.dword} directive, AArch64
 301 @item .dword @var{expressions}
 302 The @code{.dword} directive produces 64 bit values.
 303
 304 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 305
 306 @cindex @code{.even} directive, AArch64
 307 @item .even
 308 The @code{.even} directive aligns the output on the next even byte
 309 boundary.
 310
 311 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 312 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 313 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 314 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 315
 316 @cindex @code{.inst} directive, AArch64
 317 @item .inst @var{expressions}
 318 Inserts the expressions into the output as if they were instructions,
 319 rather than data.
 320
 321 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 322 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 323 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 324
 325 @cindex @code{.ltorg} directive, AArch64
 326 @item .ltorg
 327 This directive causes the current contents of the literal pool to be
 328 dumped into the current section (which is assumed to be the .text
 329 section) at the current location (aligned to a word boundary).
 330 GAS maintains a separate literal pool for each section and each
 331 sub-section.  The @code{.ltorg} directive will only affect the literal
 332 pool of the current section and sub-section.  At the end of assembly
 333 all remaining, un-empty literal pools will automatically be dumped.
 334
 335 Note - older versions of GAS would dump the current literal
 336 pool any time a section change occurred.  This is no longer done, since
 337 it prevents accurate control of the placement of literal pools.
 338
 339 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 340
 341 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 342 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 343
 344 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 345
 346 @cindex @code{.pool} directive, AArch64
 347 @item .pool
 348 This is a synonym for .ltorg.
 349
 350 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 351 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 352
 353 @cindex @code{.req} directive, AArch64
 354 @item @var{name} .req @var{register name}
 355 This creates an alias for @var{register name} called @var{name}.  For
 356 example:
 357
 358 @smallexample
 359         foo .req w0
 360 @end smallexample
 361
 362 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 363
 364 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 365
 366 @cindex @code{.tlsdescadd} directive, AArch64
 367 @item   @code{.tlsdescadd}
 368 Emits a TLSDESC_ADD reloc on the next instruction.
 369
 370 @cindex @code{.tlsdesccall} directive, AArch64
 371 @item   @code{.tlsdesccall}
 372 Emits a TLSDESC_CALL reloc on the next instruction.
 373
 374 @cindex @code{.tlsdescldr} directive, AArch64
 375 @item   @code{.tlsdescldr}
 376 Emits a TLSDESC_LDR reloc on the next instruction.
 377
 378 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 379
 380 @cindex @code{.unreq} directive, AArch64
 381 @item .unreq @var{alias-name}
 382 This undefines a register alias which was previously defined using the
 383 @code{req} directive.  For example:
 384
 385 @smallexample
 386         foo .req w0
 387         .unreq foo
 388 @end smallexample
 389
 390 An error occurs if the name is undefined.  Note - this pseudo op can
 391 be used to delete builtin in register name aliases (eg 'w0').  This
 392 should only be done if it is really necessary.
 393
 394 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 395
 396 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 397 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 398
 399 @cindex @code{.xword} directive, AArch64
 400 @item .xword @var{expressions}
 401 The @code{.xword} directive produces 64 bit values.  This is the same
 402 as the @code{.dword} directive.
 403
 404 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 405 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 406
 407 @end table
 408
 409 @node AArch64 Opcodes
 410 @section Opcodes
 411
 412 @cindex AArch64 opcodes
 413 @cindex opcodes for AArch64
 414 GAS implements all the standard AArch64 opcodes.  It also
 415 implements several pseudo opcodes, including several synthetic load
 416 instructions.
 417
 418 @table @code
 419
 420 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 421 @item LDR =
 422 @smallexample
 423   ldr <register> , =<expression>
 424 @end smallexample
 425
 426 The constant expression will be placed into the nearest literal pool (if it not
 427 already there) and a PC-relative LDR instruction will be generated.
 428
 429 @end table
 430
 431 For more information on the AArch64 instruction set and assembly language
 432 notation, see @samp{ARMv8 Instruction Set Overview} available at
 433 @uref{http://infocenter.arm.com}.
 434
 435
 436 @node AArch64 Mapping Symbols
 437 @section Mapping Symbols
 438
 439 The AArch64 ELF specification requires that special symbols be inserted
 440 into object files to mark certain features:
 441
 442 @table @code
 443
 444 @cindex @code{$x}
 445 @item $x
 446 At the start of a region of code containing AArch64 instructions.
 447
 448 @cindex @code{$d}
 449 @item $d
 450 At the start of a region of data.
 451
 452 @end table