gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2019 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{ares},
  72 @code{exynos-m1},
  73 @code{falkor},
  74 @code{neoverse-n1},
  75 @code{neoverse-e1},
  76 @code{qdf24xx},
  77 @code{saphira},
  78 @code{thunderx},
  79 @code{vulcan},
  80 @code{xgene1}
  81 and
  82 @code{xgene2}.
  83 The special name @code{all} may be used to allow the assembler to accept
  84 instructions valid for any supported processor, including all optional
  85 extensions.
  86
  87 In addition to the basic instruction set, the assembler can be told to
  88 accept, or restrict, various extension mnemonics that extend the
  89 processor.  @xref{AArch64 Extensions}.
  90
  91 If some implementations of a particular processor can have an
  92 extension, then then those extensions are automatically enabled.
  93 Consequently, you will not normally have to specify any additional
  94 extensions.
  95
  96 @cindex @option{-march=} command-line option, AArch64
  97 @item -march=@var{architecture}[+@var{extension}@dots{}]
  98 This option specifies the target architecture.  The assembler will
  99 issue an error message if an attempt is made to assemble an
 100 instruction which will not execute on the target architecture.  The
 101 following architecture names are recognized: @code{armv8-a},
 102 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 103 @code{armv8.5-a}, and @code{armv8.6-a}.
 104
 105 If both @option{-mcpu} and @option{-march} are specified, the
 106 assembler will use the setting for @option{-mcpu}.  If neither are
 107 specified, the assembler will default to @option{-mcpu=all}.
 108
 109 The architecture option can be extended with the same instruction set
 110 extension options as the @option{-mcpu} option.  Unlike
 111 @option{-mcpu}, extensions are not always enabled by default,
 112 @xref{AArch64 Extensions}.
 113
 114 @cindex @code{-mverbose-error} command-line option, AArch64
 115 @item -mverbose-error
 116 This option enables verbose error messages for AArch64 gas.  This option
 117 is enabled by default.
 118
 119 @cindex @code{-mno-verbose-error} command-line option, AArch64
 120 @item -mno-verbose-error
 121 This option disables verbose error messages in AArch64 gas.
 122
 123 @end table
 124 @c man end
 125
 126 @node AArch64 Extensions
 127 @section Architecture Extensions
 128
 129 The table below lists the permitted architecture extensions that are
 130 supported by the assembler and the conditions under which they are
 131 automatically enabled.
 132
 133 Multiple extensions may be specified, separated by a @code{+}.
 134 Extension mnemonics may also be removed from those the assembler
 135 accepts.  This is done by prepending @code{no} to the option that adds
 136 the extension.  Extensions that are removed must be listed after all
 137 extensions that have been added.
 138
 139 Enabling an extension that requires other extensions will
 140 automatically cause those extensions to be enabled.  Similarly,
 141 disabling an extension that is required by other extensions will
 142 automatically cause those extensions to be disabled.
 143
 144 @multitable @columnfractions .12 .17 .17 .54
 145 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 146  @tab Description
 147 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 148  @tab Enable BFloat16 extension.
 149 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 150  @tab Enable the complex number SIMD extensions.  This implies
 151  @code{fp16} and @code{simd}.
 152 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 153  @tab Enable CRC instructions.
 154 @item @code{crypto} @tab ARMv8-A @tab No
 155  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 156 @item @code{aes} @tab ARMv8-A @tab No
 157  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 158 @item @code{sha2} @tab ARMv8-A @tab No
 159  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 160 @item @code{sha3} @tab ARMv8.2-A @tab No
 161  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 162 @item @code{sm4} @tab ARMv8.2-A @tab No
 163  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 164 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 165  @tab Enable floating-point extensions.
 166 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 167  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 168  @code{fp}.
 169 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 170  @tab Enable Limited Ordering Regions extensions.
 171 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 172  @tab Enable Large System extensions.
 173 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 174  @tab Enable Privileged Access Never support.
 175 @item @code{profile} @tab ARMv8.2-A @tab No
 176  @tab Enable statistical profiling extensions.
 177 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 178  @tab Enable the Reliability, Availability and Serviceability
 179  extension.
 180 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 181  @tab Enable the weak release consistency extension.
 182 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 183  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 184 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 185  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 186 @item @code{sve} @tab ARMv8.2-A @tab No
 187  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 188  @code{simd} and @code{compnum}.
 189 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 190  @tab Enable the Dot Product extension.  This implies @code{simd}.
 191 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 192  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 193  This implies @code{fp16}.
 194 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 195  @tab Enable the speculation barrier instruction sb.
 196 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 197  @tab Enable the Execution and Data and Prediction instructions.
 198 @item @code{rng} @tab ARMv8.5-A @tab No
 199  @tab Enable ARMv8.5-A random number instructions.
 200 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 201  @tab Enable Speculative Store Bypassing Safe state read and write.
 202 @item @code{memtag} @tab ARMv8.5-A @tab No
 203  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 204 @item @code{tme} @tab ARMv8-A @tab No
 205  @tab Enable Transactional Memory Extensions.
 206 @item @code{sve2} @tab ARMv8-A @tab No
 207  @tab Enable the SVE2 Extension.
 208 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 209  @tab Enable SVE2 BITPERM Extension.
 210 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 211  @tab Enable SVE2 SM4 Extension.
 212 @item @code{sve2-aes} @tab ARMv8-A @tab No
 213  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 214  @code{pmullt} and @code{pmullb} instructions.
 215 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 216  @tab Enable SVE2 SHA3 Extension.
 217 @end multitable
 218
 219 @node AArch64 Syntax
 220 @section Syntax
 221 @menu
 222 * AArch64-Chars::                Special Characters
 223 * AArch64-Regs::                 Register Names
 224 * AArch64-Relocations::      Relocations
 225 @end menu
 226
 227 @node AArch64-Chars
 228 @subsection Special Characters
 229
 230 @cindex line comment character, AArch64
 231 @cindex AArch64 line comment character
 232 The presence of a @samp{//} on a line indicates the start of a comment
 233 that extends to the end of the current line.  If a @samp{#} appears as
 234 the first character of a line, the whole line is treated as a comment.
 235
 236 @cindex line separator, AArch64
 237 @cindex statement separator, AArch64
 238 @cindex AArch64 line separator
 239 The @samp{;} character can be used instead of a newline to separate
 240 statements.
 241
 242 @cindex immediate character, AArch64
 243 @cindex AArch64 immediate character
 244 The @samp{#} can be optionally used to indicate immediate operands.
 245
 246 @node AArch64-Regs
 247 @subsection Register Names
 248
 249 @cindex AArch64 register names
 250 @cindex register names, AArch64
 251 Please refer to the section @samp{4.4 Register Names} of
 252 @samp{ARMv8 Instruction Set Overview}, which is available at
 253 @uref{http://infocenter.arm.com}.
 254
 255 @node AArch64-Relocations
 256 @subsection Relocations
 257
 258 @cindex relocations, AArch64
 259 @cindex AArch64 relocations
 260 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 261 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 262 by prefixing the label with @samp{#:abs_g2:} etc.
 263 For example to load the 48-bit absolute address of @var{foo} into x0:
 264
 265 @smallexample
 266         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 267         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 268         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 269 @end smallexample
 270
 271 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 272 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 273 instructions can be generated by prefixing the label with
 274 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 275
 276 For example to use 33-bit (+/-4GB) pc-relative addressing to
 277 load the address of @var{foo} into x0:
 278
 279 @smallexample
 280         adrp x0, :pg_hi21:foo
 281         add  x0, x0, #:lo12:foo
 282 @end smallexample
 283
 284 Or to load the value of @var{foo} into x0:
 285
 286 @smallexample
 287         adrp x0, :pg_hi21:foo
 288         ldr  x0, [x0, #:lo12:foo]
 289 @end smallexample
 290
 291 Note that @samp{:pg_hi21:} is optional.
 292
 293 @smallexample
 294         adrp x0, foo
 295 @end smallexample
 296
 297 is equivalent to
 298
 299 @smallexample
 300         adrp x0, :pg_hi21:foo
 301 @end smallexample
 302
 303 @node AArch64 Floating Point
 304 @section Floating Point
 305
 306 @cindex floating point, AArch64 (@sc{ieee})
 307 @cindex AArch64 floating point (@sc{ieee})
 308 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 309
 310 @node AArch64 Directives
 311 @section AArch64 Machine Directives
 312
 313 @cindex machine directives, AArch64
 314 @cindex AArch64 machine directives
 315 @table @code
 316
 317 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 318
 319 @cindex @code{.arch} directive, AArch64
 320 @item .arch @var{name}
 321 Select the target architecture.  Valid values for @var{name} are the same as
 322 for the @option{-march} command-line option.
 323
 324 Specifying @code{.arch} clears any previously selected architecture
 325 extensions.
 326
 327 @cindex @code{.arch_extension} directive, AArch64
 328 @item .arch_extension @var{name}
 329 Add or remove an architecture extension to the target architecture.  Valid
 330 values for @var{name} are the same as those accepted as architectural
 331 extensions by the @option{-mcpu} command-line option.
 332
 333 @code{.arch_extension} may be used multiple times to add or remove extensions
 334 incrementally to the architecture being compiled for.
 335
 336 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 337
 338 @cindex @code{.bss} directive, AArch64
 339 @item .bss
 340 This directive switches to the @code{.bss} section.
 341
 342 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 343
 344 @cindex @code{.cpu} directive, AArch64
 345 @item .cpu @var{name}
 346 Set the target processor.  Valid values for @var{name} are the same as
 347 those accepted by the @option{-mcpu=} command-line option.
 348
 349 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 350
 351 @cindex @code{.dword} directive, AArch64
 352 @item .dword @var{expressions}
 353 The @code{.dword} directive produces 64 bit values.
 354
 355 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 356
 357 @cindex @code{.even} directive, AArch64
 358 @item .even
 359 The @code{.even} directive aligns the output on the next even byte
 360 boundary.
 361
 362 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 363
 364 @cindex @code{.float16} directive, AArch64
 365 @item .float16 @var{value [,...,value_n]}
 366 Place the half precision floating point representation of one or more
 367 floating-point values into the current section.
 368 The format used to encode the floating point values is always the
 369 IEEE 754-2008 half precision floating point format.
 370
 371 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 372 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 373 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 374
 375 @cindex @code{.inst} directive, AArch64
 376 @item .inst @var{expressions}
 377 Inserts the expressions into the output as if they were instructions,
 378 rather than data.
 379
 380 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 381 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 382 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 383
 384 @cindex @code{.ltorg} directive, AArch64
 385 @item .ltorg
 386 This directive causes the current contents of the literal pool to be
 387 dumped into the current section (which is assumed to be the .text
 388 section) at the current location (aligned to a word boundary).
 389 GAS maintains a separate literal pool for each section and each
 390 sub-section.  The @code{.ltorg} directive will only affect the literal
 391 pool of the current section and sub-section.  At the end of assembly
 392 all remaining, un-empty literal pools will automatically be dumped.
 393
 394 Note - older versions of GAS would dump the current literal
 395 pool any time a section change occurred.  This is no longer done, since
 396 it prevents accurate control of the placement of literal pools.
 397
 398 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 399
 400 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 401 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 402
 403 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 404
 405 @cindex @code{.pool} directive, AArch64
 406 @item .pool
 407 This is a synonym for .ltorg.
 408
 409 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 410 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 411
 412 @cindex @code{.req} directive, AArch64
 413 @item @var{name} .req @var{register name}
 414 This creates an alias for @var{register name} called @var{name}.  For
 415 example:
 416
 417 @smallexample
 418         foo .req w0
 419 @end smallexample
 420
 421 ip0, ip1, lr and fp are automatically defined to
 422 alias to X16, X17, X30 and X29 respectively.
 423
 424 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 425
 426 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 427
 428 @cindex @code{.tlsdescadd} directive, AArch64
 429 @item   @code{.tlsdescadd}
 430 Emits a TLSDESC_ADD reloc on the next instruction.
 431
 432 @cindex @code{.tlsdesccall} directive, AArch64
 433 @item   @code{.tlsdesccall}
 434 Emits a TLSDESC_CALL reloc on the next instruction.
 435
 436 @cindex @code{.tlsdescldr} directive, AArch64
 437 @item   @code{.tlsdescldr}
 438 Emits a TLSDESC_LDR reloc on the next instruction.
 439
 440 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 441
 442 @cindex @code{.unreq} directive, AArch64
 443 @item .unreq @var{alias-name}
 444 This undefines a register alias which was previously defined using the
 445 @code{req} directive.  For example:
 446
 447 @smallexample
 448         foo .req w0
 449         .unreq foo
 450 @end smallexample
 451
 452 An error occurs if the name is undefined.  Note - this pseudo op can
 453 be used to delete builtin in register name aliases (eg 'w0').  This
 454 should only be done if it is really necessary.
 455
 456 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 457
 458 @cindex @code{.variant_pcs} directive, AArch64
 459 @item .variant_pcs @var{symbol}
 460 This directive marks @var{symbol} referencing a function that may
 461 follow a variant procedure call standard with different register
 462 usage convention from the base procedure call standard.
 463
 464 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 465 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 466
 467 @cindex @code{.xword} directive, AArch64
 468 @item .xword @var{expressions}
 469 The @code{.xword} directive produces 64 bit values.  This is the same
 470 as the @code{.dword} directive.
 471
 472 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 473 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 474
 475 @cindex @code{.cfi_b_key_frame} directive, AArch64
 476 @item   @code{.cfi_b_key_frame}
 477 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 478 corresponding to the current frame's FDE, meaning that its return address has
 479 been signed with the B-key.  If two frames are signed with differing keys then
 480 they will not share the same CIE.  This information is intended to be used by
 481 the stack unwinder in order to properly authenticate return addresses.
 482
 483 @end table
 484
 485 @node AArch64 Opcodes
 486 @section Opcodes
 487
 488 @cindex AArch64 opcodes
 489 @cindex opcodes for AArch64
 490 GAS implements all the standard AArch64 opcodes.  It also
 491 implements several pseudo opcodes, including several synthetic load
 492 instructions.
 493
 494 @table @code
 495
 496 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 497 @item LDR =
 498 @smallexample
 499   ldr <register> , =<expression>
 500 @end smallexample
 501
 502 The constant expression will be placed into the nearest literal pool (if it not
 503 already there) and a PC-relative LDR instruction will be generated.
 504
 505 @end table
 506
 507 For more information on the AArch64 instruction set and assembly language
 508 notation, see @samp{ARMv8 Instruction Set Overview} available at
 509 @uref{http://infocenter.arm.com}.
 510
 511
 512 @node AArch64 Mapping Symbols
 513 @section Mapping Symbols
 514
 515 The AArch64 ELF specification requires that special symbols be inserted
 516 into object files to mark certain features:
 517
 518 @table @code
 519
 520 @cindex @code{$x}
 521 @item $x
 522 At the start of a region of code containing AArch64 instructions.
 523
 524 @cindex @code{$d}
 525 @item $d
 526 At the start of a region of data.
 527
 528 @end table