1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command-line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command-line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command-line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command-line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
90 The special name @code{all} may be used to allow the assembler to accept
91 instructions valid for any supported processor, including all optional
94 In addition to the basic instruction set, the assembler can be told to
95 accept, or restrict, various extension mnemonics that extend the
96 processor. @xref{AArch64 Extensions}.
98 If some implementations of a particular processor can have an
99 extension, then then those extensions are automatically enabled.
100 Consequently, you will not normally have to specify any additional
103 @cindex @option{-march=} command-line option, AArch64
104 @item -march=@var{architecture}[+@var{extension}@dots{}]
105 This option specifies the target architecture. The assembler will
106 issue an error message if an attempt is made to assemble an
107 instruction which will not execute on the target architecture. The
108 following architecture names are recognized: @code{armv8-a},
109 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
110 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}.
112 If both @option{-mcpu} and @option{-march} are specified, the
113 assembler will use the setting for @option{-mcpu}. If neither are
114 specified, the assembler will default to @option{-mcpu=all}.
116 The architecture option can be extended with the same instruction set
117 extension options as the @option{-mcpu} option. Unlike
118 @option{-mcpu}, extensions are not always enabled by default,
119 @xref{AArch64 Extensions}.
121 @cindex @code{-mverbose-error} command-line option, AArch64
122 @item -mverbose-error
123 This option enables verbose error messages for AArch64 gas. This option
124 is enabled by default.
126 @cindex @code{-mno-verbose-error} command-line option, AArch64
127 @item -mno-verbose-error
128 This option disables verbose error messages in AArch64 gas.
133 @node AArch64 Extensions
134 @section Architecture Extensions
136 The table below lists the permitted architecture extensions that are
137 supported by the assembler and the conditions under which they are
138 automatically enabled.
140 Multiple extensions may be specified, separated by a @code{+}.
141 Extension mnemonics may also be removed from those the assembler
142 accepts. This is done by prepending @code{no} to the option that adds
143 the extension. Extensions that are removed must be listed after all
144 extensions that have been added.
146 Enabling an extension that requires other extensions will
147 automatically cause those extensions to be enabled. Similarly,
148 disabling an extension that is required by other extensions will
149 automatically cause those extensions to be disabled.
151 @multitable @columnfractions .12 .17 .17 .54
152 @headitem Extension @tab Minimum Architecture @tab Enabled by default
154 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
155 @tab Enable Int8 Matrix Multiply extension.
156 @item @code{f32mm} @tab ARMv8.2-A @tab No
157 @tab Enable F32 Matrix Multiply extension.
158 @item @code{f64mm} @tab ARMv8.2-A @tab No
159 @tab Enable F64 Matrix Multiply extension.
160 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
161 @tab Enable BFloat16 extension.
162 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
163 @tab Enable the complex number SIMD extensions. This implies
164 @code{fp16} and @code{simd}.
165 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
166 @tab Enable CRC instructions.
167 @item @code{crypto} @tab ARMv8-A @tab No
168 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
169 @item @code{aes} @tab ARMv8-A @tab No
170 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
171 @item @code{sha2} @tab ARMv8-A @tab No
172 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
173 @item @code{sha3} @tab ARMv8.2-A @tab No
174 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
175 @item @code{sm4} @tab ARMv8.2-A @tab No
176 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
177 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
178 @tab Enable floating-point extensions.
179 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
180 @tab Enable ARMv8.2 16-bit floating-point support. This implies
182 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
183 @tab Enable Limited Ordering Regions extensions.
184 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
185 @tab Enable Large System extensions.
186 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
187 @tab Enable Privileged Access Never support.
188 @item @code{profile} @tab ARMv8.2-A @tab No
189 @tab Enable statistical profiling extensions.
190 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
191 @tab Enable the Reliability, Availability and Serviceability
193 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
194 @tab Enable the weak release consistency extension.
195 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
196 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
197 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
198 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
199 @item @code{sve} @tab ARMv8.2-A @tab No
200 @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
201 @code{simd} and @code{compnum}.
202 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
203 @tab Enable the Dot Product extension. This implies @code{simd}.
204 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
205 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
206 This implies @code{fp16}.
207 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
208 @tab Enable the speculation barrier instruction sb.
209 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
210 @tab Enable the Execution and Data and Prediction instructions.
211 @item @code{rng} @tab ARMv8.5-A @tab No
212 @tab Enable ARMv8.5-A random number instructions.
213 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
214 @tab Enable Speculative Store Bypassing Safe state read and write.
215 @item @code{memtag} @tab ARMv8.5-A @tab No
216 @tab Enable ARMv8.5-A Memory Tagging Extensions.
217 @item @code{tme} @tab ARMv8-A @tab No
218 @tab Enable Transactional Memory Extensions.
219 @item @code{sve2} @tab ARMv8-A @tab No
220 @tab Enable the SVE2 Extension.
221 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
222 @tab Enable SVE2 BITPERM Extension.
223 @item @code{sve2-sm4} @tab ARMv8-A @tab No
224 @tab Enable SVE2 SM4 Extension.
225 @item @code{sve2-aes} @tab ARMv8-A @tab No
226 @tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the
227 @code{pmullt} and @code{pmullb} instructions.
228 @item @code{sve2-sha3} @tab ARMv8-A @tab No
229 @tab Enable SVE2 SHA3 Extension.
230 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
231 @tab Enable Flag Manipulation instructions.
232 @item @code{csre} @tab ARMv8-A @tab No
233 @tab Enable Call Stack Recorder Extension.
234 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
235 @tab Enable 64 Byte Loads/Stores.
236 @item @code{pauth} @tab ARMv8-A @tab No
237 @tab Enable Pointer Authentication.
243 * AArch64-Chars:: Special Characters
244 * AArch64-Regs:: Register Names
245 * AArch64-Relocations:: Relocations
249 @subsection Special Characters
251 @cindex line comment character, AArch64
252 @cindex AArch64 line comment character
253 The presence of a @samp{//} on a line indicates the start of a comment
254 that extends to the end of the current line. If a @samp{#} appears as
255 the first character of a line, the whole line is treated as a comment.
257 @cindex line separator, AArch64
258 @cindex statement separator, AArch64
259 @cindex AArch64 line separator
260 The @samp{;} character can be used instead of a newline to separate
263 @cindex immediate character, AArch64
264 @cindex AArch64 immediate character
265 The @samp{#} can be optionally used to indicate immediate operands.
268 @subsection Register Names
270 @cindex AArch64 register names
271 @cindex register names, AArch64
272 Please refer to the section @samp{4.4 Register Names} of
273 @samp{ARMv8 Instruction Set Overview}, which is available at
274 @uref{http://infocenter.arm.com}.
276 @node AArch64-Relocations
277 @subsection Relocations
279 @cindex relocations, AArch64
280 @cindex AArch64 relocations
281 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
282 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
283 by prefixing the label with @samp{#:abs_g2:} etc.
284 For example to load the 48-bit absolute address of @var{foo} into x0:
287 movz x0, #:abs_g2:foo // bits 32-47, overflow check
288 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
289 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
292 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
293 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
294 instructions can be generated by prefixing the label with
295 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
297 For example to use 33-bit (+/-4GB) pc-relative addressing to
298 load the address of @var{foo} into x0:
301 adrp x0, :pg_hi21:foo
302 add x0, x0, #:lo12:foo
305 Or to load the value of @var{foo} into x0:
308 adrp x0, :pg_hi21:foo
309 ldr x0, [x0, #:lo12:foo]
312 Note that @samp{:pg_hi21:} is optional.
321 adrp x0, :pg_hi21:foo
324 @node AArch64 Floating Point
325 @section Floating Point
327 @cindex floating point, AArch64 (@sc{ieee})
328 @cindex AArch64 floating point (@sc{ieee})
329 The AArch64 architecture uses @sc{ieee} floating-point numbers.
331 @node AArch64 Directives
332 @section AArch64 Machine Directives
334 @cindex machine directives, AArch64
335 @cindex AArch64 machine directives
338 @c AAAAAAAAAAAAAAAAAAAAAAAAA
340 @cindex @code{.arch} directive, AArch64
341 @item .arch @var{name}
342 Select the target architecture. Valid values for @var{name} are the same as
343 for the @option{-march} command-line option.
345 Specifying @code{.arch} clears any previously selected architecture
348 @cindex @code{.arch_extension} directive, AArch64
349 @item .arch_extension @var{name}
350 Add or remove an architecture extension to the target architecture. Valid
351 values for @var{name} are the same as those accepted as architectural
352 extensions by the @option{-mcpu} command-line option.
354 @code{.arch_extension} may be used multiple times to add or remove extensions
355 incrementally to the architecture being compiled for.
357 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
359 @cindex @code{.bss} directive, AArch64
361 This directive switches to the @code{.bss} section.
363 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
365 @cindex @code{.cpu} directive, AArch64
366 @item .cpu @var{name}
367 Set the target processor. Valid values for @var{name} are the same as
368 those accepted by the @option{-mcpu=} command-line option.
370 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
372 @cindex @code{.dword} directive, AArch64
373 @item .dword @var{expressions}
374 The @code{.dword} directive produces 64 bit values.
376 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
378 @cindex @code{.even} directive, AArch64
380 The @code{.even} directive aligns the output on the next even byte
383 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
385 @cindex @code{.float16} directive, AArch64
386 @item .float16 @var{value [,...,value_n]}
387 Place the half precision floating point representation of one or more
388 floating-point values into the current section.
389 The format used to encode the floating point values is always the
390 IEEE 754-2008 half precision floating point format.
392 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
393 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
394 @c IIIIIIIIIIIIIIIIIIIIIIIIII
396 @cindex @code{.inst} directive, AArch64
397 @item .inst @var{expressions}
398 Inserts the expressions into the output as if they were instructions,
401 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
402 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
403 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
405 @cindex @code{.ltorg} directive, AArch64
407 This directive causes the current contents of the literal pool to be
408 dumped into the current section (which is assumed to be the .text
409 section) at the current location (aligned to a word boundary).
410 GAS maintains a separate literal pool for each section and each
411 sub-section. The @code{.ltorg} directive will only affect the literal
412 pool of the current section and sub-section. At the end of assembly
413 all remaining, un-empty literal pools will automatically be dumped.
415 Note - older versions of GAS would dump the current literal
416 pool any time a section change occurred. This is no longer done, since
417 it prevents accurate control of the placement of literal pools.
419 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
421 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
422 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
424 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
426 @cindex @code{.pool} directive, AArch64
428 This is a synonym for .ltorg.
430 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
431 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
433 @cindex @code{.req} directive, AArch64
434 @item @var{name} .req @var{register name}
435 This creates an alias for @var{register name} called @var{name}. For
442 ip0, ip1, lr and fp are automatically defined to
443 alias to X16, X17, X30 and X29 respectively.
445 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
447 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
449 @cindex @code{.tlsdescadd} directive, AArch64
450 @item @code{.tlsdescadd}
451 Emits a TLSDESC_ADD reloc on the next instruction.
453 @cindex @code{.tlsdesccall} directive, AArch64
454 @item @code{.tlsdesccall}
455 Emits a TLSDESC_CALL reloc on the next instruction.
457 @cindex @code{.tlsdescldr} directive, AArch64
458 @item @code{.tlsdescldr}
459 Emits a TLSDESC_LDR reloc on the next instruction.
461 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
463 @cindex @code{.unreq} directive, AArch64
464 @item .unreq @var{alias-name}
465 This undefines a register alias which was previously defined using the
466 @code{req} directive. For example:
473 An error occurs if the name is undefined. Note - this pseudo op can
474 be used to delete builtin in register name aliases (eg 'w0'). This
475 should only be done if it is really necessary.
477 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
479 @cindex @code{.variant_pcs} directive, AArch64
480 @item .variant_pcs @var{symbol}
481 This directive marks @var{symbol} referencing a function that may
482 follow a variant procedure call standard with different register
483 usage convention from the base procedure call standard.
485 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
486 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
488 @cindex @code{.xword} directive, AArch64
489 @item .xword @var{expressions}
490 The @code{.xword} directive produces 64 bit values. This is the same
491 as the @code{.dword} directive.
493 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
494 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
496 @cindex @code{.cfi_b_key_frame} directive, AArch64
497 @item @code{.cfi_b_key_frame}
498 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
499 corresponding to the current frame's FDE, meaning that its return address has
500 been signed with the B-key. If two frames are signed with differing keys then
501 they will not share the same CIE. This information is intended to be used by
502 the stack unwinder in order to properly authenticate return addresses.
506 @node AArch64 Opcodes
509 @cindex AArch64 opcodes
510 @cindex opcodes for AArch64
511 GAS implements all the standard AArch64 opcodes. It also
512 implements several pseudo opcodes, including several synthetic load
517 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
520 ldr <register> , =<expression>
523 The constant expression will be placed into the nearest literal pool (if it not
524 already there) and a PC-relative LDR instruction will be generated.
528 For more information on the AArch64 instruction set and assembly language
529 notation, see @samp{ARMv8 Instruction Set Overview} available at
530 @uref{http://infocenter.arm.com}.
533 @node AArch64 Mapping Symbols
534 @section Mapping Symbols
536 The AArch64 ELF specification requires that special symbols be inserted
537 into object files to mark certain features:
543 At the start of a region of code containing AArch64 instructions.
547 At the start of a region of data.