gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2019 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a55},
  61 @code{cortex-a57},
  62 @code{cortex-a72},
  63 @code{cortex-a73},
  64 @code{cortex-a75},
  65 @code{cortex-a76},
  66 @code{ares},
  67 @code{exynos-m1},
  68 @code{falkor},
  69 @code{neoverse-n1},
  70 @code{neoverse-e1},
  71 @code{qdf24xx},
  72 @code{saphira},
  73 @code{thunderx},
  74 @code{vulcan},
  75 @code{xgene1}
  76 and
  77 @code{xgene2}.
  78 The special name @code{all} may be used to allow the assembler to accept
  79 instructions valid for any supported processor, including all optional
  80 extensions.
  81
  82 In addition to the basic instruction set, the assembler can be told to
  83 accept, or restrict, various extension mnemonics that extend the
  84 processor.  @xref{AArch64 Extensions}.
  85
  86 If some implementations of a particular processor can have an
  87 extension, then then those extensions are automatically enabled.
  88 Consequently, you will not normally have to specify any additional
  89 extensions.
  90
  91 @cindex @option{-march=} command-line option, AArch64
  92 @item -march=@var{architecture}[+@var{extension}@dots{}]
  93 This option specifies the target architecture.  The assembler will
  94 issue an error message if an attempt is made to assemble an
  95 instruction which will not execute on the target architecture.  The
  96 following architecture names are recognized: @code{armv8-a},
  97 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
  98 and @code{armv8.5-a}.
  99
 100 If both @option{-mcpu} and @option{-march} are specified, the
 101 assembler will use the setting for @option{-mcpu}.  If neither are
 102 specified, the assembler will default to @option{-mcpu=all}.
 103
 104 The architecture option can be extended with the same instruction set
 105 extension options as the @option{-mcpu} option.  Unlike
 106 @option{-mcpu}, extensions are not always enabled by default,
 107 @xref{AArch64 Extensions}.
 108
 109 @cindex @code{-mverbose-error} command-line option, AArch64
 110 @item -mverbose-error
 111 This option enables verbose error messages for AArch64 gas.  This option
 112 is enabled by default.
 113
 114 @cindex @code{-mno-verbose-error} command-line option, AArch64
 115 @item -mno-verbose-error
 116 This option disables verbose error messages in AArch64 gas.
 117
 118 @end table
 119 @c man end
 120
 121 @node AArch64 Extensions
 122 @section Architecture Extensions
 123
 124 The table below lists the permitted architecture extensions that are
 125 supported by the assembler and the conditions under which they are
 126 automatically enabled.
 127
 128 Multiple extensions may be specified, separated by a @code{+}.
 129 Extension mnemonics may also be removed from those the assembler
 130 accepts.  This is done by prepending @code{no} to the option that adds
 131 the extension.  Extensions that are removed must be listed after all
 132 extensions that have been added.
 133
 134 Enabling an extension that requires other extensions will
 135 automatically cause those extensions to be enabled.  Similarly,
 136 disabling an extension that is required by other extensions will
 137 automatically cause those extensions to be disabled.
 138
 139 @multitable @columnfractions .12 .17 .17 .54
 140 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 141  @tab Description
 142 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 143  @tab Enable the complex number SIMD extensions.  This implies
 144  @code{fp16} and @code{simd}.
 145 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 146  @tab Enable CRC instructions.
 147 @item @code{crypto} @tab ARMv8-A @tab No
 148  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 149 @item @code{aes} @tab ARMv8-A @tab No
 150  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 151 @item @code{sha2} @tab ARMv8-A @tab No
 152  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 153 @item @code{sha3} @tab ARMv8.2-A @tab No
 154  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 155 @item @code{sm4} @tab ARMv8.2-A @tab No
 156  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 157 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 158  @tab Enable floating-point extensions.
 159 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 160  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 161  @code{fp}.
 162 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 163  @tab Enable Limited Ordering Regions extensions.
 164 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 165  @tab Enable Large System extensions.
 166 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 167  @tab Enable Privileged Access Never support.
 168 @item @code{profile} @tab ARMv8.2-A @tab No
 169  @tab Enable statistical profiling extensions.
 170 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 171  @tab Enable the Reliability, Availability and Serviceability
 172  extension.
 173 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 174  @tab Enable the weak release consistency extension.
 175 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 176  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 177 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 178  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 179 @item @code{sve} @tab ARMv8.2-A @tab No
 180  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 181  @code{simd} and @code{compnum}.
 182 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 183  @tab Enable the Dot Product extension.  This implies @code{simd}.
 184 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 185  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 186  This implies @code{fp16}.
 187 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 188  @tab Enable the speculation barrier instruction sb.
 189 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 190  @tab Enable the Execution and Data and Prediction instructions.
 191 @item @code{rng} @tab ARMv8.5-A @tab No
 192  @tab Enable ARMv8.5-A random number instructions.
 193 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 194  @tab Enable Speculative Store Bypassing Safe state read and write.
 195 @item @code{memtag} @tab ARMv8.5-A @tab No
 196  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 197 @item @code{tme} @tab ARMv8-A @tab No
 198  @tab Enable Transactional Memory Extensions.
 199 @item @code{sve2} @tab ARMv8-A @tab No
 200  @tab Enable the SVE2 Extension.
 201 @item @code{bitperm} @tab ARMv8-A @tab No
 202  @tab Enable SVE2 BITPERM Extension.
 203 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 204  @tab Enable SVE2 SM4 Extension.
 205 @item @code{sve2-aes} @tab ARMv8-A @tab No
 206  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 207  @code{pmullt} and @code{pmullb} instructions.
 208 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 209  @tab Enable SVE2 SHA3 Extension.
 210 @end multitable
 211
 212 @node AArch64 Syntax
 213 @section Syntax
 214 @menu
 215 * AArch64-Chars::                Special Characters
 216 * AArch64-Regs::                 Register Names
 217 * AArch64-Relocations::      Relocations
 218 @end menu
 219
 220 @node AArch64-Chars
 221 @subsection Special Characters
 222
 223 @cindex line comment character, AArch64
 224 @cindex AArch64 line comment character
 225 The presence of a @samp{//} on a line indicates the start of a comment
 226 that extends to the end of the current line.  If a @samp{#} appears as
 227 the first character of a line, the whole line is treated as a comment.
 228
 229 @cindex line separator, AArch64
 230 @cindex statement separator, AArch64
 231 @cindex AArch64 line separator
 232 The @samp{;} character can be used instead of a newline to separate
 233 statements.
 234
 235 @cindex immediate character, AArch64
 236 @cindex AArch64 immediate character
 237 The @samp{#} can be optionally used to indicate immediate operands.
 238
 239 @node AArch64-Regs
 240 @subsection Register Names
 241
 242 @cindex AArch64 register names
 243 @cindex register names, AArch64
 244 Please refer to the section @samp{4.4 Register Names} of
 245 @samp{ARMv8 Instruction Set Overview}, which is available at
 246 @uref{http://infocenter.arm.com}.
 247
 248 @node AArch64-Relocations
 249 @subsection Relocations
 250
 251 @cindex relocations, AArch64
 252 @cindex AArch64 relocations
 253 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 254 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 255 by prefixing the label with @samp{#:abs_g2:} etc.
 256 For example to load the 48-bit absolute address of @var{foo} into x0:
 257
 258 @smallexample
 259         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 260         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 261         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 262 @end smallexample
 263
 264 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 265 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 266 instructions can be generated by prefixing the label with
 267 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 268
 269 For example to use 33-bit (+/-4GB) pc-relative addressing to
 270 load the address of @var{foo} into x0:
 271
 272 @smallexample
 273         adrp x0, :pg_hi21:foo
 274         add  x0, x0, #:lo12:foo
 275 @end smallexample
 276
 277 Or to load the value of @var{foo} into x0:
 278
 279 @smallexample
 280         adrp x0, :pg_hi21:foo
 281         ldr  x0, [x0, #:lo12:foo]
 282 @end smallexample
 283
 284 Note that @samp{:pg_hi21:} is optional.
 285
 286 @smallexample
 287         adrp x0, foo
 288 @end smallexample
 289
 290 is equivalent to
 291
 292 @smallexample
 293         adrp x0, :pg_hi21:foo
 294 @end smallexample
 295
 296 @node AArch64 Floating Point
 297 @section Floating Point
 298
 299 @cindex floating point, AArch64 (@sc{ieee})
 300 @cindex AArch64 floating point (@sc{ieee})
 301 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 302
 303 @node AArch64 Directives
 304 @section AArch64 Machine Directives
 305
 306 @cindex machine directives, AArch64
 307 @cindex AArch64 machine directives
 308 @table @code
 309
 310 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 311
 312 @cindex @code{.arch} directive, AArch64
 313 @item .arch @var{name}
 314 Select the target architecture.  Valid values for @var{name} are the same as
 315 for the @option{-march} command-line option.
 316
 317 Specifying @code{.arch} clears any previously selected architecture
 318 extensions.
 319
 320 @cindex @code{.arch_extension} directive, AArch64
 321 @item .arch_extension @var{name}
 322 Add or remove an architecture extension to the target architecture.  Valid
 323 values for @var{name} are the same as those accepted as architectural
 324 extensions by the @option{-mcpu} command-line option.
 325
 326 @code{.arch_extension} may be used multiple times to add or remove extensions
 327 incrementally to the architecture being compiled for.
 328
 329 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 330
 331 @cindex @code{.bss} directive, AArch64
 332 @item .bss
 333 This directive switches to the @code{.bss} section.
 334
 335 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 336
 337 @cindex @code{.cpu} directive, AArch64
 338 @item .cpu @var{name}
 339 Set the target processor.  Valid values for @var{name} are the same as
 340 those accepted by the @option{-mcpu=} command-line option.
 341
 342 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 343
 344 @cindex @code{.dword} directive, AArch64
 345 @item .dword @var{expressions}
 346 The @code{.dword} directive produces 64 bit values.
 347
 348 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 349
 350 @cindex @code{.even} directive, AArch64
 351 @item .even
 352 The @code{.even} directive aligns the output on the next even byte
 353 boundary.
 354
 355 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 356 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 357 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 358 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 359
 360 @cindex @code{.inst} directive, AArch64
 361 @item .inst @var{expressions}
 362 Inserts the expressions into the output as if they were instructions,
 363 rather than data.
 364
 365 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 366 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 367 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 368
 369 @cindex @code{.ltorg} directive, AArch64
 370 @item .ltorg
 371 This directive causes the current contents of the literal pool to be
 372 dumped into the current section (which is assumed to be the .text
 373 section) at the current location (aligned to a word boundary).
 374 GAS maintains a separate literal pool for each section and each
 375 sub-section.  The @code{.ltorg} directive will only affect the literal
 376 pool of the current section and sub-section.  At the end of assembly
 377 all remaining, un-empty literal pools will automatically be dumped.
 378
 379 Note - older versions of GAS would dump the current literal
 380 pool any time a section change occurred.  This is no longer done, since
 381 it prevents accurate control of the placement of literal pools.
 382
 383 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 384
 385 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 386 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 387
 388 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 389
 390 @cindex @code{.pool} directive, AArch64
 391 @item .pool
 392 This is a synonym for .ltorg.
 393
 394 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 395 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 396
 397 @cindex @code{.req} directive, AArch64
 398 @item @var{name} .req @var{register name}
 399 This creates an alias for @var{register name} called @var{name}.  For
 400 example:
 401
 402 @smallexample
 403         foo .req w0
 404 @end smallexample
 405
 406 ip0, ip1, lr and fp are automatically defined to
 407 alias to X16, X17, X30 and X29 respectively.
 408
 409 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 410
 411 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 412
 413 @cindex @code{.tlsdescadd} directive, AArch64
 414 @item   @code{.tlsdescadd}
 415 Emits a TLSDESC_ADD reloc on the next instruction.
 416
 417 @cindex @code{.tlsdesccall} directive, AArch64
 418 @item   @code{.tlsdesccall}
 419 Emits a TLSDESC_CALL reloc on the next instruction.
 420
 421 @cindex @code{.tlsdescldr} directive, AArch64
 422 @item   @code{.tlsdescldr}
 423 Emits a TLSDESC_LDR reloc on the next instruction.
 424
 425 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 426
 427 @cindex @code{.unreq} directive, AArch64
 428 @item .unreq @var{alias-name}
 429 This undefines a register alias which was previously defined using the
 430 @code{req} directive.  For example:
 431
 432 @smallexample
 433         foo .req w0
 434         .unreq foo
 435 @end smallexample
 436
 437 An error occurs if the name is undefined.  Note - this pseudo op can
 438 be used to delete builtin in register name aliases (eg 'w0').  This
 439 should only be done if it is really necessary.
 440
 441 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 442
 443 @cindex @code{.variant_pcs} directive, AArch64
 444 @item .variant_pcs @var{symbol}
 445 This directive marks @var{symbol} referencing a function that may
 446 follow a variant procedure call standard with different register
 447 usage convention from the base procedure call standard.
 448
 449 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 450 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 451
 452 @cindex @code{.xword} directive, AArch64
 453 @item .xword @var{expressions}
 454 The @code{.xword} directive produces 64 bit values.  This is the same
 455 as the @code{.dword} directive.
 456
 457 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 458 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 459
 460 @cindex @code{.cfi_b_key_frame} directive, AArch64
 461 @item   @code{.cfi_b_key_frame}
 462 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 463 corresponding to the current frame's FDE, meaning that its return address has
 464 been signed with the B-key.  If two frames are signed with differing keys then
 465 they will not share the same CIE.  This information is intended to be used by
 466 the stack unwinder in order to properly authenticate return addresses.
 467
 468 @end table
 469
 470 @node AArch64 Opcodes
 471 @section Opcodes
 472
 473 @cindex AArch64 opcodes
 474 @cindex opcodes for AArch64
 475 GAS implements all the standard AArch64 opcodes.  It also
 476 implements several pseudo opcodes, including several synthetic load
 477 instructions.
 478
 479 @table @code
 480
 481 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 482 @item LDR =
 483 @smallexample
 484   ldr <register> , =<expression>
 485 @end smallexample
 486
 487 The constant expression will be placed into the nearest literal pool (if it not
 488 already there) and a PC-relative LDR instruction will be generated.
 489
 490 @end table
 491
 492 For more information on the AArch64 instruction set and assembly language
 493 notation, see @samp{ARMv8 Instruction Set Overview} available at
 494 @uref{http://infocenter.arm.com}.
 495
 496
 497 @node AArch64 Mapping Symbols
 498 @section Mapping Symbols
 499
 500 The AArch64 ELF specification requires that special symbols be inserted
 501 into object files to mark certain features:
 502
 503 @table @code
 504
 505 @cindex @code{$x}
 506 @item $x
 507 At the start of a region of code containing AArch64 instructions.
 508
 509 @cindex @code{$d}
 510 @item $d
 511 At the start of a region of data.
 512
 513 @end table