gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{ares},
  75 @code{exynos-m1},
  76 @code{falkor},
  77 @code{neoverse-n1},
  78 @code{neoverse-n2},
  79 @code{neoverse-e1},
  80 @code{neoverse-v1},
  81 @code{qdf24xx},
  82 @code{saphira},
  83 @code{thunderx},
  84 @code{vulcan},
  85 @code{xgene1}
  86 @code{xgene2},
  87 @code{cortex-r82},
  88 and
  89 @code{cortex-x1}.
  90 The special name @code{all} may be used to allow the assembler to accept
  91 instructions valid for any supported processor, including all optional
  92 extensions.
  93
  94 In addition to the basic instruction set, the assembler can be told to
  95 accept, or restrict, various extension mnemonics that extend the
  96 processor.  @xref{AArch64 Extensions}.
  97
  98 If some implementations of a particular processor can have an
  99 extension, then then those extensions are automatically enabled.
 100 Consequently, you will not normally have to specify any additional
 101 extensions.
 102
 103 @cindex @option{-march=} command-line option, AArch64
 104 @item -march=@var{architecture}[+@var{extension}@dots{}]
 105 This option specifies the target architecture.  The assembler will
 106 issue an error message if an attempt is made to assemble an
 107 instruction which will not execute on the target architecture.  The
 108 following architecture names are recognized: @code{armv8-a},
 109 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 110 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}.
 111
 112 If both @option{-mcpu} and @option{-march} are specified, the
 113 assembler will use the setting for @option{-mcpu}.  If neither are
 114 specified, the assembler will default to @option{-mcpu=all}.
 115
 116 The architecture option can be extended with the same instruction set
 117 extension options as the @option{-mcpu} option.  Unlike
 118 @option{-mcpu}, extensions are not always enabled by default,
 119 @xref{AArch64 Extensions}.
 120
 121 @cindex @code{-mverbose-error} command-line option, AArch64
 122 @item -mverbose-error
 123 This option enables verbose error messages for AArch64 gas.  This option
 124 is enabled by default.
 125
 126 @cindex @code{-mno-verbose-error} command-line option, AArch64
 127 @item -mno-verbose-error
 128 This option disables verbose error messages in AArch64 gas.
 129
 130 @end table
 131 @c man end
 132
 133 @node AArch64 Extensions
 134 @section Architecture Extensions
 135
 136 The table below lists the permitted architecture extensions that are
 137 supported by the assembler and the conditions under which they are
 138 automatically enabled.
 139
 140 Multiple extensions may be specified, separated by a @code{+}.
 141 Extension mnemonics may also be removed from those the assembler
 142 accepts.  This is done by prepending @code{no} to the option that adds
 143 the extension.  Extensions that are removed must be listed after all
 144 extensions that have been added.
 145
 146 Enabling an extension that requires other extensions will
 147 automatically cause those extensions to be enabled.  Similarly,
 148 disabling an extension that is required by other extensions will
 149 automatically cause those extensions to be disabled.
 150
 151 @multitable @columnfractions .12 .17 .17 .54
 152 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 153  @tab Description
 154 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 155  @tab Enable Int8 Matrix Multiply extension.
 156 @item @code{f32mm} @tab ARMv8.2-A @tab No
 157  @tab Enable F32 Matrix Multiply extension.
 158 @item @code{f64mm} @tab ARMv8.2-A @tab No
 159  @tab Enable F64 Matrix Multiply extension.
 160 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 161  @tab Enable BFloat16 extension.
 162 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 163  @tab Enable the complex number SIMD extensions.  This implies
 164  @code{fp16} and @code{simd}.
 165 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 166  @tab Enable CRC instructions.
 167 @item @code{crypto} @tab ARMv8-A @tab No
 168  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 169 @item @code{aes} @tab ARMv8-A @tab No
 170  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 171 @item @code{sha2} @tab ARMv8-A @tab No
 172  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 173 @item @code{sha3} @tab ARMv8.2-A @tab No
 174  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 175 @item @code{sm4} @tab ARMv8.2-A @tab No
 176  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 177 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 178  @tab Enable floating-point extensions.
 179 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 180  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 181  @code{fp}.
 182 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 183  @tab Enable Limited Ordering Regions extensions.
 184 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 185  @tab Enable Large System extensions.
 186 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 187  @tab Enable Privileged Access Never support.
 188 @item @code{profile} @tab ARMv8.2-A @tab No
 189  @tab Enable statistical profiling extensions.
 190 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 191  @tab Enable the Reliability, Availability and Serviceability
 192  extension.
 193 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 194  @tab Enable the weak release consistency extension.
 195 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 196  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 197 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 198  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 199 @item @code{sve} @tab ARMv8.2-A @tab No
 200  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 201  @code{simd} and @code{compnum}.
 202 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 203  @tab Enable the Dot Product extension.  This implies @code{simd}.
 204 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 205  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 206  This implies @code{fp16}.
 207 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 208  @tab Enable the speculation barrier instruction sb.
 209 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 210  @tab Enable the Execution and Data and Prediction instructions.
 211 @item @code{rng} @tab ARMv8.5-A @tab No
 212  @tab Enable ARMv8.5-A random number instructions.
 213 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 214  @tab Enable Speculative Store Bypassing Safe state read and write.
 215 @item @code{memtag} @tab ARMv8.5-A @tab No
 216  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 217 @item @code{tme} @tab ARMv8-A @tab No
 218  @tab Enable Transactional Memory Extensions.
 219 @item @code{sve2} @tab ARMv8-A @tab No
 220  @tab Enable the SVE2 Extension.
 221 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 222  @tab Enable SVE2 BITPERM Extension.
 223 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 224  @tab Enable SVE2 SM4 Extension.
 225 @item @code{sve2-aes} @tab ARMv8-A @tab No
 226  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 227  @code{pmullt} and @code{pmullb} instructions.
 228 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 229  @tab Enable SVE2 SHA3 Extension.
 230 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 231  @tab Enable Flag Manipulation instructions.
 232 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 233  @tab Enable 64 Byte Loads/Stores.
 234 @item @code{pauth} @tab ARMv8-A @tab No
 235  @tab Enable Pointer Authentication.
 236 @end multitable
 237
 238 @node AArch64 Syntax
 239 @section Syntax
 240 @menu
 241 * AArch64-Chars::                Special Characters
 242 * AArch64-Regs::                 Register Names
 243 * AArch64-Relocations::      Relocations
 244 @end menu
 245
 246 @node AArch64-Chars
 247 @subsection Special Characters
 248
 249 @cindex line comment character, AArch64
 250 @cindex AArch64 line comment character
 251 The presence of a @samp{//} on a line indicates the start of a comment
 252 that extends to the end of the current line.  If a @samp{#} appears as
 253 the first character of a line, the whole line is treated as a comment.
 254
 255 @cindex line separator, AArch64
 256 @cindex statement separator, AArch64
 257 @cindex AArch64 line separator
 258 The @samp{;} character can be used instead of a newline to separate
 259 statements.
 260
 261 @cindex immediate character, AArch64
 262 @cindex AArch64 immediate character
 263 The @samp{#} can be optionally used to indicate immediate operands.
 264
 265 @node AArch64-Regs
 266 @subsection Register Names
 267
 268 @cindex AArch64 register names
 269 @cindex register names, AArch64
 270 Please refer to the section @samp{4.4 Register Names} of
 271 @samp{ARMv8 Instruction Set Overview}, which is available at
 272 @uref{http://infocenter.arm.com}.
 273
 274 @node AArch64-Relocations
 275 @subsection Relocations
 276
 277 @cindex relocations, AArch64
 278 @cindex AArch64 relocations
 279 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 280 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 281 by prefixing the label with @samp{#:abs_g2:} etc.
 282 For example to load the 48-bit absolute address of @var{foo} into x0:
 283
 284 @smallexample
 285         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 286         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 287         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 288 @end smallexample
 289
 290 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 291 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 292 instructions can be generated by prefixing the label with
 293 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 294
 295 For example to use 33-bit (+/-4GB) pc-relative addressing to
 296 load the address of @var{foo} into x0:
 297
 298 @smallexample
 299         adrp x0, :pg_hi21:foo
 300         add  x0, x0, #:lo12:foo
 301 @end smallexample
 302
 303 Or to load the value of @var{foo} into x0:
 304
 305 @smallexample
 306         adrp x0, :pg_hi21:foo
 307         ldr  x0, [x0, #:lo12:foo]
 308 @end smallexample
 309
 310 Note that @samp{:pg_hi21:} is optional.
 311
 312 @smallexample
 313         adrp x0, foo
 314 @end smallexample
 315
 316 is equivalent to
 317
 318 @smallexample
 319         adrp x0, :pg_hi21:foo
 320 @end smallexample
 321
 322 @node AArch64 Floating Point
 323 @section Floating Point
 324
 325 @cindex floating point, AArch64 (@sc{ieee})
 326 @cindex AArch64 floating point (@sc{ieee})
 327 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 328
 329 @node AArch64 Directives
 330 @section AArch64 Machine Directives
 331
 332 @cindex machine directives, AArch64
 333 @cindex AArch64 machine directives
 334 @table @code
 335
 336 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 337
 338 @cindex @code{.arch} directive, AArch64
 339 @item .arch @var{name}
 340 Select the target architecture.  Valid values for @var{name} are the same as
 341 for the @option{-march} command-line option.
 342
 343 Specifying @code{.arch} clears any previously selected architecture
 344 extensions.
 345
 346 @cindex @code{.arch_extension} directive, AArch64
 347 @item .arch_extension @var{name}
 348 Add or remove an architecture extension to the target architecture.  Valid
 349 values for @var{name} are the same as those accepted as architectural
 350 extensions by the @option{-mcpu} command-line option.
 351
 352 @code{.arch_extension} may be used multiple times to add or remove extensions
 353 incrementally to the architecture being compiled for.
 354
 355 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 356
 357 @cindex @code{.bss} directive, AArch64
 358 @item .bss
 359 This directive switches to the @code{.bss} section.
 360
 361 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 362
 363 @cindex @code{.cpu} directive, AArch64
 364 @item .cpu @var{name}
 365 Set the target processor.  Valid values for @var{name} are the same as
 366 those accepted by the @option{-mcpu=} command-line option.
 367
 368 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 369
 370 @cindex @code{.dword} directive, AArch64
 371 @item .dword @var{expressions}
 372 The @code{.dword} directive produces 64 bit values.
 373
 374 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 375
 376 @cindex @code{.even} directive, AArch64
 377 @item .even
 378 The @code{.even} directive aligns the output on the next even byte
 379 boundary.
 380
 381 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 382
 383 @cindex @code{.float16} directive, AArch64
 384 @item .float16 @var{value [,...,value_n]}
 385 Place the half precision floating point representation of one or more
 386 floating-point values into the current section.
 387 The format used to encode the floating point values is always the
 388 IEEE 754-2008 half precision floating point format.
 389
 390 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 391 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 392 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 393
 394 @cindex @code{.inst} directive, AArch64
 395 @item .inst @var{expressions}
 396 Inserts the expressions into the output as if they were instructions,
 397 rather than data.
 398
 399 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 400 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 401 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 402
 403 @cindex @code{.ltorg} directive, AArch64
 404 @item .ltorg
 405 This directive causes the current contents of the literal pool to be
 406 dumped into the current section (which is assumed to be the .text
 407 section) at the current location (aligned to a word boundary).
 408 GAS maintains a separate literal pool for each section and each
 409 sub-section.  The @code{.ltorg} directive will only affect the literal
 410 pool of the current section and sub-section.  At the end of assembly
 411 all remaining, un-empty literal pools will automatically be dumped.
 412
 413 Note - older versions of GAS would dump the current literal
 414 pool any time a section change occurred.  This is no longer done, since
 415 it prevents accurate control of the placement of literal pools.
 416
 417 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 418
 419 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 420 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 421
 422 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 423
 424 @cindex @code{.pool} directive, AArch64
 425 @item .pool
 426 This is a synonym for .ltorg.
 427
 428 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 429 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 430
 431 @cindex @code{.req} directive, AArch64
 432 @item @var{name} .req @var{register name}
 433 This creates an alias for @var{register name} called @var{name}.  For
 434 example:
 435
 436 @smallexample
 437         foo .req w0
 438 @end smallexample
 439
 440 ip0, ip1, lr and fp are automatically defined to
 441 alias to X16, X17, X30 and X29 respectively.
 442
 443 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 444
 445 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 446
 447 @cindex @code{.tlsdescadd} directive, AArch64
 448 @item   @code{.tlsdescadd}
 449 Emits a TLSDESC_ADD reloc on the next instruction.
 450
 451 @cindex @code{.tlsdesccall} directive, AArch64
 452 @item   @code{.tlsdesccall}
 453 Emits a TLSDESC_CALL reloc on the next instruction.
 454
 455 @cindex @code{.tlsdescldr} directive, AArch64
 456 @item   @code{.tlsdescldr}
 457 Emits a TLSDESC_LDR reloc on the next instruction.
 458
 459 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 460
 461 @cindex @code{.unreq} directive, AArch64
 462 @item .unreq @var{alias-name}
 463 This undefines a register alias which was previously defined using the
 464 @code{req} directive.  For example:
 465
 466 @smallexample
 467         foo .req w0
 468         .unreq foo
 469 @end smallexample
 470
 471 An error occurs if the name is undefined.  Note - this pseudo op can
 472 be used to delete builtin in register name aliases (eg 'w0').  This
 473 should only be done if it is really necessary.
 474
 475 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 476
 477 @cindex @code{.variant_pcs} directive, AArch64
 478 @item .variant_pcs @var{symbol}
 479 This directive marks @var{symbol} referencing a function that may
 480 follow a variant procedure call standard with different register
 481 usage convention from the base procedure call standard.
 482
 483 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 484 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 485
 486 @cindex @code{.xword} directive, AArch64
 487 @item .xword @var{expressions}
 488 The @code{.xword} directive produces 64 bit values.  This is the same
 489 as the @code{.dword} directive.
 490
 491 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 492 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 493
 494 @cindex @code{.cfi_b_key_frame} directive, AArch64
 495 @item   @code{.cfi_b_key_frame}
 496 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 497 corresponding to the current frame's FDE, meaning that its return address has
 498 been signed with the B-key.  If two frames are signed with differing keys then
 499 they will not share the same CIE.  This information is intended to be used by
 500 the stack unwinder in order to properly authenticate return addresses.
 501
 502 @end table
 503
 504 @node AArch64 Opcodes
 505 @section Opcodes
 506
 507 @cindex AArch64 opcodes
 508 @cindex opcodes for AArch64
 509 GAS implements all the standard AArch64 opcodes.  It also
 510 implements several pseudo opcodes, including several synthetic load
 511 instructions.
 512
 513 @table @code
 514
 515 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 516 @item LDR =
 517 @smallexample
 518   ldr <register> , =<expression>
 519 @end smallexample
 520
 521 The constant expression will be placed into the nearest literal pool (if it not
 522 already there) and a PC-relative LDR instruction will be generated.
 523
 524 @end table
 525
 526 For more information on the AArch64 instruction set and assembly language
 527 notation, see @samp{ARMv8 Instruction Set Overview} available at
 528 @uref{http://infocenter.arm.com}.
 529
 530
 531 @node AArch64 Mapping Symbols
 532 @section Mapping Symbols
 533
 534 The AArch64 ELF specification requires that special symbols be inserted
 535 into object files to mark certain features:
 536
 537 @table @code
 538
 539 @cindex @code{$x}
 540 @item $x
 541 At the start of a region of code containing AArch64 instructions.
 542
 543 @cindex @code{$d}
 544 @item $d
 545 At the start of a region of data.
 546
 547 @end table