1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
141 @code{cortex-m0plus},
144 @code{marvell-whitney},
149 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
150 @code{i80200} (Intel XScale processor)
151 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
154 The special name @code{all} may be used to allow the
155 assembler to accept instructions valid for any ARM processor.
157 In addition to the basic instruction set, the assembler can be told to
158 accept various extension mnemonics that extend the processor using the
159 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
160 is equivalent to specifying @code{-mcpu=ep9312}.
162 Multiple extensions may be specified, separated by a @code{+}. The
163 extensions should be specified in ascending alphabetical order.
165 Some extensions may be restricted to particular architectures; this is
166 documented in the list of extensions below.
168 Extension mnemonics may also be removed from those the assembler accepts.
169 This is done be prepending @code{no} to the option that adds the extension.
170 Extensions that are removed should be listed after all extensions which have
171 been added, again in ascending alphabetical order. For example,
172 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
175 The following extensions are currently supported:
177 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
178 @code{fp} (Floating Point Extensions for v8-A architecture),
179 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
184 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
186 @code{os} (Operating System for v6M architecture),
187 @code{sec} (Security Extensions for v6K and v7-A architectures),
188 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
189 @code{virt} (Virtualization Extensions for v7-A architecture, implies
191 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
192 @code{ras} (Reliability, Availability and Serviceability extensions
193 for v8-A architecture),
194 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
199 @cindex @code{-march=} command line option, ARM
200 @item -march=@var{architecture}[+@var{extension}@dots{}]
201 This option specifies the target architecture. The assembler will issue
202 an error message if an attempt is made to assemble an instruction which
203 will not execute on the target architecture. The following architecture
204 names are recognized:
240 If both @code{-mcpu} and
241 @code{-march} are specified, the assembler will use
242 the setting for @code{-mcpu}.
244 The architecture option can be extended with the same instruction set
245 extension options as the @code{-mcpu} option.
247 @cindex @code{-mfpu=} command line option, ARM
248 @item -mfpu=@var{floating-point-format}
250 This option specifies the floating point format to assemble for. The
251 assembler will issue an error message if an attempt is made to assemble
252 an instruction which will not execute on the target floating point unit.
253 The following format options are recognized:
273 @code{vfpv3-d16-fp16},
288 @code{neon-fp-armv8},
289 @code{crypto-neon-fp-armv8},
290 @code{neon-fp-armv8.1}
292 @code{crypto-neon-fp-armv8.1}.
294 In addition to determining which instructions are assembled, this option
295 also affects the way in which the @code{.double} assembler directive behaves
296 when assembling little-endian code.
298 The default is dependent on the processor selected. For Architecture 5 or
299 later, the default is to assembler for VFP instructions; for earlier
300 architectures the default is to assemble for FPA instructions.
302 @cindex @code{-mthumb} command line option, ARM
304 This option specifies that the assembler should start assembling Thumb
305 instructions; that is, it should behave as though the file starts with a
306 @code{.code 16} directive.
308 @cindex @code{-mthumb-interwork} command line option, ARM
309 @item -mthumb-interwork
310 This option specifies that the output generated by the assembler should
311 be marked as supporting interworking.
313 @cindex @code{-mimplicit-it} command line option, ARM
314 @item -mimplicit-it=never
315 @itemx -mimplicit-it=always
316 @itemx -mimplicit-it=arm
317 @itemx -mimplicit-it=thumb
318 The @code{-mimplicit-it} option controls the behavior of the assembler when
319 conditional instructions are not enclosed in IT blocks.
320 There are four possible behaviors.
321 If @code{never} is specified, such constructs cause a warning in ARM
322 code and an error in Thumb-2 code.
323 If @code{always} is specified, such constructs are accepted in both
324 ARM and Thumb-2 code, where the IT instruction is added implicitly.
325 If @code{arm} is specified, such constructs are accepted in ARM code
326 and cause an error in Thumb-2 code.
327 If @code{thumb} is specified, such constructs cause a warning in ARM
328 code and are accepted in Thumb-2 code. If you omit this option, the
329 behavior is equivalent to @code{-mimplicit-it=arm}.
331 @cindex @code{-mapcs-26} command line option, ARM
332 @cindex @code{-mapcs-32} command line option, ARM
335 These options specify that the output generated by the assembler should
336 be marked as supporting the indicated version of the Arm Procedure.
339 @cindex @code{-matpcs} command line option, ARM
341 This option specifies that the output generated by the assembler should
342 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
343 enabled this option will cause the assembler to create an empty
344 debugging section in the object file called .arm.atpcs. Debuggers can
345 use this to determine the ABI being used by.
347 @cindex @code{-mapcs-float} command line option, ARM
349 This indicates the floating point variant of the APCS should be
350 used. In this variant floating point arguments are passed in FP
351 registers rather than integer registers.
353 @cindex @code{-mapcs-reentrant} command line option, ARM
354 @item -mapcs-reentrant
355 This indicates that the reentrant variant of the APCS should be used.
356 This variant supports position independent code.
358 @cindex @code{-mfloat-abi=} command line option, ARM
359 @item -mfloat-abi=@var{abi}
360 This option specifies that the output generated by the assembler should be
361 marked as using specified floating point ABI.
362 The following values are recognized:
368 @cindex @code{-eabi=} command line option, ARM
369 @item -meabi=@var{ver}
370 This option specifies which EABI version the produced object files should
372 The following values are recognized:
378 @cindex @code{-EB} command line option, ARM
380 This option specifies that the output generated by the assembler should
381 be marked as being encoded for a big-endian processor.
383 Note: If a program is being built for a system with big-endian data
384 and little-endian instructions then it should be assembled with the
385 @option{-EB} option, (all of it, code and data) and then linked with
386 the @option{--be8} option. This will reverse the endianness of the
387 instructions back to little-endian, but leave the data as big-endian.
389 @cindex @code{-EL} command line option, ARM
391 This option specifies that the output generated by the assembler should
392 be marked as being encoded for a little-endian processor.
394 @cindex @code{-k} command line option, ARM
395 @cindex PIC code generation for ARM
397 This option specifies that the output of the assembler should be marked
398 as position-independent code (PIC).
400 @cindex @code{--fix-v4bx} command line option, ARM
402 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
403 the linker option of the same name.
405 @cindex @code{-mwarn-deprecated} command line option, ARM
406 @item -mwarn-deprecated
407 @itemx -mno-warn-deprecated
408 Enable or disable warnings about using deprecated options or
409 features. The default is to warn.
411 @cindex @code{-mccs} command line option, ARM
413 Turns on CodeComposer Studio assembly syntax compatibility mode.
415 @cindex @code{-mwarn-syms} command line option, ARM
417 @itemx -mno-warn-syms
418 Enable or disable warnings about symbols that match the names of ARM
419 instructions. The default is to warn.
427 * ARM-Instruction-Set:: Instruction Set
428 * ARM-Chars:: Special Characters
429 * ARM-Regs:: Register Names
430 * ARM-Relocations:: Relocations
431 * ARM-Neon-Alignment:: NEON Alignment Specifiers
434 @node ARM-Instruction-Set
435 @subsection Instruction Set Syntax
436 Two slightly different syntaxes are support for ARM and THUMB
437 instructions. The default, @code{divided}, uses the old style where
438 ARM and THUMB instructions had their own, separate syntaxes. The new,
439 @code{unified} syntax, which can be selected via the @code{.syntax}
440 directive, and has the following main features:
444 Immediate operands do not require a @code{#} prefix.
447 The @code{IT} instruction may appear, and if it does it is validated
448 against subsequent conditional affixes. In ARM mode it does not
449 generate machine code, in THUMB mode it does.
452 For ARM instructions the conditional affixes always appear at the end
453 of the instruction. For THUMB instructions conditional affixes can be
454 used, but only inside the scope of an @code{IT} instruction.
457 All of the instructions new to the V6T2 architecture (and later) are
458 available. (Only a few such instructions can be written in the
459 @code{divided} syntax).
462 The @code{.N} and @code{.W} suffixes are recognized and honored.
465 All instructions set the flags if and only if they have an @code{s}
470 @subsection Special Characters
472 @cindex line comment character, ARM
473 @cindex ARM line comment character
474 The presence of a @samp{@@} anywhere on a line indicates the start of
475 a comment that extends to the end of that line.
477 If a @samp{#} appears as the first character of a line then the whole
478 line is treated as a comment, but in this case the line could also be
479 a logical line number directive (@pxref{Comments}) or a preprocessor
480 control command (@pxref{Preprocessing}).
482 @cindex line separator, ARM
483 @cindex statement separator, ARM
484 @cindex ARM line separator
485 The @samp{;} character can be used instead of a newline to separate
488 @cindex immediate character, ARM
489 @cindex ARM immediate character
490 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
492 @cindex identifiers, ARM
493 @cindex ARM identifiers
494 *TODO* Explain about /data modifier on symbols.
497 @subsection Register Names
499 @cindex ARM register names
500 @cindex register names, ARM
501 *TODO* Explain about ARM register naming, and the predefined names.
503 @node ARM-Relocations
504 @subsection ARM relocation generation
506 @cindex data relocations, ARM
507 @cindex ARM data relocations
508 Specific data relocations can be generated by putting the relocation name
509 in parentheses after the symbol name. For example:
515 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
517 The following relocations are supported:
533 For compatibility with older toolchains the assembler also accepts
534 @code{(PLT)} after branch targets. On legacy targets this will
535 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
536 targets it will encode either the @samp{R_ARM_CALL} or
537 @samp{R_ARM_JUMP24} relocation, as appropriate.
539 @cindex MOVW and MOVT relocations, ARM
540 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
541 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
542 respectively. For example to load the 32-bit address of foo into r0:
545 MOVW r0, #:lower16:foo
546 MOVT r0, #:upper16:foo
549 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
550 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
551 generated by prefixing the value with @samp{#:lower0_7:#},
552 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
553 respectively. For example to load the 32-bit address of foo into r0:
556 MOVS r0, #:upper8_15:#foo
558 ADDS r0, #:upper0_7:#foo
560 ADDS r0, #:lower8_15:#foo
562 ADDS r0, #:lower0_7:#foo
565 @node ARM-Neon-Alignment
566 @subsection NEON Alignment Specifiers
568 @cindex alignment for NEON instructions
569 Some NEON load/store instructions allow an optional address
571 The ARM documentation specifies that this is indicated by
572 @samp{@@ @var{align}}. However GAS already interprets
573 the @samp{@@} character as a "line comment" start,
574 so @samp{: @var{align}} is used instead. For example:
577 vld1.8 @{q0@}, [r0, :128]
580 @node ARM Floating Point
581 @section Floating Point
583 @cindex floating point, ARM (@sc{ieee})
584 @cindex ARM floating point (@sc{ieee})
585 The ARM family uses @sc{ieee} floating-point numbers.
588 @section ARM Machine Directives
590 @cindex machine directives, ARM
591 @cindex ARM machine directives
594 @c AAAAAAAAAAAAAAAAAAAAAAAAA
596 @cindex @code{.2byte} directive, ARM
597 @cindex @code{.4byte} directive, ARM
598 @cindex @code{.8byte} directive, ARM
599 @item .2byte @var{expression} [, @var{expression}]*
600 @itemx .4byte @var{expression} [, @var{expression}]*
601 @itemx .8byte @var{expression} [, @var{expression}]*
602 These directives write 2, 4 or 8 byte values to the output section.
604 @cindex @code{.align} directive, ARM
605 @item .align @var{expression} [, @var{expression}]
606 This is the generic @var{.align} directive. For the ARM however if the
607 first argument is zero (ie no alignment is needed) the assembler will
608 behave as if the argument had been 2 (ie pad to the next four byte
609 boundary). This is for compatibility with ARM's own assembler.
611 @cindex @code{.arch} directive, ARM
612 @item .arch @var{name}
613 Select the target architecture. Valid values for @var{name} are the same as
614 for the @option{-march} commandline option.
616 Specifying @code{.arch} clears any previously selected architecture
619 @cindex @code{.arch_extension} directive, ARM
620 @item .arch_extension @var{name}
621 Add or remove an architecture extension to the target architecture. Valid
622 values for @var{name} are the same as those accepted as architectural
623 extensions by the @option{-mcpu} commandline option.
625 @code{.arch_extension} may be used multiple times to add or remove extensions
626 incrementally to the architecture being compiled for.
628 @cindex @code{.arm} directive, ARM
630 This performs the same action as @var{.code 32}.
632 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
634 @cindex @code{.bss} directive, ARM
636 This directive switches to the @code{.bss} section.
638 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
640 @cindex @code{.cantunwind} directive, ARM
642 Prevents unwinding through the current function. No personality routine
643 or exception table data is required or permitted.
645 @cindex @code{.code} directive, ARM
646 @item .code @code{[16|32]}
647 This directive selects the instruction set being generated. The value 16
648 selects Thumb, with the value 32 selecting ARM.
650 @cindex @code{.cpu} directive, ARM
651 @item .cpu @var{name}
652 Select the target processor. Valid values for @var{name} are the same as
653 for the @option{-mcpu} commandline option.
655 Specifying @code{.cpu} clears any previously selected architecture
658 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
660 @cindex @code{.dn} and @code{.qn} directives, ARM
661 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
662 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
664 The @code{dn} and @code{qn} directives are used to create typed
665 and/or indexed register aliases for use in Advanced SIMD Extension
666 (Neon) instructions. The former should be used to create aliases
667 of double-precision registers, and the latter to create aliases of
668 quad-precision registers.
670 If these directives are used to create typed aliases, those aliases can
671 be used in Neon instructions instead of writing types after the mnemonic
672 or after each operand. For example:
681 This is equivalent to writing the following:
687 Aliases created using @code{dn} or @code{qn} can be destroyed using
690 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
692 @cindex @code{.eabi_attribute} directive, ARM
693 @item .eabi_attribute @var{tag}, @var{value}
694 Set the EABI object attribute @var{tag} to @var{value}.
696 The @var{tag} is either an attribute number, or one of the following:
697 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
698 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
699 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
700 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
701 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
702 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
703 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
704 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
705 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
706 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
707 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
708 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
709 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
710 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
711 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
712 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
713 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
714 @code{Tag_conformance}, @code{Tag_T2EE_use},
715 @code{Tag_Virtualization_use}
717 The @var{value} is either a @code{number}, @code{"string"}, or
718 @code{number, "string"} depending on the tag.
720 Note - the following legacy values are also accepted by @var{tag}:
721 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
722 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
724 @cindex @code{.even} directive, ARM
726 This directive aligns to an even-numbered address.
728 @cindex @code{.extend} directive, ARM
729 @cindex @code{.ldouble} directive, ARM
730 @item .extend @var{expression} [, @var{expression}]*
731 @itemx .ldouble @var{expression} [, @var{expression}]*
732 These directives write 12byte long double floating-point values to the
733 output section. These are not compatible with current ARM processors
736 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
739 @cindex @code{.fnend} directive, ARM
741 Marks the end of a function with an unwind table entry. The unwind index
742 table entry is created when this directive is processed.
744 If no personality routine has been specified then standard personality
745 routine 0 or 1 will be used, depending on the number of unwind opcodes
749 @cindex @code{.fnstart} directive, ARM
751 Marks the start of a function with an unwind table entry.
753 @cindex @code{.force_thumb} directive, ARM
755 This directive forces the selection of Thumb instructions, even if the
756 target processor does not support those instructions
758 @cindex @code{.fpu} directive, ARM
759 @item .fpu @var{name}
760 Select the floating-point unit to assemble for. Valid values for @var{name}
761 are the same as for the @option{-mfpu} commandline option.
763 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
764 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
766 @cindex @code{.handlerdata} directive, ARM
768 Marks the end of the current function, and the start of the exception table
769 entry for that function. Anything between this directive and the
770 @code{.fnend} directive will be added to the exception table entry.
772 Must be preceded by a @code{.personality} or @code{.personalityindex}
775 @c IIIIIIIIIIIIIIIIIIIIIIIIII
777 @cindex @code{.inst} directive, ARM
778 @item .inst @var{opcode} [ , @dots{} ]
779 @itemx .inst.n @var{opcode} [ , @dots{} ]
780 @itemx .inst.w @var{opcode} [ , @dots{} ]
781 Generates the instruction corresponding to the numerical value @var{opcode}.
782 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
783 specified explicitly, overriding the normal encoding rules.
785 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
786 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
787 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
789 @item .ldouble @var{expression} [, @var{expression}]*
792 @cindex @code{.ltorg} directive, ARM
794 This directive causes the current contents of the literal pool to be
795 dumped into the current section (which is assumed to be the .text
796 section) at the current location (aligned to a word boundary).
797 @code{GAS} maintains a separate literal pool for each section and each
798 sub-section. The @code{.ltorg} directive will only affect the literal
799 pool of the current section and sub-section. At the end of assembly
800 all remaining, un-empty literal pools will automatically be dumped.
802 Note - older versions of @code{GAS} would dump the current literal
803 pool any time a section change occurred. This is no longer done, since
804 it prevents accurate control of the placement of literal pools.
806 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
808 @cindex @code{.movsp} directive, ARM
809 @item .movsp @var{reg} [, #@var{offset}]
810 Tell the unwinder that @var{reg} contains an offset from the current
811 stack pointer. If @var{offset} is not specified then it is assumed to be
814 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
815 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
817 @cindex @code{.object_arch} directive, ARM
818 @item .object_arch @var{name}
819 Override the architecture recorded in the EABI object attribute section.
820 Valid values for @var{name} are the same as for the @code{.arch} directive.
821 Typically this is useful when code uses runtime detection of CPU features.
823 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
825 @cindex @code{.packed} directive, ARM
826 @item .packed @var{expression} [, @var{expression}]*
827 This directive writes 12-byte packed floating-point values to the
828 output section. These are not compatible with current ARM processors
832 @cindex @code{.pad} directive, ARM
833 @item .pad #@var{count}
834 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
835 A positive value indicates the function prologue allocated stack space by
836 decrementing the stack pointer.
838 @cindex @code{.personality} directive, ARM
839 @item .personality @var{name}
840 Sets the personality routine for the current function to @var{name}.
842 @cindex @code{.personalityindex} directive, ARM
843 @item .personalityindex @var{index}
844 Sets the personality routine for the current function to the EABI standard
845 routine number @var{index}
847 @cindex @code{.pool} directive, ARM
849 This is a synonym for .ltorg.
851 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
852 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
854 @cindex @code{.req} directive, ARM
855 @item @var{name} .req @var{register name}
856 This creates an alias for @var{register name} called @var{name}. For
863 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
866 @cindex @code{.save} directive, ARM
867 @item .save @var{reglist}
868 Generate unwinder annotations to restore the registers in @var{reglist}.
869 The format of @var{reglist} is the same as the corresponding store-multiple
873 @exdent @emph{core registers}
874 .save @{r4, r5, r6, lr@}
875 stmfd sp!, @{r4, r5, r6, lr@}
876 @exdent @emph{FPA registers}
879 @exdent @emph{VFP registers}
880 .save @{d8, d9, d10@}
881 fstmdx sp!, @{d8, d9, d10@}
882 @exdent @emph{iWMMXt registers}
884 wstrd wr11, [sp, #-8]!
885 wstrd wr10, [sp, #-8]!
888 wstrd wr11, [sp, #-8]!
890 wstrd wr10, [sp, #-8]!
894 @cindex @code{.setfp} directive, ARM
895 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
896 Make all unwinder annotations relative to a frame pointer. Without this
897 the unwinder will use offsets from the stack pointer.
899 The syntax of this directive is the same as the @code{add} or @code{mov}
900 instruction used to set the frame pointer. @var{spreg} must be either
901 @code{sp} or mentioned in a previous @code{.movsp} directive.
911 @cindex @code{.secrel32} directive, ARM
912 @item .secrel32 @var{expression} [, @var{expression}]*
913 This directive emits relocations that evaluate to the section-relative
914 offset of each expression's symbol. This directive is only supported
917 @cindex @code{.syntax} directive, ARM
918 @item .syntax [@code{unified} | @code{divided}]
919 This directive sets the Instruction Set Syntax as described in the
920 @ref{ARM-Instruction-Set} section.
922 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
924 @cindex @code{.thumb} directive, ARM
926 This performs the same action as @var{.code 16}.
928 @cindex @code{.thumb_func} directive, ARM
930 This directive specifies that the following symbol is the name of a
931 Thumb encoded function. This information is necessary in order to allow
932 the assembler and linker to generate correct code for interworking
933 between Arm and Thumb instructions and should be used even if
934 interworking is not going to be performed. The presence of this
935 directive also implies @code{.thumb}
937 This directive is not neccessary when generating EABI objects. On these
938 targets the encoding is implicit when generating Thumb code.
940 @cindex @code{.thumb_set} directive, ARM
942 This performs the equivalent of a @code{.set} directive in that it
943 creates a symbol which is an alias for another symbol (possibly not yet
944 defined). This directive also has the added property in that it marks
945 the aliased symbol as being a thumb function entry point, in the same
946 way that the @code{.thumb_func} directive does.
948 @cindex @code{.tlsdescseq} directive, ARM
949 @item .tlsdescseq @var{tls-variable}
950 This directive is used to annotate parts of an inlined TLS descriptor
951 trampoline. Normally the trampoline is provided by the linker, and
952 this directive is not needed.
954 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
956 @cindex @code{.unreq} directive, ARM
957 @item .unreq @var{alias-name}
958 This undefines a register alias which was previously defined using the
959 @code{req}, @code{dn} or @code{qn} directives. For example:
966 An error occurs if the name is undefined. Note - this pseudo op can
967 be used to delete builtin in register name aliases (eg 'r0'). This
968 should only be done if it is really necessary.
970 @cindex @code{.unwind_raw} directive, ARM
971 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
972 Insert one of more arbitary unwind opcode bytes, which are known to adjust
973 the stack pointer by @var{offset} bytes.
975 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
978 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
980 @cindex @code{.vsave} directive, ARM
981 @item .vsave @var{vfp-reglist}
982 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
983 using FLDMD. Also works for VFPv3 registers
984 that are to be restored using VLDM.
985 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
989 @exdent @emph{VFP registers}
990 .vsave @{d8, d9, d10@}
991 fstmdd sp!, @{d8, d9, d10@}
992 @exdent @emph{VFPv3 registers}
993 .vsave @{d15, d16, d17@}
994 vstm sp!, @{d15, d16, d17@}
997 Since FLDMX and FSTMX are now deprecated, this directive should be
998 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1000 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1001 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1002 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1003 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1011 @cindex opcodes for ARM
1012 @code{@value{AS}} implements all the standard ARM opcodes. It also
1013 implements several pseudo opcodes, including several synthetic load
1018 @cindex @code{NOP} pseudo op, ARM
1024 This pseudo op will always evaluate to a legal ARM instruction that does
1025 nothing. Currently it will evaluate to MOV r0, r0.
1027 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1030 ldr <register> , = <expression>
1033 If expression evaluates to a numeric constant then a MOV or MVN
1034 instruction will be used in place of the LDR instruction, if the
1035 constant can be generated by either of these instructions. Otherwise
1036 the constant will be placed into the nearest literal pool (if it not
1037 already there) and a PC relative LDR instruction will be generated.
1039 @cindex @code{ADR reg,<label>} pseudo op, ARM
1042 adr <register> <label>
1045 This instruction will load the address of @var{label} into the indicated
1046 register. The instruction will evaluate to a PC relative ADD or SUB
1047 instruction depending upon where the label is located. If the label is
1048 out of range, or if it is not defined in the same file (and section) as
1049 the ADR instruction, then an error will be generated. This instruction
1050 will not make use of the literal pool.
1052 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1055 adrl <register> <label>
1058 This instruction will load the address of @var{label} into the indicated
1059 register. The instruction will evaluate to one or two PC relative ADD
1060 or SUB instructions depending upon where the label is located. If a
1061 second instruction is not needed a NOP instruction will be generated in
1062 its place, so that this instruction is always 8 bytes long.
1064 If the label is out of range, or if it is not defined in the same file
1065 (and section) as the ADRL instruction, then an error will be generated.
1066 This instruction will not make use of the literal pool.
1070 For information on the ARM or Thumb instruction sets, see @cite{ARM
1071 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1074 @node ARM Mapping Symbols
1075 @section Mapping Symbols
1077 The ARM ELF specification requires that special symbols be inserted
1078 into object files to mark certain features:
1084 At the start of a region of code containing ARM instructions.
1088 At the start of a region of code containing THUMB instructions.
1092 At the start of a region of data.
1096 The assembler will automatically insert these symbols for you - there
1097 is no need to code them yourself. Support for tagging symbols ($b,
1098 $f, $p and $m) which is also mentioned in the current ARM ELF
1099 specification is not implemented. This is because they have been
1100 dropped from the new EABI and so tools cannot rely upon their
1103 @node ARM Unwinding Tutorial
1106 The ABI for the ARM Architecture specifies a standard format for
1107 exception unwind information. This information is used when an
1108 exception is thrown to determine where control should be transferred.
1109 In particular, the unwind information is used to determine which
1110 function called the function that threw the exception, and which
1111 function called that one, and so forth. This information is also used
1112 to restore the values of callee-saved registers in the function
1113 catching the exception.
1115 If you are writing functions in assembly code, and those functions
1116 call other functions that throw exceptions, you must use assembly
1117 pseudo ops to ensure that appropriate exception unwind information is
1118 generated. Otherwise, if one of the functions called by your assembly
1119 code throws an exception, the run-time library will be unable to
1120 unwind the stack through your assembly code and your program will not
1123 To illustrate the use of these pseudo ops, we will examine the code
1124 that G++ generates for the following C++ input:
1127 void callee (int *);
1138 This example does not show how to throw or catch an exception from
1139 assembly code. That is a much more complex operation and should
1140 always be done in a high-level language, such as C++, that directly
1141 supports exceptions.
1143 The code generated by one particular version of G++ when compiling the
1150 @ Function supports interworking.
1151 @ args = 0, pretend = 0, frame = 8
1152 @ frame_needed = 1, uses_anonymous_args = 0
1174 Of course, the sequence of instructions varies based on the options
1175 you pass to GCC and on the version of GCC in use. The exact
1176 instructions are not important since we are focusing on the pseudo ops
1177 that are used to generate unwind information.
1179 An important assumption made by the unwinder is that the stack frame
1180 does not change during the body of the function. In particular, since
1181 we assume that the assembly code does not itself throw an exception,
1182 the only point where an exception can be thrown is from a call, such
1183 as the @code{bl} instruction above. At each call site, the same saved
1184 registers (including @code{lr}, which indicates the return address)
1185 must be located in the same locations relative to the frame pointer.
1187 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1188 op appears immediately before the first instruction of the function
1189 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1190 op appears immediately after the last instruction of the function.
1191 These pseudo ops specify the range of the function.
1193 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1194 @code{.pad}) matters; their exact locations are irrelevant. In the
1195 example above, the compiler emits the pseudo ops with particular
1196 instructions. That makes it easier to understand the code, but it is
1197 not required for correctness. It would work just as well to emit all
1198 of the pseudo ops other than @code{.fnend} in the same order, but
1199 immediately after @code{.fnstart}.
1201 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1202 indicates registers that have been saved to the stack so that they can
1203 be restored before the function returns. The argument to the
1204 @code{.save} pseudo op is a list of registers to save. If a register
1205 is ``callee-saved'' (as specified by the ABI) and is modified by the
1206 function you are writing, then your code must save the value before it
1207 is modified and restore the original value before the function
1208 returns. If an exception is thrown, the run-time library restores the
1209 values of these registers from their locations on the stack before
1210 returning control to the exception handler. (Of course, if an
1211 exception is not thrown, the function that contains the @code{.save}
1212 pseudo op restores these registers in the function epilogue, as is
1213 done with the @code{ldmfd} instruction above.)
1215 You do not have to save callee-saved registers at the very beginning
1216 of the function and you do not need to use the @code{.save} pseudo op
1217 immediately following the point at which the registers are saved.
1218 However, if you modify a callee-saved register, you must save it on
1219 the stack before modifying it and before calling any functions which
1220 might throw an exception. And, you must use the @code{.save} pseudo
1221 op to indicate that you have done so.
1223 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1224 modification of the stack pointer that does not save any registers.
1225 The argument is the number of bytes (in decimal) that are subtracted
1226 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1227 subtracting from the stack pointer increases the size of the stack.)
1229 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1230 indicates the register that contains the frame pointer. The first
1231 argument is the register that is set, which is typically @code{fp}.
1232 The second argument indicates the register from which the frame
1233 pointer takes its value. The third argument, if present, is the value
1234 (in decimal) added to the register specified by the second argument to
1235 compute the value of the frame pointer. You should not modify the
1236 frame pointer in the body of the function.
1238 If you do not use a frame pointer, then you should not use the
1239 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1240 should avoid modifying the stack pointer outside of the function
1241 prologue. Otherwise, the run-time library will be unable to find
1242 saved registers when it is unwinding the stack.
1244 The pseudo ops described above are sufficient for writing assembly
1245 code that calls functions which may throw exceptions. If you need to
1246 know more about the object-file format used to represent unwind
1247 information, you may consult the @cite{Exception Handling ABI for the
1248 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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