1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
144 @code{cortex-m0plus},
147 @code{marvell-whitney},
150 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
151 @code{i80200} (Intel XScale processor)
152 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
155 The special name @code{all} may be used to allow the
156 assembler to accept instructions valid for any ARM processor.
158 In addition to the basic instruction set, the assembler can be told to
159 accept various extension mnemonics that extend the processor using the
160 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
161 is equivalent to specifying @code{-mcpu=ep9312}.
163 Multiple extensions may be specified, separated by a @code{+}. The
164 extensions should be specified in ascending alphabetical order.
166 Some extensions may be restricted to particular architectures; this is
167 documented in the list of extensions below.
169 Extension mnemonics may also be removed from those the assembler accepts.
170 This is done be prepending @code{no} to the option that adds the extension.
171 Extensions that are removed should be listed after all extensions which have
172 been added, again in ascending alphabetical order. For example,
173 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
176 The following extensions are currently supported:
178 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
179 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
180 @code{fp} (Floating Point Extensions for v8-A architecture),
181 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
186 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
188 @code{os} (Operating System for v6M architecture),
189 @code{sec} (Security Extensions for v6K and v7-A architectures),
190 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
191 @code{virt} (Virtualization Extensions for v7-A architecture, implies
193 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
194 @code{ras} (Reliability, Availability and Serviceability extensions
195 for v8-A architecture),
196 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
201 @cindex @code{-march=} command line option, ARM
202 @item -march=@var{architecture}[+@var{extension}@dots{}]
203 This option specifies the target architecture. The assembler will issue
204 an error message if an attempt is made to assemble an instruction which
205 will not execute on the target architecture. The following architecture
206 names are recognized:
245 If both @code{-mcpu} and
246 @code{-march} are specified, the assembler will use
247 the setting for @code{-mcpu}.
249 The architecture option can be extended with the same instruction set
250 extension options as the @code{-mcpu} option.
252 @cindex @code{-mfpu=} command line option, ARM
253 @item -mfpu=@var{floating-point-format}
255 This option specifies the floating point format to assemble for. The
256 assembler will issue an error message if an attempt is made to assemble
257 an instruction which will not execute on the target floating point unit.
258 The following format options are recognized:
278 @code{vfpv3-d16-fp16},
295 @code{neon-fp-armv8},
296 @code{crypto-neon-fp-armv8},
297 @code{neon-fp-armv8.1}
299 @code{crypto-neon-fp-armv8.1}.
301 In addition to determining which instructions are assembled, this option
302 also affects the way in which the @code{.double} assembler directive behaves
303 when assembling little-endian code.
305 The default is dependent on the processor selected. For Architecture 5 or
306 later, the default is to assemble for VFP instructions; for earlier
307 architectures the default is to assemble for FPA instructions.
309 @cindex @code{-mthumb} command line option, ARM
311 This option specifies that the assembler should start assembling Thumb
312 instructions; that is, it should behave as though the file starts with a
313 @code{.code 16} directive.
315 @cindex @code{-mthumb-interwork} command line option, ARM
316 @item -mthumb-interwork
317 This option specifies that the output generated by the assembler should
318 be marked as supporting interworking.
320 @cindex @code{-mimplicit-it} command line option, ARM
321 @item -mimplicit-it=never
322 @itemx -mimplicit-it=always
323 @itemx -mimplicit-it=arm
324 @itemx -mimplicit-it=thumb
325 The @code{-mimplicit-it} option controls the behavior of the assembler when
326 conditional instructions are not enclosed in IT blocks.
327 There are four possible behaviors.
328 If @code{never} is specified, such constructs cause a warning in ARM
329 code and an error in Thumb-2 code.
330 If @code{always} is specified, such constructs are accepted in both
331 ARM and Thumb-2 code, where the IT instruction is added implicitly.
332 If @code{arm} is specified, such constructs are accepted in ARM code
333 and cause an error in Thumb-2 code.
334 If @code{thumb} is specified, such constructs cause a warning in ARM
335 code and are accepted in Thumb-2 code. If you omit this option, the
336 behavior is equivalent to @code{-mimplicit-it=arm}.
338 @cindex @code{-mapcs-26} command line option, ARM
339 @cindex @code{-mapcs-32} command line option, ARM
342 These options specify that the output generated by the assembler should
343 be marked as supporting the indicated version of the Arm Procedure.
346 @cindex @code{-matpcs} command line option, ARM
348 This option specifies that the output generated by the assembler should
349 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
350 enabled this option will cause the assembler to create an empty
351 debugging section in the object file called .arm.atpcs. Debuggers can
352 use this to determine the ABI being used by.
354 @cindex @code{-mapcs-float} command line option, ARM
356 This indicates the floating point variant of the APCS should be
357 used. In this variant floating point arguments are passed in FP
358 registers rather than integer registers.
360 @cindex @code{-mapcs-reentrant} command line option, ARM
361 @item -mapcs-reentrant
362 This indicates that the reentrant variant of the APCS should be used.
363 This variant supports position independent code.
365 @cindex @code{-mfloat-abi=} command line option, ARM
366 @item -mfloat-abi=@var{abi}
367 This option specifies that the output generated by the assembler should be
368 marked as using specified floating point ABI.
369 The following values are recognized:
375 @cindex @code{-eabi=} command line option, ARM
376 @item -meabi=@var{ver}
377 This option specifies which EABI version the produced object files should
379 The following values are recognized:
385 @cindex @code{-EB} command line option, ARM
387 This option specifies that the output generated by the assembler should
388 be marked as being encoded for a big-endian processor.
390 Note: If a program is being built for a system with big-endian data
391 and little-endian instructions then it should be assembled with the
392 @option{-EB} option, (all of it, code and data) and then linked with
393 the @option{--be8} option. This will reverse the endianness of the
394 instructions back to little-endian, but leave the data as big-endian.
396 @cindex @code{-EL} command line option, ARM
398 This option specifies that the output generated by the assembler should
399 be marked as being encoded for a little-endian processor.
401 @cindex @code{-k} command line option, ARM
402 @cindex PIC code generation for ARM
404 This option specifies that the output of the assembler should be marked
405 as position-independent code (PIC).
407 @cindex @code{--fix-v4bx} command line option, ARM
409 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
410 the linker option of the same name.
412 @cindex @code{-mwarn-deprecated} command line option, ARM
413 @item -mwarn-deprecated
414 @itemx -mno-warn-deprecated
415 Enable or disable warnings about using deprecated options or
416 features. The default is to warn.
418 @cindex @code{-mccs} command line option, ARM
420 Turns on CodeComposer Studio assembly syntax compatibility mode.
422 @cindex @code{-mwarn-syms} command line option, ARM
424 @itemx -mno-warn-syms
425 Enable or disable warnings about symbols that match the names of ARM
426 instructions. The default is to warn.
434 * ARM-Instruction-Set:: Instruction Set
435 * ARM-Chars:: Special Characters
436 * ARM-Regs:: Register Names
437 * ARM-Relocations:: Relocations
438 * ARM-Neon-Alignment:: NEON Alignment Specifiers
441 @node ARM-Instruction-Set
442 @subsection Instruction Set Syntax
443 Two slightly different syntaxes are support for ARM and THUMB
444 instructions. The default, @code{divided}, uses the old style where
445 ARM and THUMB instructions had their own, separate syntaxes. The new,
446 @code{unified} syntax, which can be selected via the @code{.syntax}
447 directive, and has the following main features:
451 Immediate operands do not require a @code{#} prefix.
454 The @code{IT} instruction may appear, and if it does it is validated
455 against subsequent conditional affixes. In ARM mode it does not
456 generate machine code, in THUMB mode it does.
459 For ARM instructions the conditional affixes always appear at the end
460 of the instruction. For THUMB instructions conditional affixes can be
461 used, but only inside the scope of an @code{IT} instruction.
464 All of the instructions new to the V6T2 architecture (and later) are
465 available. (Only a few such instructions can be written in the
466 @code{divided} syntax).
469 The @code{.N} and @code{.W} suffixes are recognized and honored.
472 All instructions set the flags if and only if they have an @code{s}
477 @subsection Special Characters
479 @cindex line comment character, ARM
480 @cindex ARM line comment character
481 The presence of a @samp{@@} anywhere on a line indicates the start of
482 a comment that extends to the end of that line.
484 If a @samp{#} appears as the first character of a line then the whole
485 line is treated as a comment, but in this case the line could also be
486 a logical line number directive (@pxref{Comments}) or a preprocessor
487 control command (@pxref{Preprocessing}).
489 @cindex line separator, ARM
490 @cindex statement separator, ARM
491 @cindex ARM line separator
492 The @samp{;} character can be used instead of a newline to separate
495 @cindex immediate character, ARM
496 @cindex ARM immediate character
497 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
499 @cindex identifiers, ARM
500 @cindex ARM identifiers
501 *TODO* Explain about /data modifier on symbols.
504 @subsection Register Names
506 @cindex ARM register names
507 @cindex register names, ARM
508 *TODO* Explain about ARM register naming, and the predefined names.
510 @node ARM-Relocations
511 @subsection ARM relocation generation
513 @cindex data relocations, ARM
514 @cindex ARM data relocations
515 Specific data relocations can be generated by putting the relocation name
516 in parentheses after the symbol name. For example:
522 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
524 The following relocations are supported:
540 For compatibility with older toolchains the assembler also accepts
541 @code{(PLT)} after branch targets. On legacy targets this will
542 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
543 targets it will encode either the @samp{R_ARM_CALL} or
544 @samp{R_ARM_JUMP24} relocation, as appropriate.
546 @cindex MOVW and MOVT relocations, ARM
547 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
548 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
549 respectively. For example to load the 32-bit address of foo into r0:
552 MOVW r0, #:lower16:foo
553 MOVT r0, #:upper16:foo
556 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
557 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
558 generated by prefixing the value with @samp{#:lower0_7:#},
559 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
560 respectively. For example to load the 32-bit address of foo into r0:
563 MOVS r0, #:upper8_15:#foo
565 ADDS r0, #:upper0_7:#foo
567 ADDS r0, #:lower8_15:#foo
569 ADDS r0, #:lower0_7:#foo
572 @node ARM-Neon-Alignment
573 @subsection NEON Alignment Specifiers
575 @cindex alignment for NEON instructions
576 Some NEON load/store instructions allow an optional address
578 The ARM documentation specifies that this is indicated by
579 @samp{@@ @var{align}}. However GAS already interprets
580 the @samp{@@} character as a "line comment" start,
581 so @samp{: @var{align}} is used instead. For example:
584 vld1.8 @{q0@}, [r0, :128]
587 @node ARM Floating Point
588 @section Floating Point
590 @cindex floating point, ARM (@sc{ieee})
591 @cindex ARM floating point (@sc{ieee})
592 The ARM family uses @sc{ieee} floating-point numbers.
595 @section ARM Machine Directives
597 @cindex machine directives, ARM
598 @cindex ARM machine directives
601 @c AAAAAAAAAAAAAAAAAAAAAAAAA
604 @cindex @code{.2byte} directive, ARM
605 @cindex @code{.4byte} directive, ARM
606 @cindex @code{.8byte} directive, ARM
607 @item .2byte @var{expression} [, @var{expression}]*
608 @itemx .4byte @var{expression} [, @var{expression}]*
609 @itemx .8byte @var{expression} [, @var{expression}]*
610 These directives write 2, 4 or 8 byte values to the output section.
613 @cindex @code{.align} directive, ARM
614 @item .align @var{expression} [, @var{expression}]
615 This is the generic @var{.align} directive. For the ARM however if the
616 first argument is zero (ie no alignment is needed) the assembler will
617 behave as if the argument had been 2 (ie pad to the next four byte
618 boundary). This is for compatibility with ARM's own assembler.
620 @cindex @code{.arch} directive, ARM
621 @item .arch @var{name}
622 Select the target architecture. Valid values for @var{name} are the same as
623 for the @option{-march} commandline option.
625 Specifying @code{.arch} clears any previously selected architecture
628 @cindex @code{.arch_extension} directive, ARM
629 @item .arch_extension @var{name}
630 Add or remove an architecture extension to the target architecture. Valid
631 values for @var{name} are the same as those accepted as architectural
632 extensions by the @option{-mcpu} commandline option.
634 @code{.arch_extension} may be used multiple times to add or remove extensions
635 incrementally to the architecture being compiled for.
637 @cindex @code{.arm} directive, ARM
639 This performs the same action as @var{.code 32}.
641 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
643 @cindex @code{.bss} directive, ARM
645 This directive switches to the @code{.bss} section.
647 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
649 @cindex @code{.cantunwind} directive, ARM
651 Prevents unwinding through the current function. No personality routine
652 or exception table data is required or permitted.
654 @cindex @code{.code} directive, ARM
655 @item .code @code{[16|32]}
656 This directive selects the instruction set being generated. The value 16
657 selects Thumb, with the value 32 selecting ARM.
659 @cindex @code{.cpu} directive, ARM
660 @item .cpu @var{name}
661 Select the target processor. Valid values for @var{name} are the same as
662 for the @option{-mcpu} commandline option.
664 Specifying @code{.cpu} clears any previously selected architecture
667 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
669 @cindex @code{.dn} and @code{.qn} directives, ARM
670 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
671 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
673 The @code{dn} and @code{qn} directives are used to create typed
674 and/or indexed register aliases for use in Advanced SIMD Extension
675 (Neon) instructions. The former should be used to create aliases
676 of double-precision registers, and the latter to create aliases of
677 quad-precision registers.
679 If these directives are used to create typed aliases, those aliases can
680 be used in Neon instructions instead of writing types after the mnemonic
681 or after each operand. For example:
690 This is equivalent to writing the following:
696 Aliases created using @code{dn} or @code{qn} can be destroyed using
699 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
701 @cindex @code{.eabi_attribute} directive, ARM
702 @item .eabi_attribute @var{tag}, @var{value}
703 Set the EABI object attribute @var{tag} to @var{value}.
705 The @var{tag} is either an attribute number, or one of the following:
706 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
707 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
708 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
709 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
710 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
711 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
712 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
713 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
714 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
715 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
716 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
717 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
718 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
719 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
720 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
721 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
722 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
723 @code{Tag_conformance}, @code{Tag_T2EE_use},
724 @code{Tag_Virtualization_use}
726 The @var{value} is either a @code{number}, @code{"string"}, or
727 @code{number, "string"} depending on the tag.
729 Note - the following legacy values are also accepted by @var{tag}:
730 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
731 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
733 @cindex @code{.even} directive, ARM
735 This directive aligns to an even-numbered address.
737 @cindex @code{.extend} directive, ARM
738 @cindex @code{.ldouble} directive, ARM
739 @item .extend @var{expression} [, @var{expression}]*
740 @itemx .ldouble @var{expression} [, @var{expression}]*
741 These directives write 12byte long double floating-point values to the
742 output section. These are not compatible with current ARM processors
745 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
748 @cindex @code{.fnend} directive, ARM
750 Marks the end of a function with an unwind table entry. The unwind index
751 table entry is created when this directive is processed.
753 If no personality routine has been specified then standard personality
754 routine 0 or 1 will be used, depending on the number of unwind opcodes
758 @cindex @code{.fnstart} directive, ARM
760 Marks the start of a function with an unwind table entry.
762 @cindex @code{.force_thumb} directive, ARM
764 This directive forces the selection of Thumb instructions, even if the
765 target processor does not support those instructions
767 @cindex @code{.fpu} directive, ARM
768 @item .fpu @var{name}
769 Select the floating-point unit to assemble for. Valid values for @var{name}
770 are the same as for the @option{-mfpu} commandline option.
772 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
773 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
775 @cindex @code{.handlerdata} directive, ARM
777 Marks the end of the current function, and the start of the exception table
778 entry for that function. Anything between this directive and the
779 @code{.fnend} directive will be added to the exception table entry.
781 Must be preceded by a @code{.personality} or @code{.personalityindex}
784 @c IIIIIIIIIIIIIIIIIIIIIIIIII
786 @cindex @code{.inst} directive, ARM
787 @item .inst @var{opcode} [ , @dots{} ]
788 @itemx .inst.n @var{opcode} [ , @dots{} ]
789 @itemx .inst.w @var{opcode} [ , @dots{} ]
790 Generates the instruction corresponding to the numerical value @var{opcode}.
791 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
792 specified explicitly, overriding the normal encoding rules.
794 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
795 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
796 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
798 @item .ldouble @var{expression} [, @var{expression}]*
801 @cindex @code{.ltorg} directive, ARM
803 This directive causes the current contents of the literal pool to be
804 dumped into the current section (which is assumed to be the .text
805 section) at the current location (aligned to a word boundary).
806 @code{GAS} maintains a separate literal pool for each section and each
807 sub-section. The @code{.ltorg} directive will only affect the literal
808 pool of the current section and sub-section. At the end of assembly
809 all remaining, un-empty literal pools will automatically be dumped.
811 Note - older versions of @code{GAS} would dump the current literal
812 pool any time a section change occurred. This is no longer done, since
813 it prevents accurate control of the placement of literal pools.
815 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
817 @cindex @code{.movsp} directive, ARM
818 @item .movsp @var{reg} [, #@var{offset}]
819 Tell the unwinder that @var{reg} contains an offset from the current
820 stack pointer. If @var{offset} is not specified then it is assumed to be
823 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
824 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
826 @cindex @code{.object_arch} directive, ARM
827 @item .object_arch @var{name}
828 Override the architecture recorded in the EABI object attribute section.
829 Valid values for @var{name} are the same as for the @code{.arch} directive.
830 Typically this is useful when code uses runtime detection of CPU features.
832 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
834 @cindex @code{.packed} directive, ARM
835 @item .packed @var{expression} [, @var{expression}]*
836 This directive writes 12-byte packed floating-point values to the
837 output section. These are not compatible with current ARM processors
841 @cindex @code{.pad} directive, ARM
842 @item .pad #@var{count}
843 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
844 A positive value indicates the function prologue allocated stack space by
845 decrementing the stack pointer.
847 @cindex @code{.personality} directive, ARM
848 @item .personality @var{name}
849 Sets the personality routine for the current function to @var{name}.
851 @cindex @code{.personalityindex} directive, ARM
852 @item .personalityindex @var{index}
853 Sets the personality routine for the current function to the EABI standard
854 routine number @var{index}
856 @cindex @code{.pool} directive, ARM
858 This is a synonym for .ltorg.
860 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
861 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
863 @cindex @code{.req} directive, ARM
864 @item @var{name} .req @var{register name}
865 This creates an alias for @var{register name} called @var{name}. For
872 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
875 @cindex @code{.save} directive, ARM
876 @item .save @var{reglist}
877 Generate unwinder annotations to restore the registers in @var{reglist}.
878 The format of @var{reglist} is the same as the corresponding store-multiple
882 @exdent @emph{core registers}
883 .save @{r4, r5, r6, lr@}
884 stmfd sp!, @{r4, r5, r6, lr@}
885 @exdent @emph{FPA registers}
888 @exdent @emph{VFP registers}
889 .save @{d8, d9, d10@}
890 fstmdx sp!, @{d8, d9, d10@}
891 @exdent @emph{iWMMXt registers}
893 wstrd wr11, [sp, #-8]!
894 wstrd wr10, [sp, #-8]!
897 wstrd wr11, [sp, #-8]!
899 wstrd wr10, [sp, #-8]!
903 @cindex @code{.setfp} directive, ARM
904 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
905 Make all unwinder annotations relative to a frame pointer. Without this
906 the unwinder will use offsets from the stack pointer.
908 The syntax of this directive is the same as the @code{add} or @code{mov}
909 instruction used to set the frame pointer. @var{spreg} must be either
910 @code{sp} or mentioned in a previous @code{.movsp} directive.
920 @cindex @code{.secrel32} directive, ARM
921 @item .secrel32 @var{expression} [, @var{expression}]*
922 This directive emits relocations that evaluate to the section-relative
923 offset of each expression's symbol. This directive is only supported
926 @cindex @code{.syntax} directive, ARM
927 @item .syntax [@code{unified} | @code{divided}]
928 This directive sets the Instruction Set Syntax as described in the
929 @ref{ARM-Instruction-Set} section.
931 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
933 @cindex @code{.thumb} directive, ARM
935 This performs the same action as @var{.code 16}.
937 @cindex @code{.thumb_func} directive, ARM
939 This directive specifies that the following symbol is the name of a
940 Thumb encoded function. This information is necessary in order to allow
941 the assembler and linker to generate correct code for interworking
942 between Arm and Thumb instructions and should be used even if
943 interworking is not going to be performed. The presence of this
944 directive also implies @code{.thumb}
946 This directive is not necessary when generating EABI objects. On these
947 targets the encoding is implicit when generating Thumb code.
949 @cindex @code{.thumb_set} directive, ARM
951 This performs the equivalent of a @code{.set} directive in that it
952 creates a symbol which is an alias for another symbol (possibly not yet
953 defined). This directive also has the added property in that it marks
954 the aliased symbol as being a thumb function entry point, in the same
955 way that the @code{.thumb_func} directive does.
957 @cindex @code{.tlsdescseq} directive, ARM
958 @item .tlsdescseq @var{tls-variable}
959 This directive is used to annotate parts of an inlined TLS descriptor
960 trampoline. Normally the trampoline is provided by the linker, and
961 this directive is not needed.
963 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
965 @cindex @code{.unreq} directive, ARM
966 @item .unreq @var{alias-name}
967 This undefines a register alias which was previously defined using the
968 @code{req}, @code{dn} or @code{qn} directives. For example:
975 An error occurs if the name is undefined. Note - this pseudo op can
976 be used to delete builtin in register name aliases (eg 'r0'). This
977 should only be done if it is really necessary.
979 @cindex @code{.unwind_raw} directive, ARM
980 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
981 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
982 the stack pointer by @var{offset} bytes.
984 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
987 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
989 @cindex @code{.vsave} directive, ARM
990 @item .vsave @var{vfp-reglist}
991 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
992 using FLDMD. Also works for VFPv3 registers
993 that are to be restored using VLDM.
994 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
998 @exdent @emph{VFP registers}
999 .vsave @{d8, d9, d10@}
1000 fstmdd sp!, @{d8, d9, d10@}
1001 @exdent @emph{VFPv3 registers}
1002 .vsave @{d15, d16, d17@}
1003 vstm sp!, @{d15, d16, d17@}
1006 Since FLDMX and FSTMX are now deprecated, this directive should be
1007 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1009 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1010 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1011 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1012 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1020 @cindex opcodes for ARM
1021 @code{@value{AS}} implements all the standard ARM opcodes. It also
1022 implements several pseudo opcodes, including several synthetic load
1027 @cindex @code{NOP} pseudo op, ARM
1033 This pseudo op will always evaluate to a legal ARM instruction that does
1034 nothing. Currently it will evaluate to MOV r0, r0.
1036 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1039 ldr <register> , = <expression>
1042 If expression evaluates to a numeric constant then a MOV or MVN
1043 instruction will be used in place of the LDR instruction, if the
1044 constant can be generated by either of these instructions. Otherwise
1045 the constant will be placed into the nearest literal pool (if it not
1046 already there) and a PC relative LDR instruction will be generated.
1048 @cindex @code{ADR reg,<label>} pseudo op, ARM
1051 adr <register> <label>
1054 This instruction will load the address of @var{label} into the indicated
1055 register. The instruction will evaluate to a PC relative ADD or SUB
1056 instruction depending upon where the label is located. If the label is
1057 out of range, or if it is not defined in the same file (and section) as
1058 the ADR instruction, then an error will be generated. This instruction
1059 will not make use of the literal pool.
1061 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1064 adrl <register> <label>
1067 This instruction will load the address of @var{label} into the indicated
1068 register. The instruction will evaluate to one or two PC relative ADD
1069 or SUB instructions depending upon where the label is located. If a
1070 second instruction is not needed a NOP instruction will be generated in
1071 its place, so that this instruction is always 8 bytes long.
1073 If the label is out of range, or if it is not defined in the same file
1074 (and section) as the ADRL instruction, then an error will be generated.
1075 This instruction will not make use of the literal pool.
1079 For information on the ARM or Thumb instruction sets, see @cite{ARM
1080 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1083 @node ARM Mapping Symbols
1084 @section Mapping Symbols
1086 The ARM ELF specification requires that special symbols be inserted
1087 into object files to mark certain features:
1093 At the start of a region of code containing ARM instructions.
1097 At the start of a region of code containing THUMB instructions.
1101 At the start of a region of data.
1105 The assembler will automatically insert these symbols for you - there
1106 is no need to code them yourself. Support for tagging symbols ($b,
1107 $f, $p and $m) which is also mentioned in the current ARM ELF
1108 specification is not implemented. This is because they have been
1109 dropped from the new EABI and so tools cannot rely upon their
1112 @node ARM Unwinding Tutorial
1115 The ABI for the ARM Architecture specifies a standard format for
1116 exception unwind information. This information is used when an
1117 exception is thrown to determine where control should be transferred.
1118 In particular, the unwind information is used to determine which
1119 function called the function that threw the exception, and which
1120 function called that one, and so forth. This information is also used
1121 to restore the values of callee-saved registers in the function
1122 catching the exception.
1124 If you are writing functions in assembly code, and those functions
1125 call other functions that throw exceptions, you must use assembly
1126 pseudo ops to ensure that appropriate exception unwind information is
1127 generated. Otherwise, if one of the functions called by your assembly
1128 code throws an exception, the run-time library will be unable to
1129 unwind the stack through your assembly code and your program will not
1132 To illustrate the use of these pseudo ops, we will examine the code
1133 that G++ generates for the following C++ input:
1136 void callee (int *);
1147 This example does not show how to throw or catch an exception from
1148 assembly code. That is a much more complex operation and should
1149 always be done in a high-level language, such as C++, that directly
1150 supports exceptions.
1152 The code generated by one particular version of G++ when compiling the
1159 @ Function supports interworking.
1160 @ args = 0, pretend = 0, frame = 8
1161 @ frame_needed = 1, uses_anonymous_args = 0
1183 Of course, the sequence of instructions varies based on the options
1184 you pass to GCC and on the version of GCC in use. The exact
1185 instructions are not important since we are focusing on the pseudo ops
1186 that are used to generate unwind information.
1188 An important assumption made by the unwinder is that the stack frame
1189 does not change during the body of the function. In particular, since
1190 we assume that the assembly code does not itself throw an exception,
1191 the only point where an exception can be thrown is from a call, such
1192 as the @code{bl} instruction above. At each call site, the same saved
1193 registers (including @code{lr}, which indicates the return address)
1194 must be located in the same locations relative to the frame pointer.
1196 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1197 op appears immediately before the first instruction of the function
1198 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1199 op appears immediately after the last instruction of the function.
1200 These pseudo ops specify the range of the function.
1202 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1203 @code{.pad}) matters; their exact locations are irrelevant. In the
1204 example above, the compiler emits the pseudo ops with particular
1205 instructions. That makes it easier to understand the code, but it is
1206 not required for correctness. It would work just as well to emit all
1207 of the pseudo ops other than @code{.fnend} in the same order, but
1208 immediately after @code{.fnstart}.
1210 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1211 indicates registers that have been saved to the stack so that they can
1212 be restored before the function returns. The argument to the
1213 @code{.save} pseudo op is a list of registers to save. If a register
1214 is ``callee-saved'' (as specified by the ABI) and is modified by the
1215 function you are writing, then your code must save the value before it
1216 is modified and restore the original value before the function
1217 returns. If an exception is thrown, the run-time library restores the
1218 values of these registers from their locations on the stack before
1219 returning control to the exception handler. (Of course, if an
1220 exception is not thrown, the function that contains the @code{.save}
1221 pseudo op restores these registers in the function epilogue, as is
1222 done with the @code{ldmfd} instruction above.)
1224 You do not have to save callee-saved registers at the very beginning
1225 of the function and you do not need to use the @code{.save} pseudo op
1226 immediately following the point at which the registers are saved.
1227 However, if you modify a callee-saved register, you must save it on
1228 the stack before modifying it and before calling any functions which
1229 might throw an exception. And, you must use the @code{.save} pseudo
1230 op to indicate that you have done so.
1232 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1233 modification of the stack pointer that does not save any registers.
1234 The argument is the number of bytes (in decimal) that are subtracted
1235 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1236 subtracting from the stack pointer increases the size of the stack.)
1238 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1239 indicates the register that contains the frame pointer. The first
1240 argument is the register that is set, which is typically @code{fp}.
1241 The second argument indicates the register from which the frame
1242 pointer takes its value. The third argument, if present, is the value
1243 (in decimal) added to the register specified by the second argument to
1244 compute the value of the frame pointer. You should not modify the
1245 frame pointer in the body of the function.
1247 If you do not use a frame pointer, then you should not use the
1248 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1249 should avoid modifying the stack pointer outside of the function
1250 prologue. Otherwise, the run-time library will be unable to find
1251 saved registers when it is unwinding the stack.
1253 The pseudo ops described above are sufficient for writing assembly
1254 code that calls functions which may throw exceptions. If you need to
1255 know more about the object-file format used to represent unwind
1256 information, you may consult the @cite{Exception Handling ABI for the
1257 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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