1 @c Copyright (C) 1996-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
149 @code{cortex-m0plus},
152 @code{marvell-whitney},
156 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
157 @code{i80200} (Intel XScale processor)
158 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
161 The special name @code{all} may be used to allow the
162 assembler to accept instructions valid for any ARM processor.
164 In addition to the basic instruction set, the assembler can be told to
165 accept various extension mnemonics that extend the processor using the
166 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
167 is equivalent to specifying @code{-mcpu=ep9312}.
169 Multiple extensions may be specified, separated by a @code{+}. The
170 extensions should be specified in ascending alphabetical order.
172 Some extensions may be restricted to particular architectures; this is
173 documented in the list of extensions below.
175 Extension mnemonics may also be removed from those the assembler accepts.
176 This is done be prepending @code{no} to the option that adds the extension.
177 Extensions that are removed should be listed after all extensions which have
178 been added, again in ascending alphabetical order. For example,
179 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
182 The following extensions are currently supported:
183 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
184 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
186 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
187 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
188 @code{fp} (Floating Point Extensions for v8-A architecture),
189 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
190 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
191 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
196 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
198 @code{os} (Operating System for v6M architecture),
199 @code{predres} (Execution and Data Prediction Restriction Instruction for
200 v8-A architectures, added by default from v8.5-A),
201 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
202 default from v8.5-A),
203 @code{sec} (Security Extensions for v6K and v7-A architectures),
204 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
205 @code{virt} (Virtualization Extensions for v7-A architecture, implies
207 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
208 @code{ras} (Reliability, Availability and Serviceability extensions
209 for v8-A architecture),
210 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
215 @cindex @code{-march=} command-line option, ARM
216 @item -march=@var{architecture}[+@var{extension}@dots{}]
217 This option specifies the target architecture. The assembler will issue
218 an error message if an attempt is made to assemble an instruction which
219 will not execute on the target architecture. The following architecture
220 names are recognized:
258 @code{armv8.1-m.main},
264 If both @code{-mcpu} and
265 @code{-march} are specified, the assembler will use
266 the setting for @code{-mcpu}.
268 The architecture option can be extended with a set extension options. These
269 extensions are context sensitive, i.e. the same extension may mean different
270 things when used with different architectures. When used together with a
271 @code{-mfpu} option, the union of both feature enablement is taken.
272 See their availability and meaning below:
274 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
276 @code{+fp}: Enables VFPv2 instructions.
277 @code{+nofp}: Disables all FPU instrunctions.
281 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
282 @code{+nofp}: Disables all FPU instructions.
286 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
287 @code{+vfpv3-d16}: Alias for @code{+fp}.
288 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
289 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
290 conversion instructions and 16 double-word registers.
291 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
292 instructions and 32 double-word registers.
293 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
294 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
295 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
297 @code{+neon}: Alias for @code{+simd}.
298 @code{+neon-vfpv3}: Alias for @code{+simd}.
299 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
300 NEONv1 instructions with 32 double-word registers.
301 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
302 double-word registers.
303 @code{+mp}: Enables Multiprocessing Extensions.
304 @code{+sec}: Enables Security Extensions.
305 @code{+nofp}: Disables all FPU and NEON instructions.
306 @code{+nosimd}: Disables all NEON instructions.
310 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
311 @code{+vfpv4-d16}: Alias for @code{+fp}.
312 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
313 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
314 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
315 conversion instructions and 16 double-word registers.
316 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
317 instructions and 32 double-word registers.
318 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
319 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
320 double-word registers.
321 @code{+neon-vfpv4}: Alias for @code{+simd}.
322 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
324 @code{+neon-vfpv3}: Alias for @code{+neon}.
325 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
326 NEONv1 instructions with 32 double-word registers.
327 double-word registers.
328 @code{+nofp}: Disables all FPU and NEON instructions.
329 @code{+nosimd}: Disables all NEON instructions.
333 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
334 double-word registers.
335 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
336 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
337 @code{+vfpv3-d16}: Alias for @code{+fp}.
338 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
339 floating-point conversion instructions with 16 double-word registers.
340 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
341 conversion instructions with 16 double-word registers.
342 @code{+idiv}: Enables integer division instructions in ARM mode.
343 @code{+nofp}: Disables all FPU instructions.
347 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
348 double-word registers.
349 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
350 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
351 double-word registers.
352 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
353 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
354 @code{+nofp}: Disables all FPU instructions.
356 For @code{armv8-m.main}:
358 @code{+dsp}: Enables DSP Extension.
359 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
360 double-word registers.
361 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
362 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
363 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
364 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
365 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
366 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
367 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
368 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
369 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
370 @code{+nofp}: Disables all FPU instructions.
371 @code{+nodsp}: Disables DSP Extension.
373 For @code{armv8.1-m.main}:
375 @code{+dsp}: Enables DSP Extension.
376 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
377 for Armv8.1-M Mainline with 16 double-word registers.
378 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
379 Armv8.1-M Mainline, implies @code{+fp}.
380 @code{+mve}: Enables integer only M-profile Vector Extension for
381 Armv8.1-M Mainline, implies @code{+dsp}.
382 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
383 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
384 @code{+nofp}: Disables all FPU instructions.
385 @code{+nodsp}: Disables DSP Extension.
386 @code{+nomve}: Disables all M-profile Vector Extensions.
390 @code{+crc}: Enables CRC32 Extension.
391 @code{+simd}: Enables VFP and NEON for Armv8-A.
392 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
394 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
395 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
397 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
398 @code{+nocrypto}: Disables Cryptography Extensions.
400 For @code{armv8.1-a}:
402 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
403 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
405 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
406 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
408 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
409 @code{+nocrypto}: Disables Cryptography Extensions.
411 For @code{armv8.2-a} and @code{armv8.3-a}:
413 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
414 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
415 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
416 for Armv8.2-A, implies @code{+fp16}.
417 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
419 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
421 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
422 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
424 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
425 @code{+nocrypto}: Disables Cryptography Extensions.
427 For @code{armv8.4-a}:
429 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
431 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
432 Variant Extensions for Armv8.2-A, implies @code{+simd}.
433 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
435 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
436 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
438 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
439 @code{+nocryptp}: Disables Cryptography Extensions.
441 For @code{armv8.5-a}:
443 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
445 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
446 Variant Extensions for Armv8.2-A, implies @code{+simd}.
447 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
449 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
450 @code{+nocryptp}: Disables Cryptography Extensions.
453 @cindex @code{-mfpu=} command-line option, ARM
454 @item -mfpu=@var{floating-point-format}
456 This option specifies the floating point format to assemble for. The
457 assembler will issue an error message if an attempt is made to assemble
458 an instruction which will not execute on the target floating point unit.
459 The following format options are recognized:
479 @code{vfpv3-d16-fp16},
496 @code{neon-fp-armv8},
497 @code{crypto-neon-fp-armv8},
498 @code{neon-fp-armv8.1}
500 @code{crypto-neon-fp-armv8.1}.
502 In addition to determining which instructions are assembled, this option
503 also affects the way in which the @code{.double} assembler directive behaves
504 when assembling little-endian code.
506 The default is dependent on the processor selected. For Architecture 5 or
507 later, the default is to assemble for VFP instructions; for earlier
508 architectures the default is to assemble for FPA instructions.
510 @cindex @code{-mfp16-format=} command-line option
511 @item -mfp16-format=@var{format}
512 This option specifies the half-precision floating point format to use
513 when assembling floating point numbers emitted by the @code{.float16}
515 The following format options are recognized:
518 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
519 point format is used, if @code{alternative} is specified then the Arm
520 alternative half-precision format is used. If this option is set on the
521 command line then the format is fixed and cannot be changed with
522 the @code{float16_format} directive. If this value is not set then
523 the IEEE 754-2008 format is used until the format is explicitly set with
524 the @code{float16_format} directive.
526 @cindex @code{-mthumb} command-line option, ARM
528 This option specifies that the assembler should start assembling Thumb
529 instructions; that is, it should behave as though the file starts with a
530 @code{.code 16} directive.
532 @cindex @code{-mthumb-interwork} command-line option, ARM
533 @item -mthumb-interwork
534 This option specifies that the output generated by the assembler should
535 be marked as supporting interworking. It also affects the behaviour
536 of the @code{ADR} and @code{ADRL} pseudo opcodes.
538 @cindex @code{-mimplicit-it} command-line option, ARM
539 @item -mimplicit-it=never
540 @itemx -mimplicit-it=always
541 @itemx -mimplicit-it=arm
542 @itemx -mimplicit-it=thumb
543 The @code{-mimplicit-it} option controls the behavior of the assembler when
544 conditional instructions are not enclosed in IT blocks.
545 There are four possible behaviors.
546 If @code{never} is specified, such constructs cause a warning in ARM
547 code and an error in Thumb-2 code.
548 If @code{always} is specified, such constructs are accepted in both
549 ARM and Thumb-2 code, where the IT instruction is added implicitly.
550 If @code{arm} is specified, such constructs are accepted in ARM code
551 and cause an error in Thumb-2 code.
552 If @code{thumb} is specified, such constructs cause a warning in ARM
553 code and are accepted in Thumb-2 code. If you omit this option, the
554 behavior is equivalent to @code{-mimplicit-it=arm}.
556 @cindex @code{-mapcs-26} command-line option, ARM
557 @cindex @code{-mapcs-32} command-line option, ARM
560 These options specify that the output generated by the assembler should
561 be marked as supporting the indicated version of the Arm Procedure.
564 @cindex @code{-matpcs} command-line option, ARM
566 This option specifies that the output generated by the assembler should
567 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
568 enabled this option will cause the assembler to create an empty
569 debugging section in the object file called .arm.atpcs. Debuggers can
570 use this to determine the ABI being used by.
572 @cindex @code{-mapcs-float} command-line option, ARM
574 This indicates the floating point variant of the APCS should be
575 used. In this variant floating point arguments are passed in FP
576 registers rather than integer registers.
578 @cindex @code{-mapcs-reentrant} command-line option, ARM
579 @item -mapcs-reentrant
580 This indicates that the reentrant variant of the APCS should be used.
581 This variant supports position independent code.
583 @cindex @code{-mfloat-abi=} command-line option, ARM
584 @item -mfloat-abi=@var{abi}
585 This option specifies that the output generated by the assembler should be
586 marked as using specified floating point ABI.
587 The following values are recognized:
593 @cindex @code{-eabi=} command-line option, ARM
594 @item -meabi=@var{ver}
595 This option specifies which EABI version the produced object files should
597 The following values are recognized:
603 @cindex @code{-EB} command-line option, ARM
605 This option specifies that the output generated by the assembler should
606 be marked as being encoded for a big-endian processor.
608 Note: If a program is being built for a system with big-endian data
609 and little-endian instructions then it should be assembled with the
610 @option{-EB} option, (all of it, code and data) and then linked with
611 the @option{--be8} option. This will reverse the endianness of the
612 instructions back to little-endian, but leave the data as big-endian.
614 @cindex @code{-EL} command-line option, ARM
616 This option specifies that the output generated by the assembler should
617 be marked as being encoded for a little-endian processor.
619 @cindex @code{-k} command-line option, ARM
620 @cindex PIC code generation for ARM
622 This option specifies that the output of the assembler should be marked
623 as position-independent code (PIC).
625 @cindex @code{--fix-v4bx} command-line option, ARM
627 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
628 the linker option of the same name.
630 @cindex @code{-mwarn-deprecated} command-line option, ARM
631 @item -mwarn-deprecated
632 @itemx -mno-warn-deprecated
633 Enable or disable warnings about using deprecated options or
634 features. The default is to warn.
636 @cindex @code{-mccs} command-line option, ARM
638 Turns on CodeComposer Studio assembly syntax compatibility mode.
640 @cindex @code{-mwarn-syms} command-line option, ARM
642 @itemx -mno-warn-syms
643 Enable or disable warnings about symbols that match the names of ARM
644 instructions. The default is to warn.
652 * ARM-Instruction-Set:: Instruction Set
653 * ARM-Chars:: Special Characters
654 * ARM-Regs:: Register Names
655 * ARM-Relocations:: Relocations
656 * ARM-Neon-Alignment:: NEON Alignment Specifiers
659 @node ARM-Instruction-Set
660 @subsection Instruction Set Syntax
661 Two slightly different syntaxes are support for ARM and THUMB
662 instructions. The default, @code{divided}, uses the old style where
663 ARM and THUMB instructions had their own, separate syntaxes. The new,
664 @code{unified} syntax, which can be selected via the @code{.syntax}
665 directive, and has the following main features:
669 Immediate operands do not require a @code{#} prefix.
672 The @code{IT} instruction may appear, and if it does it is validated
673 against subsequent conditional affixes. In ARM mode it does not
674 generate machine code, in THUMB mode it does.
677 For ARM instructions the conditional affixes always appear at the end
678 of the instruction. For THUMB instructions conditional affixes can be
679 used, but only inside the scope of an @code{IT} instruction.
682 All of the instructions new to the V6T2 architecture (and later) are
683 available. (Only a few such instructions can be written in the
684 @code{divided} syntax).
687 The @code{.N} and @code{.W} suffixes are recognized and honored.
690 All instructions set the flags if and only if they have an @code{s}
695 @subsection Special Characters
697 @cindex line comment character, ARM
698 @cindex ARM line comment character
699 The presence of a @samp{@@} anywhere on a line indicates the start of
700 a comment that extends to the end of that line.
702 If a @samp{#} appears as the first character of a line then the whole
703 line is treated as a comment, but in this case the line could also be
704 a logical line number directive (@pxref{Comments}) or a preprocessor
705 control command (@pxref{Preprocessing}).
707 @cindex line separator, ARM
708 @cindex statement separator, ARM
709 @cindex ARM line separator
710 The @samp{;} character can be used instead of a newline to separate
713 @cindex immediate character, ARM
714 @cindex ARM immediate character
715 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
717 @cindex identifiers, ARM
718 @cindex ARM identifiers
719 *TODO* Explain about /data modifier on symbols.
722 @subsection Register Names
724 @cindex ARM register names
725 @cindex register names, ARM
726 *TODO* Explain about ARM register naming, and the predefined names.
728 @node ARM-Relocations
729 @subsection ARM relocation generation
731 @cindex data relocations, ARM
732 @cindex ARM data relocations
733 Specific data relocations can be generated by putting the relocation name
734 in parentheses after the symbol name. For example:
740 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
742 The following relocations are supported:
758 For compatibility with older toolchains the assembler also accepts
759 @code{(PLT)} after branch targets. On legacy targets this will
760 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
761 targets it will encode either the @samp{R_ARM_CALL} or
762 @samp{R_ARM_JUMP24} relocation, as appropriate.
764 @cindex MOVW and MOVT relocations, ARM
765 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
766 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
767 respectively. For example to load the 32-bit address of foo into r0:
770 MOVW r0, #:lower16:foo
771 MOVT r0, #:upper16:foo
774 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
775 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
776 generated by prefixing the value with @samp{#:lower0_7:#},
777 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
778 respectively. For example to load the 32-bit address of foo into r0:
781 MOVS r0, #:upper8_15:#foo
783 ADDS r0, #:upper0_7:#foo
785 ADDS r0, #:lower8_15:#foo
787 ADDS r0, #:lower0_7:#foo
790 @node ARM-Neon-Alignment
791 @subsection NEON Alignment Specifiers
793 @cindex alignment for NEON instructions
794 Some NEON load/store instructions allow an optional address
796 The ARM documentation specifies that this is indicated by
797 @samp{@@ @var{align}}. However GAS already interprets
798 the @samp{@@} character as a "line comment" start,
799 so @samp{: @var{align}} is used instead. For example:
802 vld1.8 @{q0@}, [r0, :128]
805 @node ARM Floating Point
806 @section Floating Point
808 @cindex floating point, ARM (@sc{ieee})
809 @cindex ARM floating point (@sc{ieee})
810 The ARM family uses @sc{ieee} floating-point numbers.
813 @section ARM Machine Directives
815 @cindex machine directives, ARM
816 @cindex ARM machine directives
819 @c AAAAAAAAAAAAAAAAAAAAAAAAA
822 @cindex @code{.2byte} directive, ARM
823 @cindex @code{.4byte} directive, ARM
824 @cindex @code{.8byte} directive, ARM
825 @item .2byte @var{expression} [, @var{expression}]*
826 @itemx .4byte @var{expression} [, @var{expression}]*
827 @itemx .8byte @var{expression} [, @var{expression}]*
828 These directives write 2, 4 or 8 byte values to the output section.
831 @cindex @code{.align} directive, ARM
832 @item .align @var{expression} [, @var{expression}]
833 This is the generic @var{.align} directive. For the ARM however if the
834 first argument is zero (ie no alignment is needed) the assembler will
835 behave as if the argument had been 2 (ie pad to the next four byte
836 boundary). This is for compatibility with ARM's own assembler.
838 @cindex @code{.arch} directive, ARM
839 @item .arch @var{name}
840 Select the target architecture. Valid values for @var{name} are the same as
841 for the @option{-march} command-line option without the instruction set
844 Specifying @code{.arch} clears any previously selected architecture
847 @cindex @code{.arch_extension} directive, ARM
848 @item .arch_extension @var{name}
849 Add or remove an architecture extension to the target architecture. Valid
850 values for @var{name} are the same as those accepted as architectural
851 extensions by the @option{-mcpu} and @option{-march} command-line options.
853 @code{.arch_extension} may be used multiple times to add or remove extensions
854 incrementally to the architecture being compiled for.
856 @cindex @code{.arm} directive, ARM
858 This performs the same action as @var{.code 32}.
860 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
862 @cindex @code{.bss} directive, ARM
864 This directive switches to the @code{.bss} section.
866 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
868 @cindex @code{.cantunwind} directive, ARM
870 Prevents unwinding through the current function. No personality routine
871 or exception table data is required or permitted.
873 @cindex @code{.code} directive, ARM
874 @item .code @code{[16|32]}
875 This directive selects the instruction set being generated. The value 16
876 selects Thumb, with the value 32 selecting ARM.
878 @cindex @code{.cpu} directive, ARM
879 @item .cpu @var{name}
880 Select the target processor. Valid values for @var{name} are the same as
881 for the @option{-mcpu} command-line option without the instruction set
884 Specifying @code{.cpu} clears any previously selected architecture
887 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
889 @cindex @code{.dn} and @code{.qn} directives, ARM
890 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
891 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
893 The @code{dn} and @code{qn} directives are used to create typed
894 and/or indexed register aliases for use in Advanced SIMD Extension
895 (Neon) instructions. The former should be used to create aliases
896 of double-precision registers, and the latter to create aliases of
897 quad-precision registers.
899 If these directives are used to create typed aliases, those aliases can
900 be used in Neon instructions instead of writing types after the mnemonic
901 or after each operand. For example:
910 This is equivalent to writing the following:
916 Aliases created using @code{dn} or @code{qn} can be destroyed using
919 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
921 @cindex @code{.eabi_attribute} directive, ARM
922 @item .eabi_attribute @var{tag}, @var{value}
923 Set the EABI object attribute @var{tag} to @var{value}.
925 The @var{tag} is either an attribute number, or one of the following:
926 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
927 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
928 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
929 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
930 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
931 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
932 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
933 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
934 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
935 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
936 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
937 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
938 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
939 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
940 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
941 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
942 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
943 @code{Tag_conformance}, @code{Tag_T2EE_use},
944 @code{Tag_Virtualization_use}
946 The @var{value} is either a @code{number}, @code{"string"}, or
947 @code{number, "string"} depending on the tag.
949 Note - the following legacy values are also accepted by @var{tag}:
950 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
951 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
953 @cindex @code{.even} directive, ARM
955 This directive aligns to an even-numbered address.
957 @cindex @code{.extend} directive, ARM
958 @cindex @code{.ldouble} directive, ARM
959 @item .extend @var{expression} [, @var{expression}]*
960 @itemx .ldouble @var{expression} [, @var{expression}]*
961 These directives write 12byte long double floating-point values to the
962 output section. These are not compatible with current ARM processors
965 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
967 @cindex @code{.float16} directive, ARM
968 @item .float16 @var{value [,...,value_n]}
969 Place the half precision floating point representation of one or more
970 floating-point values into the current section. The exact format of the
971 encoding is specified by @code{.float16_format}. If the format has not
972 been explicitly set yet (either via the @code{.float16_format} directive or
973 the command line option) then the IEEE 754-2008 format is used.
975 @cindex @code{.float16_format} directive, ARM
976 @item .float16_format @var{format}
977 Set the format to use when encoding float16 values emitted by
978 the @code{.float16} directive.
979 Once the format has been set it cannot be changed.
980 @code{format} should be one of the following: @code{ieee} (encode in
981 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
982 the Arm alternative half precision format).
985 @cindex @code{.fnend} directive, ARM
987 Marks the end of a function with an unwind table entry. The unwind index
988 table entry is created when this directive is processed.
990 If no personality routine has been specified then standard personality
991 routine 0 or 1 will be used, depending on the number of unwind opcodes
995 @cindex @code{.fnstart} directive, ARM
997 Marks the start of a function with an unwind table entry.
999 @cindex @code{.force_thumb} directive, ARM
1001 This directive forces the selection of Thumb instructions, even if the
1002 target processor does not support those instructions
1004 @cindex @code{.fpu} directive, ARM
1005 @item .fpu @var{name}
1006 Select the floating-point unit to assemble for. Valid values for @var{name}
1007 are the same as for the @option{-mfpu} command-line option.
1009 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1010 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1012 @cindex @code{.handlerdata} directive, ARM
1014 Marks the end of the current function, and the start of the exception table
1015 entry for that function. Anything between this directive and the
1016 @code{.fnend} directive will be added to the exception table entry.
1018 Must be preceded by a @code{.personality} or @code{.personalityindex}
1021 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1023 @cindex @code{.inst} directive, ARM
1024 @item .inst @var{opcode} [ , @dots{} ]
1025 @itemx .inst.n @var{opcode} [ , @dots{} ]
1026 @itemx .inst.w @var{opcode} [ , @dots{} ]
1027 Generates the instruction corresponding to the numerical value @var{opcode}.
1028 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1029 specified explicitly, overriding the normal encoding rules.
1031 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1032 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1033 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1035 @item .ldouble @var{expression} [, @var{expression}]*
1038 @cindex @code{.ltorg} directive, ARM
1040 This directive causes the current contents of the literal pool to be
1041 dumped into the current section (which is assumed to be the .text
1042 section) at the current location (aligned to a word boundary).
1043 @code{GAS} maintains a separate literal pool for each section and each
1044 sub-section. The @code{.ltorg} directive will only affect the literal
1045 pool of the current section and sub-section. At the end of assembly
1046 all remaining, un-empty literal pools will automatically be dumped.
1048 Note - older versions of @code{GAS} would dump the current literal
1049 pool any time a section change occurred. This is no longer done, since
1050 it prevents accurate control of the placement of literal pools.
1052 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1054 @cindex @code{.movsp} directive, ARM
1055 @item .movsp @var{reg} [, #@var{offset}]
1056 Tell the unwinder that @var{reg} contains an offset from the current
1057 stack pointer. If @var{offset} is not specified then it is assumed to be
1060 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1061 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1063 @cindex @code{.object_arch} directive, ARM
1064 @item .object_arch @var{name}
1065 Override the architecture recorded in the EABI object attribute section.
1066 Valid values for @var{name} are the same as for the @code{.arch} directive.
1067 Typically this is useful when code uses runtime detection of CPU features.
1069 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1071 @cindex @code{.packed} directive, ARM
1072 @item .packed @var{expression} [, @var{expression}]*
1073 This directive writes 12-byte packed floating-point values to the
1074 output section. These are not compatible with current ARM processors
1078 @cindex @code{.pad} directive, ARM
1079 @item .pad #@var{count}
1080 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1081 A positive value indicates the function prologue allocated stack space by
1082 decrementing the stack pointer.
1084 @cindex @code{.personality} directive, ARM
1085 @item .personality @var{name}
1086 Sets the personality routine for the current function to @var{name}.
1088 @cindex @code{.personalityindex} directive, ARM
1089 @item .personalityindex @var{index}
1090 Sets the personality routine for the current function to the EABI standard
1091 routine number @var{index}
1093 @cindex @code{.pool} directive, ARM
1095 This is a synonym for .ltorg.
1097 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1098 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1100 @cindex @code{.req} directive, ARM
1101 @item @var{name} .req @var{register name}
1102 This creates an alias for @var{register name} called @var{name}. For
1109 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1112 @cindex @code{.save} directive, ARM
1113 @item .save @var{reglist}
1114 Generate unwinder annotations to restore the registers in @var{reglist}.
1115 The format of @var{reglist} is the same as the corresponding store-multiple
1119 @exdent @emph{core registers}
1120 .save @{r4, r5, r6, lr@}
1121 stmfd sp!, @{r4, r5, r6, lr@}
1122 @exdent @emph{FPA registers}
1125 @exdent @emph{VFP registers}
1126 .save @{d8, d9, d10@}
1127 fstmdx sp!, @{d8, d9, d10@}
1128 @exdent @emph{iWMMXt registers}
1129 .save @{wr10, wr11@}
1130 wstrd wr11, [sp, #-8]!
1131 wstrd wr10, [sp, #-8]!
1134 wstrd wr11, [sp, #-8]!
1136 wstrd wr10, [sp, #-8]!
1140 @cindex @code{.setfp} directive, ARM
1141 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1142 Make all unwinder annotations relative to a frame pointer. Without this
1143 the unwinder will use offsets from the stack pointer.
1145 The syntax of this directive is the same as the @code{add} or @code{mov}
1146 instruction used to set the frame pointer. @var{spreg} must be either
1147 @code{sp} or mentioned in a previous @code{.movsp} directive.
1157 @cindex @code{.secrel32} directive, ARM
1158 @item .secrel32 @var{expression} [, @var{expression}]*
1159 This directive emits relocations that evaluate to the section-relative
1160 offset of each expression's symbol. This directive is only supported
1163 @cindex @code{.syntax} directive, ARM
1164 @item .syntax [@code{unified} | @code{divided}]
1165 This directive sets the Instruction Set Syntax as described in the
1166 @ref{ARM-Instruction-Set} section.
1168 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1170 @cindex @code{.thumb} directive, ARM
1172 This performs the same action as @var{.code 16}.
1174 @cindex @code{.thumb_func} directive, ARM
1176 This directive specifies that the following symbol is the name of a
1177 Thumb encoded function. This information is necessary in order to allow
1178 the assembler and linker to generate correct code for interworking
1179 between Arm and Thumb instructions and should be used even if
1180 interworking is not going to be performed. The presence of this
1181 directive also implies @code{.thumb}
1183 This directive is not necessary when generating EABI objects. On these
1184 targets the encoding is implicit when generating Thumb code.
1186 @cindex @code{.thumb_set} directive, ARM
1188 This performs the equivalent of a @code{.set} directive in that it
1189 creates a symbol which is an alias for another symbol (possibly not yet
1190 defined). This directive also has the added property in that it marks
1191 the aliased symbol as being a thumb function entry point, in the same
1192 way that the @code{.thumb_func} directive does.
1194 @cindex @code{.tlsdescseq} directive, ARM
1195 @item .tlsdescseq @var{tls-variable}
1196 This directive is used to annotate parts of an inlined TLS descriptor
1197 trampoline. Normally the trampoline is provided by the linker, and
1198 this directive is not needed.
1200 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1202 @cindex @code{.unreq} directive, ARM
1203 @item .unreq @var{alias-name}
1204 This undefines a register alias which was previously defined using the
1205 @code{req}, @code{dn} or @code{qn} directives. For example:
1212 An error occurs if the name is undefined. Note - this pseudo op can
1213 be used to delete builtin in register name aliases (eg 'r0'). This
1214 should only be done if it is really necessary.
1216 @cindex @code{.unwind_raw} directive, ARM
1217 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1218 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1219 the stack pointer by @var{offset} bytes.
1221 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1224 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1226 @cindex @code{.vsave} directive, ARM
1227 @item .vsave @var{vfp-reglist}
1228 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1229 using FLDMD. Also works for VFPv3 registers
1230 that are to be restored using VLDM.
1231 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1235 @exdent @emph{VFP registers}
1236 .vsave @{d8, d9, d10@}
1237 fstmdd sp!, @{d8, d9, d10@}
1238 @exdent @emph{VFPv3 registers}
1239 .vsave @{d15, d16, d17@}
1240 vstm sp!, @{d15, d16, d17@}
1243 Since FLDMX and FSTMX are now deprecated, this directive should be
1244 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1246 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1247 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1248 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1249 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1257 @cindex opcodes for ARM
1258 @code{@value{AS}} implements all the standard ARM opcodes. It also
1259 implements several pseudo opcodes, including several synthetic load
1264 @cindex @code{NOP} pseudo op, ARM
1270 This pseudo op will always evaluate to a legal ARM instruction that does
1271 nothing. Currently it will evaluate to MOV r0, r0.
1273 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1276 ldr <register> , = <expression>
1279 If expression evaluates to a numeric constant then a MOV or MVN
1280 instruction will be used in place of the LDR instruction, if the
1281 constant can be generated by either of these instructions. Otherwise
1282 the constant will be placed into the nearest literal pool (if it not
1283 already there) and a PC relative LDR instruction will be generated.
1285 @cindex @code{ADR reg,<label>} pseudo op, ARM
1288 adr <register> <label>
1291 This instruction will load the address of @var{label} into the indicated
1292 register. The instruction will evaluate to a PC relative ADD or SUB
1293 instruction depending upon where the label is located. If the label is
1294 out of range, or if it is not defined in the same file (and section) as
1295 the ADR instruction, then an error will be generated. This instruction
1296 will not make use of the literal pool.
1298 If @var{label} is a thumb function symbol, and thumb interworking has
1299 been enabled via the @option{-mthumb-interwork} option then the bottom
1300 bit of the value stored into @var{register} will be set. This allows
1301 the following sequence to work as expected:
1304 adr r0, thumb_function
1308 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1311 adrl <register> <label>
1314 This instruction will load the address of @var{label} into the indicated
1315 register. The instruction will evaluate to one or two PC relative ADD
1316 or SUB instructions depending upon where the label is located. If a
1317 second instruction is not needed a NOP instruction will be generated in
1318 its place, so that this instruction is always 8 bytes long.
1320 If the label is out of range, or if it is not defined in the same file
1321 (and section) as the ADRL instruction, then an error will be generated.
1322 This instruction will not make use of the literal pool.
1324 If @var{label} is a thumb function symbol, and thumb interworking has
1325 been enabled via the @option{-mthumb-interwork} option then the bottom
1326 bit of the value stored into @var{register} will be set.
1330 For information on the ARM or Thumb instruction sets, see @cite{ARM
1331 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1334 @node ARM Mapping Symbols
1335 @section Mapping Symbols
1337 The ARM ELF specification requires that special symbols be inserted
1338 into object files to mark certain features:
1344 At the start of a region of code containing ARM instructions.
1348 At the start of a region of code containing THUMB instructions.
1352 At the start of a region of data.
1356 The assembler will automatically insert these symbols for you - there
1357 is no need to code them yourself. Support for tagging symbols ($b,
1358 $f, $p and $m) which is also mentioned in the current ARM ELF
1359 specification is not implemented. This is because they have been
1360 dropped from the new EABI and so tools cannot rely upon their
1363 @node ARM Unwinding Tutorial
1366 The ABI for the ARM Architecture specifies a standard format for
1367 exception unwind information. This information is used when an
1368 exception is thrown to determine where control should be transferred.
1369 In particular, the unwind information is used to determine which
1370 function called the function that threw the exception, and which
1371 function called that one, and so forth. This information is also used
1372 to restore the values of callee-saved registers in the function
1373 catching the exception.
1375 If you are writing functions in assembly code, and those functions
1376 call other functions that throw exceptions, you must use assembly
1377 pseudo ops to ensure that appropriate exception unwind information is
1378 generated. Otherwise, if one of the functions called by your assembly
1379 code throws an exception, the run-time library will be unable to
1380 unwind the stack through your assembly code and your program will not
1383 To illustrate the use of these pseudo ops, we will examine the code
1384 that G++ generates for the following C++ input:
1387 void callee (int *);
1398 This example does not show how to throw or catch an exception from
1399 assembly code. That is a much more complex operation and should
1400 always be done in a high-level language, such as C++, that directly
1401 supports exceptions.
1403 The code generated by one particular version of G++ when compiling the
1410 @ Function supports interworking.
1411 @ args = 0, pretend = 0, frame = 8
1412 @ frame_needed = 1, uses_anonymous_args = 0
1434 Of course, the sequence of instructions varies based on the options
1435 you pass to GCC and on the version of GCC in use. The exact
1436 instructions are not important since we are focusing on the pseudo ops
1437 that are used to generate unwind information.
1439 An important assumption made by the unwinder is that the stack frame
1440 does not change during the body of the function. In particular, since
1441 we assume that the assembly code does not itself throw an exception,
1442 the only point where an exception can be thrown is from a call, such
1443 as the @code{bl} instruction above. At each call site, the same saved
1444 registers (including @code{lr}, which indicates the return address)
1445 must be located in the same locations relative to the frame pointer.
1447 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1448 op appears immediately before the first instruction of the function
1449 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1450 op appears immediately after the last instruction of the function.
1451 These pseudo ops specify the range of the function.
1453 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1454 @code{.pad}) matters; their exact locations are irrelevant. In the
1455 example above, the compiler emits the pseudo ops with particular
1456 instructions. That makes it easier to understand the code, but it is
1457 not required for correctness. It would work just as well to emit all
1458 of the pseudo ops other than @code{.fnend} in the same order, but
1459 immediately after @code{.fnstart}.
1461 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1462 indicates registers that have been saved to the stack so that they can
1463 be restored before the function returns. The argument to the
1464 @code{.save} pseudo op is a list of registers to save. If a register
1465 is ``callee-saved'' (as specified by the ABI) and is modified by the
1466 function you are writing, then your code must save the value before it
1467 is modified and restore the original value before the function
1468 returns. If an exception is thrown, the run-time library restores the
1469 values of these registers from their locations on the stack before
1470 returning control to the exception handler. (Of course, if an
1471 exception is not thrown, the function that contains the @code{.save}
1472 pseudo op restores these registers in the function epilogue, as is
1473 done with the @code{ldmfd} instruction above.)
1475 You do not have to save callee-saved registers at the very beginning
1476 of the function and you do not need to use the @code{.save} pseudo op
1477 immediately following the point at which the registers are saved.
1478 However, if you modify a callee-saved register, you must save it on
1479 the stack before modifying it and before calling any functions which
1480 might throw an exception. And, you must use the @code{.save} pseudo
1481 op to indicate that you have done so.
1483 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1484 modification of the stack pointer that does not save any registers.
1485 The argument is the number of bytes (in decimal) that are subtracted
1486 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1487 subtracting from the stack pointer increases the size of the stack.)
1489 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1490 indicates the register that contains the frame pointer. The first
1491 argument is the register that is set, which is typically @code{fp}.
1492 The second argument indicates the register from which the frame
1493 pointer takes its value. The third argument, if present, is the value
1494 (in decimal) added to the register specified by the second argument to
1495 compute the value of the frame pointer. You should not modify the
1496 frame pointer in the body of the function.
1498 If you do not use a frame pointer, then you should not use the
1499 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1500 should avoid modifying the stack pointer outside of the function
1501 prologue. Otherwise, the run-time library will be unable to find
1502 saved registers when it is unwinding the stack.
1504 The pseudo ops described above are sufficient for writing assembly
1505 code that calls functions which may throw exceptions. If you need to
1506 know more about the object-file format used to represent unwind
1507 information, you may consult the @cite{Exception Handling ABI for the
1508 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / deliverable / binutils-gdb.git / blob