gas/doc/c-bfin.texi

   1 @c Copyright 2005, 2006, 2009
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @ifset GENERIC
   6 @page
   7 @node Blackfin-Dependent
   8 @chapter Blackfin Dependent Features
   9 @end ifset
  10 @ifclear GENERIC
  11 @node Machine Dependencies
  12 @chapter Blackfin Dependent Features
  13 @end ifclear
  14
  15 @cindex Blackfin support
  16 @menu
  17 * Blackfin Options::            Blackfin Options
  18 * Blackfin Syntax::             Blackfin Syntax
  19 * Blackfin Directives::         Blackfin Directives
  20 @end menu
  21
  22 @node Blackfin Options
  23 @section Options
  24 @cindex Blackfin options (none)
  25 @cindex options for Blackfin (none)
  26
  27 @table @code
  28
  29 @cindex @code{-mcpu=} command line option, Blackfin
  30 @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
  31 This option specifies the target processor.  The optional @var{sirevision}
  32 is not used in assembler.  It's here such that GCC can easily pass down its
  33 @code{-mcpu=} option.  The assembler will issue an
  34 error message if an attempt is made to assemble an instruction which
  35 will not execute on the target processor.  The following processor names are
  36 recognized:
  37 @code{bf504},
  38 @code{bf506},
  39 @code{bf512},
  40 @code{bf514},
  41 @code{bf516},
  42 @code{bf518},
  43 @code{bf522},
  44 @code{bf523},
  45 @code{bf524},
  46 @code{bf525},
  47 @code{bf526},
  48 @code{bf527},
  49 @code{bf531},
  50 @code{bf532},
  51 @code{bf533},
  52 @code{bf534},
  53 @code{bf535} (not implemented yet),
  54 @code{bf536},
  55 @code{bf537},
  56 @code{bf538},
  57 @code{bf539},
  58 @code{bf542},
  59 @code{bf542m},
  60 @code{bf544},
  61 @code{bf544m},
  62 @code{bf547},
  63 @code{bf547m},
  64 @code{bf548},
  65 @code{bf548m},
  66 @code{bf549},
  67 @code{bf549m},
  68 and
  69 @code{bf561}.
  70
  71 @cindex @code{-mfdpic} command line option, Blackfin
  72 @item -mfdpic
  73 Assemble for the FDPIC ABI.
  74
  75 @cindex @code{-mno-fdpic} command line option, Blackfin
  76 @cindex @code{-mnopic} command line option, Blackfin
  77 @item -mno-fdpic
  78 @itemx -mnopic
  79 Disable -mfdpic.
  80 @end table
  81
  82 @node Blackfin Syntax
  83 @section Syntax
  84 @cindex Blackfin syntax
  85 @cindex syntax, Blackfin
  86
  87 @table @code
  88 @item Special Characters
  89 Assembler input is free format and may appear anywhere on the line.
  90 One instruction may extend across multiple lines or more than one
  91 instruction may appear on the same line.  White space (space, tab,
  92 comments or newline) may appear anywhere between tokens.  A token must
  93 not have embedded spaces.  Tokens include numbers, register names,
  94 keywords, user identifiers, and also some multicharacter special
  95 symbols like "+=", "/*" or "||".
  96
  97 @item Instruction Delimiting
  98 A semicolon must terminate every instruction.  Sometimes a complete
  99 instruction will consist of more than one operation.  There are two
 100 cases where this occurs.  The first is when two general operations
 101 are combined.  Normally a comma separates the different parts, as in
 102
 103 @smallexample
 104 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
 105 @end smallexample
 106
 107 The second case occurs when a general instruction is combined with one
 108 or two memory references for joint issue.  The latter portions are
 109 set off by a "||" token.
 110
 111 @smallexample
 112 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
 113 @end smallexample
 114
 115 @item Register Names
 116
 117 The assembler treats register names and instruction keywords in a case
 118 insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
 119 R3.L, r3.l and r3.L are all equivalent input to the assembler.
 120
 121 Register names are reserved and may not be used as program identifiers.
 122
 123 Some operations (such as "Move Register") require a register pair.
 124 Register pairs are always data registers and are denoted using a colon,
 125 eg., R3:2.  The larger number must be written firsts.  Note that the
 126 hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
 127
 128 Some instructions (such as --SP (Push Multiple)) require a group of
 129 adjacent registers.  Adjacent registers are denoted in the syntax by
 130 the range enclosed in parentheses and separated by a colon, eg., (R7:3).
 131 Again, the larger number appears first.
 132
 133 Portions of a particular register may be individually specified.  This
 134 is written with a dot (".") following the register name and then a
 135 letter denoting the desired portion.  For 32-bit registers, ".H"
 136 denotes the most significant ("High") portion.  ".L" denotes the
 137 least-significant portion.  The subdivisions of the 40-bit registers
 138 are described later.
 139
 140 @item Accumulators
 141 The set of 40-bit registers A1 and A0 that normally contain data that
 142 is being manipulated.  Each accumulator can be accessed in four ways.
 143
 144 @table @code
 145 @item one 40-bit register
 146 The register will be referred to as A1 or A0.
 147 @item one 32-bit register
 148 The registers are designated as A1.W or A0.W.
 149 @item two 16-bit registers
 150 The registers are designated as A1.H, A1.L, A0.H or A0.L.
 151 @item one 8-bit register
 152 The registers are designated as A1.X or A0.X for the bits that
 153 extend beyond bit 31.
 154 @end table
 155
 156 @item Data Registers
 157 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
 158 normally contain data for manipulation.  These are abbreviated as
 159 D-register or Dreg.  Data registers can be accessed as 32-bit registers
 160 or as two independent 16-bit registers.  The least significant 16 bits
 161 of each register is called the "low" half and is designated with ".L"
 162 following the register name.  The most significant 16 bits are called
 163 the "high" half and is designated with ".H" following the name.
 164
 165 @smallexample
 166    R7.L, r2.h, r4.L, R0.H
 167 @end smallexample
 168
 169 @item Pointer Registers
 170 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
 171 normally contain byte addresses of data structures.  These are
 172 abbreviated as P-register or Preg.
 173
 174 @smallexample
 175 p2, p5, fp, sp
 176 @end smallexample
 177
 178 @item Stack Pointer SP
 179 The stack pointer contains the 32-bit address of the last occupied
 180 byte location in the stack.  The stack grows by decrementing the
 181 stack pointer.
 182
 183 @item Frame Pointer FP
 184 The frame pointer contains the 32-bit address of the previous frame
 185 pointer in the stack.  It is located at the top of a frame.
 186
 187 @item Loop Top
 188 LT0 and LT1.  These registers contain the 32-bit address of the top of
 189 a zero overhead loop.
 190
 191 @item Loop Count
 192 LC0 and LC1.  These registers contain the 32-bit counter of the zero
 193 overhead loop executions.
 194
 195 @item Loop Bottom
 196 LB0 and LB1.  These registers contain the 32-bit address of the bottom
 197 of a zero overhead loop.
 198
 199 @item Index Registers
 200 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
 201 addresses of data structures.  Abbreviated I-register or Ireg.
 202
 203 @item Modify Registers
 204 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
 205 offset values that are added and subracted to one of the index
 206 registers.  Abbreviated as Mreg.
 207
 208 @item Length Registers
 209 The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
 210 length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
 211 the Lreg to disable circular addressing for the corresponding Ireg.
 212
 213 @item Base Registers
 214 The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
 215 base address in bytes of the circular buffer.  Abbreviated as Breg.
 216
 217 @item Floating Point
 218 The Blackfin family has no hardware floating point but the .float
 219 directive generates ieee floating point numbers for use with software
 220 floating point libraries.
 221
 222 @item Blackfin Opcodes
 223 For detailed information on the Blackfin machine instruction set, see
 224 the Blackfin(r) Processor Instruction Set Reference.
 225
 226 @end table
 227
 228 @node Blackfin Directives
 229 @section Directives
 230 @cindex Blackfin directives
 231 @cindex directives, Blackfin
 232
 233 The following directives are provided for compatibility with the VDSP assembler.
 234
 235 @table @code
 236 @item .byte2
 237 Initializes a four byte data object.
 238 @item .byte4
 239 Initializes a two byte data object.
 240 @item .db
 241 TBD
 242 @item .dd
 243 TBD
 244 @item .dw
 245 TBD
 246 @item .var
 247 Define and initialize a 32 bit data object.
 248 @end table