gas/doc/c-bfin.texi

   1 @c Copyright 2005, 2006, 2009
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @ifset GENERIC
   6 @page
   7 @node BFIN-Dependent
   8 @chapter Blackfin Dependent Features
   9 @end ifset
  10 @ifclear GENERIC
  11 @node Machine Dependencies
  12 @chapter Blackfin Dependent Features
  13 @end ifclear
  14
  15 @cindex Blackfin support
  16 @menu
  17 * Blackfin Options::            Blackfin Options
  18 * Blackfin Syntax::             Blackfin Syntax
  19 * Blackfin Directives::         Blackfin Directives
  20 @end menu
  21
  22 @node Blackfin Options
  23 @section Options
  24 @cindex Blackfin options (none)
  25 @cindex options for Blackfin (none)
  26
  27 @table @code
  28
  29 @cindex @code{-mcpu=} command line option, Blackfin
  30 @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
  31 This option specifies the target processor.  The optional @var{sirevision}
  32 is not used in assembler.  It's here such that GCC can easily pass down its
  33 @code{-mcpu=} option.  The assembler will issue an
  34 error message if an attempt is made to assemble an instruction which
  35 will not execute on the target processor.  The following processor names are
  36 recognized:
  37 @code{bf522},
  38 @code{bf523},
  39 @code{bf524},
  40 @code{bf525},
  41 @code{bf526},
  42 @code{bf527},
  43 @code{bf531},
  44 @code{bf532},
  45 @code{bf533},
  46 @code{bf534},
  47 @code{bf535} (not implemented yet),
  48 @code{bf536},
  49 @code{bf537},
  50 @code{bf538},
  51 @code{bf539},
  52 @code{bf542},
  53 @code{bf542m},
  54 @code{bf544},
  55 @code{bf544m},
  56 @code{bf547},
  57 @code{bf547m},
  58 @code{bf548},
  59 @code{bf548m},
  60 @code{bf549},
  61 @code{bf549m},
  62 and
  63 @code{bf561}.
  64
  65 @end table
  66
  67 @node Blackfin Syntax
  68 @section Syntax
  69 @cindex Blackfin syntax
  70 @cindex syntax, Blackfin
  71
  72 @table @code
  73 @item Special Characters
  74 Assembler input is free format and may appear anywhere on the line.
  75 One instruction may extend across multiple lines or more than one
  76 instruction may appear on the same line.  White space (space, tab,
  77 comments or newline) may appear anywhere between tokens.  A token must
  78 not have embedded spaces.  Tokens include numbers, register names,
  79 keywords, user identifiers, and also some multicharacter special
  80 symbols like "+=", "/*" or "||".
  81
  82 @item Instruction Delimiting
  83 A semicolon must terminate every instruction.  Sometimes a complete
  84 instruction will consist of more than one operation.  There are two
  85 cases where this occurs.  The first is when two general operations
  86 are combined.  Normally a comma separates the different parts, as in
  87
  88 @smallexample
  89 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
  90 @end smallexample
  91
  92 The second case occurs when a general instruction is combined with one
  93 or two memory references for joint issue.  The latter portions are
  94 set off by a "||" token.
  95
  96 @smallexample
  97 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
  98 @end smallexample
  99
 100 @item Register Names
 101
 102 The assembler treats register names and instruction keywords in a case
 103 insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
 104 R3.L, r3.l and r3.L are all equivalent input to the assembler.
 105
 106 Register names are reserved and may not be used as program identifiers.
 107
 108 Some operations (such as "Move Register") require a register pair.
 109 Register pairs are always data registers and are denoted using a colon,
 110 eg., R3:2.  The larger number must be written firsts.  Note that the
 111 hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
 112
 113 Some instructions (such as --SP (Push Multiple)) require a group of
 114 adjacent registers.  Adjacent registers are denoted in the syntax by
 115 the range enclosed in parentheses and separated by a colon, eg., (R7:3).
 116 Again, the larger number appears first.
 117
 118 Portions of a particular register may be individually specified.  This
 119 is written with a dot (".") following the register name and then a
 120 letter denoting the desired portion.  For 32-bit registers, ".H"
 121 denotes the most significant ("High") portion.  ".L" denotes the
 122 least-significant portion.  The subdivisions of the 40-bit registers
 123 are described later.
 124
 125 @item Accumulators
 126 The set of 40-bit registers A1 and A0 that normally contain data that
 127 is being manipulated.  Each accumulator can be accessed in four ways.
 128
 129 @table @code
 130 @item one 40-bit register
 131 The register will be referred to as A1 or A0.
 132 @item one 32-bit register
 133 The registers are designated as A1.W or A0.W.
 134 @item two 16-bit registers
 135 The registers are designated as A1.H, A1.L, A0.H or A0.L.
 136 @item one 8-bit register
 137 The registers are designated as A1.X or A0.X for the bits that
 138 extend beyond bit 31.
 139 @end table
 140
 141 @item Data Registers
 142 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
 143 normally contain data for manipulation.  These are abbreviated as
 144 D-register or Dreg.  Data registers can be accessed as 32-bit registers
 145 or as two independent 16-bit registers.  The least significant 16 bits
 146 of each register is called the "low" half and is designated with ".L"
 147 following the register name.  The most significant 16 bits are called
 148 the "high" half and is designated with ".H" following the name.
 149
 150 @smallexample
 151    R7.L, r2.h, r4.L, R0.H
 152 @end smallexample
 153
 154 @item Pointer Registers
 155 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
 156 normally contain byte addresses of data structures.  These are
 157 abbreviated as P-register or Preg.
 158
 159 @smallexample
 160 p2, p5, fp, sp
 161 @end smallexample
 162
 163 @item Stack Pointer SP
 164 The stack pointer contains the 32-bit address of the last occupied
 165 byte location in the stack.  The stack grows by decrementing the
 166 stack pointer.
 167
 168 @item Frame Pointer FP
 169 The frame pointer contains the 32-bit address of the previous frame
 170 pointer in the stack.  It is located at the top of a frame.
 171
 172 @item Loop Top
 173 LT0 and LT1.  These registers contain the 32-bit address of the top of
 174 a zero overhead loop.
 175
 176 @item Loop Count
 177 LC0 and LC1.  These registers contain the 32-bit counter of the zero
 178 overhead loop executions.
 179
 180 @item Loop Bottom
 181 LB0 and LB1.  These registers contain the 32-bit address of the bottom
 182 of a zero overhead loop.
 183
 184 @item Index Registers
 185 The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
 186 addresses of data structures.  Abbreviated I-register or Ireg.
 187
 188 @item Modify Registers
 189 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
 190 offset values that are added and subracted to one of the index
 191 registers.  Abbreviated as Mreg.
 192
 193 @item Length Registers
 194 The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
 195 length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
 196 the Lreg to disable circular addressing for the corresponding Ireg.
 197
 198 @item Base Registers
 199 The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
 200 base address in bytes of the circular buffer.  Abbreviated as Breg.
 201
 202 @item Floating Point
 203 The Blackfin family has no hardware floating point but the .float
 204 directive generates ieee floating point numbers for use with software
 205 floating point libraries.
 206
 207 @item Blackfin Opcodes
 208 For detailed information on the Blackfin machine instruction set, see
 209 the Blackfin(r) Processor Instruction Set Reference.
 210
 211 @end table
 212
 213 @node Blackfin Directives
 214 @section Directives
 215 @cindex Blackfin directives
 216 @cindex directives, Blackfin
 217
 218 The following directives are provided for compatibility with the VDSP assembler.
 219
 220 @table @code
 221 @item .byte2
 222 Initializes a four byte data object.
 223 @item .byte4
 224 Initializes a two byte data object.
 225 @item .db
 226 TBD
 227 @item .dd
 228 TBD
 229 @item .dw
 230 TBD
 231 @item .var
 232 Define and initialize a 32 bit data object.
 233 @end table