1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
80 @cindex @samp{--divide} option, i386
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
196 @code{avx512_4fmaps},
197 @code{avx512_4vnniw},
198 @code{avx512_vpopcntdq},
201 @code{avx512_bitalg},
212 @code{noavx512_4fmaps},
213 @code{noavx512_4vnniw},
214 @code{noavx512_vpopcntdq},
215 @code{noavx512_vbmi2},
216 @code{noavx512_vnni},
217 @code{noavx512_bitalg},
218 @code{noavx512_vp2intersect},
219 @code{noavx512_bf16},
261 Note that rather than extending a basic instruction set, the extension
262 mnemonics starting with @code{no} revoke the respective functionality.
264 When the @code{.arch} directive is used with @option{-march}, the
265 @code{.arch} directive will take precedent.
267 @cindex @samp{-mtune=} option, i386
268 @cindex @samp{-mtune=} option, x86-64
269 @item -mtune=@var{CPU}
270 This option specifies a processor to optimize for. When used in
271 conjunction with the @option{-march} option, only instructions
272 of the processor specified by the @option{-march} option will be
275 Valid @var{CPU} values are identical to the processor list of
276 @option{-march=@var{CPU}}.
278 @cindex @samp{-msse2avx} option, i386
279 @cindex @samp{-msse2avx} option, x86-64
281 This option specifies that the assembler should encode SSE instructions
284 @cindex @samp{-msse-check=} option, i386
285 @cindex @samp{-msse-check=} option, x86-64
286 @item -msse-check=@var{none}
287 @itemx -msse-check=@var{warning}
288 @itemx -msse-check=@var{error}
289 These options control if the assembler should check SSE instructions.
290 @option{-msse-check=@var{none}} will make the assembler not to check SSE
291 instructions, which is the default. @option{-msse-check=@var{warning}}
292 will make the assembler issue a warning for any SSE instruction.
293 @option{-msse-check=@var{error}} will make the assembler issue an error
294 for any SSE instruction.
296 @cindex @samp{-mavxscalar=} option, i386
297 @cindex @samp{-mavxscalar=} option, x86-64
298 @item -mavxscalar=@var{128}
299 @itemx -mavxscalar=@var{256}
300 These options control how the assembler should encode scalar AVX
301 instructions. @option{-mavxscalar=@var{128}} will encode scalar
302 AVX instructions with 128bit vector length, which is the default.
303 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
304 with 256bit vector length.
306 @cindex @samp{-mvexwig=} option, i386
307 @cindex @samp{-mvexwig=} option, x86-64
308 @item -mvexwig=@var{0}
309 @itemx -mvexwig=@var{1}
310 These options control how the assembler should encode VEX.W-ignored (WIG)
311 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
312 instructions with vex.w = 0, which is the default.
313 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
316 @cindex @samp{-mevexlig=} option, i386
317 @cindex @samp{-mevexlig=} option, x86-64
318 @item -mevexlig=@var{128}
319 @itemx -mevexlig=@var{256}
320 @itemx -mevexlig=@var{512}
321 These options control how the assembler should encode length-ignored
322 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
323 EVEX instructions with 128bit vector length, which is the default.
324 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
325 encode LIG EVEX instructions with 256bit and 512bit vector length,
328 @cindex @samp{-mevexwig=} option, i386
329 @cindex @samp{-mevexwig=} option, x86-64
330 @item -mevexwig=@var{0}
331 @itemx -mevexwig=@var{1}
332 These options control how the assembler should encode w-ignored (WIG)
333 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
334 EVEX instructions with evex.w = 0, which is the default.
335 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
338 @cindex @samp{-mmnemonic=} option, i386
339 @cindex @samp{-mmnemonic=} option, x86-64
340 @item -mmnemonic=@var{att}
341 @itemx -mmnemonic=@var{intel}
342 This option specifies instruction mnemonic for matching instructions.
343 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
346 @cindex @samp{-msyntax=} option, i386
347 @cindex @samp{-msyntax=} option, x86-64
348 @item -msyntax=@var{att}
349 @itemx -msyntax=@var{intel}
350 This option specifies instruction syntax when processing instructions.
351 The @code{.att_syntax} and @code{.intel_syntax} directives will
354 @cindex @samp{-mnaked-reg} option, i386
355 @cindex @samp{-mnaked-reg} option, x86-64
357 This option specifies that registers don't require a @samp{%} prefix.
358 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
360 @cindex @samp{-madd-bnd-prefix} option, i386
361 @cindex @samp{-madd-bnd-prefix} option, x86-64
362 @item -madd-bnd-prefix
363 This option forces the assembler to add BND prefix to all branches, even
364 if such prefix was not explicitly specified in the source code.
366 @cindex @samp{-mshared} option, i386
367 @cindex @samp{-mshared} option, x86-64
369 On ELF target, the assembler normally optimizes out non-PLT relocations
370 against defined non-weak global branch targets with default visibility.
371 The @samp{-mshared} option tells the assembler to generate code which
372 may go into a shared library where all non-weak global branch targets
373 with default visibility can be preempted. The resulting code is
374 slightly bigger. This option only affects the handling of branch
377 @cindex @samp{-mbig-obj} option, x86-64
379 On x86-64 PE/COFF target this option forces the use of big object file
380 format, which allows more than 32768 sections.
382 @cindex @samp{-momit-lock-prefix=} option, i386
383 @cindex @samp{-momit-lock-prefix=} option, x86-64
384 @item -momit-lock-prefix=@var{no}
385 @itemx -momit-lock-prefix=@var{yes}
386 These options control how the assembler should encode lock prefix.
387 This option is intended as a workaround for processors, that fail on
388 lock prefix. This option can only be safely used with single-core,
389 single-thread computers
390 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
391 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
392 which is the default.
394 @cindex @samp{-mfence-as-lock-add=} option, i386
395 @cindex @samp{-mfence-as-lock-add=} option, x86-64
396 @item -mfence-as-lock-add=@var{no}
397 @itemx -mfence-as-lock-add=@var{yes}
398 These options control how the assembler should encode lfence, mfence and
400 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
401 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
402 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
403 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
404 sfence as usual, which is the default.
406 @cindex @samp{-mrelax-relocations=} option, i386
407 @cindex @samp{-mrelax-relocations=} option, x86-64
408 @item -mrelax-relocations=@var{no}
409 @itemx -mrelax-relocations=@var{yes}
410 These options control whether the assembler should generate relax
411 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
412 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
413 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
414 @option{-mrelax-relocations=@var{no}} will not generate relax
415 relocations. The default can be controlled by a configure option
416 @option{--enable-x86-relax-relocations}.
418 @cindex @samp{-mx86-used-note=} option, i386
419 @cindex @samp{-mx86-used-note=} option, x86-64
420 @item -mx86-used-note=@var{no}
421 @itemx -mx86-used-note=@var{yes}
422 These options control whether the assembler should generate
423 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
424 GNU property notes. The default can be controlled by the
425 @option{--enable-x86-used-note} configure option.
427 @cindex @samp{-mevexrcig=} option, i386
428 @cindex @samp{-mevexrcig=} option, x86-64
429 @item -mevexrcig=@var{rne}
430 @itemx -mevexrcig=@var{rd}
431 @itemx -mevexrcig=@var{ru}
432 @itemx -mevexrcig=@var{rz}
433 These options control how the assembler should encode SAE-only
434 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
435 of EVEX instruction with 00, which is the default.
436 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
437 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
438 with 01, 10 and 11 RC bits, respectively.
440 @cindex @samp{-mamd64} option, x86-64
441 @cindex @samp{-mintel64} option, x86-64
444 This option specifies that the assembler should accept only AMD64 or
445 Intel64 ISA in 64-bit mode. The default is to accept both.
447 @cindex @samp{-O0} option, i386
448 @cindex @samp{-O0} option, x86-64
449 @cindex @samp{-O} option, i386
450 @cindex @samp{-O} option, x86-64
451 @cindex @samp{-O1} option, i386
452 @cindex @samp{-O1} option, x86-64
453 @cindex @samp{-O2} option, i386
454 @cindex @samp{-O2} option, x86-64
455 @cindex @samp{-Os} option, i386
456 @cindex @samp{-Os} option, x86-64
457 @item -O0 | -O | -O1 | -O2 | -Os
458 Optimize instruction encoding with smaller instruction size. @samp{-O}
459 and @samp{-O1} encode 64-bit register load instructions with 64-bit
460 immediate as 32-bit register load instructions with 31-bit or 32-bits
461 immediates, encode 64-bit register clearing instructions with 32-bit
462 register clearing instructions and encode 256-bit/512-bit VEX/EVEX
463 vector register clearing instructions with 128-bit VEX vector register
464 clearing instructions as well as encode 128-bit/256-bit EVEX vector
465 register load/store instructions with VEX vector register load/store
466 instructions. @samp{-O2} includes @samp{-O1} optimization plus
467 encodes 256-bit/512-bit EVEX vector register clearing instructions with
468 128-bit EVEX vector register clearing instructions.
469 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
470 and 64-bit register tests with immediate as 8-bit register test with
471 immediate. @samp{-O0} turns off this optimization.
476 @node i386-Directives
477 @section x86 specific Directives
479 @cindex machine directives, x86
480 @cindex x86 machine directives
483 @cindex @code{lcomm} directive, COFF
484 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
485 Reserve @var{length} (an absolute expression) bytes for a local common
486 denoted by @var{symbol}. The section and value of @var{symbol} are
487 those of the new local common. The addresses are allocated in the bss
488 section, so that at run-time the bytes start off zeroed. Since
489 @var{symbol} is not declared global, it is normally not visible to
490 @code{@value{LD}}. The optional third parameter, @var{alignment},
491 specifies the desired alignment of the symbol in the bss section.
493 This directive is only available for COFF based x86 targets.
495 @cindex @code{largecomm} directive, ELF
496 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
497 This directive behaves in the same way as the @code{comm} directive
498 except that the data is placed into the @var{.lbss} section instead of
499 the @var{.bss} section @ref{Comm}.
501 The directive is intended to be used for data which requires a large
502 amount of space, and it is only available for ELF based x86_64
505 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
510 @section i386 Syntactical Considerations
512 * i386-Variations:: AT&T Syntax versus Intel Syntax
513 * i386-Chars:: Special Characters
516 @node i386-Variations
517 @subsection AT&T Syntax versus Intel Syntax
519 @cindex i386 intel_syntax pseudo op
520 @cindex intel_syntax pseudo op, i386
521 @cindex i386 att_syntax pseudo op
522 @cindex att_syntax pseudo op, i386
523 @cindex i386 syntax compatibility
524 @cindex syntax compatibility, i386
525 @cindex x86-64 intel_syntax pseudo op
526 @cindex intel_syntax pseudo op, x86-64
527 @cindex x86-64 att_syntax pseudo op
528 @cindex att_syntax pseudo op, x86-64
529 @cindex x86-64 syntax compatibility
530 @cindex syntax compatibility, x86-64
532 @code{@value{AS}} now supports assembly using Intel assembler syntax.
533 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
534 back to the usual AT&T mode for compatibility with the output of
535 @code{@value{GCC}}. Either of these directives may have an optional
536 argument, @code{prefix}, or @code{noprefix} specifying whether registers
537 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
538 different from Intel syntax. We mention these differences because
539 almost all 80386 documents use Intel syntax. Notable differences
540 between the two syntaxes are:
542 @cindex immediate operands, i386
543 @cindex i386 immediate operands
544 @cindex register operands, i386
545 @cindex i386 register operands
546 @cindex jump/call operands, i386
547 @cindex i386 jump/call operands
548 @cindex operand delimiters, i386
550 @cindex immediate operands, x86-64
551 @cindex x86-64 immediate operands
552 @cindex register operands, x86-64
553 @cindex x86-64 register operands
554 @cindex jump/call operands, x86-64
555 @cindex x86-64 jump/call operands
556 @cindex operand delimiters, x86-64
559 AT&T immediate operands are preceded by @samp{$}; Intel immediate
560 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
561 AT&T register operands are preceded by @samp{%}; Intel register operands
562 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
563 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
565 @cindex i386 source, destination operands
566 @cindex source, destination operands; i386
567 @cindex x86-64 source, destination operands
568 @cindex source, destination operands; x86-64
570 AT&T and Intel syntax use the opposite order for source and destination
571 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
572 @samp{source, dest} convention is maintained for compatibility with
573 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
574 instructions with 2 immediate operands, such as the @samp{enter}
575 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
577 @cindex mnemonic suffixes, i386
578 @cindex sizes operands, i386
579 @cindex i386 size suffixes
580 @cindex mnemonic suffixes, x86-64
581 @cindex sizes operands, x86-64
582 @cindex x86-64 size suffixes
584 In AT&T syntax the size of memory operands is determined from the last
585 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
586 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
587 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
588 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
589 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
590 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
593 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
594 instruction with the 64-bit displacement or immediate operand.
596 @cindex return instructions, i386
597 @cindex i386 jump, call, return
598 @cindex return instructions, x86-64
599 @cindex x86-64 jump, call, return
601 Immediate form long jumps and calls are
602 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
604 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
606 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
607 @samp{ret far @var{stack-adjust}}.
609 @cindex sections, i386
610 @cindex i386 sections
611 @cindex sections, x86-64
612 @cindex x86-64 sections
614 The AT&T assembler does not provide support for multiple section
615 programs. Unix style systems expect all programs to be single sections.
619 @subsection Special Characters
621 @cindex line comment character, i386
622 @cindex i386 line comment character
623 The presence of a @samp{#} appearing anywhere on a line indicates the
624 start of a comment that extends to the end of that line.
626 If a @samp{#} appears as the first character of a line then the whole
627 line is treated as a comment, but in this case the line can also be a
628 logical line number directive (@pxref{Comments}) or a preprocessor
629 control command (@pxref{Preprocessing}).
631 If the @option{--divide} command-line option has not been specified
632 then the @samp{/} character appearing anywhere on a line also
633 introduces a line comment.
635 @cindex line separator, i386
636 @cindex statement separator, i386
637 @cindex i386 line separator
638 The @samp{;} character can be used to separate statements on the same
642 @section i386-Mnemonics
643 @subsection Instruction Naming
645 @cindex i386 instruction naming
646 @cindex instruction naming, i386
647 @cindex x86-64 instruction naming
648 @cindex instruction naming, x86-64
650 Instruction mnemonics are suffixed with one character modifiers which
651 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
652 and @samp{q} specify byte, word, long and quadruple word operands. If
653 no suffix is specified by an instruction then @code{@value{AS}} tries to
654 fill in the missing suffix based on the destination register operand
655 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
656 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
657 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
658 assembler which assumes that a missing mnemonic suffix implies long
659 operand size. (This incompatibility does not affect compiler output
660 since compilers always explicitly specify the mnemonic suffix.)
662 Almost all instructions have the same names in AT&T and Intel format.
663 There are a few exceptions. The sign extend and zero extend
664 instructions need two sizes to specify them. They need a size to
665 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
666 is accomplished by using two instruction mnemonic suffixes in AT&T
667 syntax. Base names for sign extend and zero extend are
668 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
669 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
670 are tacked on to this base name, the @emph{from} suffix before the
671 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
672 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
673 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
674 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
675 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
678 @cindex encoding options, i386
679 @cindex encoding options, x86-64
681 Different encoding options can be specified via pseudo prefixes:
685 @samp{@{disp8@}} -- prefer 8-bit displacement.
688 @samp{@{disp32@}} -- prefer 32-bit displacement.
691 @samp{@{load@}} -- prefer load-form instruction.
694 @samp{@{store@}} -- prefer store-form instruction.
697 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
700 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
703 @samp{@{evex@}} -- encode with EVEX prefix.
706 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
707 instructions (x86-64 only). Note that this differs from the @samp{rex}
708 prefix which generates REX prefix unconditionally.
711 @samp{@{nooptimize@}} -- disable instruction size optimization.
714 @cindex conversion instructions, i386
715 @cindex i386 conversion instructions
716 @cindex conversion instructions, x86-64
717 @cindex x86-64 conversion instructions
718 The Intel-syntax conversion instructions
722 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
725 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
728 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
731 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
734 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
738 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
739 @samp{%rdx:%rax} (x86-64 only),
743 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
744 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
747 @cindex jump instructions, i386
748 @cindex call instructions, i386
749 @cindex jump instructions, x86-64
750 @cindex call instructions, x86-64
751 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
752 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
755 @subsection AT&T Mnemonic versus Intel Mnemonic
757 @cindex i386 mnemonic compatibility
758 @cindex mnemonic compatibility, i386
760 @code{@value{AS}} supports assembly using Intel mnemonic.
761 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
762 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
763 syntax for compatibility with the output of @code{@value{GCC}}.
764 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
765 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
766 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
767 assembler with different mnemonics from those in Intel IA32 specification.
768 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
771 @section Register Naming
773 @cindex i386 registers
774 @cindex registers, i386
775 @cindex x86-64 registers
776 @cindex registers, x86-64
777 Register operands are always prefixed with @samp{%}. The 80386 registers
782 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
783 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
784 frame pointer), and @samp{%esp} (the stack pointer).
787 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
788 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
791 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
792 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
793 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
794 @samp{%cx}, and @samp{%dx})
797 the 6 section registers @samp{%cs} (code section), @samp{%ds}
798 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
802 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
803 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
806 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
807 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
810 the 2 test registers @samp{%tr6} and @samp{%tr7}.
813 the 8 floating point register stack @samp{%st} or equivalently
814 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
815 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
816 These registers are overloaded by 8 MMX registers @samp{%mm0},
817 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
818 @samp{%mm6} and @samp{%mm7}.
821 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
822 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
825 The AMD x86-64 architecture extends the register set by:
829 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
830 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
831 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
835 the 8 extended registers @samp{%r8}--@samp{%r15}.
838 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
841 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
844 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
847 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
850 the 8 debug registers: @samp{%db8}--@samp{%db15}.
853 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
856 With the AVX extensions more registers were made available:
861 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
862 available in 32-bit mode). The bottom 128 bits are overlaid with the
863 @samp{xmm0}--@samp{xmm15} registers.
867 The AVX2 extensions made in 64-bit mode more registers available:
872 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
873 registers @samp{%ymm16}--@samp{%ymm31}.
877 The AVX512 extensions added the following registers:
882 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
883 available in 32-bit mode). The bottom 128 bits are overlaid with the
884 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
885 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
888 the 8 mask registers @samp{%k0}--@samp{%k7}.
893 @section Instruction Prefixes
895 @cindex i386 instruction prefixes
896 @cindex instruction prefixes, i386
897 @cindex prefixes, i386
898 Instruction prefixes are used to modify the following instruction. They
899 are used to repeat string instructions, to provide section overrides, to
900 perform bus lock operations, and to change operand and address sizes.
901 (Most instructions that normally operate on 32-bit operands will use
902 16-bit operands if the instruction has an ``operand size'' prefix.)
903 Instruction prefixes are best written on the same line as the instruction
904 they act upon. For example, the @samp{scas} (scan string) instruction is
908 repne scas %es:(%edi),%al
911 You may also place prefixes on the lines immediately preceding the
912 instruction, but this circumvents checks that @code{@value{AS}} does
913 with prefixes, and will not work with all prefixes.
915 Here is a list of instruction prefixes:
917 @cindex section override prefixes, i386
920 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
921 @samp{fs}, @samp{gs}. These are automatically added by specifying
922 using the @var{section}:@var{memory-operand} form for memory references.
924 @cindex size prefixes, i386
926 Operand/Address size prefixes @samp{data16} and @samp{addr16}
927 change 32-bit operands/addresses into 16-bit operands/addresses,
928 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
929 @code{.code16} section) into 32-bit operands/addresses. These prefixes
930 @emph{must} appear on the same line of code as the instruction they
931 modify. For example, in a 16-bit @code{.code16} section, you might
938 @cindex bus lock prefixes, i386
939 @cindex inhibiting interrupts, i386
941 The bus lock prefix @samp{lock} inhibits interrupts during execution of
942 the instruction it precedes. (This is only valid with certain
943 instructions; see a 80386 manual for details).
945 @cindex coprocessor wait, i386
947 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
948 complete the current instruction. This should never be needed for the
949 80386/80387 combination.
951 @cindex repeat prefixes, i386
953 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
954 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
955 times if the current address size is 16-bits).
956 @cindex REX prefixes, i386
958 The @samp{rex} family of prefixes is used by x86-64 to encode
959 extensions to i386 instruction set. The @samp{rex} prefix has four
960 bits --- an operand size overwrite (@code{64}) used to change operand size
961 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
964 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
965 instruction emits @samp{rex} prefix with all the bits set. By omitting
966 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
967 prefixes as well. Normally, there is no need to write the prefixes
968 explicitly, since gas will automatically generate them based on the
969 instruction operands.
973 @section Memory References
975 @cindex i386 memory references
976 @cindex memory references, i386
977 @cindex x86-64 memory references
978 @cindex memory references, x86-64
979 An Intel syntax indirect memory reference of the form
982 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
986 is translated into the AT&T syntax
989 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
993 where @var{base} and @var{index} are the optional 32-bit base and
994 index registers, @var{disp} is the optional displacement, and
995 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
996 to calculate the address of the operand. If no @var{scale} is
997 specified, @var{scale} is taken to be 1. @var{section} specifies the
998 optional section register for the memory operand, and may override the
999 default section register (see a 80386 manual for section register
1000 defaults). Note that section overrides in AT&T syntax @emph{must}
1001 be preceded by a @samp{%}. If you specify a section override which
1002 coincides with the default section register, @code{@value{AS}} does @emph{not}
1003 output any section register override prefixes to assemble the given
1004 instruction. Thus, section overrides can be specified to emphasize which
1005 section register is used for a given memory operand.
1007 Here are some examples of Intel and AT&T style memory references:
1010 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1011 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1012 missing, and the default section is used (@samp{%ss} for addressing with
1013 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1015 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1016 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1017 @samp{foo}. All other fields are missing. The section register here
1018 defaults to @samp{%ds}.
1020 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1021 This uses the value pointed to by @samp{foo} as a memory operand.
1022 Note that @var{base} and @var{index} are both missing, but there is only
1023 @emph{one} @samp{,}. This is a syntactic exception.
1025 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1026 This selects the contents of the variable @samp{foo} with section
1027 register @var{section} being @samp{%gs}.
1030 Absolute (as opposed to PC relative) call and jump operands must be
1031 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1032 always chooses PC relative addressing for jump/call labels.
1034 Any instruction that has a memory operand, but no register operand,
1035 @emph{must} specify its size (byte, word, long, or quadruple) with an
1036 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1039 The x86-64 architecture adds an RIP (instruction pointer relative)
1040 addressing. This addressing mode is specified by using @samp{rip} as a
1041 base register. Only constant offsets are valid. For example:
1044 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1045 Points to the address 1234 bytes past the end of the current
1048 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1049 Points to the @code{symbol} in RIP relative way, this is shorter than
1050 the default absolute addressing.
1053 Other addressing modes remain unchanged in x86-64 architecture, except
1054 registers used are 64-bit instead of 32-bit.
1057 @section Handling of Jump Instructions
1059 @cindex jump optimization, i386
1060 @cindex i386 jump optimization
1061 @cindex jump optimization, x86-64
1062 @cindex x86-64 jump optimization
1063 Jump instructions are always optimized to use the smallest possible
1064 displacements. This is accomplished by using byte (8-bit) displacement
1065 jumps whenever the target is sufficiently close. If a byte displacement
1066 is insufficient a long displacement is used. We do not support
1067 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1068 instruction with the @samp{data16} instruction prefix), since the 80386
1069 insists upon masking @samp{%eip} to 16 bits after the word displacement
1070 is added. (See also @pxref{i386-Arch})
1072 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1073 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1074 displacements, so that if you use these instructions (@code{@value{GCC}} does
1075 not use them) you may get an error message (and incorrect code). The AT&T
1076 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1087 @section Floating Point
1089 @cindex i386 floating point
1090 @cindex floating point, i386
1091 @cindex x86-64 floating point
1092 @cindex floating point, x86-64
1093 All 80387 floating point types except packed BCD are supported.
1094 (BCD support may be added without much difficulty). These data
1095 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1096 double (64-bit), and extended (80-bit) precision floating point.
1097 Each supported type has an instruction mnemonic suffix and a constructor
1098 associated with it. Instruction mnemonic suffixes specify the operand's
1099 data type. Constructors build these data types into memory.
1101 @cindex @code{float} directive, i386
1102 @cindex @code{single} directive, i386
1103 @cindex @code{double} directive, i386
1104 @cindex @code{tfloat} directive, i386
1105 @cindex @code{float} directive, x86-64
1106 @cindex @code{single} directive, x86-64
1107 @cindex @code{double} directive, x86-64
1108 @cindex @code{tfloat} directive, x86-64
1111 Floating point constructors are @samp{.float} or @samp{.single},
1112 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1113 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1114 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1115 only supports this format via the @samp{fldt} (load 80-bit real to stack
1116 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1118 @cindex @code{word} directive, i386
1119 @cindex @code{long} directive, i386
1120 @cindex @code{int} directive, i386
1121 @cindex @code{quad} directive, i386
1122 @cindex @code{word} directive, x86-64
1123 @cindex @code{long} directive, x86-64
1124 @cindex @code{int} directive, x86-64
1125 @cindex @code{quad} directive, x86-64
1127 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1128 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1129 corresponding instruction mnemonic suffixes are @samp{s} (single),
1130 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1131 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1132 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1133 stack) instructions.
1136 Register to register operations should not use instruction mnemonic suffixes.
1137 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1138 wrote @samp{fst %st, %st(1)}, since all register to register operations
1139 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1140 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1141 then stores the result in the 4 byte location @samp{mem})
1144 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1147 @cindex 3DNow!, i386
1150 @cindex 3DNow!, x86-64
1151 @cindex SIMD, x86-64
1153 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1154 instructions for integer data), available on Intel's Pentium MMX
1155 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1156 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1157 instruction set (SIMD instructions for 32-bit floating point data)
1158 available on AMD's K6-2 processor and possibly others in the future.
1160 Currently, @code{@value{AS}} does not support Intel's floating point
1163 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1164 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1165 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1166 floating point values. The MMX registers cannot be used at the same time
1167 as the floating point stack.
1169 See Intel and AMD documentation, keeping in mind that the operand order in
1170 instructions is reversed from the Intel syntax.
1173 @section AMD's Lightweight Profiling Instructions
1178 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1179 instruction set, available on AMD's Family 15h (Orochi) processors.
1181 LWP enables applications to collect and manage performance data, and
1182 react to performance events. The collection of performance data
1183 requires no context switches. LWP runs in the context of a thread and
1184 so several counters can be used independently across multiple threads.
1185 LWP can be used in both 64-bit and legacy 32-bit modes.
1187 For detailed information on the LWP instruction set, see the
1188 @cite{AMD Lightweight Profiling Specification} available at
1189 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1192 @section Bit Manipulation Instructions
1197 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1199 BMI instructions provide several instructions implementing individual
1200 bit manipulation operations such as isolation, masking, setting, or
1203 @c Need to add a specification citation here when available.
1206 @section AMD's Trailing Bit Manipulation Instructions
1211 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1212 instruction set, available on AMD's BDVER2 processors (Trinity and
1215 TBM instructions provide instructions implementing individual bit
1216 manipulation operations such as isolating, masking, setting, resetting,
1217 complementing, and operations on trailing zeros and ones.
1219 @c Need to add a specification citation here when available.
1222 @section Writing 16-bit Code
1224 @cindex i386 16-bit code
1225 @cindex 16-bit code, i386
1226 @cindex real-mode code, i386
1227 @cindex @code{code16gcc} directive, i386
1228 @cindex @code{code16} directive, i386
1229 @cindex @code{code32} directive, i386
1230 @cindex @code{code64} directive, i386
1231 @cindex @code{code64} directive, x86-64
1232 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1233 or 64-bit x86-64 code depending on the default configuration,
1234 it also supports writing code to run in real mode or in 16-bit protected
1235 mode code segments. To do this, put a @samp{.code16} or
1236 @samp{.code16gcc} directive before the assembly language instructions to
1237 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1238 32-bit code with the @samp{.code32} directive or 64-bit code with the
1239 @samp{.code64} directive.
1241 @samp{.code16gcc} provides experimental support for generating 16-bit
1242 code from gcc, and differs from @samp{.code16} in that @samp{call},
1243 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1244 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1245 default to 32-bit size. This is so that the stack pointer is
1246 manipulated in the same way over function calls, allowing access to
1247 function parameters at the same stack offsets as in 32-bit mode.
1248 @samp{.code16gcc} also automatically adds address size prefixes where
1249 necessary to use the 32-bit addressing modes that gcc generates.
1251 The code which @code{@value{AS}} generates in 16-bit mode will not
1252 necessarily run on a 16-bit pre-80386 processor. To write code that
1253 runs on such a processor, you must refrain from using @emph{any} 32-bit
1254 constructs which require @code{@value{AS}} to output address or operand
1257 Note that writing 16-bit code instructions by explicitly specifying a
1258 prefix or an instruction mnemonic suffix within a 32-bit code section
1259 generates different machine instructions than those generated for a
1260 16-bit code segment. In a 32-bit code section, the following code
1261 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1262 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1268 The same code in a 16-bit code section would generate the machine
1269 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1270 is correct since the processor default operand size is assumed to be 16
1271 bits in a 16-bit code section.
1274 @section Specifying CPU Architecture
1276 @cindex arch directive, i386
1277 @cindex i386 arch directive
1278 @cindex arch directive, x86-64
1279 @cindex x86-64 arch directive
1281 @code{@value{AS}} may be told to assemble for a particular CPU
1282 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1283 directive enables a warning when gas detects an instruction that is not
1284 supported on the CPU specified. The choices for @var{cpu_type} are:
1286 @multitable @columnfractions .20 .20 .20 .20
1287 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1288 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1289 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1290 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1291 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1292 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1293 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1294 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1295 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1296 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1297 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1298 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1299 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1300 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1301 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1302 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1303 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1304 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1305 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1306 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1307 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1308 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1309 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1310 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1311 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1312 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1313 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1314 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1315 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
1316 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1317 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1318 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1319 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1322 Apart from the warning, there are only two other effects on
1323 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1324 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1325 will automatically use a two byte opcode sequence. The larger three
1326 byte opcode sequence is used on the 486 (and when no architecture is
1327 specified) because it executes faster on the 486. Note that you can
1328 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1329 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1330 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1331 conditional jumps will be promoted when necessary to a two instruction
1332 sequence consisting of a conditional jump of the opposite sense around
1333 an unconditional jump to the target.
1335 Following the CPU architecture (but not a sub-architecture, which are those
1336 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1337 control automatic promotion of conditional jumps. @samp{jumps} is the
1338 default, and enables jump promotion; All external jumps will be of the long
1339 variety, and file-local jumps will be promoted as necessary.
1340 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1341 byte offset jumps, and warns about file-local conditional jumps that
1342 @code{@value{AS}} promotes.
1343 Unconditional jumps are treated as for @samp{jumps}.
1352 @section AT&T Syntax bugs
1354 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1355 assemblers, generate floating point instructions with reversed source
1356 and destination registers in certain cases. Unfortunately, gcc and
1357 possibly many other programs use this reversed syntax, so we're stuck
1366 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1367 than the expected @samp{%st(3) - %st}. This happens with all the
1368 non-commutative arithmetic floating point operations with two register
1369 operands where the source register is @samp{%st} and the destination
1370 register is @samp{%st(i)}.
1375 @cindex i386 @code{mul}, @code{imul} instructions
1376 @cindex @code{mul} instruction, i386
1377 @cindex @code{imul} instruction, i386
1378 @cindex @code{mul} instruction, x86-64
1379 @cindex @code{imul} instruction, x86-64
1380 There is some trickery concerning the @samp{mul} and @samp{imul}
1381 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1382 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1383 for @samp{imul}) can be output only in the one operand form. Thus,
1384 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1385 the expanding multiply would clobber the @samp{%edx} register, and this
1386 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1387 64-bit product in @samp{%edx:%eax}.
1389 We have added a two operand form of @samp{imul} when the first operand
1390 is an immediate mode expression and the second operand is a register.
1391 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1392 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
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