1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
201 Note that rather than extending a basic instruction set, the extension
202 mnemonics starting with @code{no} revoke the respective functionality.
204 When the @code{.arch} directive is used with @option{-march}, the
205 @code{.arch} directive will take precedent.
207 @cindex @samp{-mtune=} option, i386
208 @cindex @samp{-mtune=} option, x86-64
209 @item -mtune=@var{CPU}
210 This option specifies a processor to optimize for. When used in
211 conjunction with the @option{-march} option, only instructions
212 of the processor specified by the @option{-march} option will be
215 Valid @var{CPU} values are identical to the processor list of
216 @option{-march=@var{CPU}}.
218 @cindex @samp{-msse2avx} option, i386
219 @cindex @samp{-msse2avx} option, x86-64
221 This option specifies that the assembler should encode SSE instructions
224 @cindex @samp{-msse-check=} option, i386
225 @cindex @samp{-msse-check=} option, x86-64
226 @item -msse-check=@var{none}
227 @itemx -msse-check=@var{warning}
228 @itemx -msse-check=@var{error}
229 These options control if the assembler should check SSE instructions.
230 @option{-msse-check=@var{none}} will make the assembler not to check SSE
231 instructions, which is the default. @option{-msse-check=@var{warning}}
232 will make the assembler issue a warning for any SSE instruction.
233 @option{-msse-check=@var{error}} will make the assembler issue an error
234 for any SSE instruction.
236 @cindex @samp{-mavxscalar=} option, i386
237 @cindex @samp{-mavxscalar=} option, x86-64
238 @item -mavxscalar=@var{128}
239 @itemx -mavxscalar=@var{256}
240 These options control how the assembler should encode scalar AVX
241 instructions. @option{-mavxscalar=@var{128}} will encode scalar
242 AVX instructions with 128bit vector length, which is the default.
243 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
244 with 256bit vector length.
246 @cindex @samp{-mevexlig=} option, i386
247 @cindex @samp{-mevexlig=} option, x86-64
248 @item -mevexlig=@var{128}
249 @itemx -mevexlig=@var{256}
250 @itemx -mevexlig=@var{512}
251 These options control how the assembler should encode length-ignored
252 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
253 EVEX instructions with 128bit vector length, which is the default.
254 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
255 encode LIG EVEX instructions with 256bit and 512bit vector length,
258 @cindex @samp{-mevexwig=} option, i386
259 @cindex @samp{-mevexwig=} option, x86-64
260 @item -mevexwig=@var{0}
261 @itemx -mevexwig=@var{1}
262 These options control how the assembler should encode w-ignored (WIG)
263 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
264 EVEX instructions with evex.w = 0, which is the default.
265 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
268 @cindex @samp{-mmnemonic=} option, i386
269 @cindex @samp{-mmnemonic=} option, x86-64
270 @item -mmnemonic=@var{att}
271 @itemx -mmnemonic=@var{intel}
272 This option specifies instruction mnemonic for matching instructions.
273 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
276 @cindex @samp{-msyntax=} option, i386
277 @cindex @samp{-msyntax=} option, x86-64
278 @item -msyntax=@var{att}
279 @itemx -msyntax=@var{intel}
280 This option specifies instruction syntax when processing instructions.
281 The @code{.att_syntax} and @code{.intel_syntax} directives will
284 @cindex @samp{-mnaked-reg} option, i386
285 @cindex @samp{-mnaked-reg} option, x86-64
287 This opetion specifies that registers don't require a @samp{%} prefix.
288 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
290 @cindex @samp{-madd-bnd-prefix} option, i386
291 @cindex @samp{-madd-bnd-prefix} option, x86-64
292 @item -madd-bnd-prefix
293 This option forces the assembler to add BND prefix to all branches, even
294 if such prefix was not explicitly specified in the source code.
296 @cindex @samp{-mbig-obj} option, x86-64
298 On x86-64 PE/COFF target this option forces the use of big object file
299 format, which allows more than 32768 sections.
301 @cindex @samp{-momit-lock-prefix=} option, i386
302 @cindex @samp{-momit-lock-prefix=} option, x86-64
303 @item -momit-lock-prefix=@var{no}
304 @itemx -momit-lock-prefix=@var{yes}
305 These options control how the assembler should encode lock prefix.
306 This option is intended as a workaround for processors, that fail on
307 lock prefix. This option can only be safely used with single-core,
308 single-thread computers
309 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
310 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
311 which is the default.
313 @cindex @samp{-mevexrcig=} option, i386
314 @cindex @samp{-mevexrcig=} option, x86-64
315 @item -mevexrcig=@var{rne}
316 @itemx -mevexrcig=@var{rd}
317 @itemx -mevexrcig=@var{ru}
318 @itemx -mevexrcig=@var{rz}
319 These options control how the assembler should encode SAE-only
320 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
321 of EVEX instruction with 00, which is the default.
322 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
323 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
324 with 01, 10 and 11 RC bits, respectively.
329 @node i386-Directives
330 @section x86 specific Directives
332 @cindex machine directives, x86
333 @cindex x86 machine directives
336 @cindex @code{lcomm} directive, COFF
337 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
338 Reserve @var{length} (an absolute expression) bytes for a local common
339 denoted by @var{symbol}. The section and value of @var{symbol} are
340 those of the new local common. The addresses are allocated in the bss
341 section, so that at run-time the bytes start off zeroed. Since
342 @var{symbol} is not declared global, it is normally not visible to
343 @code{@value{LD}}. The optional third parameter, @var{alignment},
344 specifies the desired alignment of the symbol in the bss section.
346 This directive is only available for COFF based x86 targets.
348 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
354 @section i386 Syntactical Considerations
356 * i386-Variations:: AT&T Syntax versus Intel Syntax
357 * i386-Chars:: Special Characters
360 @node i386-Variations
361 @subsection AT&T Syntax versus Intel Syntax
363 @cindex i386 intel_syntax pseudo op
364 @cindex intel_syntax pseudo op, i386
365 @cindex i386 att_syntax pseudo op
366 @cindex att_syntax pseudo op, i386
367 @cindex i386 syntax compatibility
368 @cindex syntax compatibility, i386
369 @cindex x86-64 intel_syntax pseudo op
370 @cindex intel_syntax pseudo op, x86-64
371 @cindex x86-64 att_syntax pseudo op
372 @cindex att_syntax pseudo op, x86-64
373 @cindex x86-64 syntax compatibility
374 @cindex syntax compatibility, x86-64
376 @code{@value{AS}} now supports assembly using Intel assembler syntax.
377 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
378 back to the usual AT&T mode for compatibility with the output of
379 @code{@value{GCC}}. Either of these directives may have an optional
380 argument, @code{prefix}, or @code{noprefix} specifying whether registers
381 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
382 different from Intel syntax. We mention these differences because
383 almost all 80386 documents use Intel syntax. Notable differences
384 between the two syntaxes are:
386 @cindex immediate operands, i386
387 @cindex i386 immediate operands
388 @cindex register operands, i386
389 @cindex i386 register operands
390 @cindex jump/call operands, i386
391 @cindex i386 jump/call operands
392 @cindex operand delimiters, i386
394 @cindex immediate operands, x86-64
395 @cindex x86-64 immediate operands
396 @cindex register operands, x86-64
397 @cindex x86-64 register operands
398 @cindex jump/call operands, x86-64
399 @cindex x86-64 jump/call operands
400 @cindex operand delimiters, x86-64
403 AT&T immediate operands are preceded by @samp{$}; Intel immediate
404 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
405 AT&T register operands are preceded by @samp{%}; Intel register operands
406 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
407 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
409 @cindex i386 source, destination operands
410 @cindex source, destination operands; i386
411 @cindex x86-64 source, destination operands
412 @cindex source, destination operands; x86-64
414 AT&T and Intel syntax use the opposite order for source and destination
415 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
416 @samp{source, dest} convention is maintained for compatibility with
417 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
418 instructions with 2 immediate operands, such as the @samp{enter}
419 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
421 @cindex mnemonic suffixes, i386
422 @cindex sizes operands, i386
423 @cindex i386 size suffixes
424 @cindex mnemonic suffixes, x86-64
425 @cindex sizes operands, x86-64
426 @cindex x86-64 size suffixes
428 In AT&T syntax the size of memory operands is determined from the last
429 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
430 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
431 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
432 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
433 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
434 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
437 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
438 instruction with the 64-bit displacement or immediate operand.
440 @cindex return instructions, i386
441 @cindex i386 jump, call, return
442 @cindex return instructions, x86-64
443 @cindex x86-64 jump, call, return
445 Immediate form long jumps and calls are
446 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
448 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
450 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
451 @samp{ret far @var{stack-adjust}}.
453 @cindex sections, i386
454 @cindex i386 sections
455 @cindex sections, x86-64
456 @cindex x86-64 sections
458 The AT&T assembler does not provide support for multiple section
459 programs. Unix style systems expect all programs to be single sections.
463 @subsection Special Characters
465 @cindex line comment character, i386
466 @cindex i386 line comment character
467 The presence of a @samp{#} appearing anywhere on a line indicates the
468 start of a comment that extends to the end of that line.
470 If a @samp{#} appears as the first character of a line then the whole
471 line is treated as a comment, but in this case the line can also be a
472 logical line number directive (@pxref{Comments}) or a preprocessor
473 control command (@pxref{Preprocessing}).
475 If the @option{--divide} command line option has not been specified
476 then the @samp{/} character appearing anywhere on a line also
477 introduces a line comment.
479 @cindex line separator, i386
480 @cindex statement separator, i386
481 @cindex i386 line separator
482 The @samp{;} character can be used to separate statements on the same
486 @section Instruction Naming
488 @cindex i386 instruction naming
489 @cindex instruction naming, i386
490 @cindex x86-64 instruction naming
491 @cindex instruction naming, x86-64
493 Instruction mnemonics are suffixed with one character modifiers which
494 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
495 and @samp{q} specify byte, word, long and quadruple word operands. If
496 no suffix is specified by an instruction then @code{@value{AS}} tries to
497 fill in the missing suffix based on the destination register operand
498 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
499 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
500 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
501 assembler which assumes that a missing mnemonic suffix implies long
502 operand size. (This incompatibility does not affect compiler output
503 since compilers always explicitly specify the mnemonic suffix.)
505 Almost all instructions have the same names in AT&T and Intel format.
506 There are a few exceptions. The sign extend and zero extend
507 instructions need two sizes to specify them. They need a size to
508 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
509 is accomplished by using two instruction mnemonic suffixes in AT&T
510 syntax. Base names for sign extend and zero extend are
511 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
512 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
513 are tacked on to this base name, the @emph{from} suffix before the
514 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
515 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
516 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
517 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
518 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
521 @cindex encoding options, i386
522 @cindex encoding options, x86-64
524 Different encoding options can be specified via optional mnemonic
525 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
526 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
527 prefers 8bit or 32bit displacement in encoding.
529 @cindex conversion instructions, i386
530 @cindex i386 conversion instructions
531 @cindex conversion instructions, x86-64
532 @cindex x86-64 conversion instructions
533 The Intel-syntax conversion instructions
537 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
540 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
543 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
546 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
549 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
553 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
554 @samp{%rdx:%rax} (x86-64 only),
558 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
559 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
562 @cindex jump instructions, i386
563 @cindex call instructions, i386
564 @cindex jump instructions, x86-64
565 @cindex call instructions, x86-64
566 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
567 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
570 @section AT&T Mnemonic versus Intel Mnemonic
572 @cindex i386 mnemonic compatibility
573 @cindex mnemonic compatibility, i386
575 @code{@value{AS}} supports assembly using Intel mnemonic.
576 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
577 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
578 syntax for compatibility with the output of @code{@value{GCC}}.
579 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
580 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
581 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
582 assembler with different mnemonics from those in Intel IA32 specification.
583 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
586 @section Register Naming
588 @cindex i386 registers
589 @cindex registers, i386
590 @cindex x86-64 registers
591 @cindex registers, x86-64
592 Register operands are always prefixed with @samp{%}. The 80386 registers
597 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
598 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
599 frame pointer), and @samp{%esp} (the stack pointer).
602 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
603 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
606 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
607 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
608 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
609 @samp{%cx}, and @samp{%dx})
612 the 6 section registers @samp{%cs} (code section), @samp{%ds}
613 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
617 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
621 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
622 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
625 the 2 test registers @samp{%tr6} and @samp{%tr7}.
628 the 8 floating point register stack @samp{%st} or equivalently
629 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
630 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
631 These registers are overloaded by 8 MMX registers @samp{%mm0},
632 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
633 @samp{%mm6} and @samp{%mm7}.
636 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
637 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
640 The AMD x86-64 architecture extends the register set by:
644 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
645 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
646 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
650 the 8 extended registers @samp{%r8}--@samp{%r15}.
653 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
656 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
659 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
662 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
665 the 8 debug registers: @samp{%db8}--@samp{%db15}.
668 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
672 @section Instruction Prefixes
674 @cindex i386 instruction prefixes
675 @cindex instruction prefixes, i386
676 @cindex prefixes, i386
677 Instruction prefixes are used to modify the following instruction. They
678 are used to repeat string instructions, to provide section overrides, to
679 perform bus lock operations, and to change operand and address sizes.
680 (Most instructions that normally operate on 32-bit operands will use
681 16-bit operands if the instruction has an ``operand size'' prefix.)
682 Instruction prefixes are best written on the same line as the instruction
683 they act upon. For example, the @samp{scas} (scan string) instruction is
687 repne scas %es:(%edi),%al
690 You may also place prefixes on the lines immediately preceding the
691 instruction, but this circumvents checks that @code{@value{AS}} does
692 with prefixes, and will not work with all prefixes.
694 Here is a list of instruction prefixes:
696 @cindex section override prefixes, i386
699 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
700 @samp{fs}, @samp{gs}. These are automatically added by specifying
701 using the @var{section}:@var{memory-operand} form for memory references.
703 @cindex size prefixes, i386
705 Operand/Address size prefixes @samp{data16} and @samp{addr16}
706 change 32-bit operands/addresses into 16-bit operands/addresses,
707 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
708 @code{.code16} section) into 32-bit operands/addresses. These prefixes
709 @emph{must} appear on the same line of code as the instruction they
710 modify. For example, in a 16-bit @code{.code16} section, you might
717 @cindex bus lock prefixes, i386
718 @cindex inhibiting interrupts, i386
720 The bus lock prefix @samp{lock} inhibits interrupts during execution of
721 the instruction it precedes. (This is only valid with certain
722 instructions; see a 80386 manual for details).
724 @cindex coprocessor wait, i386
726 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
727 complete the current instruction. This should never be needed for the
728 80386/80387 combination.
730 @cindex repeat prefixes, i386
732 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
733 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
734 times if the current address size is 16-bits).
735 @cindex REX prefixes, i386
737 The @samp{rex} family of prefixes is used by x86-64 to encode
738 extensions to i386 instruction set. The @samp{rex} prefix has four
739 bits --- an operand size overwrite (@code{64}) used to change operand size
740 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
743 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
744 instruction emits @samp{rex} prefix with all the bits set. By omitting
745 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
746 prefixes as well. Normally, there is no need to write the prefixes
747 explicitly, since gas will automatically generate them based on the
748 instruction operands.
752 @section Memory References
754 @cindex i386 memory references
755 @cindex memory references, i386
756 @cindex x86-64 memory references
757 @cindex memory references, x86-64
758 An Intel syntax indirect memory reference of the form
761 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
765 is translated into the AT&T syntax
768 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
772 where @var{base} and @var{index} are the optional 32-bit base and
773 index registers, @var{disp} is the optional displacement, and
774 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
775 to calculate the address of the operand. If no @var{scale} is
776 specified, @var{scale} is taken to be 1. @var{section} specifies the
777 optional section register for the memory operand, and may override the
778 default section register (see a 80386 manual for section register
779 defaults). Note that section overrides in AT&T syntax @emph{must}
780 be preceded by a @samp{%}. If you specify a section override which
781 coincides with the default section register, @code{@value{AS}} does @emph{not}
782 output any section register override prefixes to assemble the given
783 instruction. Thus, section overrides can be specified to emphasize which
784 section register is used for a given memory operand.
786 Here are some examples of Intel and AT&T style memory references:
789 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
790 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
791 missing, and the default section is used (@samp{%ss} for addressing with
792 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
794 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
795 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
796 @samp{foo}. All other fields are missing. The section register here
797 defaults to @samp{%ds}.
799 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
800 This uses the value pointed to by @samp{foo} as a memory operand.
801 Note that @var{base} and @var{index} are both missing, but there is only
802 @emph{one} @samp{,}. This is a syntactic exception.
804 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
805 This selects the contents of the variable @samp{foo} with section
806 register @var{section} being @samp{%gs}.
809 Absolute (as opposed to PC relative) call and jump operands must be
810 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
811 always chooses PC relative addressing for jump/call labels.
813 Any instruction that has a memory operand, but no register operand,
814 @emph{must} specify its size (byte, word, long, or quadruple) with an
815 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
818 The x86-64 architecture adds an RIP (instruction pointer relative)
819 addressing. This addressing mode is specified by using @samp{rip} as a
820 base register. Only constant offsets are valid. For example:
823 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
824 Points to the address 1234 bytes past the end of the current
827 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
828 Points to the @code{symbol} in RIP relative way, this is shorter than
829 the default absolute addressing.
832 Other addressing modes remain unchanged in x86-64 architecture, except
833 registers used are 64-bit instead of 32-bit.
836 @section Handling of Jump Instructions
838 @cindex jump optimization, i386
839 @cindex i386 jump optimization
840 @cindex jump optimization, x86-64
841 @cindex x86-64 jump optimization
842 Jump instructions are always optimized to use the smallest possible
843 displacements. This is accomplished by using byte (8-bit) displacement
844 jumps whenever the target is sufficiently close. If a byte displacement
845 is insufficient a long displacement is used. We do not support
846 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
847 instruction with the @samp{data16} instruction prefix), since the 80386
848 insists upon masking @samp{%eip} to 16 bits after the word displacement
849 is added. (See also @pxref{i386-Arch})
851 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
852 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
853 displacements, so that if you use these instructions (@code{@value{GCC}} does
854 not use them) you may get an error message (and incorrect code). The AT&T
855 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
866 @section Floating Point
868 @cindex i386 floating point
869 @cindex floating point, i386
870 @cindex x86-64 floating point
871 @cindex floating point, x86-64
872 All 80387 floating point types except packed BCD are supported.
873 (BCD support may be added without much difficulty). These data
874 types are 16-, 32-, and 64- bit integers, and single (32-bit),
875 double (64-bit), and extended (80-bit) precision floating point.
876 Each supported type has an instruction mnemonic suffix and a constructor
877 associated with it. Instruction mnemonic suffixes specify the operand's
878 data type. Constructors build these data types into memory.
880 @cindex @code{float} directive, i386
881 @cindex @code{single} directive, i386
882 @cindex @code{double} directive, i386
883 @cindex @code{tfloat} directive, i386
884 @cindex @code{float} directive, x86-64
885 @cindex @code{single} directive, x86-64
886 @cindex @code{double} directive, x86-64
887 @cindex @code{tfloat} directive, x86-64
890 Floating point constructors are @samp{.float} or @samp{.single},
891 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
892 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
893 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
894 only supports this format via the @samp{fldt} (load 80-bit real to stack
895 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
897 @cindex @code{word} directive, i386
898 @cindex @code{long} directive, i386
899 @cindex @code{int} directive, i386
900 @cindex @code{quad} directive, i386
901 @cindex @code{word} directive, x86-64
902 @cindex @code{long} directive, x86-64
903 @cindex @code{int} directive, x86-64
904 @cindex @code{quad} directive, x86-64
906 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
907 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
908 corresponding instruction mnemonic suffixes are @samp{s} (single),
909 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
910 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
911 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
915 Register to register operations should not use instruction mnemonic suffixes.
916 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
917 wrote @samp{fst %st, %st(1)}, since all register to register operations
918 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
919 which converts @samp{%st} from 80-bit to 64-bit floating point format,
920 then stores the result in the 4 byte location @samp{mem})
923 @section Intel's MMX and AMD's 3DNow! SIMD Operations
929 @cindex 3DNow!, x86-64
932 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
933 instructions for integer data), available on Intel's Pentium MMX
934 processors and Pentium II processors, AMD's K6 and K6-2 processors,
935 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
936 instruction set (SIMD instructions for 32-bit floating point data)
937 available on AMD's K6-2 processor and possibly others in the future.
939 Currently, @code{@value{AS}} does not support Intel's floating point
942 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
943 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
944 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
945 floating point values. The MMX registers cannot be used at the same time
946 as the floating point stack.
948 See Intel and AMD documentation, keeping in mind that the operand order in
949 instructions is reversed from the Intel syntax.
952 @section AMD's Lightweight Profiling Instructions
957 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
958 instruction set, available on AMD's Family 15h (Orochi) processors.
960 LWP enables applications to collect and manage performance data, and
961 react to performance events. The collection of performance data
962 requires no context switches. LWP runs in the context of a thread and
963 so several counters can be used independently across multiple threads.
964 LWP can be used in both 64-bit and legacy 32-bit modes.
966 For detailed information on the LWP instruction set, see the
967 @cite{AMD Lightweight Profiling Specification} available at
968 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
971 @section Bit Manipulation Instructions
976 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
978 BMI instructions provide several instructions implementing individual
979 bit manipulation operations such as isolation, masking, setting, or
982 @c Need to add a specification citation here when available.
985 @section AMD's Trailing Bit Manipulation Instructions
990 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
991 instruction set, available on AMD's BDVER2 processors (Trinity and
994 TBM instructions provide instructions implementing individual bit
995 manipulation operations such as isolating, masking, setting, resetting,
996 complementing, and operations on trailing zeros and ones.
998 @c Need to add a specification citation here when available.
1001 @section Writing 16-bit Code
1003 @cindex i386 16-bit code
1004 @cindex 16-bit code, i386
1005 @cindex real-mode code, i386
1006 @cindex @code{code16gcc} directive, i386
1007 @cindex @code{code16} directive, i386
1008 @cindex @code{code32} directive, i386
1009 @cindex @code{code64} directive, i386
1010 @cindex @code{code64} directive, x86-64
1011 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1012 or 64-bit x86-64 code depending on the default configuration,
1013 it also supports writing code to run in real mode or in 16-bit protected
1014 mode code segments. To do this, put a @samp{.code16} or
1015 @samp{.code16gcc} directive before the assembly language instructions to
1016 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1017 32-bit code with the @samp{.code32} directive or 64-bit code with the
1018 @samp{.code64} directive.
1020 @samp{.code16gcc} provides experimental support for generating 16-bit
1021 code from gcc, and differs from @samp{.code16} in that @samp{call},
1022 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1023 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1024 default to 32-bit size. This is so that the stack pointer is
1025 manipulated in the same way over function calls, allowing access to
1026 function parameters at the same stack offsets as in 32-bit mode.
1027 @samp{.code16gcc} also automatically adds address size prefixes where
1028 necessary to use the 32-bit addressing modes that gcc generates.
1030 The code which @code{@value{AS}} generates in 16-bit mode will not
1031 necessarily run on a 16-bit pre-80386 processor. To write code that
1032 runs on such a processor, you must refrain from using @emph{any} 32-bit
1033 constructs which require @code{@value{AS}} to output address or operand
1036 Note that writing 16-bit code instructions by explicitly specifying a
1037 prefix or an instruction mnemonic suffix within a 32-bit code section
1038 generates different machine instructions than those generated for a
1039 16-bit code segment. In a 32-bit code section, the following code
1040 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1041 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1047 The same code in a 16-bit code section would generate the machine
1048 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1049 is correct since the processor default operand size is assumed to be 16
1050 bits in a 16-bit code section.
1053 @section AT&T Syntax bugs
1055 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1056 assemblers, generate floating point instructions with reversed source
1057 and destination registers in certain cases. Unfortunately, gcc and
1058 possibly many other programs use this reversed syntax, so we're stuck
1067 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1068 than the expected @samp{%st(3) - %st}. This happens with all the
1069 non-commutative arithmetic floating point operations with two register
1070 operands where the source register is @samp{%st} and the destination
1071 register is @samp{%st(i)}.
1074 @section Specifying CPU Architecture
1076 @cindex arch directive, i386
1077 @cindex i386 arch directive
1078 @cindex arch directive, x86-64
1079 @cindex x86-64 arch directive
1081 @code{@value{AS}} may be told to assemble for a particular CPU
1082 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1083 directive enables a warning when gas detects an instruction that is not
1084 supported on the CPU specified. The choices for @var{cpu_type} are:
1086 @multitable @columnfractions .20 .20 .20 .20
1087 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1088 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1089 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1090 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1091 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1092 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1093 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1094 @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
1095 @item @samp{generic32} @tab @samp{generic64}
1096 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1097 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1098 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1099 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1100 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1101 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1102 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1103 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1104 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1105 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1106 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1107 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq}
1108 @item @samp{.clwb} @tab @samp{.pcommit}
1109 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1110 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1111 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1112 @item @samp{.padlock}
1115 Apart from the warning, there are only two other effects on
1116 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1117 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1118 will automatically use a two byte opcode sequence. The larger three
1119 byte opcode sequence is used on the 486 (and when no architecture is
1120 specified) because it executes faster on the 486. Note that you can
1121 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1122 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1123 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1124 conditional jumps will be promoted when necessary to a two instruction
1125 sequence consisting of a conditional jump of the opposite sense around
1126 an unconditional jump to the target.
1128 Following the CPU architecture (but not a sub-architecture, which are those
1129 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1130 control automatic promotion of conditional jumps. @samp{jumps} is the
1131 default, and enables jump promotion; All external jumps will be of the long
1132 variety, and file-local jumps will be promoted as necessary.
1133 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1134 byte offset jumps, and warns about file-local conditional jumps that
1135 @code{@value{AS}} promotes.
1136 Unconditional jumps are treated as for @samp{jumps}.
1147 @cindex i386 @code{mul}, @code{imul} instructions
1148 @cindex @code{mul} instruction, i386
1149 @cindex @code{imul} instruction, i386
1150 @cindex @code{mul} instruction, x86-64
1151 @cindex @code{imul} instruction, x86-64
1152 There is some trickery concerning the @samp{mul} and @samp{imul}
1153 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1154 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1155 for @samp{imul}) can be output only in the one operand form. Thus,
1156 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1157 the expanding multiply would clobber the @samp{%edx} register, and this
1158 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1159 64-bit product in @samp{%edx:%eax}.
1161 We have added a two operand form of @samp{imul} when the first operand
1162 is an immediate mode expression and the second operand is a register.
1163 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1164 example, can be done with @samp{imul $69, %eax} rather than @samp{imul