1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
11 @chapter 80386 Dependent Features
14 @node Machine Dependencies
15 @chapter 80386 Dependent Features
19 @cindex i80386 support
20 @cindex x86-64 support
22 The i386 version @code{@value{AS}} supports both the original Intel 386
23 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
24 extending the Intel architecture to 64-bits.
27 * i386-Options:: Options
28 * i386-Directives:: X86 specific directives
29 * i386-Syntax:: Syntactical considerations
30 * i386-Mnemonics:: Instruction Naming
31 * i386-Regs:: Register Naming
32 * i386-Prefixes:: Instruction Prefixes
33 * i386-Memory:: Memory References
34 * i386-Jumps:: Handling of Jump Instructions
35 * i386-Float:: Floating Point
36 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
37 * i386-LWP:: AMD's Lightweight Profiling Instructions
38 * i386-BMI:: Bit Manipulation Instruction
39 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
40 * i386-16bit:: Writing 16-bit Code
41 * i386-Arch:: Specifying an x86 CPU architecture
42 * i386-Bugs:: AT&T Syntax bugs
49 @cindex options for i386
50 @cindex options for x86-64
52 @cindex x86-64 options
54 The i386 version of @code{@value{AS}} has a few machine
59 @cindex @samp{--32} option, i386
60 @cindex @samp{--32} option, x86-64
61 @cindex @samp{--x32} option, i386
62 @cindex @samp{--x32} option, x86-64
63 @cindex @samp{--64} option, i386
64 @cindex @samp{--64} option, x86-64
65 @item --32 | --x32 | --64
66 Select the word size, either 32 bits or 64 bits. @samp{--32}
67 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
68 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
71 These options are only available with the ELF object file format, and
72 require that the necessary BFD support has been included (on a 32-bit
73 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
74 usage and use x86-64 as target platform).
77 By default, x86 GAS replaces multiple nop instructions used for
78 alignment within code sections with multi-byte nop instructions such
79 as leal 0(%esi,1),%esi. This switch disables the optimization.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics. For example,
131 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
132 @var{vmx}. The following extensions are currently supported:
188 Note that rather than extending a basic instruction set, the extension
189 mnemonics starting with @code{no} revoke the respective functionality.
191 When the @code{.arch} directive is used with @option{-march}, the
192 @code{.arch} directive will take precedent.
194 @cindex @samp{-mtune=} option, i386
195 @cindex @samp{-mtune=} option, x86-64
196 @item -mtune=@var{CPU}
197 This option specifies a processor to optimize for. When used in
198 conjunction with the @option{-march} option, only instructions
199 of the processor specified by the @option{-march} option will be
202 Valid @var{CPU} values are identical to the processor list of
203 @option{-march=@var{CPU}}.
205 @cindex @samp{-msse2avx} option, i386
206 @cindex @samp{-msse2avx} option, x86-64
208 This option specifies that the assembler should encode SSE instructions
211 @cindex @samp{-msse-check=} option, i386
212 @cindex @samp{-msse-check=} option, x86-64
213 @item -msse-check=@var{none}
214 @itemx -msse-check=@var{warning}
215 @itemx -msse-check=@var{error}
216 These options control if the assembler should check SSE intructions.
217 @option{-msse-check=@var{none}} will make the assembler not to check SSE
218 instructions, which is the default. @option{-msse-check=@var{warning}}
219 will make the assembler issue a warning for any SSE intruction.
220 @option{-msse-check=@var{error}} will make the assembler issue an error
221 for any SSE intruction.
223 @cindex @samp{-mavxscalar=} option, i386
224 @cindex @samp{-mavxscalar=} option, x86-64
225 @item -mavxscalar=@var{128}
226 @itemx -mavxscalar=@var{256}
227 These options control how the assembler should encode scalar AVX
228 instructions. @option{-mavxscalar=@var{128}} will encode scalar
229 AVX instructions with 128bit vector length, which is the default.
230 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
231 with 256bit vector length.
233 @cindex @samp{-mmnemonic=} option, i386
234 @cindex @samp{-mmnemonic=} option, x86-64
235 @item -mmnemonic=@var{att}
236 @itemx -mmnemonic=@var{intel}
237 This option specifies instruction mnemonic for matching instructions.
238 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
241 @cindex @samp{-msyntax=} option, i386
242 @cindex @samp{-msyntax=} option, x86-64
243 @item -msyntax=@var{att}
244 @itemx -msyntax=@var{intel}
245 This option specifies instruction syntax when processing instructions.
246 The @code{.att_syntax} and @code{.intel_syntax} directives will
249 @cindex @samp{-mnaked-reg} option, i386
250 @cindex @samp{-mnaked-reg} option, x86-64
252 This opetion specifies that registers don't require a @samp{%} prefix.
253 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
255 @cindex @samp{-madd-bnd-prefix} option, i386
256 @cindex @samp{-madd-bnd-prefix} option, x86-64
257 @item -madd-bnd-prefix
258 This option forces the assembler to add BND prefix to all branches, even
259 if such prefix was not explicitly specified in the source code.
264 @node i386-Directives
265 @section x86 specific Directives
267 @cindex machine directives, x86
268 @cindex x86 machine directives
271 @cindex @code{lcomm} directive, COFF
272 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
273 Reserve @var{length} (an absolute expression) bytes for a local common
274 denoted by @var{symbol}. The section and value of @var{symbol} are
275 those of the new local common. The addresses are allocated in the bss
276 section, so that at run-time the bytes start off zeroed. Since
277 @var{symbol} is not declared global, it is normally not visible to
278 @code{@value{LD}}. The optional third parameter, @var{alignment},
279 specifies the desired alignment of the symbol in the bss section.
281 This directive is only available for COFF based x86 targets.
283 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
289 @section i386 Syntactical Considerations
291 * i386-Variations:: AT&T Syntax versus Intel Syntax
292 * i386-Chars:: Special Characters
295 @node i386-Variations
296 @subsection AT&T Syntax versus Intel Syntax
298 @cindex i386 intel_syntax pseudo op
299 @cindex intel_syntax pseudo op, i386
300 @cindex i386 att_syntax pseudo op
301 @cindex att_syntax pseudo op, i386
302 @cindex i386 syntax compatibility
303 @cindex syntax compatibility, i386
304 @cindex x86-64 intel_syntax pseudo op
305 @cindex intel_syntax pseudo op, x86-64
306 @cindex x86-64 att_syntax pseudo op
307 @cindex att_syntax pseudo op, x86-64
308 @cindex x86-64 syntax compatibility
309 @cindex syntax compatibility, x86-64
311 @code{@value{AS}} now supports assembly using Intel assembler syntax.
312 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
313 back to the usual AT&T mode for compatibility with the output of
314 @code{@value{GCC}}. Either of these directives may have an optional
315 argument, @code{prefix}, or @code{noprefix} specifying whether registers
316 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
317 different from Intel syntax. We mention these differences because
318 almost all 80386 documents use Intel syntax. Notable differences
319 between the two syntaxes are:
321 @cindex immediate operands, i386
322 @cindex i386 immediate operands
323 @cindex register operands, i386
324 @cindex i386 register operands
325 @cindex jump/call operands, i386
326 @cindex i386 jump/call operands
327 @cindex operand delimiters, i386
329 @cindex immediate operands, x86-64
330 @cindex x86-64 immediate operands
331 @cindex register operands, x86-64
332 @cindex x86-64 register operands
333 @cindex jump/call operands, x86-64
334 @cindex x86-64 jump/call operands
335 @cindex operand delimiters, x86-64
338 AT&T immediate operands are preceded by @samp{$}; Intel immediate
339 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
340 AT&T register operands are preceded by @samp{%}; Intel register operands
341 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
342 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
344 @cindex i386 source, destination operands
345 @cindex source, destination operands; i386
346 @cindex x86-64 source, destination operands
347 @cindex source, destination operands; x86-64
349 AT&T and Intel syntax use the opposite order for source and destination
350 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
351 @samp{source, dest} convention is maintained for compatibility with
352 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
353 instructions with 2 immediate operands, such as the @samp{enter}
354 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
356 @cindex mnemonic suffixes, i386
357 @cindex sizes operands, i386
358 @cindex i386 size suffixes
359 @cindex mnemonic suffixes, x86-64
360 @cindex sizes operands, x86-64
361 @cindex x86-64 size suffixes
363 In AT&T syntax the size of memory operands is determined from the last
364 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
365 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
366 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
367 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
368 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
369 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
372 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
373 instruction with the 64-bit displacement or immediate operand.
375 @cindex return instructions, i386
376 @cindex i386 jump, call, return
377 @cindex return instructions, x86-64
378 @cindex x86-64 jump, call, return
380 Immediate form long jumps and calls are
381 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
383 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
385 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
386 @samp{ret far @var{stack-adjust}}.
388 @cindex sections, i386
389 @cindex i386 sections
390 @cindex sections, x86-64
391 @cindex x86-64 sections
393 The AT&T assembler does not provide support for multiple section
394 programs. Unix style systems expect all programs to be single sections.
398 @subsection Special Characters
400 @cindex line comment character, i386
401 @cindex i386 line comment character
402 The presence of a @samp{#} appearing anywhere on a line indicates the
403 start of a comment that extends to the end of that line.
405 If a @samp{#} appears as the first character of a line then the whole
406 line is treated as a comment, but in this case the line can also be a
407 logical line number directive (@pxref{Comments}) or a preprocessor
408 control command (@pxref{Preprocessing}).
410 If the @option{--divide} command line option has not been specified
411 then the @samp{/} character appearing anywhere on a line also
412 introduces a line comment.
414 @cindex line separator, i386
415 @cindex statement separator, i386
416 @cindex i386 line separator
417 The @samp{;} character can be used to separate statements on the same
421 @section Instruction Naming
423 @cindex i386 instruction naming
424 @cindex instruction naming, i386
425 @cindex x86-64 instruction naming
426 @cindex instruction naming, x86-64
428 Instruction mnemonics are suffixed with one character modifiers which
429 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
430 and @samp{q} specify byte, word, long and quadruple word operands. If
431 no suffix is specified by an instruction then @code{@value{AS}} tries to
432 fill in the missing suffix based on the destination register operand
433 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
434 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
435 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
436 assembler which assumes that a missing mnemonic suffix implies long
437 operand size. (This incompatibility does not affect compiler output
438 since compilers always explicitly specify the mnemonic suffix.)
440 Almost all instructions have the same names in AT&T and Intel format.
441 There are a few exceptions. The sign extend and zero extend
442 instructions need two sizes to specify them. They need a size to
443 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
444 is accomplished by using two instruction mnemonic suffixes in AT&T
445 syntax. Base names for sign extend and zero extend are
446 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
447 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
448 are tacked on to this base name, the @emph{from} suffix before the
449 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
450 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
451 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
452 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
453 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
456 @cindex encoding options, i386
457 @cindex encoding options, x86-64
459 Different encoding options can be specified via optional mnemonic
460 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
461 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
462 prefers 8bit or 32bit displacement in encoding.
464 @cindex conversion instructions, i386
465 @cindex i386 conversion instructions
466 @cindex conversion instructions, x86-64
467 @cindex x86-64 conversion instructions
468 The Intel-syntax conversion instructions
472 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
475 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
478 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
481 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
484 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
488 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
489 @samp{%rdx:%rax} (x86-64 only),
493 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
494 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
497 @cindex jump instructions, i386
498 @cindex call instructions, i386
499 @cindex jump instructions, x86-64
500 @cindex call instructions, x86-64
501 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
502 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
505 @section AT&T Mnemonic versus Intel Mnemonic
507 @cindex i386 mnemonic compatibility
508 @cindex mnemonic compatibility, i386
510 @code{@value{AS}} supports assembly using Intel mnemonic.
511 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
512 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
513 syntax for compatibility with the output of @code{@value{GCC}}.
514 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
515 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
516 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
517 assembler with different mnemonics from those in Intel IA32 specification.
518 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
521 @section Register Naming
523 @cindex i386 registers
524 @cindex registers, i386
525 @cindex x86-64 registers
526 @cindex registers, x86-64
527 Register operands are always prefixed with @samp{%}. The 80386 registers
532 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
533 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
534 frame pointer), and @samp{%esp} (the stack pointer).
537 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
538 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
541 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
542 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
543 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
544 @samp{%cx}, and @samp{%dx})
547 the 6 section registers @samp{%cs} (code section), @samp{%ds}
548 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
552 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
556 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
557 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
560 the 2 test registers @samp{%tr6} and @samp{%tr7}.
563 the 8 floating point register stack @samp{%st} or equivalently
564 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
565 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
566 These registers are overloaded by 8 MMX registers @samp{%mm0},
567 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
568 @samp{%mm6} and @samp{%mm7}.
571 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
572 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
575 The AMD x86-64 architecture extends the register set by:
579 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
580 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
581 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
585 the 8 extended registers @samp{%r8}--@samp{%r15}.
588 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
591 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
594 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
597 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
600 the 8 debug registers: @samp{%db8}--@samp{%db15}.
603 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
607 @section Instruction Prefixes
609 @cindex i386 instruction prefixes
610 @cindex instruction prefixes, i386
611 @cindex prefixes, i386
612 Instruction prefixes are used to modify the following instruction. They
613 are used to repeat string instructions, to provide section overrides, to
614 perform bus lock operations, and to change operand and address sizes.
615 (Most instructions that normally operate on 32-bit operands will use
616 16-bit operands if the instruction has an ``operand size'' prefix.)
617 Instruction prefixes are best written on the same line as the instruction
618 they act upon. For example, the @samp{scas} (scan string) instruction is
622 repne scas %es:(%edi),%al
625 You may also place prefixes on the lines immediately preceding the
626 instruction, but this circumvents checks that @code{@value{AS}} does
627 with prefixes, and will not work with all prefixes.
629 Here is a list of instruction prefixes:
631 @cindex section override prefixes, i386
634 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
635 @samp{fs}, @samp{gs}. These are automatically added by specifying
636 using the @var{section}:@var{memory-operand} form for memory references.
638 @cindex size prefixes, i386
640 Operand/Address size prefixes @samp{data16} and @samp{addr16}
641 change 32-bit operands/addresses into 16-bit operands/addresses,
642 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
643 @code{.code16} section) into 32-bit operands/addresses. These prefixes
644 @emph{must} appear on the same line of code as the instruction they
645 modify. For example, in a 16-bit @code{.code16} section, you might
652 @cindex bus lock prefixes, i386
653 @cindex inhibiting interrupts, i386
655 The bus lock prefix @samp{lock} inhibits interrupts during execution of
656 the instruction it precedes. (This is only valid with certain
657 instructions; see a 80386 manual for details).
659 @cindex coprocessor wait, i386
661 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
662 complete the current instruction. This should never be needed for the
663 80386/80387 combination.
665 @cindex repeat prefixes, i386
667 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
668 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
669 times if the current address size is 16-bits).
670 @cindex REX prefixes, i386
672 The @samp{rex} family of prefixes is used by x86-64 to encode
673 extensions to i386 instruction set. The @samp{rex} prefix has four
674 bits --- an operand size overwrite (@code{64}) used to change operand size
675 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
678 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
679 instruction emits @samp{rex} prefix with all the bits set. By omitting
680 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
681 prefixes as well. Normally, there is no need to write the prefixes
682 explicitly, since gas will automatically generate them based on the
683 instruction operands.
687 @section Memory References
689 @cindex i386 memory references
690 @cindex memory references, i386
691 @cindex x86-64 memory references
692 @cindex memory references, x86-64
693 An Intel syntax indirect memory reference of the form
696 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
700 is translated into the AT&T syntax
703 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
707 where @var{base} and @var{index} are the optional 32-bit base and
708 index registers, @var{disp} is the optional displacement, and
709 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
710 to calculate the address of the operand. If no @var{scale} is
711 specified, @var{scale} is taken to be 1. @var{section} specifies the
712 optional section register for the memory operand, and may override the
713 default section register (see a 80386 manual for section register
714 defaults). Note that section overrides in AT&T syntax @emph{must}
715 be preceded by a @samp{%}. If you specify a section override which
716 coincides with the default section register, @code{@value{AS}} does @emph{not}
717 output any section register override prefixes to assemble the given
718 instruction. Thus, section overrides can be specified to emphasize which
719 section register is used for a given memory operand.
721 Here are some examples of Intel and AT&T style memory references:
724 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
725 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
726 missing, and the default section is used (@samp{%ss} for addressing with
727 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
729 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
730 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
731 @samp{foo}. All other fields are missing. The section register here
732 defaults to @samp{%ds}.
734 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
735 This uses the value pointed to by @samp{foo} as a memory operand.
736 Note that @var{base} and @var{index} are both missing, but there is only
737 @emph{one} @samp{,}. This is a syntactic exception.
739 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
740 This selects the contents of the variable @samp{foo} with section
741 register @var{section} being @samp{%gs}.
744 Absolute (as opposed to PC relative) call and jump operands must be
745 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
746 always chooses PC relative addressing for jump/call labels.
748 Any instruction that has a memory operand, but no register operand,
749 @emph{must} specify its size (byte, word, long, or quadruple) with an
750 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
753 The x86-64 architecture adds an RIP (instruction pointer relative)
754 addressing. This addressing mode is specified by using @samp{rip} as a
755 base register. Only constant offsets are valid. For example:
758 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
759 Points to the address 1234 bytes past the end of the current
762 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
763 Points to the @code{symbol} in RIP relative way, this is shorter than
764 the default absolute addressing.
767 Other addressing modes remain unchanged in x86-64 architecture, except
768 registers used are 64-bit instead of 32-bit.
771 @section Handling of Jump Instructions
773 @cindex jump optimization, i386
774 @cindex i386 jump optimization
775 @cindex jump optimization, x86-64
776 @cindex x86-64 jump optimization
777 Jump instructions are always optimized to use the smallest possible
778 displacements. This is accomplished by using byte (8-bit) displacement
779 jumps whenever the target is sufficiently close. If a byte displacement
780 is insufficient a long displacement is used. We do not support
781 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
782 instruction with the @samp{data16} instruction prefix), since the 80386
783 insists upon masking @samp{%eip} to 16 bits after the word displacement
784 is added. (See also @pxref{i386-Arch})
786 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
787 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
788 displacements, so that if you use these instructions (@code{@value{GCC}} does
789 not use them) you may get an error message (and incorrect code). The AT&T
790 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
801 @section Floating Point
803 @cindex i386 floating point
804 @cindex floating point, i386
805 @cindex x86-64 floating point
806 @cindex floating point, x86-64
807 All 80387 floating point types except packed BCD are supported.
808 (BCD support may be added without much difficulty). These data
809 types are 16-, 32-, and 64- bit integers, and single (32-bit),
810 double (64-bit), and extended (80-bit) precision floating point.
811 Each supported type has an instruction mnemonic suffix and a constructor
812 associated with it. Instruction mnemonic suffixes specify the operand's
813 data type. Constructors build these data types into memory.
815 @cindex @code{float} directive, i386
816 @cindex @code{single} directive, i386
817 @cindex @code{double} directive, i386
818 @cindex @code{tfloat} directive, i386
819 @cindex @code{float} directive, x86-64
820 @cindex @code{single} directive, x86-64
821 @cindex @code{double} directive, x86-64
822 @cindex @code{tfloat} directive, x86-64
825 Floating point constructors are @samp{.float} or @samp{.single},
826 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
827 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
828 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
829 only supports this format via the @samp{fldt} (load 80-bit real to stack
830 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
832 @cindex @code{word} directive, i386
833 @cindex @code{long} directive, i386
834 @cindex @code{int} directive, i386
835 @cindex @code{quad} directive, i386
836 @cindex @code{word} directive, x86-64
837 @cindex @code{long} directive, x86-64
838 @cindex @code{int} directive, x86-64
839 @cindex @code{quad} directive, x86-64
841 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
842 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
843 corresponding instruction mnemonic suffixes are @samp{s} (single),
844 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
845 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
846 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
850 Register to register operations should not use instruction mnemonic suffixes.
851 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
852 wrote @samp{fst %st, %st(1)}, since all register to register operations
853 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
854 which converts @samp{%st} from 80-bit to 64-bit floating point format,
855 then stores the result in the 4 byte location @samp{mem})
858 @section Intel's MMX and AMD's 3DNow! SIMD Operations
864 @cindex 3DNow!, x86-64
867 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
868 instructions for integer data), available on Intel's Pentium MMX
869 processors and Pentium II processors, AMD's K6 and K6-2 processors,
870 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
871 instruction set (SIMD instructions for 32-bit floating point data)
872 available on AMD's K6-2 processor and possibly others in the future.
874 Currently, @code{@value{AS}} does not support Intel's floating point
877 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
878 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
879 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
880 floating point values. The MMX registers cannot be used at the same time
881 as the floating point stack.
883 See Intel and AMD documentation, keeping in mind that the operand order in
884 instructions is reversed from the Intel syntax.
887 @section AMD's Lightweight Profiling Instructions
892 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
893 instruction set, available on AMD's Family 15h (Orochi) processors.
895 LWP enables applications to collect and manage performance data, and
896 react to performance events. The collection of performance data
897 requires no context switches. LWP runs in the context of a thread and
898 so several counters can be used independently across multiple threads.
899 LWP can be used in both 64-bit and legacy 32-bit modes.
901 For detailed information on the LWP instruction set, see the
902 @cite{AMD Lightweight Profiling Specification} available at
903 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
906 @section Bit Manipulation Instructions
911 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
913 BMI instructions provide several instructions implementing individual
914 bit manipulation operations such as isolation, masking, setting, or
917 @c Need to add a specification citation here when available.
920 @section AMD's Trailing Bit Manipulation Instructions
925 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
926 instruction set, available on AMD's BDVER2 processors (Trinity and
929 TBM instructions provide instructions implementing individual bit
930 manipulation operations such as isolating, masking, setting, resetting,
931 complementing, and operations on trailing zeros and ones.
933 @c Need to add a specification citation here when available.
936 @section Writing 16-bit Code
938 @cindex i386 16-bit code
939 @cindex 16-bit code, i386
940 @cindex real-mode code, i386
941 @cindex @code{code16gcc} directive, i386
942 @cindex @code{code16} directive, i386
943 @cindex @code{code32} directive, i386
944 @cindex @code{code64} directive, i386
945 @cindex @code{code64} directive, x86-64
946 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
947 or 64-bit x86-64 code depending on the default configuration,
948 it also supports writing code to run in real mode or in 16-bit protected
949 mode code segments. To do this, put a @samp{.code16} or
950 @samp{.code16gcc} directive before the assembly language instructions to
951 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
952 32-bit code with the @samp{.code32} directive or 64-bit code with the
953 @samp{.code64} directive.
955 @samp{.code16gcc} provides experimental support for generating 16-bit
956 code from gcc, and differs from @samp{.code16} in that @samp{call},
957 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
958 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
959 default to 32-bit size. This is so that the stack pointer is
960 manipulated in the same way over function calls, allowing access to
961 function parameters at the same stack offsets as in 32-bit mode.
962 @samp{.code16gcc} also automatically adds address size prefixes where
963 necessary to use the 32-bit addressing modes that gcc generates.
965 The code which @code{@value{AS}} generates in 16-bit mode will not
966 necessarily run on a 16-bit pre-80386 processor. To write code that
967 runs on such a processor, you must refrain from using @emph{any} 32-bit
968 constructs which require @code{@value{AS}} to output address or operand
971 Note that writing 16-bit code instructions by explicitly specifying a
972 prefix or an instruction mnemonic suffix within a 32-bit code section
973 generates different machine instructions than those generated for a
974 16-bit code segment. In a 32-bit code section, the following code
975 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
976 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
982 The same code in a 16-bit code section would generate the machine
983 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
984 is correct since the processor default operand size is assumed to be 16
985 bits in a 16-bit code section.
988 @section AT&T Syntax bugs
990 The UnixWare assembler, and probably other AT&T derived ix86 Unix
991 assemblers, generate floating point instructions with reversed source
992 and destination registers in certain cases. Unfortunately, gcc and
993 possibly many other programs use this reversed syntax, so we're stuck
1002 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1003 than the expected @samp{%st(3) - %st}. This happens with all the
1004 non-commutative arithmetic floating point operations with two register
1005 operands where the source register is @samp{%st} and the destination
1006 register is @samp{%st(i)}.
1009 @section Specifying CPU Architecture
1011 @cindex arch directive, i386
1012 @cindex i386 arch directive
1013 @cindex arch directive, x86-64
1014 @cindex x86-64 arch directive
1016 @code{@value{AS}} may be told to assemble for a particular CPU
1017 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1018 directive enables a warning when gas detects an instruction that is not
1019 supported on the CPU specified. The choices for @var{cpu_type} are:
1021 @multitable @columnfractions .20 .20 .20 .20
1022 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1023 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1024 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1025 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1026 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1027 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1028 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1029 @item @samp{btver1} @tab @samp{btver2}
1030 @item @samp{generic32} @tab @samp{generic64}
1031 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1032 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1033 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1034 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1035 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1036 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1037 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1038 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1039 @item @samp{.smap} @tab @samp{.mpx}
1040 @item @samp{.smap} @tab @samp{.sha}
1041 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1042 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1043 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1044 @item @samp{.padlock}
1047 Apart from the warning, there are only two other effects on
1048 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1049 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1050 will automatically use a two byte opcode sequence. The larger three
1051 byte opcode sequence is used on the 486 (and when no architecture is
1052 specified) because it executes faster on the 486. Note that you can
1053 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1054 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1055 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1056 conditional jumps will be promoted when necessary to a two instruction
1057 sequence consisting of a conditional jump of the opposite sense around
1058 an unconditional jump to the target.
1060 Following the CPU architecture (but not a sub-architecture, which are those
1061 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1062 control automatic promotion of conditional jumps. @samp{jumps} is the
1063 default, and enables jump promotion; All external jumps will be of the long
1064 variety, and file-local jumps will be promoted as necessary.
1065 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1066 byte offset jumps, and warns about file-local conditional jumps that
1067 @code{@value{AS}} promotes.
1068 Unconditional jumps are treated as for @samp{jumps}.
1079 @cindex i386 @code{mul}, @code{imul} instructions
1080 @cindex @code{mul} instruction, i386
1081 @cindex @code{imul} instruction, i386
1082 @cindex @code{mul} instruction, x86-64
1083 @cindex @code{imul} instruction, x86-64
1084 There is some trickery concerning the @samp{mul} and @samp{imul}
1085 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1086 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1087 for @samp{imul}) can be output only in the one operand form. Thus,
1088 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1089 the expanding multiply would clobber the @samp{%edx} register, and this
1090 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1091 64-bit product in @samp{%edx:%eax}.
1093 We have added a two operand form of @samp{imul} when the first operand
1094 is an immediate mode expression and the second operand is a register.
1095 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1096 example, can be done with @samp{imul $69, %eax} rather than @samp{imul