1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
47 @cindex options for i386
48 @cindex options for x86-64
50 @cindex x86-64 options
52 The i386 version of @code{@value{AS}} has a few machine
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization.
79 @cindex @samp{--divide} option, i386
81 On SVR4-derived platforms, the character @samp{/} is treated as a comment
82 character, which means that it cannot be used in expressions. The
83 @samp{--divide} option turns @samp{/} into a normal character. This does
84 not disable @samp{/} at the beginning of a line starting a comment, or
85 affect using @samp{#} for starting a comment.
87 @cindex @samp{-march=} option, i386
88 @cindex @samp{-march=} option, x86-64
89 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
90 This option specifies the target processor. The assembler will
91 issue an error message if an attempt is made to assemble an instruction
92 which will not execute on the target processor. The following
93 processor names are recognized:
128 In addition to the basic instruction set, the assembler can be told to
129 accept various extension mnemonics. For example,
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
131 @var{vmx}. The following extensions are currently supported:
200 Note that rather than extending a basic instruction set, the extension
201 mnemonics starting with @code{no} revoke the respective functionality.
203 When the @code{.arch} directive is used with @option{-march}, the
204 @code{.arch} directive will take precedent.
206 @cindex @samp{-mtune=} option, i386
207 @cindex @samp{-mtune=} option, x86-64
208 @item -mtune=@var{CPU}
209 This option specifies a processor to optimize for. When used in
210 conjunction with the @option{-march} option, only instructions
211 of the processor specified by the @option{-march} option will be
214 Valid @var{CPU} values are identical to the processor list of
215 @option{-march=@var{CPU}}.
217 @cindex @samp{-msse2avx} option, i386
218 @cindex @samp{-msse2avx} option, x86-64
220 This option specifies that the assembler should encode SSE instructions
223 @cindex @samp{-msse-check=} option, i386
224 @cindex @samp{-msse-check=} option, x86-64
225 @item -msse-check=@var{none}
226 @itemx -msse-check=@var{warning}
227 @itemx -msse-check=@var{error}
228 These options control if the assembler should check SSE instructions.
229 @option{-msse-check=@var{none}} will make the assembler not to check SSE
230 instructions, which is the default. @option{-msse-check=@var{warning}}
231 will make the assembler issue a warning for any SSE instruction.
232 @option{-msse-check=@var{error}} will make the assembler issue an error
233 for any SSE instruction.
235 @cindex @samp{-mavxscalar=} option, i386
236 @cindex @samp{-mavxscalar=} option, x86-64
237 @item -mavxscalar=@var{128}
238 @itemx -mavxscalar=@var{256}
239 These options control how the assembler should encode scalar AVX
240 instructions. @option{-mavxscalar=@var{128}} will encode scalar
241 AVX instructions with 128bit vector length, which is the default.
242 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
243 with 256bit vector length.
245 @cindex @samp{-mevexlig=} option, i386
246 @cindex @samp{-mevexlig=} option, x86-64
247 @item -mevexlig=@var{128}
248 @itemx -mevexlig=@var{256}
249 @itemx -mevexlig=@var{512}
250 These options control how the assembler should encode length-ignored
251 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
252 EVEX instructions with 128bit vector length, which is the default.
253 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
254 encode LIG EVEX instructions with 256bit and 512bit vector length,
257 @cindex @samp{-mevexwig=} option, i386
258 @cindex @samp{-mevexwig=} option, x86-64
259 @item -mevexwig=@var{0}
260 @itemx -mevexwig=@var{1}
261 These options control how the assembler should encode w-ignored (WIG)
262 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
263 EVEX instructions with evex.w = 0, which is the default.
264 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
267 @cindex @samp{-mmnemonic=} option, i386
268 @cindex @samp{-mmnemonic=} option, x86-64
269 @item -mmnemonic=@var{att}
270 @itemx -mmnemonic=@var{intel}
271 This option specifies instruction mnemonic for matching instructions.
272 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
275 @cindex @samp{-msyntax=} option, i386
276 @cindex @samp{-msyntax=} option, x86-64
277 @item -msyntax=@var{att}
278 @itemx -msyntax=@var{intel}
279 This option specifies instruction syntax when processing instructions.
280 The @code{.att_syntax} and @code{.intel_syntax} directives will
283 @cindex @samp{-mnaked-reg} option, i386
284 @cindex @samp{-mnaked-reg} option, x86-64
286 This opetion specifies that registers don't require a @samp{%} prefix.
287 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
289 @cindex @samp{-madd-bnd-prefix} option, i386
290 @cindex @samp{-madd-bnd-prefix} option, x86-64
291 @item -madd-bnd-prefix
292 This option forces the assembler to add BND prefix to all branches, even
293 if such prefix was not explicitly specified in the source code.
295 @cindex @samp{-mbig-obj} option, x86-64
297 On x86-64 PE/COFF target this option forces the use of big object file
298 format, which allows more than 32768 sections.
300 @cindex @samp{-momit-lock-prefix=} option, i386
301 @cindex @samp{-momit-lock-prefix=} option, x86-64
302 @item -momit-lock-prefix=@var{no}
303 @itemx -momit-lock-prefix=@var{yes}
304 These options control how the assembler should encode lock prefix.
305 This option is intended as a workaround for processors, that fail on
306 lock prefix. This option can only be safely used with single-core,
307 single-thread computers
308 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
309 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
310 which is the default.
312 @cindex @samp{-mevexrcig=} option, i386
313 @cindex @samp{-mevexrcig=} option, x86-64
314 @item -mevexrcig=@var{rne}
315 @itemx -mevexrcig=@var{rd}
316 @itemx -mevexrcig=@var{ru}
317 @itemx -mevexrcig=@var{rz}
318 These options control how the assembler should encode SAE-only
319 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
320 of EVEX instruction with 00, which is the default.
321 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
322 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
323 with 01, 10 and 11 RC bits, respectively.
328 @node i386-Directives
329 @section x86 specific Directives
331 @cindex machine directives, x86
332 @cindex x86 machine directives
335 @cindex @code{lcomm} directive, COFF
336 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
337 Reserve @var{length} (an absolute expression) bytes for a local common
338 denoted by @var{symbol}. The section and value of @var{symbol} are
339 those of the new local common. The addresses are allocated in the bss
340 section, so that at run-time the bytes start off zeroed. Since
341 @var{symbol} is not declared global, it is normally not visible to
342 @code{@value{LD}}. The optional third parameter, @var{alignment},
343 specifies the desired alignment of the symbol in the bss section.
345 This directive is only available for COFF based x86 targets.
347 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
353 @section i386 Syntactical Considerations
355 * i386-Variations:: AT&T Syntax versus Intel Syntax
356 * i386-Chars:: Special Characters
359 @node i386-Variations
360 @subsection AT&T Syntax versus Intel Syntax
362 @cindex i386 intel_syntax pseudo op
363 @cindex intel_syntax pseudo op, i386
364 @cindex i386 att_syntax pseudo op
365 @cindex att_syntax pseudo op, i386
366 @cindex i386 syntax compatibility
367 @cindex syntax compatibility, i386
368 @cindex x86-64 intel_syntax pseudo op
369 @cindex intel_syntax pseudo op, x86-64
370 @cindex x86-64 att_syntax pseudo op
371 @cindex att_syntax pseudo op, x86-64
372 @cindex x86-64 syntax compatibility
373 @cindex syntax compatibility, x86-64
375 @code{@value{AS}} now supports assembly using Intel assembler syntax.
376 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
377 back to the usual AT&T mode for compatibility with the output of
378 @code{@value{GCC}}. Either of these directives may have an optional
379 argument, @code{prefix}, or @code{noprefix} specifying whether registers
380 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
381 different from Intel syntax. We mention these differences because
382 almost all 80386 documents use Intel syntax. Notable differences
383 between the two syntaxes are:
385 @cindex immediate operands, i386
386 @cindex i386 immediate operands
387 @cindex register operands, i386
388 @cindex i386 register operands
389 @cindex jump/call operands, i386
390 @cindex i386 jump/call operands
391 @cindex operand delimiters, i386
393 @cindex immediate operands, x86-64
394 @cindex x86-64 immediate operands
395 @cindex register operands, x86-64
396 @cindex x86-64 register operands
397 @cindex jump/call operands, x86-64
398 @cindex x86-64 jump/call operands
399 @cindex operand delimiters, x86-64
402 AT&T immediate operands are preceded by @samp{$}; Intel immediate
403 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
404 AT&T register operands are preceded by @samp{%}; Intel register operands
405 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
406 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
408 @cindex i386 source, destination operands
409 @cindex source, destination operands; i386
410 @cindex x86-64 source, destination operands
411 @cindex source, destination operands; x86-64
413 AT&T and Intel syntax use the opposite order for source and destination
414 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
415 @samp{source, dest} convention is maintained for compatibility with
416 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
417 instructions with 2 immediate operands, such as the @samp{enter}
418 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
420 @cindex mnemonic suffixes, i386
421 @cindex sizes operands, i386
422 @cindex i386 size suffixes
423 @cindex mnemonic suffixes, x86-64
424 @cindex sizes operands, x86-64
425 @cindex x86-64 size suffixes
427 In AT&T syntax the size of memory operands is determined from the last
428 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
429 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
430 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
431 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
432 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
433 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
436 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
437 instruction with the 64-bit displacement or immediate operand.
439 @cindex return instructions, i386
440 @cindex i386 jump, call, return
441 @cindex return instructions, x86-64
442 @cindex x86-64 jump, call, return
444 Immediate form long jumps and calls are
445 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
447 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
449 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
450 @samp{ret far @var{stack-adjust}}.
452 @cindex sections, i386
453 @cindex i386 sections
454 @cindex sections, x86-64
455 @cindex x86-64 sections
457 The AT&T assembler does not provide support for multiple section
458 programs. Unix style systems expect all programs to be single sections.
462 @subsection Special Characters
464 @cindex line comment character, i386
465 @cindex i386 line comment character
466 The presence of a @samp{#} appearing anywhere on a line indicates the
467 start of a comment that extends to the end of that line.
469 If a @samp{#} appears as the first character of a line then the whole
470 line is treated as a comment, but in this case the line can also be a
471 logical line number directive (@pxref{Comments}) or a preprocessor
472 control command (@pxref{Preprocessing}).
474 If the @option{--divide} command line option has not been specified
475 then the @samp{/} character appearing anywhere on a line also
476 introduces a line comment.
478 @cindex line separator, i386
479 @cindex statement separator, i386
480 @cindex i386 line separator
481 The @samp{;} character can be used to separate statements on the same
485 @section Instruction Naming
487 @cindex i386 instruction naming
488 @cindex instruction naming, i386
489 @cindex x86-64 instruction naming
490 @cindex instruction naming, x86-64
492 Instruction mnemonics are suffixed with one character modifiers which
493 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
494 and @samp{q} specify byte, word, long and quadruple word operands. If
495 no suffix is specified by an instruction then @code{@value{AS}} tries to
496 fill in the missing suffix based on the destination register operand
497 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
498 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
499 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
500 assembler which assumes that a missing mnemonic suffix implies long
501 operand size. (This incompatibility does not affect compiler output
502 since compilers always explicitly specify the mnemonic suffix.)
504 Almost all instructions have the same names in AT&T and Intel format.
505 There are a few exceptions. The sign extend and zero extend
506 instructions need two sizes to specify them. They need a size to
507 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
508 is accomplished by using two instruction mnemonic suffixes in AT&T
509 syntax. Base names for sign extend and zero extend are
510 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
511 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
512 are tacked on to this base name, the @emph{from} suffix before the
513 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
514 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
515 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
516 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
517 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
520 @cindex encoding options, i386
521 @cindex encoding options, x86-64
523 Different encoding options can be specified via optional mnemonic
524 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
525 moving from one register to another. @samp{.d8} or @samp{.d32} suffix
526 prefers 8bit or 32bit displacement in encoding.
528 @cindex conversion instructions, i386
529 @cindex i386 conversion instructions
530 @cindex conversion instructions, x86-64
531 @cindex x86-64 conversion instructions
532 The Intel-syntax conversion instructions
536 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
539 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
542 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
545 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
548 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
552 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
553 @samp{%rdx:%rax} (x86-64 only),
557 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
558 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
561 @cindex jump instructions, i386
562 @cindex call instructions, i386
563 @cindex jump instructions, x86-64
564 @cindex call instructions, x86-64
565 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
566 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
569 @section AT&T Mnemonic versus Intel Mnemonic
571 @cindex i386 mnemonic compatibility
572 @cindex mnemonic compatibility, i386
574 @code{@value{AS}} supports assembly using Intel mnemonic.
575 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
576 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
577 syntax for compatibility with the output of @code{@value{GCC}}.
578 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
579 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
580 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
581 assembler with different mnemonics from those in Intel IA32 specification.
582 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
585 @section Register Naming
587 @cindex i386 registers
588 @cindex registers, i386
589 @cindex x86-64 registers
590 @cindex registers, x86-64
591 Register operands are always prefixed with @samp{%}. The 80386 registers
596 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
597 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
598 frame pointer), and @samp{%esp} (the stack pointer).
601 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
602 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
605 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
606 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
607 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
608 @samp{%cx}, and @samp{%dx})
611 the 6 section registers @samp{%cs} (code section), @samp{%ds}
612 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
616 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
620 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
621 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
624 the 2 test registers @samp{%tr6} and @samp{%tr7}.
627 the 8 floating point register stack @samp{%st} or equivalently
628 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
629 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
630 These registers are overloaded by 8 MMX registers @samp{%mm0},
631 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
632 @samp{%mm6} and @samp{%mm7}.
635 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
636 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
639 The AMD x86-64 architecture extends the register set by:
643 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
644 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
645 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
649 the 8 extended registers @samp{%r8}--@samp{%r15}.
652 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
655 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
658 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
661 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
664 the 8 debug registers: @samp{%db8}--@samp{%db15}.
667 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
671 @section Instruction Prefixes
673 @cindex i386 instruction prefixes
674 @cindex instruction prefixes, i386
675 @cindex prefixes, i386
676 Instruction prefixes are used to modify the following instruction. They
677 are used to repeat string instructions, to provide section overrides, to
678 perform bus lock operations, and to change operand and address sizes.
679 (Most instructions that normally operate on 32-bit operands will use
680 16-bit operands if the instruction has an ``operand size'' prefix.)
681 Instruction prefixes are best written on the same line as the instruction
682 they act upon. For example, the @samp{scas} (scan string) instruction is
686 repne scas %es:(%edi),%al
689 You may also place prefixes on the lines immediately preceding the
690 instruction, but this circumvents checks that @code{@value{AS}} does
691 with prefixes, and will not work with all prefixes.
693 Here is a list of instruction prefixes:
695 @cindex section override prefixes, i386
698 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
699 @samp{fs}, @samp{gs}. These are automatically added by specifying
700 using the @var{section}:@var{memory-operand} form for memory references.
702 @cindex size prefixes, i386
704 Operand/Address size prefixes @samp{data16} and @samp{addr16}
705 change 32-bit operands/addresses into 16-bit operands/addresses,
706 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
707 @code{.code16} section) into 32-bit operands/addresses. These prefixes
708 @emph{must} appear on the same line of code as the instruction they
709 modify. For example, in a 16-bit @code{.code16} section, you might
716 @cindex bus lock prefixes, i386
717 @cindex inhibiting interrupts, i386
719 The bus lock prefix @samp{lock} inhibits interrupts during execution of
720 the instruction it precedes. (This is only valid with certain
721 instructions; see a 80386 manual for details).
723 @cindex coprocessor wait, i386
725 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
726 complete the current instruction. This should never be needed for the
727 80386/80387 combination.
729 @cindex repeat prefixes, i386
731 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
732 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
733 times if the current address size is 16-bits).
734 @cindex REX prefixes, i386
736 The @samp{rex} family of prefixes is used by x86-64 to encode
737 extensions to i386 instruction set. The @samp{rex} prefix has four
738 bits --- an operand size overwrite (@code{64}) used to change operand size
739 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
742 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
743 instruction emits @samp{rex} prefix with all the bits set. By omitting
744 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
745 prefixes as well. Normally, there is no need to write the prefixes
746 explicitly, since gas will automatically generate them based on the
747 instruction operands.
751 @section Memory References
753 @cindex i386 memory references
754 @cindex memory references, i386
755 @cindex x86-64 memory references
756 @cindex memory references, x86-64
757 An Intel syntax indirect memory reference of the form
760 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
764 is translated into the AT&T syntax
767 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
771 where @var{base} and @var{index} are the optional 32-bit base and
772 index registers, @var{disp} is the optional displacement, and
773 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
774 to calculate the address of the operand. If no @var{scale} is
775 specified, @var{scale} is taken to be 1. @var{section} specifies the
776 optional section register for the memory operand, and may override the
777 default section register (see a 80386 manual for section register
778 defaults). Note that section overrides in AT&T syntax @emph{must}
779 be preceded by a @samp{%}. If you specify a section override which
780 coincides with the default section register, @code{@value{AS}} does @emph{not}
781 output any section register override prefixes to assemble the given
782 instruction. Thus, section overrides can be specified to emphasize which
783 section register is used for a given memory operand.
785 Here are some examples of Intel and AT&T style memory references:
788 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
789 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
790 missing, and the default section is used (@samp{%ss} for addressing with
791 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
793 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
794 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
795 @samp{foo}. All other fields are missing. The section register here
796 defaults to @samp{%ds}.
798 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
799 This uses the value pointed to by @samp{foo} as a memory operand.
800 Note that @var{base} and @var{index} are both missing, but there is only
801 @emph{one} @samp{,}. This is a syntactic exception.
803 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
804 This selects the contents of the variable @samp{foo} with section
805 register @var{section} being @samp{%gs}.
808 Absolute (as opposed to PC relative) call and jump operands must be
809 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
810 always chooses PC relative addressing for jump/call labels.
812 Any instruction that has a memory operand, but no register operand,
813 @emph{must} specify its size (byte, word, long, or quadruple) with an
814 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
817 The x86-64 architecture adds an RIP (instruction pointer relative)
818 addressing. This addressing mode is specified by using @samp{rip} as a
819 base register. Only constant offsets are valid. For example:
822 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
823 Points to the address 1234 bytes past the end of the current
826 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
827 Points to the @code{symbol} in RIP relative way, this is shorter than
828 the default absolute addressing.
831 Other addressing modes remain unchanged in x86-64 architecture, except
832 registers used are 64-bit instead of 32-bit.
835 @section Handling of Jump Instructions
837 @cindex jump optimization, i386
838 @cindex i386 jump optimization
839 @cindex jump optimization, x86-64
840 @cindex x86-64 jump optimization
841 Jump instructions are always optimized to use the smallest possible
842 displacements. This is accomplished by using byte (8-bit) displacement
843 jumps whenever the target is sufficiently close. If a byte displacement
844 is insufficient a long displacement is used. We do not support
845 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
846 instruction with the @samp{data16} instruction prefix), since the 80386
847 insists upon masking @samp{%eip} to 16 bits after the word displacement
848 is added. (See also @pxref{i386-Arch})
850 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
851 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
852 displacements, so that if you use these instructions (@code{@value{GCC}} does
853 not use them) you may get an error message (and incorrect code). The AT&T
854 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
865 @section Floating Point
867 @cindex i386 floating point
868 @cindex floating point, i386
869 @cindex x86-64 floating point
870 @cindex floating point, x86-64
871 All 80387 floating point types except packed BCD are supported.
872 (BCD support may be added without much difficulty). These data
873 types are 16-, 32-, and 64- bit integers, and single (32-bit),
874 double (64-bit), and extended (80-bit) precision floating point.
875 Each supported type has an instruction mnemonic suffix and a constructor
876 associated with it. Instruction mnemonic suffixes specify the operand's
877 data type. Constructors build these data types into memory.
879 @cindex @code{float} directive, i386
880 @cindex @code{single} directive, i386
881 @cindex @code{double} directive, i386
882 @cindex @code{tfloat} directive, i386
883 @cindex @code{float} directive, x86-64
884 @cindex @code{single} directive, x86-64
885 @cindex @code{double} directive, x86-64
886 @cindex @code{tfloat} directive, x86-64
889 Floating point constructors are @samp{.float} or @samp{.single},
890 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
891 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
892 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
893 only supports this format via the @samp{fldt} (load 80-bit real to stack
894 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
896 @cindex @code{word} directive, i386
897 @cindex @code{long} directive, i386
898 @cindex @code{int} directive, i386
899 @cindex @code{quad} directive, i386
900 @cindex @code{word} directive, x86-64
901 @cindex @code{long} directive, x86-64
902 @cindex @code{int} directive, x86-64
903 @cindex @code{quad} directive, x86-64
905 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
906 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
907 corresponding instruction mnemonic suffixes are @samp{s} (single),
908 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
909 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
910 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
914 Register to register operations should not use instruction mnemonic suffixes.
915 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
916 wrote @samp{fst %st, %st(1)}, since all register to register operations
917 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
918 which converts @samp{%st} from 80-bit to 64-bit floating point format,
919 then stores the result in the 4 byte location @samp{mem})
922 @section Intel's MMX and AMD's 3DNow! SIMD Operations
928 @cindex 3DNow!, x86-64
931 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
932 instructions for integer data), available on Intel's Pentium MMX
933 processors and Pentium II processors, AMD's K6 and K6-2 processors,
934 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
935 instruction set (SIMD instructions for 32-bit floating point data)
936 available on AMD's K6-2 processor and possibly others in the future.
938 Currently, @code{@value{AS}} does not support Intel's floating point
941 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
942 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
943 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
944 floating point values. The MMX registers cannot be used at the same time
945 as the floating point stack.
947 See Intel and AMD documentation, keeping in mind that the operand order in
948 instructions is reversed from the Intel syntax.
951 @section AMD's Lightweight Profiling Instructions
956 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
957 instruction set, available on AMD's Family 15h (Orochi) processors.
959 LWP enables applications to collect and manage performance data, and
960 react to performance events. The collection of performance data
961 requires no context switches. LWP runs in the context of a thread and
962 so several counters can be used independently across multiple threads.
963 LWP can be used in both 64-bit and legacy 32-bit modes.
965 For detailed information on the LWP instruction set, see the
966 @cite{AMD Lightweight Profiling Specification} available at
967 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
970 @section Bit Manipulation Instructions
975 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
977 BMI instructions provide several instructions implementing individual
978 bit manipulation operations such as isolation, masking, setting, or
981 @c Need to add a specification citation here when available.
984 @section AMD's Trailing Bit Manipulation Instructions
989 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
990 instruction set, available on AMD's BDVER2 processors (Trinity and
993 TBM instructions provide instructions implementing individual bit
994 manipulation operations such as isolating, masking, setting, resetting,
995 complementing, and operations on trailing zeros and ones.
997 @c Need to add a specification citation here when available.
1000 @section Writing 16-bit Code
1002 @cindex i386 16-bit code
1003 @cindex 16-bit code, i386
1004 @cindex real-mode code, i386
1005 @cindex @code{code16gcc} directive, i386
1006 @cindex @code{code16} directive, i386
1007 @cindex @code{code32} directive, i386
1008 @cindex @code{code64} directive, i386
1009 @cindex @code{code64} directive, x86-64
1010 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1011 or 64-bit x86-64 code depending on the default configuration,
1012 it also supports writing code to run in real mode or in 16-bit protected
1013 mode code segments. To do this, put a @samp{.code16} or
1014 @samp{.code16gcc} directive before the assembly language instructions to
1015 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1016 32-bit code with the @samp{.code32} directive or 64-bit code with the
1017 @samp{.code64} directive.
1019 @samp{.code16gcc} provides experimental support for generating 16-bit
1020 code from gcc, and differs from @samp{.code16} in that @samp{call},
1021 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1022 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1023 default to 32-bit size. This is so that the stack pointer is
1024 manipulated in the same way over function calls, allowing access to
1025 function parameters at the same stack offsets as in 32-bit mode.
1026 @samp{.code16gcc} also automatically adds address size prefixes where
1027 necessary to use the 32-bit addressing modes that gcc generates.
1029 The code which @code{@value{AS}} generates in 16-bit mode will not
1030 necessarily run on a 16-bit pre-80386 processor. To write code that
1031 runs on such a processor, you must refrain from using @emph{any} 32-bit
1032 constructs which require @code{@value{AS}} to output address or operand
1035 Note that writing 16-bit code instructions by explicitly specifying a
1036 prefix or an instruction mnemonic suffix within a 32-bit code section
1037 generates different machine instructions than those generated for a
1038 16-bit code segment. In a 32-bit code section, the following code
1039 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1040 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1046 The same code in a 16-bit code section would generate the machine
1047 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1048 is correct since the processor default operand size is assumed to be 16
1049 bits in a 16-bit code section.
1052 @section AT&T Syntax bugs
1054 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1055 assemblers, generate floating point instructions with reversed source
1056 and destination registers in certain cases. Unfortunately, gcc and
1057 possibly many other programs use this reversed syntax, so we're stuck
1066 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1067 than the expected @samp{%st(3) - %st}. This happens with all the
1068 non-commutative arithmetic floating point operations with two register
1069 operands where the source register is @samp{%st} and the destination
1070 register is @samp{%st(i)}.
1073 @section Specifying CPU Architecture
1075 @cindex arch directive, i386
1076 @cindex i386 arch directive
1077 @cindex arch directive, x86-64
1078 @cindex x86-64 arch directive
1080 @code{@value{AS}} may be told to assemble for a particular CPU
1081 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1082 directive enables a warning when gas detects an instruction that is not
1083 supported on the CPU specified. The choices for @var{cpu_type} are:
1085 @multitable @columnfractions .20 .20 .20 .20
1086 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1087 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1088 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1089 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1090 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
1091 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1092 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1093 @item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
1094 @item @samp{generic32} @tab @samp{generic64}
1095 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1096 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1097 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1098 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1099 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1100 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1101 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1102 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1103 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1104 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1105 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1106 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq}
1108 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1109 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1110 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1111 @item @samp{.padlock}
1114 Apart from the warning, there are only two other effects on
1115 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1116 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1117 will automatically use a two byte opcode sequence. The larger three
1118 byte opcode sequence is used on the 486 (and when no architecture is
1119 specified) because it executes faster on the 486. Note that you can
1120 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1121 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1122 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1123 conditional jumps will be promoted when necessary to a two instruction
1124 sequence consisting of a conditional jump of the opposite sense around
1125 an unconditional jump to the target.
1127 Following the CPU architecture (but not a sub-architecture, which are those
1128 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1129 control automatic promotion of conditional jumps. @samp{jumps} is the
1130 default, and enables jump promotion; All external jumps will be of the long
1131 variety, and file-local jumps will be promoted as necessary.
1132 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1133 byte offset jumps, and warns about file-local conditional jumps that
1134 @code{@value{AS}} promotes.
1135 Unconditional jumps are treated as for @samp{jumps}.
1146 @cindex i386 @code{mul}, @code{imul} instructions
1147 @cindex @code{mul} instruction, i386
1148 @cindex @code{imul} instruction, i386
1149 @cindex @code{mul} instruction, x86-64
1150 @cindex @code{imul} instruction, x86-64
1151 There is some trickery concerning the @samp{mul} and @samp{imul}
1152 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1153 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1154 for @samp{imul}) can be output only in the one operand form. Thus,
1155 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1156 the expanding multiply would clobber the @samp{%edx} register, and this
1157 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1158 64-bit product in @samp{%edx:%eax}.
1160 We have added a two operand form of @samp{imul} when the first operand
1161 is an immediate mode expression and the second operand is a register.
1162 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1163 example, can be done with @samp{imul $69, %eax} rather than @samp{imul