gas/doc/c-mips.texi

   1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node MIPS-Dependent
   7 @chapter MIPS Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter MIPS Dependent Features
  12 @end ifclear
  13
  14 @cindex MIPS processor
  15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
  16 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
  17 and MIPS64.  For
  18 information about the @sc{mips} instruction set, see @cite{MIPS RISC
  19 Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
  20 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
  21 Programming'' in the same work.
  22
  23 @menu
  24 * MIPS Opts::           Assembler options
  25 * MIPS Object::         ECOFF object code
  26 * MIPS Stabs::          Directives for debugging information
  27 * MIPS ISA::            Directives to override the ISA level
  28 * MIPS autoextend::     Directives for extending MIPS 16 bit instructions
  29 * MIPS insn::           Directive to mark data as an instruction
  30 * MIPS option stack::   Directives to save and restore options
  31 @end menu
  32
  33 @node MIPS Opts
  34 @section Assembler options
  35
  36 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
  37 special options:
  38
  39 @table @code
  40 @cindex @code{-G} option (MIPS)
  41 @item -G @var{num}
  42 This option sets the largest size of an object that can be referenced
  43 implicitly with the @code{gp} register.  It is only accepted for targets
  44 that use @sc{ecoff} format.  The default value is 8.
  45
  46 @cindex @code{-EB} option (MIPS)
  47 @cindex @code{-EL} option (MIPS)
  48 @cindex MIPS big-endian output
  49 @cindex MIPS little-endian output
  50 @cindex big-endian output, MIPS
  51 @cindex little-endian output, MIPS
  52 @item -EB
  53 @itemx -EL
  54 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
  55 little-endian output at run time (unlike the other @sc{gnu} development
  56 tools, which must be configured for one or the other).  Use @samp{-EB}
  57 to select big-endian output, and @samp{-EL} for little-endian.
  58
  59 @cindex MIPS architecture options
  60 @item -mips1
  61 @itemx -mips2
  62 @itemx -mips3
  63 @itemx -mips4
  64 @itemx -mips5
  65 @itemx -mips32
  66 @itemx -mips64
  67 Generate code for a particular MIPS Instruction Set Architecture level.
  68 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
  69 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
  70 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
  71 @sc{r10000} processors.
  72 @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
  73 to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
  74 processors, respectively.
  75 You can also switch instruction sets during the
  76 assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
  77
  78 @item -mgp32
  79 Assume that 32-bit general purpose registers are available.  This
  80 affects synthetic instructions such as @code{move}, which will assemble
  81 to a 32-bit or a 64-bit instruction depending on this flag.  On some
  82 MIPS variants there is a 32-bit mode flag; when this flag is set,
  83 64-bit instructions generate a trap.  Also, some 32-bit OSes only save
  84 the 32-bit registers on a context switch, so it is essential never to
  85 use the 64-bit registers.
  86
  87 @item -mgp64
  88 Assume that 64-bit general purpose registers are available.  This is
  89 provided in the interests of symmetry with -gp32.
  90
  91 @item -mips16
  92 @itemx -no-mips16
  93 Generate code for the MIPS 16 processor.  This is equivalent to putting
  94 @samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
  95 turns off this option.
  96
  97 @item -mfix7000
  98 @itemx -no-mfix7000
  99 Cause nops to be inserted if the read of the destination register
 100 of an mfhi or mflo instruction occurs in the following two instructions.
 101
 102 @item -m4010
 103 @itemx -no-m4010
 104 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
 105 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
 106 etc.), and to not schedule @samp{nop} instructions around accesses to
 107 the @samp{HI} and @samp{LO} registers.  @samp{-no-m4010} turns off this
 108 option.
 109
 110 @item -m4650
 111 @itemx -no-m4650
 112 Generate code for the MIPS @sc{r4650} chip.  This tells the assembler to accept
 113 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
 114 instructions around accesses to the @samp{HI} and @samp{LO} registers.
 115 @samp{-no-m4650} turns off this option.
 116
 117 @itemx -m3900
 118 @itemx -no-m3900
 119 @itemx -m4100
 120 @itemx -no-m4100
 121 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
 122 @sc{r@var{nnnn}} chip.  This tells the assembler to accept instructions
 123 specific to that chip, and to schedule for that chip's hazards.
 124
 125 @item -mcpu=@var{cpu}
 126 Generate code for a particular MIPS cpu.  It is exactly equivalent to
 127 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
 128 understood.  Valid @var{cpu} value are:
 129
 130 @quotation
 131 2000,
 132 3000,
 133 3900,
 134 4000,
 135 4010,
 136 4100,
 137 4111,
 138 4300,
 139 4400,
 140 4600,
 141 4650,
 142 5000,
 143 rm5200,
 144 rm5230,
 145 rm5231,
 146 rm5261,
 147 rm5721,
 148 6000,
 149 rm7000,
 150 8000,
 151 10000,
 152 mips32-4k
 153 @end quotation
 154
 155
 156 @cindex @code{-nocpp} ignored (MIPS)
 157 @item -nocpp
 158 This option is ignored.  It is accepted for command-line compatibility with
 159 other assemblers, which use it to turn off C style preprocessing.  With
 160 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
 161 @sc{gnu} assembler itself never runs the C preprocessor.
 162
 163 @item --construct-floats
 164 @itemx --no-construct-floats
 165 @cindex --construct-floats
 166 @cindex --no-construct-floats
 167 The @code{--no-construct-floats} option disables the construction of
 168 double width floating point constants by loading the two halves of the
 169 value into the two single width floating point registers that make up
 170 the double width register.  This feature is useful if the processor
 171 support the FR bit in its status  register, and this bit is known (by
 172 the programmer) to be set.  This bit prevents the aliasing of the double
 173 width register by the single width registers.
 174
 175 By default @code{--construct-floats} is selected, allowing construction
 176 of these floating point constants.
 177
 178 @item --trap
 179 @itemx --no-break
 180 @c FIXME!  (1) reflect these options (next item too) in option summaries;
 181 @c         (2) stop teasing, say _which_ instructions expanded _how_.
 182 @code{@value{AS}} automatically macro expands certain division and
 183 multiplication instructions to check for overflow and division by zero.  This
 184 option causes @code{@value{AS}} to generate code to take a trap exception
 185 rather than a break exception when an error is detected.  The trap instructions
 186 are only supported at Instruction Set Architecture level 2 and higher.
 187
 188 @item --break
 189 @itemx --no-trap
 190 Generate code to take a break exception rather than a trap exception when an
 191 error is detected.  This is the default.
 192 @end table
 193
 194 @node MIPS Object
 195 @section MIPS ECOFF object code
 196
 197 @cindex ECOFF sections
 198 @cindex MIPS ECOFF sections
 199 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
 200 besides the usual @code{.text}, @code{.data} and @code{.bss}.  The
 201 additional sections are @code{.rdata}, used for read-only data,
 202 @code{.sdata}, used for small data, and @code{.sbss}, used for small
 203 common objects.
 204
 205 @cindex small objects, MIPS ECOFF
 206 @cindex @code{gp} register, MIPS
 207 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
 208 register to form the address of a ``small object''.  Any object in the
 209 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
 210 For external objects, or for objects in the @code{.bss} section, you can use
 211 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
 212 @code{$gp}; the default value is 8, meaning that a reference to any object
 213 eight bytes or smaller uses @code{$gp}.  Passing @samp{-G 0} to
 214 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
 215 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
 216 or @code{sbss} in any case).  The size of an object in the @code{.bss} section
 217 is set by the @code{.comm} or @code{.lcomm} directive that defines it.  The
 218 size of an external object may be set with the @code{.extern} directive.  For
 219 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
 220 in length, whie leaving @code{sym} otherwise undefined.
 221
 222 Using small @sc{ecoff} objects requires linker support, and assumes that the
 223 @code{$gp} register is correctly initialized (normally done automatically by
 224 the startup code).  @sc{mips} @sc{ecoff} assembly code must not modify the
 225 @code{$gp} register.
 226
 227 @node MIPS Stabs
 228 @section Directives for debugging information
 229
 230 @cindex MIPS debugging directives
 231 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
 232 generating debugging information which are not support by traditional @sc{mips}
 233 assemblers.  These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
 234 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
 235 @code{.stabd}, @code{.stabn}, and @code{.stabs}.  The debugging information
 236 generated by the three @code{.stab} directives can only be read by @sc{gdb},
 237 not by traditional @sc{mips} debuggers (this enhancement is required to fully
 238 support C++ debugging).  These directives are primarily used by compilers, not
 239 assembly language programmers!
 240
 241 @node MIPS ISA
 242 @section Directives to override the ISA level
 243
 244 @cindex MIPS ISA override
 245 @kindex @code{.set mips@var{n}}
 246 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 247 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
 248 mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32 or 64.
 249 The values 1 to 5, 32, and 64 make the assembler accept instructions
 250 for the corresponding
 251 @sc{isa} level, from that point on in the assembly.  @code{.set
 252 mips@var{n}} affects not only which instructions are permitted, but also
 253 how certain macros are expanded.  @code{.set mips0} restores the
 254 @sc{isa} level to its original level: either the level you selected with
 255 command line options, or the default for your configuration.  You can
 256 use this feature to permit specific @sc{r4000} instructions while
 257 assembling in 32 bit mode.  Use this directive with care!
 258
 259 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
 260 in which it will assemble instructions for the MIPS 16 processor.  Use
 261 @samp{.set nomips16} to return to normal 32 bit mode.
 262
 263 Traditional @sc{mips} assemblers do not support this directive.
 264
 265 @node MIPS autoextend
 266 @section Directives for extending MIPS 16 bit instructions
 267
 268 @kindex @code{.set autoextend}
 269 @kindex @code{.set noautoextend}
 270 By default, MIPS 16 instructions are automatically extended to 32 bits
 271 when necessary.  The directive @samp{.set noautoextend} will turn this
 272 off.  When @samp{.set noautoextend} is in effect, any 32 bit instruction
 273 must be explicitly extended with the @samp{.e} modifier (e.g.,
 274 @samp{li.e $4,1000}).  The directive @samp{.set autoextend} may be used
 275 to once again automatically extend instructions when necessary.
 276
 277 This directive is only meaningful when in MIPS 16 mode.  Traditional
 278 @sc{mips} assemblers do not support this directive.
 279
 280 @node MIPS insn
 281 @section Directive to mark data as an instruction
 282
 283 @kindex @code{.insn}
 284 The @code{.insn} directive tells @code{@value{AS}} that the following
 285 data is actually instructions.  This makes a difference in MIPS 16 mode:
 286 when loading the address of a label which precedes instructions,
 287 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
 288 the loaded address will do the right thing.
 289
 290 @node MIPS option stack
 291 @section Directives to save and restore options
 292
 293 @cindex MIPS option stack
 294 @kindex @code{.set push}
 295 @kindex @code{.set pop}
 296 The directives @code{.set push} and @code{.set pop} may be used to save
 297 and restore the current settings for all the options which are
 298 controlled by @code{.set}.  The @code{.set push} directive saves the
 299 current settings on a stack.  The @code{.set pop} directive pops the
 300 stack and restores the settings.
 301
 302 These directives can be useful inside an macro which must change an
 303 option such as the ISA level or instruction reordering but does not want
 304 to change the state of the code which invoked the macro.
 305
 306 Traditional @sc{mips} assemblers do not support these directives.