Add support for RISC-V architecture.
[deliverable/binutils-gdb.git] / gas / doc / c-riscv.texi
1 @c Copyright (C) 2016 Free Software Foundation, Inc.
2 @c This is part of the GAS anual.
3 @c For copying conditions, see the file as.texinfo
4 @c man end
5
6 @ifset GENERIC
7 @page
8 @node RISC-V-Dependent
9 @chapter RISC-V Dependent Features
10 @end ifset
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter RISC-V Dependent Features
14 @end ifclear
15
16 @cindex RISC-V support
17 @menu
18 * RISC-V Options:: RISC-V Options
19 @end menu
20
21 @node RISC-V Options
22 @section Options
23
24 The following table lists all availiable RISC-V specific options
25
26 @c man begin OPTIONS
27 @table @gcctabopt
28 @cindex @samp{-m32} option, RISC-V
29 @cindex @samp{-m64} option, RISC-V
30 @item -m32 | -m64
31 Select the base ISA, either RV32 or RV64.
32
33 @cindex @samp{-mrvc} option, RISC-V
34 @item -mrvc
35 Enables the C ISA subset for compressed instructions.
36
37 @cindex @samp{-msoft-float} option, RISC-V
38 @cindex @samp{-mhard-float} option, RISC-V
39 @item -msoft-float | -mhard-float
40 Select the floating-point ABI, hard-float has F registers while soft-float
41 doesn't.
42
43 @cindex @samp{-march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}} option, RISC-V
44 @item -march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}
45 Select the base isa, as specified by ISA. For example -march=RV32IMA.
46
47 @end table
48 @c man end
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