gas/testsuite/gas/aarch64/illegal-bfloat16.l

   1 [^ :]+: Assembler messages:
   2 [^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z2\.s'
   3 [^ :]+:[0-9]+: Info:    did you mean this\?
   4 [^ :]+:[0-9]+: Info:            bfdot z0\.s, z1\.h, z2\.h
   5 [^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z3\.s\[3\]'
   6 [^ :]+:[0-9]+: Info:    did you mean this\?
   7 [^ :]+:[0-9]+: Info:            bfdot z0\.s, z1\.h, z3\.h\[3\]
   8 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot z0\.s,z1\.h,z3\.h\[4\]'
   9 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfdot z0\.s,z1\.h,z8\.h\[3\]'
  10 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla z0\.s,z1\.h,z2\.s'
  11 [^ :]+:[0-9]+: Info:    did you mean this\?
  12 [^ :]+:[0-9]+: Info:            bfmmla z0\.s, z1\.h, z2\.h
  13 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/z,z2\.s'
  14 [^ :]+:[0-9]+: Info:    did you mean this\?
  15 [^ :]+:[0-9]+: Info:            bfcvt z0\.h, p1/m, z2\.s
  16 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/m,z2\.h'
  17 [^ :]+:[0-9]+: Info:    did you mean this\?
  18 [^ :]+:[0-9]+: Info:            bfcvt z0\.h, p1/m, z2\.s
  19 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/z,z2\.s'
  20 [^ :]+:[0-9]+: Info:    did you mean this\?
  21 [^ :]+:[0-9]+: Info:            bfcvtnt z0\.h, p1/m, z2\.s
  22 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/m,z2\.h'
  23 [^ :]+:[0-9]+: Info:    did you mean this\?
  24 [^ :]+:[0-9]+: Info:            bfcvtnt z0\.h, p1/m, z2\.s
  25 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s'
  26 [^ :]+:[0-9]+: Info:    did you mean this\?
  27 [^ :]+:[0-9]+: Info:            bfmlalt z0\.s, z0\.h, z0\.h
  28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
  29 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
  30 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
  31 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]'
  32 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]'
  33 [^ :]+:[0-9]+: Info:    did you mean this\?
  34 [^ :]+:[0-9]+: Info:            bfmlalt z0\.s, z0\.h, z0\.h\[0\]
  35 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
  36 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
  37 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]'
  38 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s'
  39 [^ :]+:[0-9]+: Info:    did you mean this\?
  40 [^ :]+:[0-9]+: Info:            bfmlalb z0\.s, z0\.h, z0\.h
  41 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
  42 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
  43 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
  44 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]'
  45 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]'
  46 [^ :]+:[0-9]+: Info:    did you mean this\?
  47 [^ :]+:[0-9]+: Info:            bfmlalb z0\.s, z0\.h, z0\.h\[0\]
  48 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
  49 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
  50 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]'
  51 [^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]'
  52 [^ :]+:[0-9]+: Info:    did you mean this\?
  53 [^ :]+:[0-9]+: Info:            bfdot v0\.2s, v1\.4h, v2\.2h\[3\]
  54 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
  55 [^ :]+:[0-9]+: Info:            bfdot v0\.4s, v1\.8h, v2\.2h\[3\]
  56 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot v0\.4s,v1\.8h,v2\.2h\[4\]'
  57 [^ :]+:[0-9]+: Error: invalid element size 8 and vector size combination s at operand 3 -- `bfmmla v0\.4s,v1\.8h,v2\.8s'
  58 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla v0\.4s,v1\.4h,v2\.8h'
  59 [^ :]+:[0-9]+: Info:    did you mean this\?
  60 [^ :]+:[0-9]+: Info:            bfmmla v0\.4s, v1\.8h, v2\.8h
  61 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h'
  62 [^ :]+:[0-9]+: Info:    did you mean this\?
  63 [^ :]+:[0-9]+: Info:            bfmlalb v0\.4s, v0\.8h, v0\.8h
  64 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
  65 [^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
  66 [^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
  67 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h'
  68 [^ :]+:[0-9]+: Info:    did you mean this\?
  69 [^ :]+:[0-9]+: Info:            bfmlalt v0\.4s, v0\.8h, v0\.8h
  70 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
  71 [^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
  72 [^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
  73 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]'
  74 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
  75 [^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
  76 [^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]'
  77 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]'
  78 [^ :]+:[0-9]+: Info:    did you mean this\?
  79 [^ :]+:[0-9]+: Info:            bfmlalb v0\.4s, v0\.8h, v0\.h\[0\]
  80 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.8h,v0\.s\[0\]'
  81 [^ :]+:[0-9]+: Info:    did you mean this\?
  82 [^ :]+:[0-9]+: Info:            bfmlalb v0\.4s, v0\.8h, v0\.h\[0\]
  83 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.s\[0\]'
  84 [^ :]+:[0-9]+: Info:    did you mean this\?
  85 [^ :]+:[0-9]+: Info:            bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
  86 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.4h,v0\.h\[0\]'
  87 [^ :]+:[0-9]+: Info:    did you mean this\?
  88 [^ :]+:[0-9]+: Info:            bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
  89 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]'
  90 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
  91 [^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
  92 [^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]'
  93 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1'
  94 [^ :]+:[0-9]+: Info:    did you mean this\?
  95 [^ :]+:[0-9]+: Info:            bfcvt h0, s1