1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "elf/common.h"
34 #include <sys/ptrace.h>
35 #include <sys/utsname.h>
39 #include "features/aarch64.c"
41 /* Defines ps_err_e, struct ps_prochandle. */
42 #include "gdb_proc_service.h"
45 #define TRAP_HWBKPT 0x0004
48 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
49 case we may be tracing more than one process at a time. In that
50 case, inferior_ptid will contain the main process ID and the
51 individual thread (process) ID. get_thread_id () is used to get
52 the thread id if it's available, and the process id otherwise. */
55 get_thread_id (ptid_t ptid
)
57 int tid
= TIDGET (ptid
);
64 /* Macro definitions, data structures, and code for the hardware
65 breakpoint and hardware watchpoint support follow. We use the
66 following abbreviations throughout the code:
72 /* Maximum number of hardware breakpoint and watchpoint registers.
73 Neither of these values may exceed the width of dr_changed_t
76 #define AARCH64_HBP_MAX_NUM 16
77 #define AARCH64_HWP_MAX_NUM 16
79 /* Alignment requirement in bytes for addresses written to
80 hardware breakpoint and watchpoint value registers.
82 A ptrace call attempting to set an address that does not meet the
83 alignment criteria will fail. Limited support has been provided in
84 this port for unaligned watchpoints, such that from a GDB user
85 perspective, an unaligned watchpoint may be requested.
87 This is achieved by minimally enlarging the watched area to meet the
88 alignment requirement, and if necessary, splitting the watchpoint
89 over several hardware watchpoint registers. */
91 #define AARCH64_HBP_ALIGNMENT 4
92 #define AARCH64_HWP_ALIGNMENT 8
94 /* The maximum length of a memory region that can be watched by one
95 hardware watchpoint register. */
97 #define AARCH64_HWP_MAX_LEN_PER_REG 8
99 /* ptrace hardware breakpoint resource info is formatted as follows:
102 +---------------+--------------+---------------+---------------+
103 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
104 +---------------+--------------+---------------+---------------+ */
107 /* Macros to extract fields from the hardware debug information word. */
108 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
109 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
111 /* Macro for the expected version of the ARMv8-A debug architecture. */
112 #define AARCH64_DEBUG_ARCH_V8 0x6
114 /* Number of hardware breakpoints/watchpoints the target supports.
115 They are initialized with values obtained via the ptrace calls
116 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
118 static int aarch64_num_bp_regs
;
119 static int aarch64_num_wp_regs
;
121 /* Debugging of hardware breakpoint/watchpoint support. */
123 static int debug_hw_points
;
125 /* Each bit of a variable of this type is used to indicate whether a
126 hardware breakpoint or watchpoint setting has been changed since
129 Bit N corresponds to the Nth hardware breakpoint or watchpoint
130 setting which is managed in aarch64_debug_reg_state, where N is
131 valid between 0 and the total number of the hardware breakpoint or
132 watchpoint debug registers minus 1.
134 When bit N is 1, the corresponding breakpoint or watchpoint setting
135 has changed, and therefore the corresponding hardware debug
136 register needs to be updated via the ptrace interface.
138 In the per-thread arch-specific data area, we define two such
139 variables for per-thread hardware breakpoint and watchpoint
140 settings respectively.
142 This type is part of the mechanism which helps reduce the number of
143 ptrace calls to the kernel, i.e. avoid asking the kernel to write
144 to the debug registers with unchanged values. */
146 typedef unsigned long long dr_changed_t
;
148 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
150 #define DR_MARK_ALL_CHANGED(x, m) \
153 gdb_assert (sizeof ((x)) * 8 >= (m)); \
154 (x) = (((dr_changed_t)1 << (m)) - 1); \
157 #define DR_MARK_N_CHANGED(x, n) \
160 (x) |= ((dr_changed_t)1 << (n)); \
163 #define DR_CLEAR_CHANGED(x) \
169 #define DR_HAS_CHANGED(x) ((x) != 0)
170 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
172 /* Structure for managing the hardware breakpoint/watchpoint resources.
173 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
174 content, and DR_REF_COUNT_* counts the numbers of references to the
175 corresponding bp/wp, by which way the limited hardware resources
176 are not wasted on duplicated bp/wp settings (though so far gdb has
177 done a good job by not sending duplicated bp/wp requests). */
179 struct aarch64_debug_reg_state
181 /* hardware breakpoint */
182 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
183 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
184 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
186 /* hardware watchpoint */
187 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
188 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
189 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
192 /* Clear the reference counts and forget everything we knew about the
196 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
200 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
202 state
->dr_addr_bp
[i
] = 0;
203 state
->dr_ctrl_bp
[i
] = 0;
204 state
->dr_ref_count_bp
[i
] = 0;
207 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
209 state
->dr_addr_wp
[i
] = 0;
210 state
->dr_ctrl_wp
[i
] = 0;
211 state
->dr_ref_count_wp
[i
] = 0;
215 /* Per-inferior data key. */
216 static const struct inferior_data
*aarch64_inferior_data
;
218 /* Per-inferior data. */
219 struct aarch64_inferior_data
221 /* Copy of AArch64 hardware debug registers for performance reasons. */
222 struct aarch64_debug_reg_state state
;
225 /* Per-inferior hook for register_inferior_data_with_cleanup. */
228 aarch64_inferior_data_cleanup (struct inferior
*inf
, void *arg
)
230 struct aarch64_inferior_data
*inf_data
= arg
;
235 /* Get data specific for INFERIOR_PTID LWP. Return special data area
236 for processes being detached. */
238 static struct aarch64_inferior_data
*
239 aarch64_inferior_data_get (void)
241 struct inferior
*inf
= current_inferior ();
242 struct aarch64_inferior_data
*inf_data
;
244 inf_data
= inferior_data (inf
, aarch64_inferior_data
);
245 if (inf_data
== NULL
)
247 inf_data
= xzalloc (sizeof (*inf_data
));
248 set_inferior_data (inf
, aarch64_inferior_data
, inf_data
);
254 /* Get debug registers state for INFERIOR_PTID, see
255 aarch64_inferior_data_get. */
257 static struct aarch64_debug_reg_state
*
258 aarch64_get_debug_reg_state (void)
260 return &aarch64_inferior_data_get ()->state
;
263 /* Per-thread arch-specific data we want to keep. */
267 /* When bit N is 1, it indicates the Nth hardware breakpoint or
268 watchpoint register pair needs to be updated when the thread is
269 resumed; see aarch64_linux_prepare_to_resume. */
270 dr_changed_t dr_changed_bp
;
271 dr_changed_t dr_changed_wp
;
274 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
275 registers with data from *STATE. */
278 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
279 int tid
, int watchpoint
)
283 struct user_hwdebug_state regs
;
284 const CORE_ADDR
*addr
;
285 const unsigned int *ctrl
;
287 iov
.iov_base
= ®s
;
288 iov
.iov_len
= sizeof (regs
);
289 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
290 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
291 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
293 for (i
= 0; i
< count
; i
++)
295 regs
.dbg_regs
[i
].addr
= addr
[i
];
296 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
299 if (ptrace (PTRACE_SETREGSET
, tid
,
300 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
302 error (_("Unexpected error setting hardware debug registers"));
305 struct aarch64_dr_update_callback_param
311 /* Callback for linux_nat_iterate_watchpoint_lwps. Records the
312 information about the change of one hardware breakpoint/watchpoint
313 setting for the thread LWP.
314 The information is passed in via PTR.
315 N.B. The actual updating of hardware debug registers is not
316 carried out until the moment the thread is resumed. */
319 debug_reg_change_callback (struct lwp_info
*lwp
, void *ptr
)
321 struct aarch64_dr_update_callback_param
*param_p
322 = (struct aarch64_dr_update_callback_param
*) ptr
;
323 int pid
= get_thread_id (lwp
->ptid
);
324 int idx
= param_p
->idx
;
325 int is_watchpoint
= param_p
->is_watchpoint
;
326 struct arch_lwp_info
*info
= lwp
->arch_private
;
327 dr_changed_t
*dr_changed_ptr
;
328 dr_changed_t dr_changed
;
331 info
= lwp
->arch_private
= XCNEW (struct arch_lwp_info
);
335 fprintf_unfiltered (gdb_stdlog
,
336 "debug_reg_change_callback: \n\tOn entry:\n");
337 fprintf_unfiltered (gdb_stdlog
,
338 "\tpid%d, dr_changed_bp=0x%llx, "
339 "dr_changed_wp=0x%llx\n",
340 pid
, info
->dr_changed_bp
, info
->dr_changed_wp
);
343 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
344 : &info
->dr_changed_bp
;
345 dr_changed
= *dr_changed_ptr
;
348 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
349 : aarch64_num_bp_regs
)));
351 /* The actual update is done later just before resuming the lwp,
352 we just mark that one register pair needs updating. */
353 DR_MARK_N_CHANGED (dr_changed
, idx
);
354 *dr_changed_ptr
= dr_changed
;
356 /* If the lwp isn't stopped, force it to momentarily pause, so
357 we can update its debug registers. */
359 linux_stop_lwp (lwp
);
363 fprintf_unfiltered (gdb_stdlog
,
364 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%llx, "
365 "dr_changed_wp=0x%llx\n",
366 pid
, info
->dr_changed_bp
, info
->dr_changed_wp
);
369 /* Continue the iteration. */
373 /* Notify each thread that their IDXth breakpoint/watchpoint register
374 pair needs to be updated. The message will be recorded in each
375 thread's arch-specific data area, the actual updating will be done
376 when the thread is resumed. */
379 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
380 int is_watchpoint
, unsigned int idx
)
382 struct aarch64_dr_update_callback_param param
;
384 param
.is_watchpoint
= is_watchpoint
;
387 linux_nat_iterate_watchpoint_lwps (debug_reg_change_callback
,
391 /* Print the values of the cached breakpoint/watchpoint registers. */
394 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
395 const char *func
, CORE_ADDR addr
,
400 fprintf_unfiltered (gdb_stdlog
, "%s", func
);
402 fprintf_unfiltered (gdb_stdlog
, " (addr=0x%08lx, len=%d, type=%s)",
403 (unsigned long) addr
, len
,
404 type
== hw_write
? "hw-write-watchpoint"
405 : (type
== hw_read
? "hw-read-watchpoint"
406 : (type
== hw_access
? "hw-access-watchpoint"
407 : (type
== hw_execute
? "hw-breakpoint"
409 fprintf_unfiltered (gdb_stdlog
, ":\n");
411 fprintf_unfiltered (gdb_stdlog
, "\tBREAKPOINTs:\n");
412 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
413 fprintf_unfiltered (gdb_stdlog
,
414 "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
415 i
, state
->dr_addr_bp
[i
],
416 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
418 fprintf_unfiltered (gdb_stdlog
, "\tWATCHPOINTs:\n");
419 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
420 fprintf_unfiltered (gdb_stdlog
,
421 "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
422 i
, state
->dr_addr_wp
[i
],
423 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
426 /* Fill GDB's register array with the general-purpose register values
427 from the current thread. */
430 fetch_gregs_from_thread (struct regcache
*regcache
)
436 tid
= get_thread_id (inferior_ptid
);
438 iovec
.iov_base
= ®s
;
439 iovec
.iov_len
= sizeof (regs
);
441 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
443 perror_with_name (_("Unable to fetch general registers."));
445 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
446 regcache_raw_supply (regcache
, regno
,
447 (char *) ®s
[regno
- AARCH64_X0_REGNUM
]);
450 /* Store to the current thread the valid general-purpose register
451 values in the GDB's register array. */
454 store_gregs_to_thread (const struct regcache
*regcache
)
460 tid
= get_thread_id (inferior_ptid
);
462 iovec
.iov_base
= ®s
;
463 iovec
.iov_len
= sizeof (regs
);
465 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
467 perror_with_name (_("Unable to fetch general registers."));
469 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
470 if (REG_VALID
== regcache_register_status (regcache
, regno
))
471 regcache_raw_collect (regcache
, regno
,
472 (char *) ®s
[regno
- AARCH64_X0_REGNUM
]);
474 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
476 perror_with_name (_("Unable to store general registers."));
479 /* Fill GDB's register array with the fp/simd register values
480 from the current thread. */
483 fetch_fpregs_from_thread (struct regcache
*regcache
)
489 tid
= get_thread_id (inferior_ptid
);
491 iovec
.iov_base
= ®s
;
492 iovec
.iov_len
= sizeof (regs
);
494 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
496 perror_with_name (_("Unable to fetch FP/SIMD registers."));
498 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
499 regcache_raw_supply (regcache
, regno
,
500 (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
502 regcache_raw_supply (regcache
, AARCH64_FPSR_REGNUM
, (char *) ®s
.fpsr
);
503 regcache_raw_supply (regcache
, AARCH64_FPCR_REGNUM
, (char *) ®s
.fpcr
);
506 /* Store to the current thread the valid fp/simd register
507 values in the GDB's register array. */
510 store_fpregs_to_thread (const struct regcache
*regcache
)
516 tid
= get_thread_id (inferior_ptid
);
518 iovec
.iov_base
= ®s
;
519 iovec
.iov_len
= sizeof (regs
);
521 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
523 perror_with_name (_("Unable to fetch FP/SIMD registers."));
525 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
526 if (REG_VALID
== regcache_register_status (regcache
, regno
))
527 regcache_raw_collect (regcache
, regno
,
528 (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
530 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPSR_REGNUM
))
531 regcache_raw_collect (regcache
, AARCH64_FPSR_REGNUM
, (char *) ®s
.fpsr
);
532 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPCR_REGNUM
))
533 regcache_raw_collect (regcache
, AARCH64_FPCR_REGNUM
, (char *) ®s
.fpcr
);
535 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_FPREGSET
, &iovec
);
537 perror_with_name (_("Unable to store FP/SIMD registers."));
540 /* Implement the "to_fetch_register" target_ops method. */
543 aarch64_linux_fetch_inferior_registers (struct target_ops
*ops
,
544 struct regcache
*regcache
,
549 fetch_gregs_from_thread (regcache
);
550 fetch_fpregs_from_thread (regcache
);
552 else if (regno
< AARCH64_V0_REGNUM
)
553 fetch_gregs_from_thread (regcache
);
555 fetch_fpregs_from_thread (regcache
);
558 /* Implement the "to_store_register" target_ops method. */
561 aarch64_linux_store_inferior_registers (struct target_ops
*ops
,
562 struct regcache
*regcache
,
567 store_gregs_to_thread (regcache
);
568 store_fpregs_to_thread (regcache
);
570 else if (regno
< AARCH64_V0_REGNUM
)
571 store_gregs_to_thread (regcache
);
573 store_fpregs_to_thread (regcache
);
576 /* Fill register REGNO (if it is a general-purpose register) in
577 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
578 do this for all registers. */
581 fill_gregset (const struct regcache
*regcache
,
582 gdb_gregset_t
*gregsetp
, int regno
)
584 gdb_byte
*gregs_buf
= (gdb_byte
*) gregsetp
;
587 for (i
= AARCH64_X0_REGNUM
; i
<= AARCH64_CPSR_REGNUM
; i
++)
588 if (regno
== -1 || regno
== i
)
589 regcache_raw_collect (regcache
, i
,
590 gregs_buf
+ X_REGISTER_SIZE
591 * (i
- AARCH64_X0_REGNUM
));
594 /* Fill GDB's register array with the general-purpose register values
598 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
600 aarch64_linux_supply_gregset (regcache
, (const gdb_byte
*) gregsetp
);
603 /* Fill register REGNO (if it is a floating-point register) in
604 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
605 do this for all registers. */
608 fill_fpregset (const struct regcache
*regcache
,
609 gdb_fpregset_t
*fpregsetp
, int regno
)
611 gdb_byte
*fpregs_buf
= (gdb_byte
*) fpregsetp
;
614 for (i
= AARCH64_V0_REGNUM
; i
<= AARCH64_V31_REGNUM
; i
++)
615 if (regno
== -1 || regno
== i
)
616 regcache_raw_collect (regcache
, i
,
617 fpregs_buf
+ V_REGISTER_SIZE
618 * (i
- AARCH64_V0_REGNUM
));
620 if (regno
== -1 || regno
== AARCH64_FPSR_REGNUM
)
621 regcache_raw_collect (regcache
, AARCH64_FPSR_REGNUM
,
622 fpregs_buf
+ V_REGISTER_SIZE
* 32);
624 if (regno
== -1 || regno
== AARCH64_FPCR_REGNUM
)
625 regcache_raw_collect (regcache
, AARCH64_FPCR_REGNUM
,
626 fpregs_buf
+ V_REGISTER_SIZE
* 32 + 4);
629 /* Fill GDB's register array with the floating-point register values
633 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
635 aarch64_linux_supply_fpregset (regcache
, (const gdb_byte
*) fpregsetp
);
638 /* Called when resuming a thread.
639 The hardware debug registers are updated when there is any change. */
642 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
644 struct arch_lwp_info
*info
= lwp
->arch_private
;
646 /* NULL means this is the main thread still going through the shell,
647 or, no watchpoint has been set yet. In that case, there's
652 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
653 || DR_HAS_CHANGED (info
->dr_changed_wp
))
655 int tid
= GET_LWP (lwp
->ptid
);
656 struct aarch64_debug_reg_state
*state
= aarch64_get_debug_reg_state ();
659 fprintf_unfiltered (gdb_stdlog
, "prepare_to_resume thread %d\n", tid
);
662 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
664 aarch64_linux_set_debug_regs (state
, tid
, 1);
665 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
669 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
671 aarch64_linux_set_debug_regs (state
, tid
, 0);
672 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
678 aarch64_linux_new_thread (struct lwp_info
*lp
)
680 struct arch_lwp_info
*info
= XCNEW (struct arch_lwp_info
);
682 /* Mark that all the hardware breakpoint/watchpoint register pairs
683 for this thread need to be initialized. */
684 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
685 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
687 lp
->arch_private
= info
;
691 /* Called by libthread_db. Returns a pointer to the thread local
692 storage (or its descriptor). */
695 ps_get_thread_area (const struct ps_prochandle
*ph
,
696 lwpid_t lwpid
, int idx
, void **base
)
701 iovec
.iov_base
= ®
;
702 iovec
.iov_len
= sizeof (reg
);
704 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
707 /* IDX is the bias from the thread pointer to the beginning of the
708 thread descriptor. It has to be subtracted due to implementation
709 quirks in libthread_db. */
710 *base
= (void *) (reg
- idx
);
716 /* Get the hardware debug register capacity information. */
719 aarch64_linux_get_debug_reg_capacity (void)
723 struct user_hwdebug_state dreg_state
;
725 tid
= get_thread_id (inferior_ptid
);
726 iov
.iov_base
= &dreg_state
;
727 iov
.iov_len
= sizeof (dreg_state
);
729 /* Get hardware watchpoint register info. */
730 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_WATCH
, &iov
) == 0
731 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
733 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
734 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
736 warning ("Unexpected number of hardware watchpoint registers reported"
737 " by ptrace, got %d, expected %d.",
738 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
739 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
744 warning ("Unable to determine the number of hardware watchpoints"
746 aarch64_num_wp_regs
= 0;
749 /* Get hardware breakpoint register info. */
750 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_BREAK
, &iov
) == 0
751 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
753 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
754 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
756 warning ("Unexpected number of hardware breakpoint registers reported"
757 " by ptrace, got %d, expected %d.",
758 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
759 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
764 warning ("Unable to determine the number of hardware breakpoints"
766 aarch64_num_bp_regs
= 0;
770 static void (*super_post_startup_inferior
) (ptid_t ptid
);
772 /* Implement the "to_post_startup_inferior" target_ops method. */
775 aarch64_linux_child_post_startup_inferior (ptid_t ptid
)
777 struct aarch64_debug_reg_state
*state
= aarch64_get_debug_reg_state ();
779 aarch64_init_debug_reg_state (state
);
780 aarch64_linux_get_debug_reg_capacity ();
781 super_post_startup_inferior (ptid
);
784 /* Implement the "to_read_description" target_ops method. */
786 static const struct target_desc
*
787 aarch64_linux_read_description (struct target_ops
*ops
)
789 initialize_tdesc_aarch64 ();
790 return tdesc_aarch64
;
793 /* Given the (potentially unaligned) watchpoint address in ADDR and
794 length in LEN, return the aligned address and aligned length in
795 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
796 aligned address and length will be valid values to write to the
797 hardware watchpoint value and control registers.
799 The given watchpoint may get truncated if more than one hardware
800 register is needed to cover the watched region. *NEXT_ADDR_P
801 and *NEXT_LEN_P, if non-NULL, will return the address and length
802 of the remaining part of the watchpoint (which can be processed
803 by calling this routine again to generate another aligned address
806 See the comment above the function of the same name in
807 gdbserver/linux-aarch64-low.c for more information. */
810 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
811 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
816 CORE_ADDR aligned_addr
;
817 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
818 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
820 /* As assumed by the algorithm. */
821 gdb_assert (alignment
== max_wp_len
);
826 /* Address to be put into the hardware watchpoint value register
828 offset
= addr
& (alignment
- 1);
829 aligned_addr
= addr
- offset
;
831 gdb_assert (offset
>= 0 && offset
< alignment
);
832 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
833 gdb_assert (offset
+ len
> 0);
835 if (offset
+ len
>= max_wp_len
)
837 /* Need more than one watchpoint registers; truncate it at the
838 alignment boundary. */
839 aligned_len
= max_wp_len
;
840 len
-= (max_wp_len
- offset
);
841 addr
+= (max_wp_len
- offset
);
842 gdb_assert ((addr
& (alignment
- 1)) == 0);
846 /* Find the smallest valid length that is large enough to
847 accommodate this watchpoint. */
848 static const unsigned char
849 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
850 { 1, 2, 4, 4, 8, 8, 8, 8 };
852 aligned_len
= aligned_len_array
[offset
+ len
- 1];
858 *aligned_addr_p
= aligned_addr
;
860 *aligned_len_p
= aligned_len
;
867 /* Returns the number of hardware watchpoints of type TYPE that we can
868 set. Value is positive if we can set CNT watchpoints, zero if
869 setting watchpoints of type TYPE is not supported, and negative if
870 CNT is more than the maximum number of watchpoints of type TYPE
871 that we can support. TYPE is one of bp_hardware_watchpoint,
872 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
873 CNT is the number of such watchpoints used so far (including this
874 one). OTHERTYPE is non-zero if other types of watchpoints are
877 We always return 1 here because we don't have enough information
878 about possible overlap of addresses that they want to watch. As an
879 extreme example, consider the case where all the watchpoints watch
880 the same address and the same region length: then we can handle a
881 virtually unlimited number of watchpoints, due to debug register
882 sharing implemented via reference counts. */
885 aarch64_linux_can_use_hw_breakpoint (int type
, int cnt
, int othertype
)
890 /* ptrace expects control registers to be formatted as follows:
893 +--------------------------------+----------+------+------+----+
894 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
895 +--------------------------------+----------+------+------+----+
897 The TYPE field is ignored for breakpoints. */
899 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
900 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
902 /* Utility function that returns the length in bytes of a watchpoint
903 according to the content of a hardware debug control register CTRL.
904 Note that the kernel currently only supports the following Byte
905 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
906 that for a hardware watchpoint, its valid length can only be 1
907 byte, 2 bytes, 4 bytes or 8 bytes. */
909 static inline unsigned int
910 aarch64_watchpoint_length (unsigned int ctrl
)
912 switch (DR_CONTROL_LENGTH (ctrl
))
927 /* Given the hardware breakpoint or watchpoint type TYPE and its
928 length LEN, return the expected encoding for a hardware
929 breakpoint/watchpoint control register. */
932 aarch64_point_encode_ctrl_reg (int type
, int len
)
934 unsigned int ctrl
, ttype
;
952 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
957 ctrl
|= ((1 << len
) - 1) << 5;
959 ctrl
|= (2 << 1) | 1;
964 /* Addresses to be written to the hardware breakpoint and watchpoint
965 value registers need to be aligned; the alignment is 4-byte and
966 8-type respectively. Linux kernel rejects any non-aligned address
967 it receives from the related ptrace call. Furthermore, the kernel
968 currently only supports the following Byte Address Select (BAS)
969 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
970 watchpoint to be accepted by the kernel (via ptrace call), its
971 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
972 Despite these limitations, the unaligned watchpoint is supported in
975 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
978 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
980 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
981 : AARCH64_HBP_ALIGNMENT
;
983 if (addr
& (alignment
- 1))
986 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
992 /* Record the insertion of one breakpoint/watchpoint, as represented
993 by ADDR and CTRL, in the cached debug register state area *STATE. */
996 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
997 int type
, CORE_ADDR addr
, int len
)
999 int i
, idx
, num_regs
, is_watchpoint
;
1000 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1001 CORE_ADDR
*dr_addr_p
;
1003 /* Set up state pointers. */
1004 is_watchpoint
= (type
!= hw_execute
);
1005 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1008 num_regs
= aarch64_num_wp_regs
;
1009 dr_addr_p
= state
->dr_addr_wp
;
1010 dr_ctrl_p
= state
->dr_ctrl_wp
;
1011 dr_ref_count
= state
->dr_ref_count_wp
;
1015 num_regs
= aarch64_num_bp_regs
;
1016 dr_addr_p
= state
->dr_addr_bp
;
1017 dr_ctrl_p
= state
->dr_ctrl_bp
;
1018 dr_ref_count
= state
->dr_ref_count_bp
;
1021 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1023 /* Find an existing or free register in our cache. */
1025 for (i
= 0; i
< num_regs
; ++i
)
1027 if ((dr_ctrl_p
[i
] & 1) == 0)
1029 gdb_assert (dr_ref_count
[i
] == 0);
1031 /* no break; continue hunting for an existing one. */
1033 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1035 gdb_assert (dr_ref_count
[i
] != 0);
1045 /* Update our cache. */
1046 if ((dr_ctrl_p
[idx
] & 1) == 0)
1049 dr_addr_p
[idx
] = addr
;
1050 dr_ctrl_p
[idx
] = ctrl
;
1051 dr_ref_count
[idx
] = 1;
1052 /* Notify the change. */
1053 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
1057 /* existing entry */
1058 dr_ref_count
[idx
]++;
1064 /* Record the removal of one breakpoint/watchpoint, as represented by
1065 ADDR and CTRL, in the cached debug register state area *STATE. */
1068 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
1069 int type
, CORE_ADDR addr
, int len
)
1071 int i
, num_regs
, is_watchpoint
;
1072 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1073 CORE_ADDR
*dr_addr_p
;
1075 /* Set up state pointers. */
1076 is_watchpoint
= (type
!= hw_execute
);
1077 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1080 num_regs
= aarch64_num_wp_regs
;
1081 dr_addr_p
= state
->dr_addr_wp
;
1082 dr_ctrl_p
= state
->dr_ctrl_wp
;
1083 dr_ref_count
= state
->dr_ref_count_wp
;
1087 num_regs
= aarch64_num_bp_regs
;
1088 dr_addr_p
= state
->dr_addr_bp
;
1089 dr_ctrl_p
= state
->dr_ctrl_bp
;
1090 dr_ref_count
= state
->dr_ref_count_bp
;
1093 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1095 /* Find the entry that matches the ADDR and CTRL. */
1096 for (i
= 0; i
< num_regs
; ++i
)
1097 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1099 gdb_assert (dr_ref_count
[i
] != 0);
1107 /* Clear our cache. */
1108 if (--dr_ref_count
[i
] == 0)
1110 /* Clear the enable bit. */
1113 dr_ctrl_p
[i
] = ctrl
;
1114 /* Notify the change. */
1115 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
1121 /* Implement insertion and removal of a single breakpoint. */
1124 aarch64_handle_breakpoint (int type
, CORE_ADDR addr
, int len
, int is_insert
)
1126 struct aarch64_debug_reg_state
*state
;
1128 /* The hardware breakpoint on AArch64 should always be 4-byte
1130 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
1133 state
= aarch64_get_debug_reg_state ();
1136 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1138 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1141 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
1142 Return 0 on success, -1 on failure. */
1145 aarch64_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1146 struct bp_target_info
*bp_tgt
)
1149 CORE_ADDR addr
= bp_tgt
->placed_address
;
1151 const int type
= hw_execute
;
1153 if (debug_hw_points
)
1156 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1157 (unsigned long) addr
, len
);
1159 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 1 /* is_insert */);
1161 if (debug_hw_points
> 1)
1162 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1163 "insert_hw_watchpoint", addr
, len
, type
);
1168 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1169 Return 0 on success, -1 on failure. */
1172 aarch64_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1173 struct bp_target_info
*bp_tgt
)
1176 CORE_ADDR addr
= bp_tgt
->placed_address
;
1178 const int type
= hw_execute
;
1180 if (debug_hw_points
)
1182 (gdb_stdlog
, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1183 (unsigned long) addr
, len
);
1185 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 0 /* is_insert */);
1187 if (debug_hw_points
> 1)
1188 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1189 "remove_hw_watchpoint", addr
, len
, type
);
1194 /* This is essentially the same as aarch64_handle_breakpoint, apart
1195 from that it is an aligned watchpoint to be handled. */
1198 aarch64_handle_aligned_watchpoint (int type
, CORE_ADDR addr
, int len
,
1201 struct aarch64_debug_reg_state
*state
= aarch64_get_debug_reg_state ();
1204 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1206 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1209 /* Insert/remove unaligned watchpoint by calling
1210 aarch64_align_watchpoint repeatedly until the whole watched region,
1211 as represented by ADDR and LEN, has been properly aligned and ready
1212 to be written to one or more hardware watchpoint registers.
1213 IS_INSERT indicates whether this is an insertion or a deletion.
1214 Return 0 if succeed. */
1217 aarch64_handle_unaligned_watchpoint (int type
, CORE_ADDR addr
, int len
,
1220 struct aarch64_debug_reg_state
*state
= aarch64_get_debug_reg_state ();
1224 CORE_ADDR aligned_addr
;
1225 int aligned_len
, ret
;
1227 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
1231 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
1234 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
1237 if (debug_hw_points
)
1238 fprintf_unfiltered (gdb_stdlog
,
1239 "handle_unaligned_watchpoint: is_insert: %d\n"
1240 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1241 " next_addr: 0x%08lx, next_len: %d\n",
1242 is_insert
, aligned_addr
, aligned_len
, addr
, len
);
1251 /* Implements insertion and removal of a single watchpoint. */
1254 aarch64_handle_watchpoint (int type
, CORE_ADDR addr
, int len
, int is_insert
)
1256 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
1257 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
);
1259 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
);
1262 /* Implement the "to_insert_watchpoint" target_ops method.
1264 Insert a watchpoint to watch a memory region which starts at
1265 address ADDR and whose length is LEN bytes. Watch memory accesses
1266 of the type TYPE. Return 0 on success, -1 on failure. */
1269 aarch64_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int type
,
1270 struct expression
*cond
)
1274 if (debug_hw_points
)
1275 fprintf_unfiltered (gdb_stdlog
,
1276 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1277 (unsigned long) addr
, len
);
1279 gdb_assert (type
!= hw_execute
);
1281 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 1 /* is_insert */);
1283 if (debug_hw_points
> 1)
1284 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1285 "insert_watchpoint", addr
, len
, type
);
1290 /* Implement the "to_remove_watchpoint" target_ops method.
1291 Remove a watchpoint that watched the memory region which starts at
1292 address ADDR, whose length is LEN bytes, and for accesses of the
1293 type TYPE. Return 0 on success, -1 on failure. */
1296 aarch64_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int type
,
1297 struct expression
*cond
)
1301 if (debug_hw_points
)
1302 fprintf_unfiltered (gdb_stdlog
,
1303 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1304 (unsigned long) addr
, len
);
1306 gdb_assert (type
!= hw_execute
);
1308 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 0 /* is_insert */);
1310 if (debug_hw_points
> 1)
1311 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1312 "remove_watchpoint", addr
, len
, type
);
1317 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1320 aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1322 CORE_ADDR aligned_addr
;
1324 /* Can not set watchpoints for zero or negative lengths. */
1328 /* Must have hardware watchpoint debug register(s). */
1329 if (aarch64_num_wp_regs
== 0)
1332 /* We support unaligned watchpoint address and arbitrary length,
1333 as long as the size of the whole watched area after alignment
1334 doesn't exceed size of the total area that all watchpoint debug
1335 registers can watch cooperatively.
1337 This is a very relaxed rule, but unfortunately there are
1338 limitations, e.g. false-positive hits, due to limited support of
1339 hardware debug registers in the kernel. See comment above
1340 aarch64_align_watchpoint for more information. */
1342 aligned_addr
= addr
& ~(AARCH64_HWP_MAX_LEN_PER_REG
- 1);
1343 if (aligned_addr
+ aarch64_num_wp_regs
* AARCH64_HWP_MAX_LEN_PER_REG
1347 /* All tests passed so we are likely to be able to set the watchpoint.
1348 The reason that it is 'likely' rather than 'must' is because
1349 we don't check the current usage of the watchpoint registers, and
1350 there may not be enough registers available for this watchpoint.
1351 Ideally we should check the cached debug register state, however
1352 the checking is costly. */
1356 /* Implement the "to_stopped_data_address" target_ops method. */
1359 aarch64_linux_stopped_data_address (struct target_ops
*target
,
1364 struct aarch64_debug_reg_state
*state
;
1366 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
1369 /* This must be a hardware breakpoint. */
1370 if (siginfo
.si_signo
!= SIGTRAP
1371 || (siginfo
.si_code
& 0xffff) != TRAP_HWBKPT
)
1374 /* Check if the address matches any watched address. */
1375 state
= aarch64_get_debug_reg_state ();
1376 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1378 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1379 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1380 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1382 if (state
->dr_ref_count_wp
[i
]
1383 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1384 && addr_trap
>= addr_watch
1385 && addr_trap
< addr_watch
+ len
)
1387 *addr_p
= addr_trap
;
1395 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1398 aarch64_linux_stopped_by_watchpoint (void)
1402 return aarch64_linux_stopped_data_address (¤t_target
, &addr
);
1405 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1408 aarch64_linux_watchpoint_addr_within_range (struct target_ops
*target
,
1410 CORE_ADDR start
, int length
)
1412 return start
<= addr
&& start
+ length
- 1 >= addr
;
1415 /* Define AArch64 maintenance commands. */
1418 add_show_debug_regs_command (void)
1420 /* A maintenance command to enable printing the internal DRi mirror
1422 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
1423 &debug_hw_points
, _("\
1424 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1425 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1426 Use \"on\" to enable, \"off\" to disable.\n\
1427 If enabled, the debug registers values are shown when GDB inserts\n\
1428 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1429 triggers a breakpoint or watchpoint."),
1432 &maintenance_set_cmdlist
,
1433 &maintenance_show_cmdlist
);
1436 /* -Wmissing-prototypes. */
1437 void _initialize_aarch64_linux_nat (void);
1440 _initialize_aarch64_linux_nat (void)
1442 struct target_ops
*t
;
1444 /* Fill in the generic GNU/Linux methods. */
1445 t
= linux_target ();
1447 add_show_debug_regs_command ();
1449 /* Add our register access methods. */
1450 t
->to_fetch_registers
= aarch64_linux_fetch_inferior_registers
;
1451 t
->to_store_registers
= aarch64_linux_store_inferior_registers
;
1453 t
->to_read_description
= aarch64_linux_read_description
;
1455 t
->to_can_use_hw_breakpoint
= aarch64_linux_can_use_hw_breakpoint
;
1456 t
->to_insert_hw_breakpoint
= aarch64_linux_insert_hw_breakpoint
;
1457 t
->to_remove_hw_breakpoint
= aarch64_linux_remove_hw_breakpoint
;
1458 t
->to_region_ok_for_hw_watchpoint
=
1459 aarch64_linux_region_ok_for_hw_watchpoint
;
1460 t
->to_insert_watchpoint
= aarch64_linux_insert_watchpoint
;
1461 t
->to_remove_watchpoint
= aarch64_linux_remove_watchpoint
;
1462 t
->to_stopped_by_watchpoint
= aarch64_linux_stopped_by_watchpoint
;
1463 t
->to_stopped_data_address
= aarch64_linux_stopped_data_address
;
1464 t
->to_watchpoint_addr_within_range
=
1465 aarch64_linux_watchpoint_addr_within_range
;
1466 if (aarch64_inferior_data
== NULL
)
1467 aarch64_inferior_data
1468 = register_inferior_data_with_cleanup (NULL
,
1469 aarch64_inferior_data_cleanup
);
1471 /* Override the GNU/Linux inferior startup hook. */
1472 super_post_startup_inferior
= t
->to_post_startup_inferior
;
1473 t
->to_post_startup_inferior
= aarch64_linux_child_post_startup_inferior
;
1475 /* Register the target. */
1476 linux_nat_add_target (t
);
1477 linux_nat_set_new_thread (t
, aarch64_linux_new_thread
);
1478 linux_nat_set_prepare_to_resume (t
, aarch64_linux_prepare_to_resume
);