1 /* Native-dependent code for GNU/Linux AArch64.
3 Copyright (C) 2011-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "linux-nat.h"
27 #include "target-descriptions.h"
30 #include "aarch64-tdep.h"
31 #include "aarch64-linux-tdep.h"
32 #include "aarch32-linux-nat.h"
34 #include "elf/external.h"
35 #include "elf/common.h"
37 #include <sys/ptrace.h>
38 #include <sys/utsname.h>
39 #include <asm/ptrace.h>
43 /* Defines ps_err_e, struct ps_prochandle. */
44 #include "gdb_proc_service.h"
47 #define TRAP_HWBKPT 0x0004
50 /* On GNU/Linux, threads are implemented as pseudo-processes, in which
51 case we may be tracing more than one process at a time. In that
52 case, inferior_ptid will contain the main process ID and the
53 individual thread (process) ID. get_thread_id () is used to get
54 the thread id if it's available, and the process id otherwise. */
57 get_thread_id (ptid_t ptid
)
59 int tid
= ptid_get_lwp (ptid
);
62 tid
= ptid_get_pid (ptid
);
66 /* Macro definitions, data structures, and code for the hardware
67 breakpoint and hardware watchpoint support follow. We use the
68 following abbreviations throughout the code:
74 /* Maximum number of hardware breakpoint and watchpoint registers.
75 Neither of these values may exceed the width of dr_changed_t
78 #define AARCH64_HBP_MAX_NUM 16
79 #define AARCH64_HWP_MAX_NUM 16
81 /* Alignment requirement in bytes for addresses written to
82 hardware breakpoint and watchpoint value registers.
84 A ptrace call attempting to set an address that does not meet the
85 alignment criteria will fail. Limited support has been provided in
86 this port for unaligned watchpoints, such that from a GDB user
87 perspective, an unaligned watchpoint may be requested.
89 This is achieved by minimally enlarging the watched area to meet the
90 alignment requirement, and if necessary, splitting the watchpoint
91 over several hardware watchpoint registers. */
93 #define AARCH64_HBP_ALIGNMENT 4
94 #define AARCH64_HWP_ALIGNMENT 8
96 /* The maximum length of a memory region that can be watched by one
97 hardware watchpoint register. */
99 #define AARCH64_HWP_MAX_LEN_PER_REG 8
101 /* ptrace hardware breakpoint resource info is formatted as follows:
104 +---------------+--------------+---------------+---------------+
105 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
106 +---------------+--------------+---------------+---------------+ */
109 /* Macros to extract fields from the hardware debug information word. */
110 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
111 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
113 /* Macro for the expected version of the ARMv8-A debug architecture. */
114 #define AARCH64_DEBUG_ARCH_V8 0x6
116 /* Number of hardware breakpoints/watchpoints the target supports.
117 They are initialized with values obtained via the ptrace calls
118 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
120 static int aarch64_num_bp_regs
;
121 static int aarch64_num_wp_regs
;
123 /* Each bit of a variable of this type is used to indicate whether a
124 hardware breakpoint or watchpoint setting has been changed since
127 Bit N corresponds to the Nth hardware breakpoint or watchpoint
128 setting which is managed in aarch64_debug_reg_state, where N is
129 valid between 0 and the total number of the hardware breakpoint or
130 watchpoint debug registers minus 1.
132 When bit N is 1, the corresponding breakpoint or watchpoint setting
133 has changed, and therefore the corresponding hardware debug
134 register needs to be updated via the ptrace interface.
136 In the per-thread arch-specific data area, we define two such
137 variables for per-thread hardware breakpoint and watchpoint
138 settings respectively.
140 This type is part of the mechanism which helps reduce the number of
141 ptrace calls to the kernel, i.e. avoid asking the kernel to write
142 to the debug registers with unchanged values. */
144 typedef ULONGEST dr_changed_t
;
146 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
148 #define DR_MARK_ALL_CHANGED(x, m) \
151 gdb_assert (sizeof ((x)) * 8 >= (m)); \
152 (x) = (((dr_changed_t)1 << (m)) - 1); \
155 #define DR_MARK_N_CHANGED(x, n) \
158 (x) |= ((dr_changed_t)1 << (n)); \
161 #define DR_CLEAR_CHANGED(x) \
167 #define DR_HAS_CHANGED(x) ((x) != 0)
168 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
170 /* Structure for managing the hardware breakpoint/watchpoint resources.
171 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
172 content, and DR_REF_COUNT_* counts the numbers of references to the
173 corresponding bp/wp, by which way the limited hardware resources
174 are not wasted on duplicated bp/wp settings (though so far gdb has
175 done a good job by not sending duplicated bp/wp requests). */
177 struct aarch64_debug_reg_state
179 /* hardware breakpoint */
180 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
181 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
182 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
184 /* hardware watchpoint */
185 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
186 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
187 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
190 /* Per-process data. We don't bind this to a per-inferior registry
191 because of targets like x86 GNU/Linux that need to keep track of
192 processes that aren't bound to any inferior (e.g., fork children,
195 struct aarch64_process_info
198 struct aarch64_process_info
*next
;
200 /* The process identifier. */
203 /* Copy of aarch64 hardware debug registers. */
204 struct aarch64_debug_reg_state state
;
207 static struct aarch64_process_info
*aarch64_process_list
= NULL
;
209 /* Find process data for process PID. */
211 static struct aarch64_process_info
*
212 aarch64_find_process_pid (pid_t pid
)
214 struct aarch64_process_info
*proc
;
216 for (proc
= aarch64_process_list
; proc
; proc
= proc
->next
)
217 if (proc
->pid
== pid
)
223 /* Add process data for process PID. Returns newly allocated info
226 static struct aarch64_process_info
*
227 aarch64_add_process (pid_t pid
)
229 struct aarch64_process_info
*proc
;
231 proc
= xcalloc (1, sizeof (*proc
));
234 proc
->next
= aarch64_process_list
;
235 aarch64_process_list
= proc
;
240 /* Get data specific info for process PID, creating it if necessary.
241 Never returns NULL. */
243 static struct aarch64_process_info
*
244 aarch64_process_info_get (pid_t pid
)
246 struct aarch64_process_info
*proc
;
248 proc
= aarch64_find_process_pid (pid
);
250 proc
= aarch64_add_process (pid
);
255 /* Called whenever GDB is no longer debugging process PID. It deletes
256 data structures that keep track of debug register state. */
259 aarch64_forget_process (pid_t pid
)
261 struct aarch64_process_info
*proc
, **proc_link
;
263 proc
= aarch64_process_list
;
264 proc_link
= &aarch64_process_list
;
268 if (proc
->pid
== pid
)
270 *proc_link
= proc
->next
;
276 proc_link
= &proc
->next
;
281 /* Get debug registers state for process PID. */
283 static struct aarch64_debug_reg_state
*
284 aarch64_get_debug_reg_state (pid_t pid
)
286 return &aarch64_process_info_get (pid
)->state
;
289 /* Per-thread arch-specific data we want to keep. */
293 /* When bit N is 1, it indicates the Nth hardware breakpoint or
294 watchpoint register pair needs to be updated when the thread is
295 resumed; see aarch64_linux_prepare_to_resume. */
296 dr_changed_t dr_changed_bp
;
297 dr_changed_t dr_changed_wp
;
300 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
301 registers with data from *STATE. */
304 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
305 int tid
, int watchpoint
)
309 struct user_hwdebug_state regs
;
310 const CORE_ADDR
*addr
;
311 const unsigned int *ctrl
;
313 memset (®s
, 0, sizeof (regs
));
314 iov
.iov_base
= ®s
;
315 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
316 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
317 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
320 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
[count
- 1])
321 + sizeof (regs
.dbg_regs
[count
- 1]));
323 for (i
= 0; i
< count
; i
++)
325 regs
.dbg_regs
[i
].addr
= addr
[i
];
326 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
329 if (ptrace (PTRACE_SETREGSET
, tid
,
330 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
332 error (_("Unexpected error setting hardware debug registers"));
335 struct aarch64_dr_update_callback_param
341 /* Callback for iterate_over_lwps. Records the
342 information about the change of one hardware breakpoint/watchpoint
343 setting for the thread LWP.
344 The information is passed in via PTR.
345 N.B. The actual updating of hardware debug registers is not
346 carried out until the moment the thread is resumed. */
349 debug_reg_change_callback (struct lwp_info
*lwp
, void *ptr
)
351 struct aarch64_dr_update_callback_param
*param_p
352 = (struct aarch64_dr_update_callback_param
*) ptr
;
353 int pid
= get_thread_id (lwp
->ptid
);
354 int idx
= param_p
->idx
;
355 int is_watchpoint
= param_p
->is_watchpoint
;
356 struct arch_lwp_info
*info
= lwp
->arch_private
;
357 dr_changed_t
*dr_changed_ptr
;
358 dr_changed_t dr_changed
;
361 info
= lwp
->arch_private
= XCNEW (struct arch_lwp_info
);
365 fprintf_unfiltered (gdb_stdlog
,
366 "debug_reg_change_callback: \n\tOn entry:\n");
367 fprintf_unfiltered (gdb_stdlog
,
368 "\tpid%d, dr_changed_bp=0x%s, "
369 "dr_changed_wp=0x%s\n",
370 pid
, phex (info
->dr_changed_bp
, 8),
371 phex (info
->dr_changed_wp
, 8));
374 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
375 : &info
->dr_changed_bp
;
376 dr_changed
= *dr_changed_ptr
;
379 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
380 : aarch64_num_bp_regs
)));
382 /* The actual update is done later just before resuming the lwp,
383 we just mark that one register pair needs updating. */
384 DR_MARK_N_CHANGED (dr_changed
, idx
);
385 *dr_changed_ptr
= dr_changed
;
387 /* If the lwp isn't stopped, force it to momentarily pause, so
388 we can update its debug registers. */
390 linux_stop_lwp (lwp
);
394 fprintf_unfiltered (gdb_stdlog
,
395 "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
396 "dr_changed_wp=0x%s\n",
397 pid
, phex (info
->dr_changed_bp
, 8),
398 phex (info
->dr_changed_wp
, 8));
401 /* Continue the iteration. */
405 /* Notify each thread that their IDXth breakpoint/watchpoint register
406 pair needs to be updated. The message will be recorded in each
407 thread's arch-specific data area, the actual updating will be done
408 when the thread is resumed. */
411 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
412 int is_watchpoint
, unsigned int idx
)
414 struct aarch64_dr_update_callback_param param
;
415 ptid_t pid_ptid
= pid_to_ptid (ptid_get_pid (inferior_ptid
));
417 param
.is_watchpoint
= is_watchpoint
;
420 iterate_over_lwps (pid_ptid
, debug_reg_change_callback
, (void *) ¶m
);
423 /* Print the values of the cached breakpoint/watchpoint registers. */
426 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
427 const char *func
, CORE_ADDR addr
,
432 debug_printf ("%s", func
);
434 debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
435 (unsigned long) addr
, len
,
436 type
== hw_write
? "hw-write-watchpoint"
437 : (type
== hw_read
? "hw-read-watchpoint"
438 : (type
== hw_access
? "hw-access-watchpoint"
439 : (type
== hw_execute
? "hw-breakpoint"
441 debug_printf (":\n");
443 debug_printf ("\tBREAKPOINTs:\n");
444 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
445 debug_printf ("\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
446 i
, state
->dr_addr_bp
[i
],
447 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
449 debug_printf ("\tWATCHPOINTs:\n");
450 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
451 debug_printf ("\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
452 i
, state
->dr_addr_wp
[i
],
453 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
456 /* Fill GDB's register array with the general-purpose register values
457 from the current thread. */
460 fetch_gregs_from_thread (struct regcache
*regcache
)
463 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
467 /* Make sure REGS can hold all registers contents on both aarch64
469 gdb_static_assert (sizeof (regs
) >= 18 * 4);
471 tid
= get_thread_id (inferior_ptid
);
473 iovec
.iov_base
= ®s
;
474 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
475 iovec
.iov_len
= 18 * 4;
477 iovec
.iov_len
= sizeof (regs
);
479 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
481 perror_with_name (_("Unable to fetch general registers."));
483 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
484 aarch32_gp_regcache_supply (regcache
, (uint32_t *) regs
, 1);
489 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
490 regcache_raw_supply (regcache
, regno
, ®s
[regno
- AARCH64_X0_REGNUM
]);
494 /* Store to the current thread the valid general-purpose register
495 values in the GDB's register array. */
498 store_gregs_to_thread (const struct regcache
*regcache
)
503 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
505 /* Make sure REGS can hold all registers contents on both aarch64
507 gdb_static_assert (sizeof (regs
) >= 18 * 4);
508 tid
= get_thread_id (inferior_ptid
);
510 iovec
.iov_base
= ®s
;
511 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
512 iovec
.iov_len
= 18 * 4;
514 iovec
.iov_len
= sizeof (regs
);
516 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
518 perror_with_name (_("Unable to fetch general registers."));
520 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
521 aarch32_gp_regcache_collect (regcache
, (uint32_t *) regs
, 1);
526 for (regno
= AARCH64_X0_REGNUM
; regno
<= AARCH64_CPSR_REGNUM
; regno
++)
527 if (REG_VALID
== regcache_register_status (regcache
, regno
))
528 regcache_raw_collect (regcache
, regno
,
529 ®s
[regno
- AARCH64_X0_REGNUM
]);
532 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_PRSTATUS
, &iovec
);
534 perror_with_name (_("Unable to store general registers."));
537 /* Fill GDB's register array with the fp/simd register values
538 from the current thread. */
541 fetch_fpregs_from_thread (struct regcache
*regcache
)
546 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
548 /* Make sure REGS can hold all VFP registers contents on both aarch64
550 gdb_static_assert (sizeof regs
>= VFP_REGS_SIZE
);
552 tid
= get_thread_id (inferior_ptid
);
554 iovec
.iov_base
= ®s
;
556 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
558 iovec
.iov_len
= VFP_REGS_SIZE
;
560 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
562 perror_with_name (_("Unable to fetch VFP registers."));
564 aarch32_vfp_regcache_supply (regcache
, (gdb_byte
*) ®s
, 32);
570 iovec
.iov_len
= sizeof (regs
);
572 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
574 perror_with_name (_("Unable to fetch vFP/SIMD registers."));
576 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
577 regcache_raw_supply (regcache
, regno
,
578 ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
580 regcache_raw_supply (regcache
, AARCH64_FPSR_REGNUM
, ®s
.fpsr
);
581 regcache_raw_supply (regcache
, AARCH64_FPCR_REGNUM
, ®s
.fpcr
);
585 /* Store to the current thread the valid fp/simd register
586 values in the GDB's register array. */
589 store_fpregs_to_thread (const struct regcache
*regcache
)
594 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
596 /* Make sure REGS can hold all VFP registers contents on both aarch64
598 gdb_static_assert (sizeof regs
>= VFP_REGS_SIZE
);
599 tid
= get_thread_id (inferior_ptid
);
601 iovec
.iov_base
= ®s
;
603 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
605 iovec
.iov_len
= VFP_REGS_SIZE
;
607 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
609 perror_with_name (_("Unable to fetch VFP registers."));
611 aarch32_vfp_regcache_collect (regcache
, (gdb_byte
*) ®s
, 32);
617 iovec
.iov_len
= sizeof (regs
);
619 ret
= ptrace (PTRACE_GETREGSET
, tid
, NT_FPREGSET
, &iovec
);
621 perror_with_name (_("Unable to fetch FP/SIMD registers."));
623 for (regno
= AARCH64_V0_REGNUM
; regno
<= AARCH64_V31_REGNUM
; regno
++)
624 if (REG_VALID
== regcache_register_status (regcache
, regno
))
625 regcache_raw_collect (regcache
, regno
,
626 (char *) ®s
.vregs
[regno
- AARCH64_V0_REGNUM
]);
628 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPSR_REGNUM
))
629 regcache_raw_collect (regcache
, AARCH64_FPSR_REGNUM
,
630 (char *) ®s
.fpsr
);
631 if (REG_VALID
== regcache_register_status (regcache
, AARCH64_FPCR_REGNUM
))
632 regcache_raw_collect (regcache
, AARCH64_FPCR_REGNUM
,
633 (char *) ®s
.fpcr
);
636 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 32)
638 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_ARM_VFP
, &iovec
);
640 perror_with_name (_("Unable to store VFP registers."));
644 ret
= ptrace (PTRACE_SETREGSET
, tid
, NT_FPREGSET
, &iovec
);
646 perror_with_name (_("Unable to store FP/SIMD registers."));
650 /* Implement the "to_fetch_register" target_ops method. */
653 aarch64_linux_fetch_inferior_registers (struct target_ops
*ops
,
654 struct regcache
*regcache
,
659 fetch_gregs_from_thread (regcache
);
660 fetch_fpregs_from_thread (regcache
);
662 else if (regno
< AARCH64_V0_REGNUM
)
663 fetch_gregs_from_thread (regcache
);
665 fetch_fpregs_from_thread (regcache
);
668 /* Implement the "to_store_register" target_ops method. */
671 aarch64_linux_store_inferior_registers (struct target_ops
*ops
,
672 struct regcache
*regcache
,
677 store_gregs_to_thread (regcache
);
678 store_fpregs_to_thread (regcache
);
680 else if (regno
< AARCH64_V0_REGNUM
)
681 store_gregs_to_thread (regcache
);
683 store_fpregs_to_thread (regcache
);
686 /* Fill register REGNO (if it is a general-purpose register) in
687 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
688 do this for all registers. */
691 fill_gregset (const struct regcache
*regcache
,
692 gdb_gregset_t
*gregsetp
, int regno
)
694 regcache_collect_regset (&aarch64_linux_gregset
, regcache
,
695 regno
, (gdb_byte
*) gregsetp
,
696 AARCH64_LINUX_SIZEOF_GREGSET
);
699 /* Fill GDB's register array with the general-purpose register values
703 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
705 regcache_supply_regset (&aarch64_linux_gregset
, regcache
, -1,
706 (const gdb_byte
*) gregsetp
,
707 AARCH64_LINUX_SIZEOF_GREGSET
);
710 /* Fill register REGNO (if it is a floating-point register) in
711 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
712 do this for all registers. */
715 fill_fpregset (const struct regcache
*regcache
,
716 gdb_fpregset_t
*fpregsetp
, int regno
)
718 regcache_collect_regset (&aarch64_linux_fpregset
, regcache
,
719 regno
, (gdb_byte
*) fpregsetp
,
720 AARCH64_LINUX_SIZEOF_FPREGSET
);
723 /* Fill GDB's register array with the floating-point register values
727 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
729 regcache_supply_regset (&aarch64_linux_fpregset
, regcache
, -1,
730 (const gdb_byte
*) fpregsetp
,
731 AARCH64_LINUX_SIZEOF_FPREGSET
);
734 /* Called when resuming a thread.
735 The hardware debug registers are updated when there is any change. */
738 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
740 struct arch_lwp_info
*info
= lwp
->arch_private
;
742 /* NULL means this is the main thread still going through the shell,
743 or, no watchpoint has been set yet. In that case, there's
748 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
749 || DR_HAS_CHANGED (info
->dr_changed_wp
))
751 int tid
= ptid_get_lwp (lwp
->ptid
);
752 struct aarch64_debug_reg_state
*state
753 = aarch64_get_debug_reg_state (ptid_get_pid (lwp
->ptid
));
756 fprintf_unfiltered (gdb_stdlog
, "prepare_to_resume thread %d\n", tid
);
759 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
761 aarch64_linux_set_debug_regs (state
, tid
, 1);
762 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
766 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
768 aarch64_linux_set_debug_regs (state
, tid
, 0);
769 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
775 aarch64_linux_new_thread (struct lwp_info
*lp
)
777 struct arch_lwp_info
*info
= XCNEW (struct arch_lwp_info
);
779 /* Mark that all the hardware breakpoint/watchpoint register pairs
780 for this thread need to be initialized. */
781 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
782 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
784 lp
->arch_private
= info
;
787 /* linux_nat_new_fork hook. */
790 aarch64_linux_new_fork (struct lwp_info
*parent
, pid_t child_pid
)
793 struct aarch64_debug_reg_state
*parent_state
;
794 struct aarch64_debug_reg_state
*child_state
;
796 /* NULL means no watchpoint has ever been set in the parent. In
797 that case, there's nothing to do. */
798 if (parent
->arch_private
== NULL
)
801 /* GDB core assumes the child inherits the watchpoints/hw
802 breakpoints of the parent, and will remove them all from the
803 forked off process. Copy the debug registers mirrors into the
804 new process so that all breakpoints and watchpoints can be
807 parent_pid
= ptid_get_pid (parent
->ptid
);
808 parent_state
= aarch64_get_debug_reg_state (parent_pid
);
809 child_state
= aarch64_get_debug_reg_state (child_pid
);
810 *child_state
= *parent_state
;
814 /* Called by libthread_db. Returns a pointer to the thread local
815 storage (or its descriptor). */
818 ps_get_thread_area (const struct ps_prochandle
*ph
,
819 lwpid_t lwpid
, int idx
, void **base
)
824 iovec
.iov_base
= ®
;
825 iovec
.iov_len
= sizeof (reg
);
827 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
830 /* IDX is the bias from the thread pointer to the beginning of the
831 thread descriptor. It has to be subtracted due to implementation
832 quirks in libthread_db. */
833 *base
= (void *) (reg
- idx
);
839 /* Get the hardware debug register capacity information from the
840 inferior represented by PTID. */
843 aarch64_linux_get_debug_reg_capacity (ptid_t ptid
)
847 struct user_hwdebug_state dreg_state
;
849 tid
= ptid_get_pid (ptid
);
850 iov
.iov_base
= &dreg_state
;
851 iov
.iov_len
= sizeof (dreg_state
);
853 /* Get hardware watchpoint register info. */
854 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_WATCH
, &iov
) == 0
855 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
857 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
858 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
860 warning (_("Unexpected number of hardware watchpoint registers"
861 " reported by ptrace, got %d, expected %d."),
862 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
863 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
868 warning (_("Unable to determine the number of hardware watchpoints"
870 aarch64_num_wp_regs
= 0;
873 /* Get hardware breakpoint register info. */
874 if (ptrace (PTRACE_GETREGSET
, tid
, NT_ARM_HW_BREAK
, &iov
) == 0
875 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
877 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
878 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
880 warning (_("Unexpected number of hardware breakpoint registers"
881 " reported by ptrace, got %d, expected %d."),
882 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
883 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
888 warning (_("Unable to determine the number of hardware breakpoints"
890 aarch64_num_bp_regs
= 0;
894 static void (*super_post_startup_inferior
) (struct target_ops
*self
,
897 /* Implement the "to_post_startup_inferior" target_ops method. */
900 aarch64_linux_child_post_startup_inferior (struct target_ops
*self
,
903 aarch64_forget_process (ptid_get_pid (ptid
));
904 aarch64_linux_get_debug_reg_capacity (ptid
);
905 super_post_startup_inferior (self
, ptid
);
908 extern struct target_desc
*tdesc_arm_with_vfpv3
;
909 extern struct target_desc
*tdesc_arm_with_neon
;
911 /* Implement the "to_read_description" target_ops method. */
913 static const struct target_desc
*
914 aarch64_linux_read_description (struct target_ops
*ops
)
918 if (target_auxv_search (ops
, AT_PHENT
, &at_phent
) == 1)
920 if (at_phent
== sizeof (Elf64_External_Phdr
))
921 return tdesc_aarch64
;
924 CORE_ADDR arm_hwcap
= 0;
926 if (target_auxv_search (ops
, AT_HWCAP
, &arm_hwcap
) != 1)
927 return ops
->beneath
->to_read_description (ops
->beneath
);
929 #ifndef COMPAT_HWCAP_VFP
930 #define COMPAT_HWCAP_VFP (1 << 6)
932 #ifndef COMPAT_HWCAP_NEON
933 #define COMPAT_HWCAP_NEON (1 << 12)
935 #ifndef COMPAT_HWCAP_VFPv3
936 #define COMPAT_HWCAP_VFPv3 (1 << 13)
939 if (arm_hwcap
& COMPAT_HWCAP_VFP
)
942 const struct target_desc
*result
= NULL
;
944 if (arm_hwcap
& COMPAT_HWCAP_NEON
)
945 result
= tdesc_arm_with_neon
;
946 else if (arm_hwcap
& COMPAT_HWCAP_VFPv3
)
947 result
= tdesc_arm_with_vfpv3
;
956 return tdesc_aarch64
;
959 /* Given the (potentially unaligned) watchpoint address in ADDR and
960 length in LEN, return the aligned address and aligned length in
961 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
962 aligned address and length will be valid values to write to the
963 hardware watchpoint value and control registers.
965 The given watchpoint may get truncated if more than one hardware
966 register is needed to cover the watched region. *NEXT_ADDR_P
967 and *NEXT_LEN_P, if non-NULL, will return the address and length
968 of the remaining part of the watchpoint (which can be processed
969 by calling this routine again to generate another aligned address
972 See the comment above the function of the same name in
973 gdbserver/linux-aarch64-low.c for more information. */
976 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
977 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
982 CORE_ADDR aligned_addr
;
983 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
984 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
986 /* As assumed by the algorithm. */
987 gdb_assert (alignment
== max_wp_len
);
992 /* Address to be put into the hardware watchpoint value register
994 offset
= addr
& (alignment
- 1);
995 aligned_addr
= addr
- offset
;
997 gdb_assert (offset
>= 0 && offset
< alignment
);
998 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
999 gdb_assert (offset
+ len
> 0);
1001 if (offset
+ len
>= max_wp_len
)
1003 /* Need more than one watchpoint registers; truncate it at the
1004 alignment boundary. */
1005 aligned_len
= max_wp_len
;
1006 len
-= (max_wp_len
- offset
);
1007 addr
+= (max_wp_len
- offset
);
1008 gdb_assert ((addr
& (alignment
- 1)) == 0);
1012 /* Find the smallest valid length that is large enough to
1013 accommodate this watchpoint. */
1014 static const unsigned char
1015 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
1016 { 1, 2, 4, 4, 8, 8, 8, 8 };
1018 aligned_len
= aligned_len_array
[offset
+ len
- 1];
1024 *aligned_addr_p
= aligned_addr
;
1026 *aligned_len_p
= aligned_len
;
1028 *next_addr_p
= addr
;
1033 /* Returns the number of hardware watchpoints of type TYPE that we can
1034 set. Value is positive if we can set CNT watchpoints, zero if
1035 setting watchpoints of type TYPE is not supported, and negative if
1036 CNT is more than the maximum number of watchpoints of type TYPE
1037 that we can support. TYPE is one of bp_hardware_watchpoint,
1038 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
1039 CNT is the number of such watchpoints used so far (including this
1040 one). OTHERTYPE is non-zero if other types of watchpoints are
1043 We always return 1 here because we don't have enough information
1044 about possible overlap of addresses that they want to watch. As an
1045 extreme example, consider the case where all the watchpoints watch
1046 the same address and the same region length: then we can handle a
1047 virtually unlimited number of watchpoints, due to debug register
1048 sharing implemented via reference counts. */
1051 aarch64_linux_can_use_hw_breakpoint (struct target_ops
*self
,
1052 int type
, int cnt
, int othertype
)
1057 /* ptrace expects control registers to be formatted as follows:
1060 +--------------------------------+----------+------+------+----+
1061 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
1062 +--------------------------------+----------+------+------+----+
1064 The TYPE field is ignored for breakpoints. */
1066 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
1067 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
1069 /* Utility function that returns the length in bytes of a watchpoint
1070 according to the content of a hardware debug control register CTRL.
1071 Note that the kernel currently only supports the following Byte
1072 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
1073 that for a hardware watchpoint, its valid length can only be 1
1074 byte, 2 bytes, 4 bytes or 8 bytes. */
1076 static inline unsigned int
1077 aarch64_watchpoint_length (unsigned int ctrl
)
1079 switch (DR_CONTROL_LENGTH (ctrl
))
1094 /* Given the hardware breakpoint or watchpoint type TYPE and its
1095 length LEN, return the expected encoding for a hardware
1096 breakpoint/watchpoint control register. */
1099 aarch64_point_encode_ctrl_reg (int type
, int len
)
1101 unsigned int ctrl
, ttype
;
1119 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
1123 /* length bitmask */
1124 ctrl
|= ((1 << len
) - 1) << 5;
1125 /* enabled at el0 */
1126 ctrl
|= (2 << 1) | 1;
1131 /* Addresses to be written to the hardware breakpoint and watchpoint
1132 value registers need to be aligned; the alignment is 4-byte and
1133 8-type respectively. Linux kernel rejects any non-aligned address
1134 it receives from the related ptrace call. Furthermore, the kernel
1135 currently only supports the following Byte Address Select (BAS)
1136 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
1137 watchpoint to be accepted by the kernel (via ptrace call), its
1138 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
1139 Despite these limitations, the unaligned watchpoint is supported in
1142 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
1145 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
1147 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
1148 : AARCH64_HBP_ALIGNMENT
;
1150 if (addr
& (alignment
- 1))
1153 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
1159 /* Record the insertion of one breakpoint/watchpoint, as represented
1160 by ADDR and CTRL, in the cached debug register state area *STATE. */
1163 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
1164 enum target_hw_bp_type type
, CORE_ADDR addr
,
1167 int i
, idx
, num_regs
, is_watchpoint
;
1168 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1169 CORE_ADDR
*dr_addr_p
;
1171 /* Set up state pointers. */
1172 is_watchpoint
= (type
!= hw_execute
);
1173 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1176 num_regs
= aarch64_num_wp_regs
;
1177 dr_addr_p
= state
->dr_addr_wp
;
1178 dr_ctrl_p
= state
->dr_ctrl_wp
;
1179 dr_ref_count
= state
->dr_ref_count_wp
;
1183 num_regs
= aarch64_num_bp_regs
;
1184 dr_addr_p
= state
->dr_addr_bp
;
1185 dr_ctrl_p
= state
->dr_ctrl_bp
;
1186 dr_ref_count
= state
->dr_ref_count_bp
;
1189 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1191 /* Find an existing or free register in our cache. */
1193 for (i
= 0; i
< num_regs
; ++i
)
1195 if ((dr_ctrl_p
[i
] & 1) == 0)
1197 gdb_assert (dr_ref_count
[i
] == 0);
1199 /* no break; continue hunting for an existing one. */
1201 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1203 gdb_assert (dr_ref_count
[i
] != 0);
1213 /* Update our cache. */
1214 if ((dr_ctrl_p
[idx
] & 1) == 0)
1217 dr_addr_p
[idx
] = addr
;
1218 dr_ctrl_p
[idx
] = ctrl
;
1219 dr_ref_count
[idx
] = 1;
1220 /* Notify the change. */
1221 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
1225 /* existing entry */
1226 dr_ref_count
[idx
]++;
1232 /* Record the removal of one breakpoint/watchpoint, as represented by
1233 ADDR and CTRL, in the cached debug register state area *STATE. */
1236 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
1237 enum target_hw_bp_type type
, CORE_ADDR addr
,
1240 int i
, num_regs
, is_watchpoint
;
1241 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
1242 CORE_ADDR
*dr_addr_p
;
1244 /* Set up state pointers. */
1245 is_watchpoint
= (type
!= hw_execute
);
1246 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
1249 num_regs
= aarch64_num_wp_regs
;
1250 dr_addr_p
= state
->dr_addr_wp
;
1251 dr_ctrl_p
= state
->dr_ctrl_wp
;
1252 dr_ref_count
= state
->dr_ref_count_wp
;
1256 num_regs
= aarch64_num_bp_regs
;
1257 dr_addr_p
= state
->dr_addr_bp
;
1258 dr_ctrl_p
= state
->dr_ctrl_bp
;
1259 dr_ref_count
= state
->dr_ref_count_bp
;
1262 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
1264 /* Find the entry that matches the ADDR and CTRL. */
1265 for (i
= 0; i
< num_regs
; ++i
)
1266 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
1268 gdb_assert (dr_ref_count
[i
] != 0);
1276 /* Clear our cache. */
1277 if (--dr_ref_count
[i
] == 0)
1279 /* Clear the enable bit. */
1282 dr_ctrl_p
[i
] = ctrl
;
1283 /* Notify the change. */
1284 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
1290 /* Implement insertion and removal of a single breakpoint. */
1293 aarch64_handle_breakpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
1294 int len
, int is_insert
,
1295 struct aarch64_debug_reg_state
*state
)
1297 /* The hardware breakpoint on AArch64 should always be 4-byte
1299 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
1303 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1305 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1308 /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address.
1309 Return 0 on success, -1 on failure. */
1312 aarch64_linux_insert_hw_breakpoint (struct target_ops
*self
,
1313 struct gdbarch
*gdbarch
,
1314 struct bp_target_info
*bp_tgt
)
1317 CORE_ADDR addr
= bp_tgt
->placed_address
= bp_tgt
->reqstd_address
;
1319 const enum target_hw_bp_type type
= hw_execute
;
1320 struct aarch64_debug_reg_state
*state
1321 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1323 if (show_debug_regs
)
1326 "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1327 (unsigned long) addr
, len
);
1329 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 1 /* is_insert */, state
);
1331 if (show_debug_regs
)
1333 aarch64_show_debug_reg_state (state
,
1334 "insert_hw_breakpoint", addr
, len
, type
);
1340 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
1341 Return 0 on success, -1 on failure. */
1344 aarch64_linux_remove_hw_breakpoint (struct target_ops
*self
,
1345 struct gdbarch
*gdbarch
,
1346 struct bp_target_info
*bp_tgt
)
1349 CORE_ADDR addr
= bp_tgt
->placed_address
;
1351 const enum target_hw_bp_type type
= hw_execute
;
1352 struct aarch64_debug_reg_state
*state
1353 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1355 if (show_debug_regs
)
1357 (gdb_stdlog
, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
1358 (unsigned long) addr
, len
);
1360 ret
= aarch64_handle_breakpoint (type
, addr
, len
, 0 /* is_insert */, state
);
1362 if (show_debug_regs
)
1364 aarch64_show_debug_reg_state (state
,
1365 "remove_hw_watchpoint", addr
, len
, type
);
1371 /* This is essentially the same as aarch64_handle_breakpoint, apart
1372 from that it is an aligned watchpoint to be handled. */
1375 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
1376 int len
, int is_insert
,
1377 struct aarch64_debug_reg_state
*state
)
1380 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
1382 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
1385 /* Insert/remove unaligned watchpoint by calling
1386 aarch64_align_watchpoint repeatedly until the whole watched region,
1387 as represented by ADDR and LEN, has been properly aligned and ready
1388 to be written to one or more hardware watchpoint registers.
1389 IS_INSERT indicates whether this is an insertion or a deletion.
1390 Return 0 if succeed. */
1393 aarch64_handle_unaligned_watchpoint (int type
, CORE_ADDR addr
, int len
,
1395 struct aarch64_debug_reg_state
*state
)
1399 CORE_ADDR aligned_addr
;
1400 int aligned_len
, ret
;
1402 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
1406 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
1409 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
1412 if (show_debug_regs
)
1414 "handle_unaligned_watchpoint: is_insert: %d\n"
1415 " aligned_addr: 0x%08lx, aligned_len: %d\n"
1416 " next_addr: 0x%08lx, next_len: %d\n",
1417 is_insert
, aligned_addr
, aligned_len
, addr
, len
);
1426 /* Implements insertion and removal of a single watchpoint. */
1429 aarch64_handle_watchpoint (int type
, CORE_ADDR addr
, int len
, int is_insert
,
1430 struct aarch64_debug_reg_state
*state
)
1432 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
1433 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
,
1436 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
,
1440 /* Implement the "to_insert_watchpoint" target_ops method.
1442 Insert a watchpoint to watch a memory region which starts at
1443 address ADDR and whose length is LEN bytes. Watch memory accesses
1444 of the type TYPE. Return 0 on success, -1 on failure. */
1447 aarch64_linux_insert_watchpoint (struct target_ops
*self
,
1448 CORE_ADDR addr
, int len
, int type
,
1449 struct expression
*cond
)
1452 struct aarch64_debug_reg_state
*state
1453 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1455 if (show_debug_regs
)
1456 fprintf_unfiltered (gdb_stdlog
,
1457 "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1458 (unsigned long) addr
, len
);
1460 gdb_assert (type
!= hw_execute
);
1462 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 1 /* is_insert */, state
);
1464 if (show_debug_regs
)
1466 aarch64_show_debug_reg_state (state
,
1467 "insert_watchpoint", addr
, len
, type
);
1473 /* Implement the "to_remove_watchpoint" target_ops method.
1474 Remove a watchpoint that watched the memory region which starts at
1475 address ADDR, whose length is LEN bytes, and for accesses of the
1476 type TYPE. Return 0 on success, -1 on failure. */
1479 aarch64_linux_remove_watchpoint (struct target_ops
*self
,
1480 CORE_ADDR addr
, int len
, int type
,
1481 struct expression
*cond
)
1484 struct aarch64_debug_reg_state
*state
1485 = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1487 if (show_debug_regs
)
1488 fprintf_unfiltered (gdb_stdlog
,
1489 "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
1490 (unsigned long) addr
, len
);
1492 gdb_assert (type
!= hw_execute
);
1494 ret
= aarch64_handle_watchpoint (type
, addr
, len
, 0 /* is_insert */, state
);
1496 if (show_debug_regs
)
1498 aarch64_show_debug_reg_state (state
,
1499 "remove_watchpoint", addr
, len
, type
);
1505 /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */
1508 aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops
*self
,
1509 CORE_ADDR addr
, int len
)
1511 CORE_ADDR aligned_addr
;
1513 /* Can not set watchpoints for zero or negative lengths. */
1517 /* Must have hardware watchpoint debug register(s). */
1518 if (aarch64_num_wp_regs
== 0)
1521 /* We support unaligned watchpoint address and arbitrary length,
1522 as long as the size of the whole watched area after alignment
1523 doesn't exceed size of the total area that all watchpoint debug
1524 registers can watch cooperatively.
1526 This is a very relaxed rule, but unfortunately there are
1527 limitations, e.g. false-positive hits, due to limited support of
1528 hardware debug registers in the kernel. See comment above
1529 aarch64_align_watchpoint for more information. */
1531 aligned_addr
= addr
& ~(AARCH64_HWP_MAX_LEN_PER_REG
- 1);
1532 if (aligned_addr
+ aarch64_num_wp_regs
* AARCH64_HWP_MAX_LEN_PER_REG
1536 /* All tests passed so we are likely to be able to set the watchpoint.
1537 The reason that it is 'likely' rather than 'must' is because
1538 we don't check the current usage of the watchpoint registers, and
1539 there may not be enough registers available for this watchpoint.
1540 Ideally we should check the cached debug register state, however
1541 the checking is costly. */
1545 /* Implement the "to_stopped_data_address" target_ops method. */
1548 aarch64_linux_stopped_data_address (struct target_ops
*target
,
1553 struct aarch64_debug_reg_state
*state
;
1555 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
1558 /* This must be a hardware breakpoint. */
1559 if (siginfo
.si_signo
!= SIGTRAP
1560 || (siginfo
.si_code
& 0xffff) != TRAP_HWBKPT
)
1563 /* Check if the address matches any watched address. */
1564 state
= aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid
));
1565 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1567 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1568 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1569 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1571 if (state
->dr_ref_count_wp
[i
]
1572 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1573 && addr_trap
>= addr_watch
1574 && addr_trap
< addr_watch
+ len
)
1576 *addr_p
= addr_trap
;
1584 /* Implement the "to_stopped_by_watchpoint" target_ops method. */
1587 aarch64_linux_stopped_by_watchpoint (struct target_ops
*ops
)
1591 return aarch64_linux_stopped_data_address (ops
, &addr
);
1594 /* Implement the "to_watchpoint_addr_within_range" target_ops method. */
1597 aarch64_linux_watchpoint_addr_within_range (struct target_ops
*target
,
1599 CORE_ADDR start
, int length
)
1601 return start
<= addr
&& start
+ length
- 1 >= addr
;
1604 /* Define AArch64 maintenance commands. */
1607 add_show_debug_regs_command (void)
1609 /* A maintenance command to enable printing the internal DRi mirror
1611 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
1612 &show_debug_regs
, _("\
1613 Set whether to show variables that mirror the AArch64 debug registers."), _("\
1614 Show whether to show variables that mirror the AArch64 debug registers."), _("\
1615 Use \"on\" to enable, \"off\" to disable.\n\
1616 If enabled, the debug registers values are shown when GDB inserts\n\
1617 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1618 triggers a breakpoint or watchpoint."),
1621 &maintenance_set_cmdlist
,
1622 &maintenance_show_cmdlist
);
1625 /* -Wmissing-prototypes. */
1626 void _initialize_aarch64_linux_nat (void);
1629 _initialize_aarch64_linux_nat (void)
1631 struct target_ops
*t
;
1633 /* Fill in the generic GNU/Linux methods. */
1634 t
= linux_target ();
1636 add_show_debug_regs_command ();
1638 /* Add our register access methods. */
1639 t
->to_fetch_registers
= aarch64_linux_fetch_inferior_registers
;
1640 t
->to_store_registers
= aarch64_linux_store_inferior_registers
;
1642 t
->to_read_description
= aarch64_linux_read_description
;
1644 t
->to_can_use_hw_breakpoint
= aarch64_linux_can_use_hw_breakpoint
;
1645 t
->to_insert_hw_breakpoint
= aarch64_linux_insert_hw_breakpoint
;
1646 t
->to_remove_hw_breakpoint
= aarch64_linux_remove_hw_breakpoint
;
1647 t
->to_region_ok_for_hw_watchpoint
=
1648 aarch64_linux_region_ok_for_hw_watchpoint
;
1649 t
->to_insert_watchpoint
= aarch64_linux_insert_watchpoint
;
1650 t
->to_remove_watchpoint
= aarch64_linux_remove_watchpoint
;
1651 t
->to_stopped_by_watchpoint
= aarch64_linux_stopped_by_watchpoint
;
1652 t
->to_stopped_data_address
= aarch64_linux_stopped_data_address
;
1653 t
->to_watchpoint_addr_within_range
=
1654 aarch64_linux_watchpoint_addr_within_range
;
1656 /* Override the GNU/Linux inferior startup hook. */
1657 super_post_startup_inferior
= t
->to_post_startup_inferior
;
1658 t
->to_post_startup_inferior
= aarch64_linux_child_post_startup_inferior
;
1660 /* Register the target. */
1661 linux_nat_add_target (t
);
1662 linux_nat_set_new_thread (t
, aarch64_linux_new_thread
);
1663 linux_nat_set_new_fork (t
, aarch64_linux_new_fork
);
1664 linux_nat_set_forget_process (t
, aarch64_forget_process
);
1665 linux_nat_set_prepare_to_resume (t
, aarch64_linux_prepare_to_resume
);