gdb/arc-tdep.c

   1 /* ARC target-dependent stuff.
   2    Copyright (C) 1995, 1997 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330,
  19    Boston, MA 02111-1307, USA.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "inferior.h"
  24 #include "gdbcore.h"
  25 #include "target.h"
  26 #include "floatformat.h"
  27 #include "symtab.h"
  28 #include "gdbcmd.h"
  29
  30 /* Local functions */
  31
  32 static int arc_set_cpu_type (char *str);
  33
  34 /* Current CPU, set with the "set cpu" command.  */
  35 static int arc_bfd_mach_type;
  36 char *arc_cpu_type;
  37 char *tmp_arc_cpu_type;
  38
  39 /* Table of cpu names.  */
  40 struct
  41   {
  42     char *name;
  43     int value;
  44   }
  45 arc_cpu_type_table[] =
  46 {
  47   {
  48     "base", bfd_mach_arc_base
  49   }
  50   ,
  51   {
  52     NULL, 0
  53   }
  54 };
  55
  56 /* Used by simulator.  */
  57 int display_pipeline_p;
  58 int cpu_timer;
  59 /* This one must have the same type as used in the emulator.
  60    It's currently an enum so this should be ok for now.  */
  61 int debug_pipeline_p;
  62
  63 #define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
  64
  65 #define OPMASK  0xf8000000
  66
  67 /* Instruction field accessor macros.
  68    See the Programmer's Reference Manual.  */
  69 #define X_OP(i) (((i) >> 27) & 0x1f)
  70 #define X_A(i) (((i) >> 21) & 0x3f)
  71 #define X_B(i) (((i) >> 15) & 0x3f)
  72 #define X_C(i) (((i) >> 9) & 0x3f)
  73 #define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
  74 #define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
  75 #define X_N(i) (((i) >> 5) & 3)
  76 #define X_Q(i) ((i) & 0x1f)
  77
  78 /* Return non-zero if X is a short immediate data indicator.  */
  79 #define SHIMM_P(x) ((x) == 61 || (x) == 63)
  80
  81 /* Return non-zero if X is a "long" (32 bit) immediate data indicator.  */
  82 #define LIMM_P(x) ((x) == 62)
  83
  84 /* Build a simple instruction.  */
  85 #define BUILD_INSN(op, a, b, c, d) \
  86   ((((op) & 31) << 27) \
  87    | (((a) & 63) << 21) \
  88    | (((b) & 63) << 15) \
  89    | (((c) & 63) << 9) \
  90    | ((d) & 511))
  91 \f
  92 /* Codestream stuff.  */
  93 static void codestream_read (unsigned int *, int);
  94 static void codestream_seek (CORE_ADDR);
  95 static unsigned int codestream_fill (int);
  96
  97 #define CODESTREAM_BUFSIZ 16
  98 static CORE_ADDR codestream_next_addr;
  99 static CORE_ADDR codestream_addr;
 100 /* FIXME assumes sizeof (int) == 32? */
 101 static unsigned int codestream_buf[CODESTREAM_BUFSIZ];
 102 static int codestream_off;
 103 static int codestream_cnt;
 104
 105 #define codestream_tell() \
 106   (codestream_addr + codestream_off * sizeof (codestream_buf[0]))
 107 #define codestream_peek() \
 108   (codestream_cnt == 0 \
 109    ? codestream_fill (1) \
 110    : codestream_buf[codestream_off])
 111 #define codestream_get() \
 112   (codestream_cnt-- == 0 \
 113    ? codestream_fill (0) \
 114    : codestream_buf[codestream_off++])
 115
 116 static unsigned int
 117 codestream_fill (int peek_flag)
 118 {
 119   codestream_addr = codestream_next_addr;
 120   codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]);
 121   codestream_off = 0;
 122   codestream_cnt = CODESTREAM_BUFSIZ;
 123   read_memory (codestream_addr, (char *) codestream_buf,
 124                CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]));
 125   /* FIXME: check return code?  */
 126
 127
 128   /* Handle byte order differences -> convert to host byte ordering.  */
 129   {
 130     int i;
 131     for (i = 0; i < CODESTREAM_BUFSIZ; i++)
 132       codestream_buf[i] =
 133         extract_unsigned_integer (&codestream_buf[i],
 134                                   sizeof (codestream_buf[i]));
 135   }
 136
 137   if (peek_flag)
 138     return codestream_peek ();
 139   else
 140     return codestream_get ();
 141 }
 142
 143 static void
 144 codestream_seek (CORE_ADDR place)
 145 {
 146   codestream_next_addr = place / CODESTREAM_BUFSIZ;
 147   codestream_next_addr *= CODESTREAM_BUFSIZ;
 148   codestream_cnt = 0;
 149   codestream_fill (1);
 150   while (codestream_tell () != place)
 151     codestream_get ();
 152 }
 153
 154 /* This function is currently unused but leave in for now.  */
 155
 156 static void
 157 codestream_read (unsigned int *buf, int count)
 158 {
 159   unsigned int *p;
 160   int i;
 161   p = buf;
 162   for (i = 0; i < count; i++)
 163     *p++ = codestream_get ();
 164 }
 165 \f
 166 /* Set up prologue scanning and return the first insn.  */
 167
 168 static unsigned int
 169 setup_prologue_scan (CORE_ADDR pc)
 170 {
 171   unsigned int insn;
 172
 173   codestream_seek (pc);
 174   insn = codestream_get ();
 175
 176   return insn;
 177 }
 178
 179 /*
 180  * Find & return amount a local space allocated, and advance codestream to
 181  * first register push (if any).
 182  * If entry sequence doesn't make sense, return -1, and leave
 183  * codestream pointer random.
 184  */
 185
 186 static long
 187 arc_get_frame_setup (CORE_ADDR pc)
 188 {
 189   unsigned int insn;
 190   /* Size of frame or -1 if unrecognizable prologue.  */
 191   int frame_size = -1;
 192   /* An initial "sub sp,sp,N" may or may not be for a stdarg fn.  */
 193   int maybe_stdarg_decr = -1;
 194
 195   insn = setup_prologue_scan (pc);
 196
 197   /* The authority for what appears here is the home-grown ABI.
 198      The most recent version is 1.2.  */
 199
 200   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 201   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 202       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 203     {
 204       maybe_stdarg_decr = X_D (insn);
 205       insn = codestream_get ();
 206     }
 207
 208   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 209       == BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 210     {
 211       insn = codestream_get ();
 212       /* Frame may not be necessary, even though blink is saved.
 213          At least this is something we recognize.  */
 214       frame_size = 0;
 215     }
 216
 217   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st fp,[sp] */
 218       == BUILD_INSN (2, 0, SP_REGNUM, FP_REGNUM, 0))
 219     {
 220       insn = codestream_get ();
 221       if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 222           != BUILD_INSN (12, FP_REGNUM, SP_REGNUM, SP_REGNUM, 0))
 223         return -1;
 224
 225       /* Check for stack adjustment sub sp,sp,N.  */
 226       insn = codestream_peek ();
 227       if ((insn & BUILD_INSN (-1, -1, -1, 0, 0))
 228           == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, 0, 0))
 229         {
 230           if (LIMM_P (X_C (insn)))
 231             frame_size = codestream_get ();
 232           else if (SHIMM_P (X_C (insn)))
 233             frame_size = X_D (insn);
 234           else
 235             return -1;
 236           if (frame_size < 0)
 237             return -1;
 238
 239           codestream_get ();
 240
 241           /* This sequence is used to get the address of the return
 242              buffer for a function that returns a structure.  */
 243           insn = codestream_peek ();
 244           if ((insn & OPMASK) == 0x60000000)
 245             codestream_get ();
 246         }
 247       /* Frameless fn.  */
 248       else
 249         {
 250           frame_size = 0;
 251         }
 252     }
 253
 254   /* If we found a "sub sp,sp,N" and nothing else, it may or may not be a
 255      stdarg fn.  The stdarg decrement is not treated as part of the frame size,
 256      so we have a dilemma: what do we return?  For now, if we get a
 257      "sub sp,sp,N" and nothing else assume this isn't a stdarg fn.  One way
 258      to fix this completely would be to add a bit to the function descriptor
 259      that says the function is a stdarg function.  */
 260
 261   if (frame_size < 0 && maybe_stdarg_decr > 0)
 262     return maybe_stdarg_decr;
 263   return frame_size;
 264 }
 265
 266 /* Given a pc value, skip it forward past the function prologue by
 267    disassembling instructions that appear to be a prologue.
 268
 269    If FRAMELESS_P is set, we are only testing to see if the function
 270    is frameless.  If it is a frameless function, return PC unchanged.
 271    This allows a quicker answer.  */
 272
 273 CORE_ADDR
 274 arc_skip_prologue (CORE_ADDR pc, int frameless_p)
 275 {
 276   unsigned int insn;
 277   int i, frame_size;
 278
 279   if ((frame_size = arc_get_frame_setup (pc)) < 0)
 280     return (pc);
 281
 282   if (frameless_p)
 283     return frame_size == 0 ? pc : codestream_tell ();
 284
 285   /* Skip over register saves.  */
 286   for (i = 0; i < 8; i++)
 287     {
 288       insn = codestream_peek ();
 289       if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 290           != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 291         break;                  /* not st insn */
 292       if (!ARC_CALL_SAVED_REG (X_C (insn)))
 293         break;
 294       codestream_get ();
 295     }
 296
 297   return codestream_tell ();
 298 }
 299
 300 /* Return the return address for a frame.
 301    This is used to implement FRAME_SAVED_PC.
 302    This is taken from frameless_look_for_prologue.  */
 303
 304 CORE_ADDR
 305 arc_frame_saved_pc (struct frame_info *frame)
 306 {
 307   CORE_ADDR func_start;
 308   unsigned int insn;
 309
 310   func_start = get_pc_function_start (frame->pc) + FUNCTION_START_OFFSET;
 311   if (func_start == 0)
 312     {
 313       /* Best guess.  */
 314       return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 315     }
 316
 317   /* The authority for what appears here is the home-grown ABI.
 318      The most recent version is 1.2.  */
 319
 320   insn = setup_prologue_scan (func_start);
 321
 322   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 323   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 324       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 325     insn = codestream_get ();
 326
 327   /* If the next insn is "st blink,[sp,4]" we can get blink from there.
 328      Otherwise this is a leaf function and we can use blink.  Note that
 329      this still allows for the case where a leaf function saves/clobbers/
 330      restores blink.  */
 331
 332   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 333       != BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 334     return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM));
 335   else
 336     return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 337 }
 338
 339 /*
 340  * Parse the first few instructions of the function to see
 341  * what registers were stored.
 342  *
 343  * The startup sequence can be at the start of the function.
 344  * 'st blink,[sp+4], st fp,[sp], mov fp,sp'
 345  *
 346  * Local space is allocated just below by sub sp,sp,nnn.
 347  * Next, the registers used by this function are stored (as offsets from sp).
 348  */
 349
 350 void
 351 frame_find_saved_regs (struct frame_info *fip, struct frame_saved_regs *fsrp)
 352 {
 353   long locals;
 354   unsigned int insn;
 355   CORE_ADDR dummy_bottom;
 356   CORE_ADDR adr;
 357   int i, regnum, offset;
 358
 359   memset (fsrp, 0, sizeof *fsrp);
 360
 361   /* If frame is the end of a dummy, compute where the beginning would be.  */
 362   dummy_bottom = fip->frame - 4 - REGISTER_BYTES - CALL_DUMMY_LENGTH;
 363
 364   /* Check if the PC is in the stack, in a dummy frame.  */
 365   if (dummy_bottom <= fip->pc && fip->pc <= fip->frame)
 366     {
 367       /* all regs were saved by push_call_dummy () */
 368       adr = fip->frame;
 369       for (i = 0; i < NUM_REGS; i++)
 370         {
 371           adr -= REGISTER_RAW_SIZE (i);
 372           fsrp->regs[i] = adr;
 373         }
 374       return;
 375     }
 376
 377   locals = arc_get_frame_setup (get_pc_function_start (fip->pc));
 378
 379   if (locals >= 0)
 380     {
 381       /* Set `adr' to the value of `sp'.  */
 382       adr = fip->frame - locals;
 383       for (i = 0; i < 8; i++)
 384         {
 385           insn = codestream_get ();
 386           if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 387               != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 388             break;
 389           regnum = X_C (insn);
 390           offset = X_D (insn);
 391           fsrp->regs[regnum] = adr + offset;
 392         }
 393     }
 394
 395   fsrp->regs[PC_REGNUM] = fip->frame + 4;
 396   fsrp->regs[FP_REGNUM] = fip->frame;
 397 }
 398
 399 void
 400 arc_push_dummy_frame (void)
 401 {
 402   CORE_ADDR sp = read_register (SP_REGNUM);
 403   int regnum;
 404   char regbuf[MAX_REGISTER_RAW_SIZE];
 405
 406   read_register_gen (PC_REGNUM, regbuf);
 407   write_memory (sp + 4, regbuf, REGISTER_SIZE);
 408   read_register_gen (FP_REGNUM, regbuf);
 409   write_memory (sp, regbuf, REGISTER_SIZE);
 410   write_register (FP_REGNUM, sp);
 411   for (regnum = 0; regnum < NUM_REGS; regnum++)
 412     {
 413       read_register_gen (regnum, regbuf);
 414       sp = push_bytes (sp, regbuf, REGISTER_RAW_SIZE (regnum));
 415     }
 416   sp += (2 * REGISTER_SIZE);
 417   write_register (SP_REGNUM, sp);
 418 }
 419
 420 void
 421 arc_pop_frame (void)
 422 {
 423   struct frame_info *frame = get_current_frame ();
 424   CORE_ADDR fp;
 425   int regnum;
 426   struct frame_saved_regs fsr;
 427   char regbuf[MAX_REGISTER_RAW_SIZE];
 428
 429   fp = FRAME_FP (frame);
 430   get_frame_saved_regs (frame, &fsr);
 431   for (regnum = 0; regnum < NUM_REGS; regnum++)
 432     {
 433       CORE_ADDR adr;
 434       adr = fsr.regs[regnum];
 435       if (adr)
 436         {
 437           read_memory (adr, regbuf, REGISTER_RAW_SIZE (regnum));
 438           write_register_bytes (REGISTER_BYTE (regnum), regbuf,
 439                                 REGISTER_RAW_SIZE (regnum));
 440         }
 441     }
 442   write_register (FP_REGNUM, read_memory_integer (fp, 4));
 443   write_register (PC_REGNUM, read_memory_integer (fp + 4, 4));
 444   write_register (SP_REGNUM, fp + 8);
 445   flush_cached_frames ();
 446 }
 447 \f
 448 /* Simulate single-step.  */
 449
 450 typedef enum
 451 {
 452   NORMAL4,                      /* a normal 4 byte insn */
 453   NORMAL8,                      /* a normal 8 byte insn */
 454   BRANCH4,                      /* a 4 byte branch insn, including ones without delay slots */
 455   BRANCH8,                      /* an 8 byte branch insn, including ones with delay slots */
 456 }
 457 insn_type;
 458
 459 /* Return the type of INSN and store in TARGET the destination address of a
 460    branch if this is one.  */
 461 /* ??? Need to verify all cases are properly handled.  */
 462
 463 static insn_type
 464 get_insn_type (unsigned long insn, CORE_ADDR pc, CORE_ADDR *target)
 465 {
 466   unsigned long limm;
 467
 468   switch (insn >> 27)
 469     {
 470     case 0:
 471     case 1:
 472     case 2:                     /* load/store insns */
 473       if (LIMM_P (X_A (insn))
 474           || LIMM_P (X_B (insn))
 475           || LIMM_P (X_C (insn)))
 476         return NORMAL8;
 477       return NORMAL4;
 478     case 4:
 479     case 5:
 480     case 6:                     /* branch insns */
 481       *target = pc + 4 + X_L (insn);
 482       /* ??? It isn't clear that this is always the right answer.
 483          The problem occurs when the next insn is an 8 byte insn.  If the
 484          branch is conditional there's no worry as there shouldn't be an 8
 485          byte insn following.  The programmer may be cheating if s/he knows
 486          the branch will never be taken, but we don't deal with that.
 487          Note that the programmer is also allowed to play games by putting
 488          an insn with long immediate data in the delay slot and then duplicate
 489          the long immediate data at the branch target.  Ugh!  */
 490       if (X_N (insn) == 0)
 491         return BRANCH4;
 492       return BRANCH8;
 493     case 7:                     /* jump insns */
 494       if (LIMM_P (X_B (insn)))
 495         {
 496           limm = read_memory_integer (pc + 4, 4);
 497           *target = ARC_PC_TO_REAL_ADDRESS (limm);
 498           return BRANCH8;
 499         }
 500       if (SHIMM_P (X_B (insn)))
 501         *target = ARC_PC_TO_REAL_ADDRESS (X_D (insn));
 502       else
 503         *target = ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn)));
 504       if (X_Q (insn) == 0 && X_N (insn) == 0)
 505         return BRANCH4;
 506       return BRANCH8;
 507     default:                    /* arithmetic insns, etc. */
 508       if (LIMM_P (X_A (insn))
 509           || LIMM_P (X_B (insn))
 510           || LIMM_P (X_C (insn)))
 511         return NORMAL8;
 512       return NORMAL4;
 513     }
 514 }
 515
 516 /* single_step() is called just before we want to resume the inferior, if we
 517    want to single-step it but there is no hardware or kernel single-step
 518    support.  We find all the possible targets of the coming instruction and
 519    breakpoint them.
 520
 521    single_step is also called just after the inferior stops.  If we had
 522    set up a simulated single-step, we undo our damage.  */
 523
 524 void
 525 arc_software_single_step (enum target_signal ignore,    /* sig but we don't need it */
 526                           int insert_breakpoints_p)
 527 {
 528   static CORE_ADDR next_pc, target;
 529   static int brktrg_p;
 530   typedef char binsn_quantum[BREAKPOINT_MAX];
 531   static binsn_quantum break_mem[2];
 532
 533   if (insert_breakpoints_p)
 534     {
 535       insn_type type;
 536       CORE_ADDR pc;
 537       unsigned long insn;
 538
 539       pc = read_register (PC_REGNUM);
 540       insn = read_memory_integer (pc, 4);
 541       type = get_insn_type (insn, pc, &target);
 542
 543       /* Always set a breakpoint for the insn after the branch.  */
 544       next_pc = pc + ((type == NORMAL8 || type == BRANCH8) ? 8 : 4);
 545       target_insert_breakpoint (next_pc, break_mem[0]);
 546
 547       brktrg_p = 0;
 548
 549       if ((type == BRANCH4 || type == BRANCH8)
 550       /* Watch out for branches to the following location.
 551          We just stored a breakpoint there and another call to
 552          target_insert_breakpoint will think the real insn is the
 553          breakpoint we just stored there.  */
 554           && target != next_pc)
 555         {
 556           brktrg_p = 1;
 557           target_insert_breakpoint (target, break_mem[1]);
 558         }
 559
 560     }
 561   else
 562     {
 563       /* Remove breakpoints.  */
 564       target_remove_breakpoint (next_pc, break_mem[0]);
 565
 566       if (brktrg_p)
 567         target_remove_breakpoint (target, break_mem[1]);
 568
 569       /* Fix the pc.  */
 570       stop_pc -= DECR_PC_AFTER_BREAK;
 571       write_pc (stop_pc);
 572     }
 573 }
 574 \f
 575 #ifdef GET_LONGJMP_TARGET
 576 /* Figure out where the longjmp will land.  Slurp the args out of the stack.
 577    We expect the first arg to be a pointer to the jmp_buf structure from which
 578    we extract the pc (JB_PC) that we will land at.  The pc is copied into PC.
 579    This routine returns true on success. */
 580
 581 int
 582 get_longjmp_target (CORE_ADDR *pc)
 583 {
 584   char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
 585   CORE_ADDR sp, jb_addr;
 586
 587   sp = read_register (SP_REGNUM);
 588
 589   if (target_read_memory (sp + SP_ARG0,         /* Offset of first arg on stack */
 590                           buf,
 591                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 592     return 0;
 593
 594   jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 595
 596   if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
 597                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 598     return 0;
 599
 600   *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 601
 602   return 1;
 603 }
 604 #endif /* GET_LONGJMP_TARGET */
 605 \f
 606 /* Disassemble one instruction.  */
 607
 608 static int
 609 arc_print_insn (bfd_vma vma, disassemble_info *info)
 610 {
 611   static int current_mach;
 612   static int current_endian;
 613   static disassembler_ftype current_disasm;
 614
 615   if (current_disasm == NULL
 616       || arc_bfd_mach_type != current_mach
 617       || TARGET_BYTE_ORDER != current_endian)
 618     {
 619       current_mach = arc_bfd_mach_type;
 620       current_endian = TARGET_BYTE_ORDER;
 621       current_disasm = arc_get_disassembler (current_mach,
 622                                              current_endian == BIG_ENDIAN);
 623     }
 624
 625   return (*current_disasm) (vma, info);
 626 }
 627 \f
 628 /* Command to set cpu type.  */
 629
 630 void
 631 arc_set_cpu_type_command (char *args, int from_tty)
 632 {
 633   int i;
 634
 635   if (tmp_arc_cpu_type == NULL || *tmp_arc_cpu_type == '\0')
 636     {
 637       printf_unfiltered ("The known ARC cpu types are as follows:\n");
 638       for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 639         printf_unfiltered ("%s\n", arc_cpu_type_table[i].name);
 640
 641       /* Restore the value.  */
 642       tmp_arc_cpu_type = strsave (arc_cpu_type);
 643
 644       return;
 645     }
 646
 647   if (!arc_set_cpu_type (tmp_arc_cpu_type))
 648     {
 649       error ("Unknown cpu type `%s'.", tmp_arc_cpu_type);
 650       /* Restore its value.  */
 651       tmp_arc_cpu_type = strsave (arc_cpu_type);
 652     }
 653 }
 654
 655 static void
 656 arc_show_cpu_type_command (char *args, int from_tty)
 657 {
 658 }
 659
 660 /* Modify the actual cpu type.
 661    Result is a boolean indicating success.  */
 662
 663 static int
 664 arc_set_cpu_type (char *str)
 665 {
 666   int i, j;
 667
 668   if (str == NULL)
 669     return 0;
 670
 671   for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 672     {
 673       if (strcasecmp (str, arc_cpu_type_table[i].name) == 0)
 674         {
 675           arc_cpu_type = str;
 676           arc_bfd_mach_type = arc_cpu_type_table[i].value;
 677           return 1;
 678         }
 679     }
 680
 681   return 0;
 682 }
 683 \f
 684 void
 685 _initialize_arc_tdep (void)
 686 {
 687   struct cmd_list_element *c;
 688
 689   c = add_set_cmd ("cpu", class_support, var_string_noescape,
 690                    (char *) &tmp_arc_cpu_type,
 691                    "Set the type of ARC cpu in use.\n\
 692 This command has two purposes.  In a multi-cpu system it lets one\n\
 693 change the cpu being debugged.  It also gives one access to\n\
 694 cpu-type-specific registers and recognize cpu-type-specific instructions.\
 695 ",
 696                    &setlist);
 697   c->function.cfunc = arc_set_cpu_type_command;
 698   c = add_show_from_set (c, &showlist);
 699   c->function.cfunc = arc_show_cpu_type_command;
 700
 701   /* We have to use strsave here because the `set' command frees it before
 702      setting a new value.  */
 703   tmp_arc_cpu_type = strsave (DEFAULT_ARC_CPU_TYPE);
 704   arc_set_cpu_type (tmp_arc_cpu_type);
 705
 706   c = add_set_cmd ("displaypipeline", class_support, var_zinteger,
 707                    (char *) &display_pipeline_p,
 708                    "Set pipeline display (simulator only).\n\
 709 When enabled, the state of the pipeline after each cycle is displayed.",
 710                    &setlist);
 711   c = add_show_from_set (c, &showlist);
 712
 713   c = add_set_cmd ("debugpipeline", class_support, var_zinteger,
 714                    (char *) &debug_pipeline_p,
 715                    "Set pipeline debug display (simulator only).\n\
 716 When enabled, debugging information about the pipeline is displayed.",
 717                    &setlist);
 718   c = add_show_from_set (c, &showlist);
 719
 720   c = add_set_cmd ("cputimer", class_support, var_zinteger,
 721                    (char *) &cpu_timer,
 722                    "Set maximum cycle count (simulator only).\n\
 723 Control will return to gdb if the timer expires.\n\
 724 A negative value disables the timer.",
 725                    &setlist);
 726   c = add_show_from_set (c, &showlist);
 727
 728   tm_print_insn = arc_print_insn;
 729 }