gdb/arc-tdep.h

   1 /* Target dependent code for ARC architecture, for GDB.
   2
   3    Copyright 2005-2020 Free Software Foundation, Inc.
   4    Contributed by Synopsys Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef ARC_TDEP_H
  22 #define ARC_TDEP_H
  23
  24 /* Need disassemble_info.  */
  25 #include "dis-asm.h"
  26
  27 /* To simplify GDB code this enum assumes that internal regnums should be same
  28    as architectural register numbers, i.e. PCL regnum is 63.  This allows to
  29    use internal GDB regnums as architectural numbers when dealing with
  30    instruction encodings, for example when analyzing what are the registers
  31    saved in function prologue.  */
  32
  33 enum arc_regnum
  34   {
  35     /* Core registers.  */
  36     ARC_R0_REGNUM = 0,
  37     ARC_FIRST_CORE_REGNUM = ARC_R0_REGNUM,
  38     ARC_R1_REGNUM = 1,
  39     ARC_R4_REGNUM = 4,
  40     ARC_R7_REGNUM = 7,
  41     ARC_R9_REGNUM = 9,
  42     ARC_R13_REGNUM = 13,
  43     ARC_R16_REGNUM = 16,
  44     ARC_R25_REGNUM = 25,
  45     /* Global data pointer.  */
  46     ARC_GP_REGNUM,
  47     /* Frame pointer.  */
  48     ARC_FP_REGNUM,
  49     /* Stack pointer.  */
  50     ARC_SP_REGNUM,
  51     /* Return address from interrupt.  */
  52     ARC_ILINK_REGNUM,
  53     ARC_R30_REGNUM,
  54     /* Return address from function.  */
  55     ARC_BLINK_REGNUM,
  56     /* Zero-delay loop counter.  */
  57     ARC_LP_COUNT_REGNUM = 60,
  58     /* Reserved register number.  There should never be a register with such
  59        number, this name is needed only for a sanity check in
  60       arc_cannot_(fetch|store)_register.  */
  61     ARC_RESERVED_REGNUM,
  62     /* Long-immediate value.  This is not a physical register - if instruction
  63        has register 62 as an operand, then this operand is a literal value
  64        stored in the instruction memory right after the instruction itself.
  65        This value is required in this enumeration as an architectural number
  66        for instruction analysis.  */
  67     ARC_LIMM_REGNUM,
  68     /* Program counter, aligned to 4-bytes, read-only.  */
  69     ARC_PCL_REGNUM,
  70     ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
  71     /* AUX registers.  */
  72     /* Actual program counter.  */
  73     ARC_PC_REGNUM,
  74     ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM,
  75     /* Status register.  */
  76     ARC_STATUS32_REGNUM,
  77     ARC_LAST_REGNUM = ARC_STATUS32_REGNUM,
  78     ARC_LAST_AUX_REGNUM = ARC_STATUS32_REGNUM,
  79
  80     /* Additional ABI constants.  */
  81     ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM,
  82     ARC_LAST_ARG_REGNUM = ARC_R7_REGNUM,
  83     ARC_FIRST_CALLEE_SAVED_REGNUM = ARC_R13_REGNUM,
  84     ARC_LAST_CALLEE_SAVED_REGNUM = ARC_R25_REGNUM,
  85   };
  86
  87 /* Number of bytes in ARC register.  All ARC registers are considered 32-bit.
  88    Those registers, which are actually shorter has zero-on-read for extra bits.
  89    Longer registers are represented as pairs of 32-bit registers.  */
  90 #define ARC_REGISTER_SIZE  4
  91
  92 #define arc_print(fmt, args...) fprintf_unfiltered (gdb_stdlog, fmt, ##args)
  93
  94 extern int arc_debug;
  95
  96 /* Target-dependent information.  */
  97
  98 struct gdbarch_tdep
  99 {
 100   /* Offset to PC value in jump buffer.  If this is negative, longjmp
 101      support will be disabled.  */
 102   int jb_pc;
 103 };
 104
 105 /* Utility functions used by other ARC-specific modules.  */
 106
 107 static inline int
 108 arc_mach_is_arc600 (struct gdbarch *gdbarch)
 109 {
 110   return (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc600
 111           || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc601);
 112 }
 113
 114 static inline int
 115 arc_mach_is_arc700 (struct gdbarch *gdbarch)
 116 {
 117   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc700;
 118 }
 119
 120 static inline int
 121 arc_mach_is_arcv2 (struct gdbarch *gdbarch)
 122 {
 123   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
 124 }
 125
 126 /* ARC EM and ARC HS are unique BFD arches, however they share the same machine
 127    number as "ARCv2".  */
 128
 129 static inline bool
 130 arc_arch_is_hs (const struct bfd_arch_info* arch)
 131 {
 132   return startswith (arch->printable_name, "HS");
 133 }
 134
 135 static inline bool
 136 arc_arch_is_em (const struct bfd_arch_info* arch)
 137 {
 138   return startswith (arch->printable_name, "EM");
 139 }
 140
 141 /* Function to access ARC disassembler.  Underlying opcodes disassembler will
 142    print an instruction into stream specified in the INFO, so if it is
 143    undesired, then this stream should be set to some invisible stream, but it
 144    can't be set to an actual NULL value - that would cause a crash.  */
 145 int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
 146
 147 /* Return properly initialized disassemble_info for ARC disassembler - it will
 148    not print disassembled instructions to stderr.  */
 149
 150 struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch);
 151
 152 /* Get branch/jump target address for the INSN.  Note that this function
 153    returns branch target and doesn't evaluate if this branch is taken or not.
 154    For the indirect jumps value depends in register state, hence can change.
 155    It is an error to call this function for a non-branch instruction.  */
 156
 157 CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
 158
 159 /* Get address of next instruction after INSN, assuming linear execution (no
 160    taken branches).  If instruction has a delay slot, then returned value will
 161    point at the instruction in delay slot.  That is - "address of instruction +
 162    instruction length with LIMM".  */
 163
 164 CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
 165
 166 #endif /* ARC_TDEP_H */