1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
33 #include "target-float.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
47 #include "observable.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
58 #include "common/vec.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
73 #include "common/selftest.h"
78 /* Macros for setting and testing a bit in a minimal symbol that marks
79 it as Thumb function. The MSB of the minimal symbol's "info" field
80 is used for this purpose.
82 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
83 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_TARGET_FLAG_1 (msym) = 1
88 #define MSYMBOL_IS_SPECIAL(msym) \
89 MSYMBOL_TARGET_FLAG_1 (msym)
91 /* Per-objfile data used for mapping symbols. */
92 static const struct objfile_data
*arm_objfile_data_key
;
94 struct arm_mapping_symbol
99 bool operator< (const arm_mapping_symbol
&other
) const
100 { return this->value
< other
.value
; }
103 typedef std::vector
<arm_mapping_symbol
> arm_mapping_symbol_vec
;
105 struct arm_per_objfile
107 explicit arm_per_objfile (size_t num_sections
)
108 : section_maps (new arm_mapping_symbol_vec
[num_sections
])
111 DISABLE_COPY_AND_ASSIGN (arm_per_objfile
);
113 /* Information about mapping symbols ($a, $d, $t) in the objfile.
115 The format is an array of vectors of arm_mapping_symbols, there is one
116 vector for each section of the objfile (the array is index by BFD section
119 For each section, the vector of arm_mapping_symbol is sorted by
120 symbol value (address). */
121 std::unique_ptr
<arm_mapping_symbol_vec
[]> section_maps
;
124 /* The list of available "set arm ..." and "show arm ..." commands. */
125 static struct cmd_list_element
*setarmcmdlist
= NULL
;
126 static struct cmd_list_element
*showarmcmdlist
= NULL
;
128 /* The type of floating-point to use. Keep this in sync with enum
129 arm_float_model, and the help string in _initialize_arm_tdep. */
130 static const char *const fp_model_strings
[] =
140 /* A variable that can be configured by the user. */
141 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
142 static const char *current_fp_model
= "auto";
144 /* The ABI to use. Keep this in sync with arm_abi_kind. */
145 static const char *const arm_abi_strings
[] =
153 /* A variable that can be configured by the user. */
154 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
155 static const char *arm_abi_string
= "auto";
157 /* The execution mode to assume. */
158 static const char *const arm_mode_strings
[] =
166 static const char *arm_fallback_mode_string
= "auto";
167 static const char *arm_force_mode_string
= "auto";
169 /* The standard register names, and all the valid aliases for them. Note
170 that `fp', `sp' and `pc' are not added in this alias list, because they
171 have been added as builtin user registers in
172 std-regs.c:_initialize_frame_reg. */
177 } arm_register_aliases
[] = {
178 /* Basic register numbers. */
195 /* Synonyms (argument and variable registers). */
208 /* Other platform-specific names for r9. */
214 /* Names used by GCC (not listed in the ARM EABI). */
216 /* A special name from the older ATPCS. */
220 static const char *const arm_register_names
[] =
221 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
222 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
223 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
224 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
225 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
226 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
227 "fps", "cpsr" }; /* 24 25 */
229 /* Holds the current set of options to be passed to the disassembler. */
230 static char *arm_disassembler_options
;
232 /* Valid register name styles. */
233 static const char **valid_disassembly_styles
;
235 /* Disassembly style to use. Default to "std" register names. */
236 static const char *disassembly_style
;
238 /* This is used to keep the bfd arch_info in sync with the disassembly
240 static void set_disassembly_style_sfunc (const char *, int,
241 struct cmd_list_element
*);
242 static void show_disassembly_style_sfunc (struct ui_file
*, int,
243 struct cmd_list_element
*,
246 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
247 readable_regcache
*regcache
,
248 int regnum
, gdb_byte
*buf
);
249 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
250 struct regcache
*regcache
,
251 int regnum
, const gdb_byte
*buf
);
254 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
257 /* get_next_pcs operations. */
258 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
259 arm_get_next_pcs_read_memory_unsigned_integer
,
260 arm_get_next_pcs_syscall_next_pc
,
261 arm_get_next_pcs_addr_bits_remove
,
262 arm_get_next_pcs_is_thumb
,
266 struct arm_prologue_cache
268 /* The stack pointer at the time this frame was created; i.e. the
269 caller's stack pointer when this function was called. It is used
270 to identify this frame. */
273 /* The frame base for this frame is just prev_sp - frame size.
274 FRAMESIZE is the distance from the frame pointer to the
275 initial stack pointer. */
279 /* The register used to hold the frame pointer for this frame. */
282 /* Saved register offsets. */
283 struct trad_frame_saved_reg
*saved_regs
;
286 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
287 CORE_ADDR prologue_start
,
288 CORE_ADDR prologue_end
,
289 struct arm_prologue_cache
*cache
);
291 /* Architecture version for displaced stepping. This effects the behaviour of
292 certain instructions, and really should not be hard-wired. */
294 #define DISPLACED_STEPPING_ARCH_VERSION 5
296 /* Set to true if the 32-bit mode is in use. */
300 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
303 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
305 if (gdbarch_tdep (gdbarch
)->is_m
)
311 /* Determine if the processor is currently executing in Thumb mode. */
314 arm_is_thumb (struct regcache
*regcache
)
317 ULONGEST t_bit
= arm_psr_thumb_bit (regcache
->arch ());
319 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
321 return (cpsr
& t_bit
) != 0;
324 /* Determine if FRAME is executing in Thumb mode. */
327 arm_frame_is_thumb (struct frame_info
*frame
)
330 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
332 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
333 directly (from a signal frame or dummy frame) or by interpreting
334 the saved LR (from a prologue or DWARF frame). So consult it and
335 trust the unwinders. */
336 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
338 return (cpsr
& t_bit
) != 0;
341 /* Search for the mapping symbol covering MEMADDR. If one is found,
342 return its type. Otherwise, return 0. If START is non-NULL,
343 set *START to the location of the mapping symbol. */
346 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
348 struct obj_section
*sec
;
350 /* If there are mapping symbols, consult them. */
351 sec
= find_pc_section (memaddr
);
354 arm_per_objfile
*data
355 = (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
356 arm_objfile_data_key
);
359 struct arm_mapping_symbol map_key
360 = { memaddr
- obj_section_addr (sec
), 0 };
361 const arm_mapping_symbol_vec
&map
362 = data
->section_maps
[sec
->the_bfd_section
->index
];
363 arm_mapping_symbol_vec::const_iterator it
364 = std::lower_bound (map
.begin (), map
.end (), map_key
);
366 /* std::lower_bound finds the earliest ordered insertion
367 point. If the symbol at this position starts at this exact
368 address, we use that; otherwise, the preceding
369 mapping symbol covers this address. */
372 if (it
->value
== map_key
.value
)
375 *start
= it
->value
+ obj_section_addr (sec
);
380 if (it
> map
.begin ())
382 arm_mapping_symbol_vec::const_iterator prev_it
386 *start
= prev_it
->value
+ obj_section_addr (sec
);
387 return prev_it
->type
;
395 /* Determine if the program counter specified in MEMADDR is in a Thumb
396 function. This function should be called for addresses unrelated to
397 any executing frame; otherwise, prefer arm_frame_is_thumb. */
400 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
402 struct bound_minimal_symbol sym
;
404 arm_displaced_step_closure
*dsc
405 = ((arm_displaced_step_closure
* )
406 get_displaced_step_closure_by_addr (memaddr
));
408 /* If checking the mode of displaced instruction in copy area, the mode
409 should be determined by instruction on the original address. */
413 fprintf_unfiltered (gdb_stdlog
,
414 "displaced: check mode of %.8lx instead of %.8lx\n",
415 (unsigned long) dsc
->insn_addr
,
416 (unsigned long) memaddr
);
417 memaddr
= dsc
->insn_addr
;
420 /* If bit 0 of the address is set, assume this is a Thumb address. */
421 if (IS_THUMB_ADDR (memaddr
))
424 /* If the user wants to override the symbol table, let him. */
425 if (strcmp (arm_force_mode_string
, "arm") == 0)
427 if (strcmp (arm_force_mode_string
, "thumb") == 0)
430 /* ARM v6-M and v7-M are always in Thumb mode. */
431 if (gdbarch_tdep (gdbarch
)->is_m
)
434 /* If there are mapping symbols, consult them. */
435 type
= arm_find_mapping_symbol (memaddr
, NULL
);
439 /* Thumb functions have a "special" bit set in minimal symbols. */
440 sym
= lookup_minimal_symbol_by_pc (memaddr
);
442 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
444 /* If the user wants to override the fallback mode, let them. */
445 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
447 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
450 /* If we couldn't find any symbol, but we're talking to a running
451 target, then trust the current value of $cpsr. This lets
452 "display/i $pc" always show the correct mode (though if there is
453 a symbol table we will not reach here, so it still may not be
454 displayed in the mode it will be executed). */
455 if (target_has_registers
)
456 return arm_frame_is_thumb (get_current_frame ());
458 /* Otherwise we're out of luck; we assume ARM. */
462 /* Determine if the address specified equals any of these magic return
463 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
466 From ARMv6-M Reference Manual B1.5.8
467 Table B1-5 Exception return behavior
469 EXC_RETURN Return To Return Stack
470 0xFFFFFFF1 Handler mode Main
471 0xFFFFFFF9 Thread mode Main
472 0xFFFFFFFD Thread mode Process
474 From ARMv7-M Reference Manual B1.5.8
475 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
477 EXC_RETURN Return To Return Stack
478 0xFFFFFFF1 Handler mode Main
479 0xFFFFFFF9 Thread mode Main
480 0xFFFFFFFD Thread mode Process
482 Table B1-9 EXC_RETURN definition of exception return behavior, with
485 EXC_RETURN Return To Return Stack Frame Type
486 0xFFFFFFE1 Handler mode Main Extended
487 0xFFFFFFE9 Thread mode Main Extended
488 0xFFFFFFED Thread mode Process Extended
489 0xFFFFFFF1 Handler mode Main Basic
490 0xFFFFFFF9 Thread mode Main Basic
491 0xFFFFFFFD Thread mode Process Basic
493 For more details see "B1.5.8 Exception return behavior"
494 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
497 arm_m_addr_is_magic (CORE_ADDR addr
)
501 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
502 the exception return behavior. */
509 /* Address is magic. */
513 /* Address is not magic. */
518 /* Remove useless bits from addresses in a running program. */
520 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
522 /* On M-profile devices, do not strip the low bit from EXC_RETURN
523 (the magic exception return address). */
524 if (gdbarch_tdep (gdbarch
)->is_m
525 && arm_m_addr_is_magic (val
))
529 return UNMAKE_THUMB_ADDR (val
);
531 return (val
& 0x03fffffc);
534 /* Return 1 if PC is the start of a compiler helper function which
535 can be safely ignored during prologue skipping. IS_THUMB is true
536 if the function is known to be a Thumb function due to the way it
539 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
541 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
542 struct bound_minimal_symbol msym
;
544 msym
= lookup_minimal_symbol_by_pc (pc
);
545 if (msym
.minsym
!= NULL
546 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
547 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
549 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
551 /* The GNU linker's Thumb call stub to foo is named
553 if (strstr (name
, "_from_thumb") != NULL
)
556 /* On soft-float targets, __truncdfsf2 is called to convert promoted
557 arguments to their argument types in non-prototyped
559 if (startswith (name
, "__truncdfsf2"))
561 if (startswith (name
, "__aeabi_d2f"))
564 /* Internal functions related to thread-local storage. */
565 if (startswith (name
, "__tls_get_addr"))
567 if (startswith (name
, "__aeabi_read_tp"))
572 /* If we run against a stripped glibc, we may be unable to identify
573 special functions by name. Check for one important case,
574 __aeabi_read_tp, by comparing the *code* against the default
575 implementation (this is hand-written ARM assembler in glibc). */
578 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
579 == 0xe3e00a0f /* mov r0, #0xffff0fff */
580 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
581 == 0xe240f01f) /* sub pc, r0, #31 */
588 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
589 the first 16-bit of instruction, and INSN2 is the second 16-bit of
591 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
592 ((bits ((insn1), 0, 3) << 12) \
593 | (bits ((insn1), 10, 10) << 11) \
594 | (bits ((insn2), 12, 14) << 8) \
595 | bits ((insn2), 0, 7))
597 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
598 the 32-bit instruction. */
599 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
600 ((bits ((insn), 16, 19) << 12) \
601 | bits ((insn), 0, 11))
603 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
606 thumb_expand_immediate (unsigned int imm
)
608 unsigned int count
= imm
>> 7;
616 return (imm
& 0xff) | ((imm
& 0xff) << 16);
618 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
620 return (imm
& 0xff) | ((imm
& 0xff) << 8)
621 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
624 return (0x80 | (imm
& 0x7f)) << (32 - count
);
627 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
628 epilogue, 0 otherwise. */
631 thumb_instruction_restores_sp (unsigned short insn
)
633 return (insn
== 0x46bd /* mov sp, r7 */
634 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
635 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
638 /* Analyze a Thumb prologue, looking for a recognizable stack frame
639 and frame pointer. Scan until we encounter a store that could
640 clobber the stack frame unexpectedly, or an unknown instruction.
641 Return the last address which is definitely safe to skip for an
642 initial breakpoint. */
645 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
646 CORE_ADDR start
, CORE_ADDR limit
,
647 struct arm_prologue_cache
*cache
)
649 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
650 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
654 CORE_ADDR unrecognized_pc
= 0;
656 for (i
= 0; i
< 16; i
++)
657 regs
[i
] = pv_register (i
, 0);
658 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
660 while (start
< limit
)
664 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
666 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
671 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
674 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
675 whether to save LR (R14). */
676 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
678 /* Calculate offsets of saved R0-R7 and LR. */
679 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
680 if (mask
& (1 << regno
))
682 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
684 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
687 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
689 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
690 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
693 else if (thumb_instruction_restores_sp (insn
))
695 /* Don't scan past the epilogue. */
698 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
699 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
701 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
702 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
703 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
705 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
706 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
707 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
709 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
710 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
711 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
712 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
713 regs
[bits (insn
, 6, 8)]);
714 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
715 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
717 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
718 int rm
= bits (insn
, 3, 6);
719 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
721 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
723 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
724 int src_reg
= (insn
& 0x78) >> 3;
725 regs
[dst_reg
] = regs
[src_reg
];
727 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
729 /* Handle stores to the stack. Normally pushes are used,
730 but with GCC -mtpcs-frame, there may be other stores
731 in the prologue to create the frame. */
732 int regno
= (insn
>> 8) & 0x7;
735 offset
= (insn
& 0xff) << 2;
736 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
738 if (stack
.store_would_trash (addr
))
741 stack
.store (addr
, 4, regs
[regno
]);
743 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
745 int rd
= bits (insn
, 0, 2);
746 int rn
= bits (insn
, 3, 5);
749 offset
= bits (insn
, 6, 10) << 2;
750 addr
= pv_add_constant (regs
[rn
], offset
);
752 if (stack
.store_would_trash (addr
))
755 stack
.store (addr
, 4, regs
[rd
]);
757 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
758 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
759 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
760 /* Ignore stores of argument registers to the stack. */
762 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
763 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
764 /* Ignore block loads from the stack, potentially copying
765 parameters from memory. */
767 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
768 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
769 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
770 /* Similarly ignore single loads from the stack. */
772 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
773 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
774 /* Skip register copies, i.e. saves to another register
775 instead of the stack. */
777 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
778 /* Recognize constant loads; even with small stacks these are necessary
780 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
781 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
783 /* Constant pool loads, for the same reason. */
784 unsigned int constant
;
787 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
788 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
789 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
791 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
793 unsigned short inst2
;
795 inst2
= read_code_unsigned_integer (start
+ 2, 2,
796 byte_order_for_code
);
798 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
800 /* BL, BLX. Allow some special function calls when
801 skipping the prologue; GCC generates these before
802 storing arguments to the stack. */
804 int j1
, j2
, imm1
, imm2
;
806 imm1
= sbits (insn
, 0, 10);
807 imm2
= bits (inst2
, 0, 10);
808 j1
= bit (inst2
, 13);
809 j2
= bit (inst2
, 11);
811 offset
= ((imm1
<< 12) + (imm2
<< 1));
812 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
814 nextpc
= start
+ 4 + offset
;
815 /* For BLX make sure to clear the low bits. */
816 if (bit (inst2
, 12) == 0)
817 nextpc
= nextpc
& 0xfffffffc;
819 if (!skip_prologue_function (gdbarch
, nextpc
,
820 bit (inst2
, 12) != 0))
824 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
826 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
828 pv_t addr
= regs
[bits (insn
, 0, 3)];
831 if (stack
.store_would_trash (addr
))
834 /* Calculate offsets of saved registers. */
835 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
836 if (inst2
& (1 << regno
))
838 addr
= pv_add_constant (addr
, -4);
839 stack
.store (addr
, 4, regs
[regno
]);
843 regs
[bits (insn
, 0, 3)] = addr
;
846 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
848 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
850 int regno1
= bits (inst2
, 12, 15);
851 int regno2
= bits (inst2
, 8, 11);
852 pv_t addr
= regs
[bits (insn
, 0, 3)];
854 offset
= inst2
& 0xff;
856 addr
= pv_add_constant (addr
, offset
);
858 addr
= pv_add_constant (addr
, -offset
);
860 if (stack
.store_would_trash (addr
))
863 stack
.store (addr
, 4, regs
[regno1
]);
864 stack
.store (pv_add_constant (addr
, 4),
868 regs
[bits (insn
, 0, 3)] = addr
;
871 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
872 && (inst2
& 0x0c00) == 0x0c00
873 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
875 int regno
= bits (inst2
, 12, 15);
876 pv_t addr
= regs
[bits (insn
, 0, 3)];
878 offset
= inst2
& 0xff;
880 addr
= pv_add_constant (addr
, offset
);
882 addr
= pv_add_constant (addr
, -offset
);
884 if (stack
.store_would_trash (addr
))
887 stack
.store (addr
, 4, regs
[regno
]);
890 regs
[bits (insn
, 0, 3)] = addr
;
893 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
894 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
896 int regno
= bits (inst2
, 12, 15);
899 offset
= inst2
& 0xfff;
900 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
902 if (stack
.store_would_trash (addr
))
905 stack
.store (addr
, 4, regs
[regno
]);
908 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
909 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
910 /* Ignore stores of argument registers to the stack. */
913 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
914 && (inst2
& 0x0d00) == 0x0c00
915 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
916 /* Ignore stores of argument registers to the stack. */
919 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
921 && (inst2
& 0x8000) == 0x0000
922 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
923 /* Ignore block loads from the stack, potentially copying
924 parameters from memory. */
927 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
929 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
930 /* Similarly ignore dual loads from the stack. */
933 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
934 && (inst2
& 0x0d00) == 0x0c00
935 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
936 /* Similarly ignore single loads from the stack. */
939 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
940 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
941 /* Similarly ignore single loads from the stack. */
944 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
945 && (inst2
& 0x8000) == 0x0000)
947 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
948 | (bits (inst2
, 12, 14) << 8)
949 | bits (inst2
, 0, 7));
951 regs
[bits (inst2
, 8, 11)]
952 = pv_add_constant (regs
[bits (insn
, 0, 3)],
953 thumb_expand_immediate (imm
));
956 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
957 && (inst2
& 0x8000) == 0x0000)
959 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
960 | (bits (inst2
, 12, 14) << 8)
961 | bits (inst2
, 0, 7));
963 regs
[bits (inst2
, 8, 11)]
964 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
967 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
968 && (inst2
& 0x8000) == 0x0000)
970 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
971 | (bits (inst2
, 12, 14) << 8)
972 | bits (inst2
, 0, 7));
974 regs
[bits (inst2
, 8, 11)]
975 = pv_add_constant (regs
[bits (insn
, 0, 3)],
976 - (CORE_ADDR
) thumb_expand_immediate (imm
));
979 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
980 && (inst2
& 0x8000) == 0x0000)
982 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
983 | (bits (inst2
, 12, 14) << 8)
984 | bits (inst2
, 0, 7));
986 regs
[bits (inst2
, 8, 11)]
987 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
990 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
992 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
993 | (bits (inst2
, 12, 14) << 8)
994 | bits (inst2
, 0, 7));
996 regs
[bits (inst2
, 8, 11)]
997 = pv_constant (thumb_expand_immediate (imm
));
1000 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1003 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1005 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1008 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1009 && (inst2
& 0xf0f0) == 0)
1011 int dst_reg
= (inst2
& 0x0f00) >> 8;
1012 int src_reg
= inst2
& 0xf;
1013 regs
[dst_reg
] = regs
[src_reg
];
1016 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1018 /* Constant pool loads. */
1019 unsigned int constant
;
1022 offset
= bits (inst2
, 0, 11);
1024 loc
= start
+ 4 + offset
;
1026 loc
= start
+ 4 - offset
;
1028 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1029 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1032 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1034 /* Constant pool loads. */
1035 unsigned int constant
;
1038 offset
= bits (inst2
, 0, 7) << 2;
1040 loc
= start
+ 4 + offset
;
1042 loc
= start
+ 4 - offset
;
1044 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1045 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1047 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1048 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1051 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1053 /* Don't scan past anything that might change control flow. */
1058 /* The optimizer might shove anything into the prologue,
1059 so we just skip what we don't recognize. */
1060 unrecognized_pc
= start
;
1065 else if (thumb_instruction_changes_pc (insn
))
1067 /* Don't scan past anything that might change control flow. */
1072 /* The optimizer might shove anything into the prologue,
1073 so we just skip what we don't recognize. */
1074 unrecognized_pc
= start
;
1081 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1082 paddress (gdbarch
, start
));
1084 if (unrecognized_pc
== 0)
1085 unrecognized_pc
= start
;
1088 return unrecognized_pc
;
1090 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1092 /* Frame pointer is fp. Frame size is constant. */
1093 cache
->framereg
= ARM_FP_REGNUM
;
1094 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1096 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1098 /* Frame pointer is r7. Frame size is constant. */
1099 cache
->framereg
= THUMB_FP_REGNUM
;
1100 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1104 /* Try the stack pointer... this is a bit desperate. */
1105 cache
->framereg
= ARM_SP_REGNUM
;
1106 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1109 for (i
= 0; i
< 16; i
++)
1110 if (stack
.find_reg (gdbarch
, i
, &offset
))
1111 cache
->saved_regs
[i
].addr
= offset
;
1113 return unrecognized_pc
;
1117 /* Try to analyze the instructions starting from PC, which load symbol
1118 __stack_chk_guard. Return the address of instruction after loading this
1119 symbol, set the dest register number to *BASEREG, and set the size of
1120 instructions for loading symbol in OFFSET. Return 0 if instructions are
1124 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1125 unsigned int *destreg
, int *offset
)
1127 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1128 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1129 unsigned int low
, high
, address
;
1134 unsigned short insn1
1135 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1137 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1139 *destreg
= bits (insn1
, 8, 10);
1141 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1142 address
= read_memory_unsigned_integer (address
, 4,
1143 byte_order_for_code
);
1145 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1147 unsigned short insn2
1148 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1150 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1153 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1155 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1157 /* movt Rd, #const */
1158 if ((insn1
& 0xfbc0) == 0xf2c0)
1160 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1161 *destreg
= bits (insn2
, 8, 11);
1163 address
= (high
<< 16 | low
);
1170 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1172 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1174 address
= bits (insn
, 0, 11) + pc
+ 8;
1175 address
= read_memory_unsigned_integer (address
, 4,
1176 byte_order_for_code
);
1178 *destreg
= bits (insn
, 12, 15);
1181 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1183 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1186 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1188 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1190 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1191 *destreg
= bits (insn
, 12, 15);
1193 address
= (high
<< 16 | low
);
1201 /* Try to skip a sequence of instructions used for stack protector. If PC
1202 points to the first instruction of this sequence, return the address of
1203 first instruction after this sequence, otherwise, return original PC.
1205 On arm, this sequence of instructions is composed of mainly three steps,
1206 Step 1: load symbol __stack_chk_guard,
1207 Step 2: load from address of __stack_chk_guard,
1208 Step 3: store it to somewhere else.
1210 Usually, instructions on step 2 and step 3 are the same on various ARM
1211 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1212 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1213 instructions in step 1 vary from different ARM architectures. On ARMv7,
1216 movw Rn, #:lower16:__stack_chk_guard
1217 movt Rn, #:upper16:__stack_chk_guard
1224 .word __stack_chk_guard
1226 Since ldr/str is a very popular instruction, we can't use them as
1227 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1228 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1229 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1232 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1234 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1235 unsigned int basereg
;
1236 struct bound_minimal_symbol stack_chk_guard
;
1238 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1241 /* Try to parse the instructions in Step 1. */
1242 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1247 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1248 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1249 Otherwise, this sequence cannot be for stack protector. */
1250 if (stack_chk_guard
.minsym
== NULL
1251 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1256 unsigned int destreg
;
1258 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1260 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1261 if ((insn
& 0xf800) != 0x6800)
1263 if (bits (insn
, 3, 5) != basereg
)
1265 destreg
= bits (insn
, 0, 2);
1267 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1268 byte_order_for_code
);
1269 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1270 if ((insn
& 0xf800) != 0x6000)
1272 if (destreg
!= bits (insn
, 0, 2))
1277 unsigned int destreg
;
1279 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1281 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1282 if ((insn
& 0x0e500000) != 0x04100000)
1284 if (bits (insn
, 16, 19) != basereg
)
1286 destreg
= bits (insn
, 12, 15);
1287 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1288 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1289 4, byte_order_for_code
);
1290 if ((insn
& 0x0e500000) != 0x04000000)
1292 if (bits (insn
, 12, 15) != destreg
)
1295 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1298 return pc
+ offset
+ 4;
1300 return pc
+ offset
+ 8;
1303 /* Advance the PC across any function entry prologue instructions to
1304 reach some "real" code.
1306 The APCS (ARM Procedure Call Standard) defines the following
1310 [stmfd sp!, {a1,a2,a3,a4}]
1311 stmfd sp!, {...,fp,ip,lr,pc}
1312 [stfe f7, [sp, #-12]!]
1313 [stfe f6, [sp, #-12]!]
1314 [stfe f5, [sp, #-12]!]
1315 [stfe f4, [sp, #-12]!]
1316 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1319 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1321 CORE_ADDR func_addr
, limit_pc
;
1323 /* See if we can determine the end of the prologue via the symbol table.
1324 If so, then return either PC, or the PC after the prologue, whichever
1326 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1328 CORE_ADDR post_prologue_pc
1329 = skip_prologue_using_sal (gdbarch
, func_addr
);
1330 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1332 if (post_prologue_pc
)
1334 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1337 /* GCC always emits a line note before the prologue and another
1338 one after, even if the two are at the same address or on the
1339 same line. Take advantage of this so that we do not need to
1340 know every instruction that might appear in the prologue. We
1341 will have producer information for most binaries; if it is
1342 missing (e.g. for -gstabs), assuming the GNU tools. */
1343 if (post_prologue_pc
1345 || COMPUNIT_PRODUCER (cust
) == NULL
1346 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1347 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1348 return post_prologue_pc
;
1350 if (post_prologue_pc
!= 0)
1352 CORE_ADDR analyzed_limit
;
1354 /* For non-GCC compilers, make sure the entire line is an
1355 acceptable prologue; GDB will round this function's
1356 return value up to the end of the following line so we
1357 can not skip just part of a line (and we do not want to).
1359 RealView does not treat the prologue specially, but does
1360 associate prologue code with the opening brace; so this
1361 lets us skip the first line if we think it is the opening
1363 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1364 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1365 post_prologue_pc
, NULL
);
1367 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1368 post_prologue_pc
, NULL
);
1370 if (analyzed_limit
!= post_prologue_pc
)
1373 return post_prologue_pc
;
1377 /* Can't determine prologue from the symbol table, need to examine
1380 /* Find an upper limit on the function prologue using the debug
1381 information. If the debug information could not be used to provide
1382 that bound, then use an arbitrary large number as the upper bound. */
1383 /* Like arm_scan_prologue, stop no later than pc + 64. */
1384 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1386 limit_pc
= pc
+ 64; /* Magic. */
1389 /* Check if this is Thumb code. */
1390 if (arm_pc_is_thumb (gdbarch
, pc
))
1391 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1393 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1397 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1398 This function decodes a Thumb function prologue to determine:
1399 1) the size of the stack frame
1400 2) which registers are saved on it
1401 3) the offsets of saved regs
1402 4) the offset from the stack pointer to the frame pointer
1404 A typical Thumb function prologue would create this stack frame
1405 (offsets relative to FP)
1406 old SP -> 24 stack parameters
1409 R7 -> 0 local variables (16 bytes)
1410 SP -> -12 additional stack space (12 bytes)
1411 The frame size would thus be 36 bytes, and the frame offset would be
1412 12 bytes. The frame register is R7.
1414 The comments for thumb_skip_prolog() describe the algorithm we use
1415 to detect the end of the prolog. */
1419 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1420 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1422 CORE_ADDR prologue_start
;
1423 CORE_ADDR prologue_end
;
1425 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1428 /* See comment in arm_scan_prologue for an explanation of
1430 if (prologue_end
> prologue_start
+ 64)
1432 prologue_end
= prologue_start
+ 64;
1436 /* We're in the boondocks: we have no idea where the start of the
1440 prologue_end
= std::min (prologue_end
, prev_pc
);
1442 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1445 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1449 arm_instruction_restores_sp (unsigned int insn
)
1451 if (bits (insn
, 28, 31) != INST_NV
)
1453 if ((insn
& 0x0df0f000) == 0x0080d000
1454 /* ADD SP (register or immediate). */
1455 || (insn
& 0x0df0f000) == 0x0040d000
1456 /* SUB SP (register or immediate). */
1457 || (insn
& 0x0ffffff0) == 0x01a0d000
1459 || (insn
& 0x0fff0000) == 0x08bd0000
1461 || (insn
& 0x0fff0000) == 0x049d0000)
1462 /* POP of a single register. */
1469 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1470 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1471 fill it in. Return the first address not recognized as a prologue
1474 We recognize all the instructions typically found in ARM prologues,
1475 plus harmless instructions which can be skipped (either for analysis
1476 purposes, or a more restrictive set that can be skipped when finding
1477 the end of the prologue). */
1480 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1481 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1482 struct arm_prologue_cache
*cache
)
1484 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1486 CORE_ADDR offset
, current_pc
;
1487 pv_t regs
[ARM_FPS_REGNUM
];
1488 CORE_ADDR unrecognized_pc
= 0;
1490 /* Search the prologue looking for instructions that set up the
1491 frame pointer, adjust the stack pointer, and save registers.
1493 Be careful, however, and if it doesn't look like a prologue,
1494 don't try to scan it. If, for instance, a frameless function
1495 begins with stmfd sp!, then we will tell ourselves there is
1496 a frame, which will confuse stack traceback, as well as "finish"
1497 and other operations that rely on a knowledge of the stack
1500 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1501 regs
[regno
] = pv_register (regno
, 0);
1502 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1504 for (current_pc
= prologue_start
;
1505 current_pc
< prologue_end
;
1509 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1511 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1513 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1516 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1517 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1519 unsigned imm
= insn
& 0xff; /* immediate value */
1520 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1521 int rd
= bits (insn
, 12, 15);
1522 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1523 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1526 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1527 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1529 unsigned imm
= insn
& 0xff; /* immediate value */
1530 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1531 int rd
= bits (insn
, 12, 15);
1532 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1533 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1536 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1539 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1541 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1542 stack
.store (regs
[ARM_SP_REGNUM
], 4,
1543 regs
[bits (insn
, 12, 15)]);
1546 else if ((insn
& 0xffff0000) == 0xe92d0000)
1547 /* stmfd sp!, {..., fp, ip, lr, pc}
1549 stmfd sp!, {a1, a2, a3, a4} */
1551 int mask
= insn
& 0xffff;
1553 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1556 /* Calculate offsets of saved registers. */
1557 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1558 if (mask
& (1 << regno
))
1561 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1562 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1565 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1566 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1567 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1569 /* No need to add this to saved_regs -- it's just an arg reg. */
1572 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1573 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1574 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1576 /* No need to add this to saved_regs -- it's just an arg reg. */
1579 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1581 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1583 /* No need to add this to saved_regs -- it's just arg regs. */
1586 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1588 unsigned imm
= insn
& 0xff; /* immediate value */
1589 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1590 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1591 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1593 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1595 unsigned imm
= insn
& 0xff; /* immediate value */
1596 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1597 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1598 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1600 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1602 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1604 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1607 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1608 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1609 stack
.store (regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1611 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1613 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1615 int n_saved_fp_regs
;
1616 unsigned int fp_start_reg
, fp_bound_reg
;
1618 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1621 if ((insn
& 0x800) == 0x800) /* N0 is set */
1623 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1624 n_saved_fp_regs
= 3;
1626 n_saved_fp_regs
= 1;
1630 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1631 n_saved_fp_regs
= 2;
1633 n_saved_fp_regs
= 4;
1636 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1637 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1638 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1640 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1641 stack
.store (regs
[ARM_SP_REGNUM
], 12,
1642 regs
[fp_start_reg
++]);
1645 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1647 /* Allow some special function calls when skipping the
1648 prologue; GCC generates these before storing arguments to
1650 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1652 if (skip_prologue_function (gdbarch
, dest
, 0))
1657 else if ((insn
& 0xf0000000) != 0xe0000000)
1658 break; /* Condition not true, exit early. */
1659 else if (arm_instruction_changes_pc (insn
))
1660 /* Don't scan past anything that might change control flow. */
1662 else if (arm_instruction_restores_sp (insn
))
1664 /* Don't scan past the epilogue. */
1667 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1668 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1669 /* Ignore block loads from the stack, potentially copying
1670 parameters from memory. */
1672 else if ((insn
& 0xfc500000) == 0xe4100000
1673 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1674 /* Similarly ignore single loads from the stack. */
1676 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1677 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1678 register instead of the stack. */
1682 /* The optimizer might shove anything into the prologue, if
1683 we build up cache (cache != NULL) from scanning prologue,
1684 we just skip what we don't recognize and scan further to
1685 make cache as complete as possible. However, if we skip
1686 prologue, we'll stop immediately on unrecognized
1688 unrecognized_pc
= current_pc
;
1696 if (unrecognized_pc
== 0)
1697 unrecognized_pc
= current_pc
;
1701 int framereg
, framesize
;
1703 /* The frame size is just the distance from the frame register
1704 to the original stack pointer. */
1705 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1707 /* Frame pointer is fp. */
1708 framereg
= ARM_FP_REGNUM
;
1709 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1713 /* Try the stack pointer... this is a bit desperate. */
1714 framereg
= ARM_SP_REGNUM
;
1715 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1718 cache
->framereg
= framereg
;
1719 cache
->framesize
= framesize
;
1721 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1722 if (stack
.find_reg (gdbarch
, regno
, &offset
))
1723 cache
->saved_regs
[regno
].addr
= offset
;
1727 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1728 paddress (gdbarch
, unrecognized_pc
));
1730 return unrecognized_pc
;
1734 arm_scan_prologue (struct frame_info
*this_frame
,
1735 struct arm_prologue_cache
*cache
)
1737 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1738 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1739 CORE_ADDR prologue_start
, prologue_end
;
1740 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1741 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1743 /* Assume there is no frame until proven otherwise. */
1744 cache
->framereg
= ARM_SP_REGNUM
;
1745 cache
->framesize
= 0;
1747 /* Check for Thumb prologue. */
1748 if (arm_frame_is_thumb (this_frame
))
1750 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1754 /* Find the function prologue. If we can't find the function in
1755 the symbol table, peek in the stack frame to find the PC. */
1756 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1759 /* One way to find the end of the prologue (which works well
1760 for unoptimized code) is to do the following:
1762 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1765 prologue_end = prev_pc;
1766 else if (sal.end < prologue_end)
1767 prologue_end = sal.end;
1769 This mechanism is very accurate so long as the optimizer
1770 doesn't move any instructions from the function body into the
1771 prologue. If this happens, sal.end will be the last
1772 instruction in the first hunk of prologue code just before
1773 the first instruction that the scheduler has moved from
1774 the body to the prologue.
1776 In order to make sure that we scan all of the prologue
1777 instructions, we use a slightly less accurate mechanism which
1778 may scan more than necessary. To help compensate for this
1779 lack of accuracy, the prologue scanning loop below contains
1780 several clauses which'll cause the loop to terminate early if
1781 an implausible prologue instruction is encountered.
1787 is a suitable endpoint since it accounts for the largest
1788 possible prologue plus up to five instructions inserted by
1791 if (prologue_end
> prologue_start
+ 64)
1793 prologue_end
= prologue_start
+ 64; /* See above. */
1798 /* We have no symbol information. Our only option is to assume this
1799 function has a standard stack frame and the normal frame register.
1800 Then, we can find the value of our frame pointer on entrance to
1801 the callee (or at the present moment if this is the innermost frame).
1802 The value stored there should be the address of the stmfd + 8. */
1803 CORE_ADDR frame_loc
;
1804 ULONGEST return_value
;
1806 /* AAPCS does not use a frame register, so we can abort here. */
1807 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_AAPCS
)
1810 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1811 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1816 prologue_start
= gdbarch_addr_bits_remove
1817 (gdbarch
, return_value
) - 8;
1818 prologue_end
= prologue_start
+ 64; /* See above. */
1822 if (prev_pc
< prologue_end
)
1823 prologue_end
= prev_pc
;
1825 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1828 static struct arm_prologue_cache
*
1829 arm_make_prologue_cache (struct frame_info
*this_frame
)
1832 struct arm_prologue_cache
*cache
;
1833 CORE_ADDR unwound_fp
;
1835 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1836 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1838 arm_scan_prologue (this_frame
, cache
);
1840 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1841 if (unwound_fp
== 0)
1844 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1846 /* Calculate actual addresses of saved registers using offsets
1847 determined by arm_scan_prologue. */
1848 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1849 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1850 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1855 /* Implementation of the stop_reason hook for arm_prologue frames. */
1857 static enum unwind_stop_reason
1858 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1861 struct arm_prologue_cache
*cache
;
1864 if (*this_cache
== NULL
)
1865 *this_cache
= arm_make_prologue_cache (this_frame
);
1866 cache
= (struct arm_prologue_cache
*) *this_cache
;
1868 /* This is meant to halt the backtrace at "_start". */
1869 pc
= get_frame_pc (this_frame
);
1870 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1871 return UNWIND_OUTERMOST
;
1873 /* If we've hit a wall, stop. */
1874 if (cache
->prev_sp
== 0)
1875 return UNWIND_OUTERMOST
;
1877 return UNWIND_NO_REASON
;
1880 /* Our frame ID for a normal frame is the current function's starting PC
1881 and the caller's SP when we were called. */
1884 arm_prologue_this_id (struct frame_info
*this_frame
,
1886 struct frame_id
*this_id
)
1888 struct arm_prologue_cache
*cache
;
1892 if (*this_cache
== NULL
)
1893 *this_cache
= arm_make_prologue_cache (this_frame
);
1894 cache
= (struct arm_prologue_cache
*) *this_cache
;
1896 /* Use function start address as part of the frame ID. If we cannot
1897 identify the start address (due to missing symbol information),
1898 fall back to just using the current PC. */
1899 pc
= get_frame_pc (this_frame
);
1900 func
= get_frame_func (this_frame
);
1904 id
= frame_id_build (cache
->prev_sp
, func
);
1908 static struct value
*
1909 arm_prologue_prev_register (struct frame_info
*this_frame
,
1913 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1914 struct arm_prologue_cache
*cache
;
1916 if (*this_cache
== NULL
)
1917 *this_cache
= arm_make_prologue_cache (this_frame
);
1918 cache
= (struct arm_prologue_cache
*) *this_cache
;
1920 /* If we are asked to unwind the PC, then we need to return the LR
1921 instead. The prologue may save PC, but it will point into this
1922 frame's prologue, not the next frame's resume location. Also
1923 strip the saved T bit. A valid LR may have the low bit set, but
1924 a valid PC never does. */
1925 if (prev_regnum
== ARM_PC_REGNUM
)
1929 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1930 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1931 arm_addr_bits_remove (gdbarch
, lr
));
1934 /* SP is generally not saved to the stack, but this frame is
1935 identified by the next frame's stack pointer at the time of the call.
1936 The value was already reconstructed into PREV_SP. */
1937 if (prev_regnum
== ARM_SP_REGNUM
)
1938 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1940 /* The CPSR may have been changed by the call instruction and by the
1941 called function. The only bit we can reconstruct is the T bit,
1942 by checking the low bit of LR as of the call. This is a reliable
1943 indicator of Thumb-ness except for some ARM v4T pre-interworking
1944 Thumb code, which could get away with a clear low bit as long as
1945 the called function did not use bx. Guess that all other
1946 bits are unchanged; the condition flags are presumably lost,
1947 but the processor status is likely valid. */
1948 if (prev_regnum
== ARM_PS_REGNUM
)
1951 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1953 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1954 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1955 if (IS_THUMB_ADDR (lr
))
1959 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1962 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1966 struct frame_unwind arm_prologue_unwind
= {
1968 arm_prologue_unwind_stop_reason
,
1969 arm_prologue_this_id
,
1970 arm_prologue_prev_register
,
1972 default_frame_sniffer
1975 /* Maintain a list of ARM exception table entries per objfile, similar to the
1976 list of mapping symbols. We only cache entries for standard ARM-defined
1977 personality routines; the cache will contain only the frame unwinding
1978 instructions associated with the entry (not the descriptors). */
1980 static const struct objfile_data
*arm_exidx_data_key
;
1982 struct arm_exidx_entry
1987 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1988 DEF_VEC_O(arm_exidx_entry_s
);
1990 struct arm_exidx_data
1992 VEC(arm_exidx_entry_s
) **section_maps
;
1996 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1998 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2001 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2002 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2006 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2007 const struct arm_exidx_entry
*rhs
)
2009 return lhs
->addr
< rhs
->addr
;
2012 static struct obj_section
*
2013 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2015 struct obj_section
*osect
;
2017 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2018 if (bfd_get_section_flags (objfile
->obfd
,
2019 osect
->the_bfd_section
) & SEC_ALLOC
)
2021 bfd_vma start
, size
;
2022 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2023 size
= bfd_get_section_size (osect
->the_bfd_section
);
2025 if (start
<= vma
&& vma
< start
+ size
)
2032 /* Parse contents of exception table and exception index sections
2033 of OBJFILE, and fill in the exception table entry cache.
2035 For each entry that refers to a standard ARM-defined personality
2036 routine, extract the frame unwinding instructions (from either
2037 the index or the table section). The unwinding instructions
2039 - extracting them from the rest of the table data
2040 - converting to host endianness
2041 - appending the implicit 0xb0 ("Finish") code
2043 The extracted and normalized instructions are stored for later
2044 retrieval by the arm_find_exidx_entry routine. */
2047 arm_exidx_new_objfile (struct objfile
*objfile
)
2049 struct arm_exidx_data
*data
;
2050 asection
*exidx
, *extab
;
2051 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2054 /* If we've already touched this file, do nothing. */
2055 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2058 /* Read contents of exception table and index. */
2059 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2060 gdb::byte_vector exidx_data
;
2063 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2064 exidx_data
.resize (bfd_get_section_size (exidx
));
2066 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2067 exidx_data
.data (), 0,
2068 exidx_data
.size ()))
2072 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2073 gdb::byte_vector extab_data
;
2076 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2077 extab_data
.resize (bfd_get_section_size (extab
));
2079 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2080 extab_data
.data (), 0,
2081 extab_data
.size ()))
2085 /* Allocate exception table data structure. */
2086 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2087 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2088 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2089 objfile
->obfd
->section_count
,
2090 VEC(arm_exidx_entry_s
) *);
2092 /* Fill in exception table. */
2093 for (i
= 0; i
< exidx_data
.size () / 8; i
++)
2095 struct arm_exidx_entry new_exidx_entry
;
2096 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
.data () + i
* 8);
2097 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
,
2098 exidx_data
.data () + i
* 8 + 4);
2099 bfd_vma addr
= 0, word
= 0;
2100 int n_bytes
= 0, n_words
= 0;
2101 struct obj_section
*sec
;
2102 gdb_byte
*entry
= NULL
;
2104 /* Extract address of start of function. */
2105 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2106 idx
+= exidx_vma
+ i
* 8;
2108 /* Find section containing function and compute section offset. */
2109 sec
= arm_obj_section_from_vma (objfile
, idx
);
2112 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2114 /* Determine address of exception table entry. */
2117 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2119 else if ((val
& 0xff000000) == 0x80000000)
2121 /* Exception table entry embedded in .ARM.exidx
2122 -- must be short form. */
2126 else if (!(val
& 0x80000000))
2128 /* Exception table entry in .ARM.extab. */
2129 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2130 addr
+= exidx_vma
+ i
* 8 + 4;
2132 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_data
.size ())
2134 word
= bfd_h_get_32 (objfile
->obfd
,
2135 extab_data
.data () + addr
- extab_vma
);
2138 if ((word
& 0xff000000) == 0x80000000)
2143 else if ((word
& 0xff000000) == 0x81000000
2144 || (word
& 0xff000000) == 0x82000000)
2148 n_words
= ((word
>> 16) & 0xff);
2150 else if (!(word
& 0x80000000))
2153 struct obj_section
*pers_sec
;
2154 int gnu_personality
= 0;
2156 /* Custom personality routine. */
2157 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2158 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2160 /* Check whether we've got one of the variants of the
2161 GNU personality routines. */
2162 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2165 static const char *personality
[] =
2167 "__gcc_personality_v0",
2168 "__gxx_personality_v0",
2169 "__gcj_personality_v0",
2170 "__gnu_objc_personality_v0",
2174 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2177 for (k
= 0; personality
[k
]; k
++)
2178 if (lookup_minimal_symbol_by_pc_name
2179 (pc
, personality
[k
], objfile
))
2181 gnu_personality
= 1;
2186 /* If so, the next word contains a word count in the high
2187 byte, followed by the same unwind instructions as the
2188 pre-defined forms. */
2190 && addr
+ 4 <= extab_vma
+ extab_data
.size ())
2192 word
= bfd_h_get_32 (objfile
->obfd
,
2194 + addr
- extab_vma
));
2197 n_words
= ((word
>> 24) & 0xff);
2203 /* Sanity check address. */
2205 if (addr
< extab_vma
2206 || addr
+ 4 * n_words
> extab_vma
+ extab_data
.size ())
2207 n_words
= n_bytes
= 0;
2209 /* The unwind instructions reside in WORD (only the N_BYTES least
2210 significant bytes are valid), followed by N_WORDS words in the
2211 extab section starting at ADDR. */
2212 if (n_bytes
|| n_words
)
2215 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2216 n_bytes
+ n_words
* 4 + 1);
2219 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2223 word
= bfd_h_get_32 (objfile
->obfd
,
2224 extab_data
.data () + addr
- extab_vma
);
2227 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2228 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2229 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2230 *p
++ = (gdb_byte
) (word
& 0xff);
2233 /* Implied "Finish" to terminate the list. */
2237 /* Push entry onto vector. They are guaranteed to always
2238 appear in order of increasing addresses. */
2239 new_exidx_entry
.addr
= idx
;
2240 new_exidx_entry
.entry
= entry
;
2241 VEC_safe_push (arm_exidx_entry_s
,
2242 data
->section_maps
[sec
->the_bfd_section
->index
],
2247 /* Search for the exception table entry covering MEMADDR. If one is found,
2248 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2249 set *START to the start of the region covered by this entry. */
2252 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2254 struct obj_section
*sec
;
2256 sec
= find_pc_section (memaddr
);
2259 struct arm_exidx_data
*data
;
2260 VEC(arm_exidx_entry_s
) *map
;
2261 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2264 data
= ((struct arm_exidx_data
*)
2265 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2268 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2269 if (!VEC_empty (arm_exidx_entry_s
, map
))
2271 struct arm_exidx_entry
*map_sym
;
2273 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2274 arm_compare_exidx_entries
);
2276 /* VEC_lower_bound finds the earliest ordered insertion
2277 point. If the following symbol starts at this exact
2278 address, we use that; otherwise, the preceding
2279 exception table entry covers this address. */
2280 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2282 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2283 if (map_sym
->addr
== map_key
.addr
)
2286 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2287 return map_sym
->entry
;
2293 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2295 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2296 return map_sym
->entry
;
2305 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2306 instruction list from the ARM exception table entry ENTRY, allocate and
2307 return a prologue cache structure describing how to unwind this frame.
2309 Return NULL if the unwinding instruction list contains a "spare",
2310 "reserved" or "refuse to unwind" instruction as defined in section
2311 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2312 for the ARM Architecture" document. */
2314 static struct arm_prologue_cache
*
2315 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2320 struct arm_prologue_cache
*cache
;
2321 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2322 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2328 /* Whenever we reload SP, we actually have to retrieve its
2329 actual value in the current frame. */
2332 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2334 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2335 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2339 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2340 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2346 /* Decode next unwind instruction. */
2349 if ((insn
& 0xc0) == 0)
2351 int offset
= insn
& 0x3f;
2352 vsp
+= (offset
<< 2) + 4;
2354 else if ((insn
& 0xc0) == 0x40)
2356 int offset
= insn
& 0x3f;
2357 vsp
-= (offset
<< 2) + 4;
2359 else if ((insn
& 0xf0) == 0x80)
2361 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2364 /* The special case of an all-zero mask identifies
2365 "Refuse to unwind". We return NULL to fall back
2366 to the prologue analyzer. */
2370 /* Pop registers r4..r15 under mask. */
2371 for (i
= 0; i
< 12; i
++)
2372 if (mask
& (1 << i
))
2374 cache
->saved_regs
[4 + i
].addr
= vsp
;
2378 /* Special-case popping SP -- we need to reload vsp. */
2379 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2382 else if ((insn
& 0xf0) == 0x90)
2384 int reg
= insn
& 0xf;
2386 /* Reserved cases. */
2387 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2390 /* Set SP from another register and mark VSP for reload. */
2391 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2394 else if ((insn
& 0xf0) == 0xa0)
2396 int count
= insn
& 0x7;
2397 int pop_lr
= (insn
& 0x8) != 0;
2400 /* Pop r4..r[4+count]. */
2401 for (i
= 0; i
<= count
; i
++)
2403 cache
->saved_regs
[4 + i
].addr
= vsp
;
2407 /* If indicated by flag, pop LR as well. */
2410 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2414 else if (insn
== 0xb0)
2416 /* We could only have updated PC by popping into it; if so, it
2417 will show up as address. Otherwise, copy LR into PC. */
2418 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2419 cache
->saved_regs
[ARM_PC_REGNUM
]
2420 = cache
->saved_regs
[ARM_LR_REGNUM
];
2425 else if (insn
== 0xb1)
2427 int mask
= *entry
++;
2430 /* All-zero mask and mask >= 16 is "spare". */
2431 if (mask
== 0 || mask
>= 16)
2434 /* Pop r0..r3 under mask. */
2435 for (i
= 0; i
< 4; i
++)
2436 if (mask
& (1 << i
))
2438 cache
->saved_regs
[i
].addr
= vsp
;
2442 else if (insn
== 0xb2)
2444 ULONGEST offset
= 0;
2449 offset
|= (*entry
& 0x7f) << shift
;
2452 while (*entry
++ & 0x80);
2454 vsp
+= 0x204 + (offset
<< 2);
2456 else if (insn
== 0xb3)
2458 int start
= *entry
>> 4;
2459 int count
= (*entry
++) & 0xf;
2462 /* Only registers D0..D15 are valid here. */
2463 if (start
+ count
>= 16)
2466 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2467 for (i
= 0; i
<= count
; i
++)
2469 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2473 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2476 else if ((insn
& 0xf8) == 0xb8)
2478 int count
= insn
& 0x7;
2481 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2482 for (i
= 0; i
<= count
; i
++)
2484 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2488 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2491 else if (insn
== 0xc6)
2493 int start
= *entry
>> 4;
2494 int count
= (*entry
++) & 0xf;
2497 /* Only registers WR0..WR15 are valid. */
2498 if (start
+ count
>= 16)
2501 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2502 for (i
= 0; i
<= count
; i
++)
2504 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2508 else if (insn
== 0xc7)
2510 int mask
= *entry
++;
2513 /* All-zero mask and mask >= 16 is "spare". */
2514 if (mask
== 0 || mask
>= 16)
2517 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2518 for (i
= 0; i
< 4; i
++)
2519 if (mask
& (1 << i
))
2521 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2525 else if ((insn
& 0xf8) == 0xc0)
2527 int count
= insn
& 0x7;
2530 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2531 for (i
= 0; i
<= count
; i
++)
2533 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2537 else if (insn
== 0xc8)
2539 int start
= *entry
>> 4;
2540 int count
= (*entry
++) & 0xf;
2543 /* Only registers D0..D31 are valid. */
2544 if (start
+ count
>= 16)
2547 /* Pop VFP double-precision registers
2548 D[16+start]..D[16+start+count]. */
2549 for (i
= 0; i
<= count
; i
++)
2551 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2555 else if (insn
== 0xc9)
2557 int start
= *entry
>> 4;
2558 int count
= (*entry
++) & 0xf;
2561 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2562 for (i
= 0; i
<= count
; i
++)
2564 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2568 else if ((insn
& 0xf8) == 0xd0)
2570 int count
= insn
& 0x7;
2573 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2574 for (i
= 0; i
<= count
; i
++)
2576 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2582 /* Everything else is "spare". */
2587 /* If we restore SP from a register, assume this was the frame register.
2588 Otherwise just fall back to SP as frame register. */
2589 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2590 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2592 cache
->framereg
= ARM_SP_REGNUM
;
2594 /* Determine offset to previous frame. */
2596 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2598 /* We already got the previous SP. */
2599 cache
->prev_sp
= vsp
;
2604 /* Unwinding via ARM exception table entries. Note that the sniffer
2605 already computes a filled-in prologue cache, which is then used
2606 with the same arm_prologue_this_id and arm_prologue_prev_register
2607 routines also used for prologue-parsing based unwinding. */
2610 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2611 struct frame_info
*this_frame
,
2612 void **this_prologue_cache
)
2614 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2615 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2616 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2617 struct arm_prologue_cache
*cache
;
2620 /* See if we have an ARM exception table entry covering this address. */
2621 addr_in_block
= get_frame_address_in_block (this_frame
);
2622 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2626 /* The ARM exception table does not describe unwind information
2627 for arbitrary PC values, but is guaranteed to be correct only
2628 at call sites. We have to decide here whether we want to use
2629 ARM exception table information for this frame, or fall back
2630 to using prologue parsing. (Note that if we have DWARF CFI,
2631 this sniffer isn't even called -- CFI is always preferred.)
2633 Before we make this decision, however, we check whether we
2634 actually have *symbol* information for the current frame.
2635 If not, prologue parsing would not work anyway, so we might
2636 as well use the exception table and hope for the best. */
2637 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2641 /* If the next frame is "normal", we are at a call site in this
2642 frame, so exception information is guaranteed to be valid. */
2643 if (get_next_frame (this_frame
)
2644 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2647 /* We also assume exception information is valid if we're currently
2648 blocked in a system call. The system library is supposed to
2649 ensure this, so that e.g. pthread cancellation works. */
2650 if (arm_frame_is_thumb (this_frame
))
2654 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2655 2, byte_order_for_code
, &insn
)
2656 && (insn
& 0xff00) == 0xdf00 /* svc */)
2663 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2664 4, byte_order_for_code
, &insn
)
2665 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2669 /* Bail out if we don't know that exception information is valid. */
2673 /* The ARM exception index does not mark the *end* of the region
2674 covered by the entry, and some functions will not have any entry.
2675 To correctly recognize the end of the covered region, the linker
2676 should have inserted dummy records with a CANTUNWIND marker.
2678 Unfortunately, current versions of GNU ld do not reliably do
2679 this, and thus we may have found an incorrect entry above.
2680 As a (temporary) sanity check, we only use the entry if it
2681 lies *within* the bounds of the function. Note that this check
2682 might reject perfectly valid entries that just happen to cover
2683 multiple functions; therefore this check ought to be removed
2684 once the linker is fixed. */
2685 if (func_start
> exidx_region
)
2689 /* Decode the list of unwinding instructions into a prologue cache.
2690 Note that this may fail due to e.g. a "refuse to unwind" code. */
2691 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2695 *this_prologue_cache
= cache
;
2699 struct frame_unwind arm_exidx_unwind
= {
2701 default_frame_unwind_stop_reason
,
2702 arm_prologue_this_id
,
2703 arm_prologue_prev_register
,
2705 arm_exidx_unwind_sniffer
2708 static struct arm_prologue_cache
*
2709 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2711 struct arm_prologue_cache
*cache
;
2714 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2715 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2717 /* Still rely on the offset calculated from prologue. */
2718 arm_scan_prologue (this_frame
, cache
);
2720 /* Since we are in epilogue, the SP has been restored. */
2721 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2723 /* Calculate actual addresses of saved registers using offsets
2724 determined by arm_scan_prologue. */
2725 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2726 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2727 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2732 /* Implementation of function hook 'this_id' in
2733 'struct frame_uwnind' for epilogue unwinder. */
2736 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2738 struct frame_id
*this_id
)
2740 struct arm_prologue_cache
*cache
;
2743 if (*this_cache
== NULL
)
2744 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2745 cache
= (struct arm_prologue_cache
*) *this_cache
;
2747 /* Use function start address as part of the frame ID. If we cannot
2748 identify the start address (due to missing symbol information),
2749 fall back to just using the current PC. */
2750 pc
= get_frame_pc (this_frame
);
2751 func
= get_frame_func (this_frame
);
2755 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2758 /* Implementation of function hook 'prev_register' in
2759 'struct frame_uwnind' for epilogue unwinder. */
2761 static struct value
*
2762 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2763 void **this_cache
, int regnum
)
2765 if (*this_cache
== NULL
)
2766 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2768 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2771 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2773 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2776 /* Implementation of function hook 'sniffer' in
2777 'struct frame_uwnind' for epilogue unwinder. */
2780 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2781 struct frame_info
*this_frame
,
2782 void **this_prologue_cache
)
2784 if (frame_relative_level (this_frame
) == 0)
2786 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2787 CORE_ADDR pc
= get_frame_pc (this_frame
);
2789 if (arm_frame_is_thumb (this_frame
))
2790 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2792 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2798 /* Frame unwinder from epilogue. */
2800 static const struct frame_unwind arm_epilogue_frame_unwind
=
2803 default_frame_unwind_stop_reason
,
2804 arm_epilogue_frame_this_id
,
2805 arm_epilogue_frame_prev_register
,
2807 arm_epilogue_frame_sniffer
,
2810 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2811 trampoline, return the target PC. Otherwise return 0.
2813 void call0a (char c, short s, int i, long l) {}
2817 (*pointer_to_call0a) (c, s, i, l);
2820 Instead of calling a stub library function _call_via_xx (xx is
2821 the register name), GCC may inline the trampoline in the object
2822 file as below (register r2 has the address of call0a).
2825 .type main, %function
2834 The trampoline 'bx r2' doesn't belong to main. */
2837 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2839 /* The heuristics of recognizing such trampoline is that FRAME is
2840 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2841 if (arm_frame_is_thumb (frame
))
2845 if (target_read_memory (pc
, buf
, 2) == 0)
2847 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2848 enum bfd_endian byte_order_for_code
2849 = gdbarch_byte_order_for_code (gdbarch
);
2851 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2853 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2856 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2858 /* Clear the LSB so that gdb core sets step-resume
2859 breakpoint at the right address. */
2860 return UNMAKE_THUMB_ADDR (dest
);
2868 static struct arm_prologue_cache
*
2869 arm_make_stub_cache (struct frame_info
*this_frame
)
2871 struct arm_prologue_cache
*cache
;
2873 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2874 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2876 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2881 /* Our frame ID for a stub frame is the current SP and LR. */
2884 arm_stub_this_id (struct frame_info
*this_frame
,
2886 struct frame_id
*this_id
)
2888 struct arm_prologue_cache
*cache
;
2890 if (*this_cache
== NULL
)
2891 *this_cache
= arm_make_stub_cache (this_frame
);
2892 cache
= (struct arm_prologue_cache
*) *this_cache
;
2894 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2898 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2899 struct frame_info
*this_frame
,
2900 void **this_prologue_cache
)
2902 CORE_ADDR addr_in_block
;
2904 CORE_ADDR pc
, start_addr
;
2907 addr_in_block
= get_frame_address_in_block (this_frame
);
2908 pc
= get_frame_pc (this_frame
);
2909 if (in_plt_section (addr_in_block
)
2910 /* We also use the stub winder if the target memory is unreadable
2911 to avoid having the prologue unwinder trying to read it. */
2912 || target_read_memory (pc
, dummy
, 4) != 0)
2915 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2916 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2922 struct frame_unwind arm_stub_unwind
= {
2924 default_frame_unwind_stop_reason
,
2926 arm_prologue_prev_register
,
2928 arm_stub_unwind_sniffer
2931 /* Put here the code to store, into CACHE->saved_regs, the addresses
2932 of the saved registers of frame described by THIS_FRAME. CACHE is
2935 static struct arm_prologue_cache
*
2936 arm_m_exception_cache (struct frame_info
*this_frame
)
2938 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2939 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2940 struct arm_prologue_cache
*cache
;
2941 CORE_ADDR unwound_sp
;
2944 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2945 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2947 unwound_sp
= get_frame_register_unsigned (this_frame
,
2950 /* The hardware saves eight 32-bit words, comprising xPSR,
2951 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2952 "B1.5.6 Exception entry behavior" in
2953 "ARMv7-M Architecture Reference Manual". */
2954 cache
->saved_regs
[0].addr
= unwound_sp
;
2955 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2956 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2957 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2958 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2959 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2960 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2961 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2963 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2964 aligner between the top of the 32-byte stack frame and the
2965 previous context's stack pointer. */
2966 cache
->prev_sp
= unwound_sp
+ 32;
2967 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2968 && (xpsr
& (1 << 9)) != 0)
2969 cache
->prev_sp
+= 4;
2974 /* Implementation of function hook 'this_id' in
2975 'struct frame_uwnind'. */
2978 arm_m_exception_this_id (struct frame_info
*this_frame
,
2980 struct frame_id
*this_id
)
2982 struct arm_prologue_cache
*cache
;
2984 if (*this_cache
== NULL
)
2985 *this_cache
= arm_m_exception_cache (this_frame
);
2986 cache
= (struct arm_prologue_cache
*) *this_cache
;
2988 /* Our frame ID for a stub frame is the current SP and LR. */
2989 *this_id
= frame_id_build (cache
->prev_sp
,
2990 get_frame_pc (this_frame
));
2993 /* Implementation of function hook 'prev_register' in
2994 'struct frame_uwnind'. */
2996 static struct value
*
2997 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3001 struct arm_prologue_cache
*cache
;
3003 if (*this_cache
== NULL
)
3004 *this_cache
= arm_m_exception_cache (this_frame
);
3005 cache
= (struct arm_prologue_cache
*) *this_cache
;
3007 /* The value was already reconstructed into PREV_SP. */
3008 if (prev_regnum
== ARM_SP_REGNUM
)
3009 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3012 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3016 /* Implementation of function hook 'sniffer' in
3017 'struct frame_uwnind'. */
3020 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3021 struct frame_info
*this_frame
,
3022 void **this_prologue_cache
)
3024 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3026 /* No need to check is_m; this sniffer is only registered for
3027 M-profile architectures. */
3029 /* Check if exception frame returns to a magic PC value. */
3030 return arm_m_addr_is_magic (this_pc
);
3033 /* Frame unwinder for M-profile exceptions. */
3035 struct frame_unwind arm_m_exception_unwind
=
3038 default_frame_unwind_stop_reason
,
3039 arm_m_exception_this_id
,
3040 arm_m_exception_prev_register
,
3042 arm_m_exception_unwind_sniffer
3046 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3048 struct arm_prologue_cache
*cache
;
3050 if (*this_cache
== NULL
)
3051 *this_cache
= arm_make_prologue_cache (this_frame
);
3052 cache
= (struct arm_prologue_cache
*) *this_cache
;
3054 return cache
->prev_sp
- cache
->framesize
;
3057 struct frame_base arm_normal_base
= {
3058 &arm_prologue_unwind
,
3059 arm_normal_frame_base
,
3060 arm_normal_frame_base
,
3061 arm_normal_frame_base
3064 static struct value
*
3065 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3068 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3070 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3075 /* The PC is normally copied from the return column, which
3076 describes saves of LR. However, that version may have an
3077 extra bit set to indicate Thumb state. The bit is not
3079 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3080 return frame_unwind_got_constant (this_frame
, regnum
,
3081 arm_addr_bits_remove (gdbarch
, lr
));
3084 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3085 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3086 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3087 if (IS_THUMB_ADDR (lr
))
3091 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3094 internal_error (__FILE__
, __LINE__
,
3095 _("Unexpected register %d"), regnum
);
3100 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3101 struct dwarf2_frame_state_reg
*reg
,
3102 struct frame_info
*this_frame
)
3108 reg
->how
= DWARF2_FRAME_REG_FN
;
3109 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3112 reg
->how
= DWARF2_FRAME_REG_CFA
;
3117 /* Implement the stack_frame_destroyed_p gdbarch method. */
3120 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3122 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3123 unsigned int insn
, insn2
;
3124 int found_return
= 0, found_stack_adjust
= 0;
3125 CORE_ADDR func_start
, func_end
;
3129 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3132 /* The epilogue is a sequence of instructions along the following lines:
3134 - add stack frame size to SP or FP
3135 - [if frame pointer used] restore SP from FP
3136 - restore registers from SP [may include PC]
3137 - a return-type instruction [if PC wasn't already restored]
3139 In a first pass, we scan forward from the current PC and verify the
3140 instructions we find as compatible with this sequence, ending in a
3143 However, this is not sufficient to distinguish indirect function calls
3144 within a function from indirect tail calls in the epilogue in some cases.
3145 Therefore, if we didn't already find any SP-changing instruction during
3146 forward scan, we add a backward scanning heuristic to ensure we actually
3147 are in the epilogue. */
3150 while (scan_pc
< func_end
&& !found_return
)
3152 if (target_read_memory (scan_pc
, buf
, 2))
3156 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3158 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3160 else if (insn
== 0x46f7) /* mov pc, lr */
3162 else if (thumb_instruction_restores_sp (insn
))
3164 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3167 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3169 if (target_read_memory (scan_pc
, buf
, 2))
3173 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3175 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3177 if (insn2
& 0x8000) /* <registers> include PC. */
3180 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3181 && (insn2
& 0x0fff) == 0x0b04)
3183 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3186 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3187 && (insn2
& 0x0e00) == 0x0a00)
3199 /* Since any instruction in the epilogue sequence, with the possible
3200 exception of return itself, updates the stack pointer, we need to
3201 scan backwards for at most one instruction. Try either a 16-bit or
3202 a 32-bit instruction. This is just a heuristic, so we do not worry
3203 too much about false positives. */
3205 if (pc
- 4 < func_start
)
3207 if (target_read_memory (pc
- 4, buf
, 4))
3210 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3211 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3213 if (thumb_instruction_restores_sp (insn2
))
3214 found_stack_adjust
= 1;
3215 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3216 found_stack_adjust
= 1;
3217 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3218 && (insn2
& 0x0fff) == 0x0b04)
3219 found_stack_adjust
= 1;
3220 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3221 && (insn2
& 0x0e00) == 0x0a00)
3222 found_stack_adjust
= 1;
3224 return found_stack_adjust
;
3228 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3230 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3233 CORE_ADDR func_start
, func_end
;
3235 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3238 /* We are in the epilogue if the previous instruction was a stack
3239 adjustment and the next instruction is a possible return (bx, mov
3240 pc, or pop). We could have to scan backwards to find the stack
3241 adjustment, or forwards to find the return, but this is a decent
3242 approximation. First scan forwards. */
3245 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3246 if (bits (insn
, 28, 31) != INST_NV
)
3248 if ((insn
& 0x0ffffff0) == 0x012fff10)
3251 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3254 else if ((insn
& 0x0fff0000) == 0x08bd0000
3255 && (insn
& 0x0000c000) != 0)
3256 /* POP (LDMIA), including PC or LR. */
3263 /* Scan backwards. This is just a heuristic, so do not worry about
3264 false positives from mode changes. */
3266 if (pc
< func_start
+ 4)
3269 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3270 if (arm_instruction_restores_sp (insn
))
3276 /* Implement the stack_frame_destroyed_p gdbarch method. */
3279 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3281 if (arm_pc_is_thumb (gdbarch
, pc
))
3282 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3284 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3287 /* When arguments must be pushed onto the stack, they go on in reverse
3288 order. The code below implements a FILO (stack) to do this. */
3293 struct stack_item
*prev
;
3297 static struct stack_item
*
3298 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3300 struct stack_item
*si
;
3301 si
= XNEW (struct stack_item
);
3302 si
->data
= (gdb_byte
*) xmalloc (len
);
3305 memcpy (si
->data
, contents
, len
);
3309 static struct stack_item
*
3310 pop_stack_item (struct stack_item
*si
)
3312 struct stack_item
*dead
= si
;
3319 /* Implement the gdbarch type alignment method, overrides the generic
3320 alignment algorithm for anything that is arm specific. */
3323 arm_type_align (gdbarch
*gdbarch
, struct type
*t
)
3325 t
= check_typedef (t
);
3326 if (TYPE_CODE (t
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (t
))
3328 /* Use the natural alignment for vector types (the same for
3329 scalar type), but the maximum alignment is 64-bit. */
3330 if (TYPE_LENGTH (t
) > 8)
3333 return TYPE_LENGTH (t
);
3336 /* Allow the common code to calculate the alignment. */
3340 /* Possible base types for a candidate for passing and returning in
3343 enum arm_vfp_cprc_base_type
3352 /* The length of one element of base type B. */
3355 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3359 case VFP_CPRC_SINGLE
:
3361 case VFP_CPRC_DOUBLE
:
3363 case VFP_CPRC_VEC64
:
3365 case VFP_CPRC_VEC128
:
3368 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3373 /* The character ('s', 'd' or 'q') for the type of VFP register used
3374 for passing base type B. */
3377 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3381 case VFP_CPRC_SINGLE
:
3383 case VFP_CPRC_DOUBLE
:
3385 case VFP_CPRC_VEC64
:
3387 case VFP_CPRC_VEC128
:
3390 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3395 /* Determine whether T may be part of a candidate for passing and
3396 returning in VFP registers, ignoring the limit on the total number
3397 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3398 classification of the first valid component found; if it is not
3399 VFP_CPRC_UNKNOWN, all components must have the same classification
3400 as *BASE_TYPE. If it is found that T contains a type not permitted
3401 for passing and returning in VFP registers, a type differently
3402 classified from *BASE_TYPE, or two types differently classified
3403 from each other, return -1, otherwise return the total number of
3404 base-type elements found (possibly 0 in an empty structure or
3405 array). Vector types are not currently supported, matching the
3406 generic AAPCS support. */
3409 arm_vfp_cprc_sub_candidate (struct type
*t
,
3410 enum arm_vfp_cprc_base_type
*base_type
)
3412 t
= check_typedef (t
);
3413 switch (TYPE_CODE (t
))
3416 switch (TYPE_LENGTH (t
))
3419 if (*base_type
== VFP_CPRC_UNKNOWN
)
3420 *base_type
= VFP_CPRC_SINGLE
;
3421 else if (*base_type
!= VFP_CPRC_SINGLE
)
3426 if (*base_type
== VFP_CPRC_UNKNOWN
)
3427 *base_type
= VFP_CPRC_DOUBLE
;
3428 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3437 case TYPE_CODE_COMPLEX
:
3438 /* Arguments of complex T where T is one of the types float or
3439 double get treated as if they are implemented as:
3448 switch (TYPE_LENGTH (t
))
3451 if (*base_type
== VFP_CPRC_UNKNOWN
)
3452 *base_type
= VFP_CPRC_SINGLE
;
3453 else if (*base_type
!= VFP_CPRC_SINGLE
)
3458 if (*base_type
== VFP_CPRC_UNKNOWN
)
3459 *base_type
= VFP_CPRC_DOUBLE
;
3460 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3469 case TYPE_CODE_ARRAY
:
3471 if (TYPE_VECTOR (t
))
3473 /* A 64-bit or 128-bit containerized vector type are VFP
3475 switch (TYPE_LENGTH (t
))
3478 if (*base_type
== VFP_CPRC_UNKNOWN
)
3479 *base_type
= VFP_CPRC_VEC64
;
3482 if (*base_type
== VFP_CPRC_UNKNOWN
)
3483 *base_type
= VFP_CPRC_VEC128
;
3494 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3498 if (TYPE_LENGTH (t
) == 0)
3500 gdb_assert (count
== 0);
3503 else if (count
== 0)
3505 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3506 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3507 return TYPE_LENGTH (t
) / unitlen
;
3512 case TYPE_CODE_STRUCT
:
3517 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3521 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3522 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3524 if (sub_count
== -1)
3528 if (TYPE_LENGTH (t
) == 0)
3530 gdb_assert (count
== 0);
3533 else if (count
== 0)
3535 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3536 if (TYPE_LENGTH (t
) != unitlen
* count
)
3541 case TYPE_CODE_UNION
:
3546 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3548 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3550 if (sub_count
== -1)
3552 count
= (count
> sub_count
? count
: sub_count
);
3554 if (TYPE_LENGTH (t
) == 0)
3556 gdb_assert (count
== 0);
3559 else if (count
== 0)
3561 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3562 if (TYPE_LENGTH (t
) != unitlen
* count
)
3574 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3575 if passed to or returned from a non-variadic function with the VFP
3576 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3577 *BASE_TYPE to the base type for T and *COUNT to the number of
3578 elements of that base type before returning. */
3581 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3584 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3585 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3586 if (c
<= 0 || c
> 4)
3593 /* Return 1 if the VFP ABI should be used for passing arguments to and
3594 returning values from a function of type FUNC_TYPE, 0
3598 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3600 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3601 /* Variadic functions always use the base ABI. Assume that functions
3602 without debug info are not variadic. */
3603 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3605 /* The VFP ABI is only supported as a variant of AAPCS. */
3606 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3608 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3611 /* We currently only support passing parameters in integer registers, which
3612 conforms with GCC's default model, and VFP argument passing following
3613 the VFP variant of AAPCS. Several other variants exist and
3614 we should probably support some of them based on the selected ABI. */
3617 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3618 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3619 struct value
**args
, CORE_ADDR sp
,
3620 function_call_return_method return_method
,
3621 CORE_ADDR struct_addr
)
3623 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3627 struct stack_item
*si
= NULL
;
3630 unsigned vfp_regs_free
= (1 << 16) - 1;
3632 /* Determine the type of this function and whether the VFP ABI
3634 ftype
= check_typedef (value_type (function
));
3635 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3636 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3637 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3639 /* Set the return address. For the ARM, the return breakpoint is
3640 always at BP_ADDR. */
3641 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3643 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3645 /* Walk through the list of args and determine how large a temporary
3646 stack is required. Need to take care here as structs may be
3647 passed on the stack, and we have to push them. */
3650 argreg
= ARM_A1_REGNUM
;
3653 /* The struct_return pointer occupies the first parameter
3654 passing register. */
3655 if (return_method
== return_method_struct
)
3658 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3659 gdbarch_register_name (gdbarch
, argreg
),
3660 paddress (gdbarch
, struct_addr
));
3661 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3665 for (argnum
= 0; argnum
< nargs
; argnum
++)
3668 struct type
*arg_type
;
3669 struct type
*target_type
;
3670 enum type_code typecode
;
3671 const bfd_byte
*val
;
3673 enum arm_vfp_cprc_base_type vfp_base_type
;
3675 int may_use_core_reg
= 1;
3677 arg_type
= check_typedef (value_type (args
[argnum
]));
3678 len
= TYPE_LENGTH (arg_type
);
3679 target_type
= TYPE_TARGET_TYPE (arg_type
);
3680 typecode
= TYPE_CODE (arg_type
);
3681 val
= value_contents (args
[argnum
]);
3683 align
= type_align (arg_type
);
3684 /* Round alignment up to a whole number of words. */
3685 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3686 /* Different ABIs have different maximum alignments. */
3687 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3689 /* The APCS ABI only requires word alignment. */
3690 align
= INT_REGISTER_SIZE
;
3694 /* The AAPCS requires at most doubleword alignment. */
3695 if (align
> INT_REGISTER_SIZE
* 2)
3696 align
= INT_REGISTER_SIZE
* 2;
3700 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3708 /* Because this is a CPRC it cannot go in a core register or
3709 cause a core register to be skipped for alignment.
3710 Either it goes in VFP registers and the rest of this loop
3711 iteration is skipped for this argument, or it goes on the
3712 stack (and the stack alignment code is correct for this
3714 may_use_core_reg
= 0;
3716 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3717 shift
= unit_length
/ 4;
3718 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3719 for (regno
= 0; regno
< 16; regno
+= shift
)
3720 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3729 vfp_regs_free
&= ~(mask
<< regno
);
3730 reg_scaled
= regno
/ shift
;
3731 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3732 for (i
= 0; i
< vfp_base_count
; i
++)
3736 if (reg_char
== 'q')
3737 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3738 val
+ i
* unit_length
);
3741 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3742 reg_char
, reg_scaled
+ i
);
3743 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3745 regcache
->cooked_write (regnum
, val
+ i
* unit_length
);
3752 /* This CPRC could not go in VFP registers, so all VFP
3753 registers are now marked as used. */
3758 /* Push stack padding for dowubleword alignment. */
3759 if (nstack
& (align
- 1))
3761 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3762 nstack
+= INT_REGISTER_SIZE
;
3765 /* Doubleword aligned quantities must go in even register pairs. */
3766 if (may_use_core_reg
3767 && argreg
<= ARM_LAST_ARG_REGNUM
3768 && align
> INT_REGISTER_SIZE
3772 /* If the argument is a pointer to a function, and it is a
3773 Thumb function, create a LOCAL copy of the value and set
3774 the THUMB bit in it. */
3775 if (TYPE_CODE_PTR
== typecode
3776 && target_type
!= NULL
3777 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3779 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3780 if (arm_pc_is_thumb (gdbarch
, regval
))
3782 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3783 store_unsigned_integer (copy
, len
, byte_order
,
3784 MAKE_THUMB_ADDR (regval
));
3789 /* Copy the argument to general registers or the stack in
3790 register-sized pieces. Large arguments are split between
3791 registers and stack. */
3794 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3796 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3798 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3800 /* The argument is being passed in a general purpose
3802 if (byte_order
== BFD_ENDIAN_BIG
)
3803 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3805 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3807 gdbarch_register_name
3809 phex (regval
, INT_REGISTER_SIZE
));
3810 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3815 gdb_byte buf
[INT_REGISTER_SIZE
];
3817 memset (buf
, 0, sizeof (buf
));
3818 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3820 /* Push the arguments onto the stack. */
3822 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3824 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3825 nstack
+= INT_REGISTER_SIZE
;
3832 /* If we have an odd number of words to push, then decrement the stack
3833 by one word now, so first stack argument will be dword aligned. */
3840 write_memory (sp
, si
->data
, si
->len
);
3841 si
= pop_stack_item (si
);
3844 /* Finally, update teh SP register. */
3845 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3851 /* Always align the frame to an 8-byte boundary. This is required on
3852 some platforms and harmless on the rest. */
3855 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3857 /* Align the stack to eight bytes. */
3858 return sp
& ~ (CORE_ADDR
) 7;
3862 print_fpu_flags (struct ui_file
*file
, int flags
)
3864 if (flags
& (1 << 0))
3865 fputs_filtered ("IVO ", file
);
3866 if (flags
& (1 << 1))
3867 fputs_filtered ("DVZ ", file
);
3868 if (flags
& (1 << 2))
3869 fputs_filtered ("OFL ", file
);
3870 if (flags
& (1 << 3))
3871 fputs_filtered ("UFL ", file
);
3872 if (flags
& (1 << 4))
3873 fputs_filtered ("INX ", file
);
3874 fputc_filtered ('\n', file
);
3877 /* Print interesting information about the floating point processor
3878 (if present) or emulator. */
3880 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3881 struct frame_info
*frame
, const char *args
)
3883 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3886 type
= (status
>> 24) & 127;
3887 if (status
& (1 << 31))
3888 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3890 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3891 /* i18n: [floating point unit] mask */
3892 fputs_filtered (_("mask: "), file
);
3893 print_fpu_flags (file
, status
>> 16);
3894 /* i18n: [floating point unit] flags */
3895 fputs_filtered (_("flags: "), file
);
3896 print_fpu_flags (file
, status
);
3899 /* Construct the ARM extended floating point type. */
3900 static struct type
*
3901 arm_ext_type (struct gdbarch
*gdbarch
)
3903 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3905 if (!tdep
->arm_ext_type
)
3907 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3908 floatformats_arm_ext
);
3910 return tdep
->arm_ext_type
;
3913 static struct type
*
3914 arm_neon_double_type (struct gdbarch
*gdbarch
)
3916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3918 if (tdep
->neon_double_type
== NULL
)
3920 struct type
*t
, *elem
;
3922 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3924 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3925 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3926 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3927 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3928 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3929 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3930 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3931 append_composite_type_field (t
, "u64", elem
);
3932 elem
= builtin_type (gdbarch
)->builtin_float
;
3933 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3934 elem
= builtin_type (gdbarch
)->builtin_double
;
3935 append_composite_type_field (t
, "f64", elem
);
3937 TYPE_VECTOR (t
) = 1;
3938 TYPE_NAME (t
) = "neon_d";
3939 tdep
->neon_double_type
= t
;
3942 return tdep
->neon_double_type
;
3945 /* FIXME: The vector types are not correctly ordered on big-endian
3946 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3947 bits of d0 - regardless of what unit size is being held in d0. So
3948 the offset of the first uint8 in d0 is 7, but the offset of the
3949 first float is 4. This code works as-is for little-endian
3952 static struct type
*
3953 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3957 if (tdep
->neon_quad_type
== NULL
)
3959 struct type
*t
, *elem
;
3961 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3963 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3964 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3965 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3966 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3967 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3968 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3969 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3970 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3971 elem
= builtin_type (gdbarch
)->builtin_float
;
3972 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
3973 elem
= builtin_type (gdbarch
)->builtin_double
;
3974 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
3976 TYPE_VECTOR (t
) = 1;
3977 TYPE_NAME (t
) = "neon_q";
3978 tdep
->neon_quad_type
= t
;
3981 return tdep
->neon_quad_type
;
3984 /* Return the GDB type object for the "standard" data type of data in
3987 static struct type
*
3988 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
3990 int num_regs
= gdbarch_num_regs (gdbarch
);
3992 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
3993 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
3994 return builtin_type (gdbarch
)->builtin_float
;
3996 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
3997 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
3998 return arm_neon_quad_type (gdbarch
);
4000 /* If the target description has register information, we are only
4001 in this function so that we can override the types of
4002 double-precision registers for NEON. */
4003 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4005 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4007 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4008 && TYPE_CODE (t
) == TYPE_CODE_FLT
4009 && gdbarch_tdep (gdbarch
)->have_neon
)
4010 return arm_neon_double_type (gdbarch
);
4015 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4017 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4018 return builtin_type (gdbarch
)->builtin_void
;
4020 return arm_ext_type (gdbarch
);
4022 else if (regnum
== ARM_SP_REGNUM
)
4023 return builtin_type (gdbarch
)->builtin_data_ptr
;
4024 else if (regnum
== ARM_PC_REGNUM
)
4025 return builtin_type (gdbarch
)->builtin_func_ptr
;
4026 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4027 /* These registers are only supported on targets which supply
4028 an XML description. */
4029 return builtin_type (gdbarch
)->builtin_int0
;
4031 return builtin_type (gdbarch
)->builtin_uint32
;
4034 /* Map a DWARF register REGNUM onto the appropriate GDB register
4038 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4040 /* Core integer regs. */
4041 if (reg
>= 0 && reg
<= 15)
4044 /* Legacy FPA encoding. These were once used in a way which
4045 overlapped with VFP register numbering, so their use is
4046 discouraged, but GDB doesn't support the ARM toolchain
4047 which used them for VFP. */
4048 if (reg
>= 16 && reg
<= 23)
4049 return ARM_F0_REGNUM
+ reg
- 16;
4051 /* New assignments for the FPA registers. */
4052 if (reg
>= 96 && reg
<= 103)
4053 return ARM_F0_REGNUM
+ reg
- 96;
4055 /* WMMX register assignments. */
4056 if (reg
>= 104 && reg
<= 111)
4057 return ARM_WCGR0_REGNUM
+ reg
- 104;
4059 if (reg
>= 112 && reg
<= 127)
4060 return ARM_WR0_REGNUM
+ reg
- 112;
4062 if (reg
>= 192 && reg
<= 199)
4063 return ARM_WC0_REGNUM
+ reg
- 192;
4065 /* VFP v2 registers. A double precision value is actually
4066 in d1 rather than s2, but the ABI only defines numbering
4067 for the single precision registers. This will "just work"
4068 in GDB for little endian targets (we'll read eight bytes,
4069 starting in s0 and then progressing to s1), but will be
4070 reversed on big endian targets with VFP. This won't
4071 be a problem for the new Neon quad registers; you're supposed
4072 to use DW_OP_piece for those. */
4073 if (reg
>= 64 && reg
<= 95)
4077 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4078 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4082 /* VFP v3 / Neon registers. This range is also used for VFP v2
4083 registers, except that it now describes d0 instead of s0. */
4084 if (reg
>= 256 && reg
<= 287)
4088 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4089 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4096 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4098 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4101 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4103 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4104 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4106 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4107 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4109 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4110 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4112 if (reg
< NUM_GREGS
)
4113 return SIM_ARM_R0_REGNUM
+ reg
;
4116 if (reg
< NUM_FREGS
)
4117 return SIM_ARM_FP0_REGNUM
+ reg
;
4120 if (reg
< NUM_SREGS
)
4121 return SIM_ARM_FPS_REGNUM
+ reg
;
4124 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4127 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4128 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4129 NULL if an error occurs. BUF is freed. */
4132 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4133 int old_len
, int new_len
)
4136 int bytes_to_read
= new_len
- old_len
;
4138 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4139 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4141 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4149 /* An IT block is at most the 2-byte IT instruction followed by
4150 four 4-byte instructions. The furthest back we must search to
4151 find an IT block that affects the current instruction is thus
4152 2 + 3 * 4 == 14 bytes. */
4153 #define MAX_IT_BLOCK_PREFIX 14
4155 /* Use a quick scan if there are more than this many bytes of
4157 #define IT_SCAN_THRESHOLD 32
4159 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4160 A breakpoint in an IT block may not be hit, depending on the
4163 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4167 CORE_ADDR boundary
, func_start
;
4169 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4170 int i
, any
, last_it
, last_it_count
;
4172 /* If we are using BKPT breakpoints, none of this is necessary. */
4173 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4176 /* ARM mode does not have this problem. */
4177 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4180 /* We are setting a breakpoint in Thumb code that could potentially
4181 contain an IT block. The first step is to find how much Thumb
4182 code there is; we do not need to read outside of known Thumb
4184 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4186 /* Thumb-2 code must have mapping symbols to have a chance. */
4189 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4191 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4192 && func_start
> boundary
)
4193 boundary
= func_start
;
4195 /* Search for a candidate IT instruction. We have to do some fancy
4196 footwork to distinguish a real IT instruction from the second
4197 half of a 32-bit instruction, but there is no need for that if
4198 there's no candidate. */
4199 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4201 /* No room for an IT instruction. */
4204 buf
= (gdb_byte
*) xmalloc (buf_len
);
4205 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4208 for (i
= 0; i
< buf_len
; i
+= 2)
4210 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4211 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4224 /* OK, the code bytes before this instruction contain at least one
4225 halfword which resembles an IT instruction. We know that it's
4226 Thumb code, but there are still two possibilities. Either the
4227 halfword really is an IT instruction, or it is the second half of
4228 a 32-bit Thumb instruction. The only way we can tell is to
4229 scan forwards from a known instruction boundary. */
4230 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4234 /* There's a lot of code before this instruction. Start with an
4235 optimistic search; it's easy to recognize halfwords that can
4236 not be the start of a 32-bit instruction, and use that to
4237 lock on to the instruction boundaries. */
4238 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4241 buf_len
= IT_SCAN_THRESHOLD
;
4244 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4246 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4247 if (thumb_insn_size (inst1
) == 2)
4254 /* At this point, if DEFINITE, BUF[I] is the first place we
4255 are sure that we know the instruction boundaries, and it is far
4256 enough from BPADDR that we could not miss an IT instruction
4257 affecting BPADDR. If ! DEFINITE, give up - start from a
4261 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4265 buf_len
= bpaddr
- boundary
;
4271 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4274 buf_len
= bpaddr
- boundary
;
4278 /* Scan forwards. Find the last IT instruction before BPADDR. */
4283 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4285 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4290 else if (inst1
& 0x0002)
4292 else if (inst1
& 0x0004)
4297 i
+= thumb_insn_size (inst1
);
4303 /* There wasn't really an IT instruction after all. */
4306 if (last_it_count
< 1)
4307 /* It was too far away. */
4310 /* This really is a trouble spot. Move the breakpoint to the IT
4312 return bpaddr
- buf_len
+ last_it
;
4315 /* ARM displaced stepping support.
4317 Generally ARM displaced stepping works as follows:
4319 1. When an instruction is to be single-stepped, it is first decoded by
4320 arm_process_displaced_insn. Depending on the type of instruction, it is
4321 then copied to a scratch location, possibly in a modified form. The
4322 copy_* set of functions performs such modification, as necessary. A
4323 breakpoint is placed after the modified instruction in the scratch space
4324 to return control to GDB. Note in particular that instructions which
4325 modify the PC will no longer do so after modification.
4327 2. The instruction is single-stepped, by setting the PC to the scratch
4328 location address, and resuming. Control returns to GDB when the
4331 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4332 function used for the current instruction. This function's job is to
4333 put the CPU/memory state back to what it would have been if the
4334 instruction had been executed unmodified in its original location. */
4336 /* NOP instruction (mov r0, r0). */
4337 #define ARM_NOP 0xe1a00000
4338 #define THUMB_NOP 0x4600
4340 /* Helper for register reads for displaced stepping. In particular, this
4341 returns the PC as it would be seen by the instruction at its original
4345 displaced_read_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4349 CORE_ADDR from
= dsc
->insn_addr
;
4351 if (regno
== ARM_PC_REGNUM
)
4353 /* Compute pipeline offset:
4354 - When executing an ARM instruction, PC reads as the address of the
4355 current instruction plus 8.
4356 - When executing a Thumb instruction, PC reads as the address of the
4357 current instruction plus 4. */
4364 if (debug_displaced
)
4365 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4366 (unsigned long) from
);
4367 return (ULONGEST
) from
;
4371 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4372 if (debug_displaced
)
4373 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4374 regno
, (unsigned long) ret
);
4380 displaced_in_arm_mode (struct regcache
*regs
)
4383 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4385 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4387 return (ps
& t_bit
) == 0;
4390 /* Write to the PC as from a branch instruction. */
4393 branch_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4397 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4398 architecture versions < 6. */
4399 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4400 val
& ~(ULONGEST
) 0x3);
4402 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4403 val
& ~(ULONGEST
) 0x1);
4406 /* Write to the PC as from a branch-exchange instruction. */
4409 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4412 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4414 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4418 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4419 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4421 else if ((val
& 2) == 0)
4423 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4424 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4428 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4429 mode, align dest to 4 bytes). */
4430 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4431 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4432 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4436 /* Write to the PC as if from a load instruction. */
4439 load_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4442 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4443 bx_write_pc (regs
, val
);
4445 branch_write_pc (regs
, dsc
, val
);
4448 /* Write to the PC as if from an ALU instruction. */
4451 alu_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4454 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4455 bx_write_pc (regs
, val
);
4457 branch_write_pc (regs
, dsc
, val
);
4460 /* Helper for writing to registers for displaced stepping. Writing to the PC
4461 has a varying effects depending on the instruction which does the write:
4462 this is controlled by the WRITE_PC argument. */
4465 displaced_write_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4466 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4468 if (regno
== ARM_PC_REGNUM
)
4470 if (debug_displaced
)
4471 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4472 (unsigned long) val
);
4475 case BRANCH_WRITE_PC
:
4476 branch_write_pc (regs
, dsc
, val
);
4480 bx_write_pc (regs
, val
);
4484 load_write_pc (regs
, dsc
, val
);
4488 alu_write_pc (regs
, dsc
, val
);
4491 case CANNOT_WRITE_PC
:
4492 warning (_("Instruction wrote to PC in an unexpected way when "
4493 "single-stepping"));
4497 internal_error (__FILE__
, __LINE__
,
4498 _("Invalid argument to displaced_write_reg"));
4501 dsc
->wrote_to_pc
= 1;
4505 if (debug_displaced
)
4506 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4507 regno
, (unsigned long) val
);
4508 regcache_cooked_write_unsigned (regs
, regno
, val
);
4512 /* This function is used to concisely determine if an instruction INSN
4513 references PC. Register fields of interest in INSN should have the
4514 corresponding fields of BITMASK set to 0b1111. The function
4515 returns return 1 if any of these fields in INSN reference the PC
4516 (also 0b1111, r15), else it returns 0. */
4519 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4521 uint32_t lowbit
= 1;
4523 while (bitmask
!= 0)
4527 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4533 mask
= lowbit
* 0xf;
4535 if ((insn
& mask
) == mask
)
4544 /* The simplest copy function. Many instructions have the same effect no
4545 matter what address they are executed at: in those cases, use this. */
4548 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4549 const char *iname
, arm_displaced_step_closure
*dsc
)
4551 if (debug_displaced
)
4552 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4553 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4556 dsc
->modinsn
[0] = insn
;
4562 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4563 uint16_t insn2
, const char *iname
,
4564 arm_displaced_step_closure
*dsc
)
4566 if (debug_displaced
)
4567 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4568 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4571 dsc
->modinsn
[0] = insn1
;
4572 dsc
->modinsn
[1] = insn2
;
4578 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4581 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4583 arm_displaced_step_closure
*dsc
)
4585 if (debug_displaced
)
4586 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4587 "opcode/class '%s' unmodified\n", insn
,
4590 dsc
->modinsn
[0] = insn
;
4595 /* Preload instructions with immediate offset. */
4598 cleanup_preload (struct gdbarch
*gdbarch
,
4599 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4601 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4602 if (!dsc
->u
.preload
.immed
)
4603 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4607 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4608 arm_displaced_step_closure
*dsc
, unsigned int rn
)
4611 /* Preload instructions:
4613 {pli/pld} [rn, #+/-imm]
4615 {pli/pld} [r0, #+/-imm]. */
4617 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4618 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4619 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4620 dsc
->u
.preload
.immed
= 1;
4622 dsc
->cleanup
= &cleanup_preload
;
4626 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4627 arm_displaced_step_closure
*dsc
)
4629 unsigned int rn
= bits (insn
, 16, 19);
4631 if (!insn_references_pc (insn
, 0x000f0000ul
))
4632 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4634 if (debug_displaced
)
4635 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4636 (unsigned long) insn
);
4638 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4640 install_preload (gdbarch
, regs
, dsc
, rn
);
4646 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4647 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4649 unsigned int rn
= bits (insn1
, 0, 3);
4650 unsigned int u_bit
= bit (insn1
, 7);
4651 int imm12
= bits (insn2
, 0, 11);
4654 if (rn
!= ARM_PC_REGNUM
)
4655 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4657 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4658 PLD (literal) Encoding T1. */
4659 if (debug_displaced
)
4660 fprintf_unfiltered (gdb_stdlog
,
4661 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4662 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4668 /* Rewrite instruction {pli/pld} PC imm12 into:
4669 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4673 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4675 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4676 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4678 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4680 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4681 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4682 dsc
->u
.preload
.immed
= 0;
4684 /* {pli/pld} [r0, r1] */
4685 dsc
->modinsn
[0] = insn1
& 0xfff0;
4686 dsc
->modinsn
[1] = 0xf001;
4689 dsc
->cleanup
= &cleanup_preload
;
4693 /* Preload instructions with register offset. */
4696 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4697 arm_displaced_step_closure
*dsc
, unsigned int rn
,
4700 ULONGEST rn_val
, rm_val
;
4702 /* Preload register-offset instructions:
4704 {pli/pld} [rn, rm {, shift}]
4706 {pli/pld} [r0, r1 {, shift}]. */
4708 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4709 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4710 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4711 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4712 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4713 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4714 dsc
->u
.preload
.immed
= 0;
4716 dsc
->cleanup
= &cleanup_preload
;
4720 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4721 struct regcache
*regs
,
4722 arm_displaced_step_closure
*dsc
)
4724 unsigned int rn
= bits (insn
, 16, 19);
4725 unsigned int rm
= bits (insn
, 0, 3);
4728 if (!insn_references_pc (insn
, 0x000f000ful
))
4729 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4731 if (debug_displaced
)
4732 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4733 (unsigned long) insn
);
4735 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4737 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4741 /* Copy/cleanup coprocessor load and store instructions. */
4744 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4745 struct regcache
*regs
,
4746 arm_displaced_step_closure
*dsc
)
4748 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4750 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4752 if (dsc
->u
.ldst
.writeback
)
4753 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4757 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4758 arm_displaced_step_closure
*dsc
,
4759 int writeback
, unsigned int rn
)
4763 /* Coprocessor load/store instructions:
4765 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4767 {stc/stc2} [r0, #+/-imm].
4769 ldc/ldc2 are handled identically. */
4771 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4772 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4773 /* PC should be 4-byte aligned. */
4774 rn_val
= rn_val
& 0xfffffffc;
4775 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4777 dsc
->u
.ldst
.writeback
= writeback
;
4778 dsc
->u
.ldst
.rn
= rn
;
4780 dsc
->cleanup
= &cleanup_copro_load_store
;
4784 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4785 struct regcache
*regs
,
4786 arm_displaced_step_closure
*dsc
)
4788 unsigned int rn
= bits (insn
, 16, 19);
4790 if (!insn_references_pc (insn
, 0x000f0000ul
))
4791 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4793 if (debug_displaced
)
4794 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4795 "load/store insn %.8lx\n", (unsigned long) insn
);
4797 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4799 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4805 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4806 uint16_t insn2
, struct regcache
*regs
,
4807 arm_displaced_step_closure
*dsc
)
4809 unsigned int rn
= bits (insn1
, 0, 3);
4811 if (rn
!= ARM_PC_REGNUM
)
4812 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4813 "copro load/store", dsc
);
4815 if (debug_displaced
)
4816 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4817 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4819 dsc
->modinsn
[0] = insn1
& 0xfff0;
4820 dsc
->modinsn
[1] = insn2
;
4823 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4824 doesn't support writeback, so pass 0. */
4825 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4830 /* Clean up branch instructions (actually perform the branch, by setting
4834 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4835 arm_displaced_step_closure
*dsc
)
4837 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4838 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4839 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4840 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4845 if (dsc
->u
.branch
.link
)
4847 /* The value of LR should be the next insn of current one. In order
4848 not to confuse logic hanlding later insn `bx lr', if current insn mode
4849 is Thumb, the bit 0 of LR value should be set to 1. */
4850 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4853 next_insn_addr
|= 0x1;
4855 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4859 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4862 /* Copy B/BL/BLX instructions with immediate destinations. */
4865 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4866 arm_displaced_step_closure
*dsc
,
4867 unsigned int cond
, int exchange
, int link
, long offset
)
4869 /* Implement "BL<cond> <label>" as:
4871 Preparation: cond <- instruction condition
4872 Insn: mov r0, r0 (nop)
4873 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4875 B<cond> similar, but don't set r14 in cleanup. */
4877 dsc
->u
.branch
.cond
= cond
;
4878 dsc
->u
.branch
.link
= link
;
4879 dsc
->u
.branch
.exchange
= exchange
;
4881 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4882 if (link
&& exchange
)
4883 /* For BLX, offset is computed from the Align (PC, 4). */
4884 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4887 dsc
->u
.branch
.dest
+= 4 + offset
;
4889 dsc
->u
.branch
.dest
+= 8 + offset
;
4891 dsc
->cleanup
= &cleanup_branch
;
4894 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4895 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4897 unsigned int cond
= bits (insn
, 28, 31);
4898 int exchange
= (cond
== 0xf);
4899 int link
= exchange
|| bit (insn
, 24);
4902 if (debug_displaced
)
4903 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4904 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4905 (unsigned long) insn
);
4907 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4908 then arrange the switch into Thumb mode. */
4909 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
4911 offset
= bits (insn
, 0, 23) << 2;
4913 if (bit (offset
, 25))
4914 offset
= offset
| ~0x3ffffff;
4916 dsc
->modinsn
[0] = ARM_NOP
;
4918 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
4923 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
4924 uint16_t insn2
, struct regcache
*regs
,
4925 arm_displaced_step_closure
*dsc
)
4927 int link
= bit (insn2
, 14);
4928 int exchange
= link
&& !bit (insn2
, 12);
4931 int j1
= bit (insn2
, 13);
4932 int j2
= bit (insn2
, 11);
4933 int s
= sbits (insn1
, 10, 10);
4934 int i1
= !(j1
^ bit (insn1
, 10));
4935 int i2
= !(j2
^ bit (insn1
, 10));
4937 if (!link
&& !exchange
) /* B */
4939 offset
= (bits (insn2
, 0, 10) << 1);
4940 if (bit (insn2
, 12)) /* Encoding T4 */
4942 offset
|= (bits (insn1
, 0, 9) << 12)
4948 else /* Encoding T3 */
4950 offset
|= (bits (insn1
, 0, 5) << 12)
4954 cond
= bits (insn1
, 6, 9);
4959 offset
= (bits (insn1
, 0, 9) << 12);
4960 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
4961 offset
|= exchange
?
4962 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
4965 if (debug_displaced
)
4966 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
4967 "%.4x %.4x with offset %.8lx\n",
4968 link
? (exchange
) ? "blx" : "bl" : "b",
4969 insn1
, insn2
, offset
);
4971 dsc
->modinsn
[0] = THUMB_NOP
;
4973 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
4977 /* Copy B Thumb instructions. */
4979 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
4980 arm_displaced_step_closure
*dsc
)
4982 unsigned int cond
= 0;
4984 unsigned short bit_12_15
= bits (insn
, 12, 15);
4985 CORE_ADDR from
= dsc
->insn_addr
;
4987 if (bit_12_15
== 0xd)
4989 /* offset = SignExtend (imm8:0, 32) */
4990 offset
= sbits ((insn
<< 1), 0, 8);
4991 cond
= bits (insn
, 8, 11);
4993 else if (bit_12_15
== 0xe) /* Encoding T2 */
4995 offset
= sbits ((insn
<< 1), 0, 11);
4999 if (debug_displaced
)
5000 fprintf_unfiltered (gdb_stdlog
,
5001 "displaced: copying b immediate insn %.4x "
5002 "with offset %d\n", insn
, offset
);
5004 dsc
->u
.branch
.cond
= cond
;
5005 dsc
->u
.branch
.link
= 0;
5006 dsc
->u
.branch
.exchange
= 0;
5007 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5009 dsc
->modinsn
[0] = THUMB_NOP
;
5011 dsc
->cleanup
= &cleanup_branch
;
5016 /* Copy BX/BLX with register-specified destinations. */
5019 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5020 arm_displaced_step_closure
*dsc
, int link
,
5021 unsigned int cond
, unsigned int rm
)
5023 /* Implement {BX,BLX}<cond> <reg>" as:
5025 Preparation: cond <- instruction condition
5026 Insn: mov r0, r0 (nop)
5027 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5029 Don't set r14 in cleanup for BX. */
5031 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5033 dsc
->u
.branch
.cond
= cond
;
5034 dsc
->u
.branch
.link
= link
;
5036 dsc
->u
.branch
.exchange
= 1;
5038 dsc
->cleanup
= &cleanup_branch
;
5042 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5043 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5045 unsigned int cond
= bits (insn
, 28, 31);
5048 int link
= bit (insn
, 5);
5049 unsigned int rm
= bits (insn
, 0, 3);
5051 if (debug_displaced
)
5052 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5053 (unsigned long) insn
);
5055 dsc
->modinsn
[0] = ARM_NOP
;
5057 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5062 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5063 struct regcache
*regs
,
5064 arm_displaced_step_closure
*dsc
)
5066 int link
= bit (insn
, 7);
5067 unsigned int rm
= bits (insn
, 3, 6);
5069 if (debug_displaced
)
5070 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5071 (unsigned short) insn
);
5073 dsc
->modinsn
[0] = THUMB_NOP
;
5075 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5081 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5084 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5085 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5087 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5088 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5089 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5090 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5094 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5095 arm_displaced_step_closure
*dsc
)
5097 unsigned int rn
= bits (insn
, 16, 19);
5098 unsigned int rd
= bits (insn
, 12, 15);
5099 unsigned int op
= bits (insn
, 21, 24);
5100 int is_mov
= (op
== 0xd);
5101 ULONGEST rd_val
, rn_val
;
5103 if (!insn_references_pc (insn
, 0x000ff000ul
))
5104 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5106 if (debug_displaced
)
5107 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5108 "%.8lx\n", is_mov
? "move" : "ALU",
5109 (unsigned long) insn
);
5111 /* Instruction is of form:
5113 <op><cond> rd, [rn,] #imm
5117 Preparation: tmp1, tmp2 <- r0, r1;
5119 Insn: <op><cond> r0, r1, #imm
5120 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5123 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5124 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5125 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5126 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5127 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5128 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5132 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5134 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5136 dsc
->cleanup
= &cleanup_alu_imm
;
5142 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5143 uint16_t insn2
, struct regcache
*regs
,
5144 arm_displaced_step_closure
*dsc
)
5146 unsigned int op
= bits (insn1
, 5, 8);
5147 unsigned int rn
, rm
, rd
;
5148 ULONGEST rd_val
, rn_val
;
5150 rn
= bits (insn1
, 0, 3); /* Rn */
5151 rm
= bits (insn2
, 0, 3); /* Rm */
5152 rd
= bits (insn2
, 8, 11); /* Rd */
5154 /* This routine is only called for instruction MOV. */
5155 gdb_assert (op
== 0x2 && rn
== 0xf);
5157 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5158 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5160 if (debug_displaced
)
5161 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5162 "ALU", insn1
, insn2
);
5164 /* Instruction is of form:
5166 <op><cond> rd, [rn,] #imm
5170 Preparation: tmp1, tmp2 <- r0, r1;
5172 Insn: <op><cond> r0, r1, #imm
5173 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5176 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5177 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5178 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5179 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5180 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5181 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5184 dsc
->modinsn
[0] = insn1
;
5185 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5188 dsc
->cleanup
= &cleanup_alu_imm
;
5193 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5196 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5197 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5202 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5204 for (i
= 0; i
< 3; i
++)
5205 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5207 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5211 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5212 arm_displaced_step_closure
*dsc
,
5213 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5215 ULONGEST rd_val
, rn_val
, rm_val
;
5217 /* Instruction is of form:
5219 <op><cond> rd, [rn,] rm [, <shift>]
5223 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5224 r0, r1, r2 <- rd, rn, rm
5225 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5226 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5229 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5230 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5231 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5232 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5233 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5234 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5235 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5236 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5237 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5240 dsc
->cleanup
= &cleanup_alu_reg
;
5244 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5245 arm_displaced_step_closure
*dsc
)
5247 unsigned int op
= bits (insn
, 21, 24);
5248 int is_mov
= (op
== 0xd);
5250 if (!insn_references_pc (insn
, 0x000ff00ful
))
5251 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5253 if (debug_displaced
)
5254 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5255 is_mov
? "move" : "ALU", (unsigned long) insn
);
5258 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5260 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5262 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5268 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5269 struct regcache
*regs
,
5270 arm_displaced_step_closure
*dsc
)
5274 rm
= bits (insn
, 3, 6);
5275 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5277 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5278 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5280 if (debug_displaced
)
5281 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5282 (unsigned short) insn
);
5284 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5286 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5291 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5294 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5295 struct regcache
*regs
,
5296 arm_displaced_step_closure
*dsc
)
5298 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5301 for (i
= 0; i
< 4; i
++)
5302 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5304 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5308 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5309 arm_displaced_step_closure
*dsc
,
5310 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5314 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5316 /* Instruction is of form:
5318 <op><cond> rd, [rn,] rm, <shift> rs
5322 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5323 r0, r1, r2, r3 <- rd, rn, rm, rs
5324 Insn: <op><cond> r0, r1, r2, <shift> r3
5326 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5330 for (i
= 0; i
< 4; i
++)
5331 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5333 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5334 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5335 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5336 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5337 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5338 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5339 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5340 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5342 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5346 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5347 struct regcache
*regs
,
5348 arm_displaced_step_closure
*dsc
)
5350 unsigned int op
= bits (insn
, 21, 24);
5351 int is_mov
= (op
== 0xd);
5352 unsigned int rd
, rn
, rm
, rs
;
5354 if (!insn_references_pc (insn
, 0x000fff0ful
))
5355 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5357 if (debug_displaced
)
5358 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5359 "%.8lx\n", is_mov
? "move" : "ALU",
5360 (unsigned long) insn
);
5362 rn
= bits (insn
, 16, 19);
5363 rm
= bits (insn
, 0, 3);
5364 rs
= bits (insn
, 8, 11);
5365 rd
= bits (insn
, 12, 15);
5368 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5370 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5372 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5377 /* Clean up load instructions. */
5380 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5381 arm_displaced_step_closure
*dsc
)
5383 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5385 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5386 if (dsc
->u
.ldst
.xfersize
== 8)
5387 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5388 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5390 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5391 if (dsc
->u
.ldst
.xfersize
> 4)
5392 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5393 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5394 if (!dsc
->u
.ldst
.immed
)
5395 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5397 /* Handle register writeback. */
5398 if (dsc
->u
.ldst
.writeback
)
5399 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5400 /* Put result in right place. */
5401 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5402 if (dsc
->u
.ldst
.xfersize
== 8)
5403 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5406 /* Clean up store instructions. */
5409 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5410 arm_displaced_step_closure
*dsc
)
5412 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5414 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5415 if (dsc
->u
.ldst
.xfersize
> 4)
5416 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5417 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5418 if (!dsc
->u
.ldst
.immed
)
5419 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5420 if (!dsc
->u
.ldst
.restore_r4
)
5421 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5424 if (dsc
->u
.ldst
.writeback
)
5425 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5428 /* Copy "extra" load/store instructions. These are halfword/doubleword
5429 transfers, which have a different encoding to byte/word transfers. */
5432 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5433 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5435 unsigned int op1
= bits (insn
, 20, 24);
5436 unsigned int op2
= bits (insn
, 5, 6);
5437 unsigned int rt
= bits (insn
, 12, 15);
5438 unsigned int rn
= bits (insn
, 16, 19);
5439 unsigned int rm
= bits (insn
, 0, 3);
5440 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5441 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5442 int immed
= (op1
& 0x4) != 0;
5444 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5446 if (!insn_references_pc (insn
, 0x000ff00ful
))
5447 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5449 if (debug_displaced
)
5450 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5451 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5452 (unsigned long) insn
);
5454 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5457 internal_error (__FILE__
, __LINE__
,
5458 _("copy_extra_ld_st: instruction decode error"));
5460 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5461 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5462 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5464 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5466 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5467 if (bytesize
[opcode
] == 8)
5468 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5469 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5471 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5473 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5474 if (bytesize
[opcode
] == 8)
5475 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5476 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5478 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5481 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5482 dsc
->u
.ldst
.rn
= rn
;
5483 dsc
->u
.ldst
.immed
= immed
;
5484 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5485 dsc
->u
.ldst
.restore_r4
= 0;
5488 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5490 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5491 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5493 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5495 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5496 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5498 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5503 /* Copy byte/half word/word loads and stores. */
5506 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5507 arm_displaced_step_closure
*dsc
, int load
,
5508 int immed
, int writeback
, int size
, int usermode
,
5509 int rt
, int rm
, int rn
)
5511 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5513 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5514 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5516 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5518 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5520 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5521 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5523 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5525 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5526 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5528 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5530 dsc
->u
.ldst
.xfersize
= size
;
5531 dsc
->u
.ldst
.rn
= rn
;
5532 dsc
->u
.ldst
.immed
= immed
;
5533 dsc
->u
.ldst
.writeback
= writeback
;
5535 /* To write PC we can do:
5537 Before this sequence of instructions:
5538 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5539 r2 is the Rn value got from dispalced_read_reg.
5541 Insn1: push {pc} Write address of STR instruction + offset on stack
5542 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5543 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5544 = addr(Insn1) + offset - addr(Insn3) - 8
5546 Insn4: add r4, r4, #8 r4 = offset - 8
5547 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5549 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5551 Otherwise we don't know what value to write for PC, since the offset is
5552 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5553 of this can be found in Section "Saving from r15" in
5554 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5556 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5561 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5562 uint16_t insn2
, struct regcache
*regs
,
5563 arm_displaced_step_closure
*dsc
, int size
)
5565 unsigned int u_bit
= bit (insn1
, 7);
5566 unsigned int rt
= bits (insn2
, 12, 15);
5567 int imm12
= bits (insn2
, 0, 11);
5570 if (debug_displaced
)
5571 fprintf_unfiltered (gdb_stdlog
,
5572 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5573 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5579 /* Rewrite instruction LDR Rt imm12 into:
5581 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5585 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5588 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5589 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5590 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5592 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5594 pc_val
= pc_val
& 0xfffffffc;
5596 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5597 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5601 dsc
->u
.ldst
.xfersize
= size
;
5602 dsc
->u
.ldst
.immed
= 0;
5603 dsc
->u
.ldst
.writeback
= 0;
5604 dsc
->u
.ldst
.restore_r4
= 0;
5606 /* LDR R0, R2, R3 */
5607 dsc
->modinsn
[0] = 0xf852;
5608 dsc
->modinsn
[1] = 0x3;
5611 dsc
->cleanup
= &cleanup_load
;
5617 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5618 uint16_t insn2
, struct regcache
*regs
,
5619 arm_displaced_step_closure
*dsc
,
5620 int writeback
, int immed
)
5622 unsigned int rt
= bits (insn2
, 12, 15);
5623 unsigned int rn
= bits (insn1
, 0, 3);
5624 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5625 /* In LDR (register), there is also a register Rm, which is not allowed to
5626 be PC, so we don't have to check it. */
5628 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5629 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5632 if (debug_displaced
)
5633 fprintf_unfiltered (gdb_stdlog
,
5634 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5635 rt
, rn
, insn1
, insn2
);
5637 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5640 dsc
->u
.ldst
.restore_r4
= 0;
5643 /* ldr[b]<cond> rt, [rn, #imm], etc.
5645 ldr[b]<cond> r0, [r2, #imm]. */
5647 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5648 dsc
->modinsn
[1] = insn2
& 0x0fff;
5651 /* ldr[b]<cond> rt, [rn, rm], etc.
5653 ldr[b]<cond> r0, [r2, r3]. */
5655 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5656 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5666 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5667 struct regcache
*regs
,
5668 arm_displaced_step_closure
*dsc
,
5669 int load
, int size
, int usermode
)
5671 int immed
= !bit (insn
, 25);
5672 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5673 unsigned int rt
= bits (insn
, 12, 15);
5674 unsigned int rn
= bits (insn
, 16, 19);
5675 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5677 if (!insn_references_pc (insn
, 0x000ff00ful
))
5678 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5680 if (debug_displaced
)
5681 fprintf_unfiltered (gdb_stdlog
,
5682 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5683 load
? (size
== 1 ? "ldrb" : "ldr")
5684 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5686 (unsigned long) insn
);
5688 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5689 usermode
, rt
, rm
, rn
);
5691 if (load
|| rt
!= ARM_PC_REGNUM
)
5693 dsc
->u
.ldst
.restore_r4
= 0;
5696 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5698 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5699 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5701 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5703 {ldr,str}[b]<cond> r0, [r2, r3]. */
5704 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5708 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5709 dsc
->u
.ldst
.restore_r4
= 1;
5710 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5711 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5712 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5713 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5714 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5718 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5720 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5725 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5730 /* Cleanup LDM instructions with fully-populated register list. This is an
5731 unfortunate corner case: it's impossible to implement correctly by modifying
5732 the instruction. The issue is as follows: we have an instruction,
5736 which we must rewrite to avoid loading PC. A possible solution would be to
5737 do the load in two halves, something like (with suitable cleanup
5741 ldm[id][ab] r8!, {r0-r7}
5743 ldm[id][ab] r8, {r7-r14}
5746 but at present there's no suitable place for <temp>, since the scratch space
5747 is overwritten before the cleanup routine is called. For now, we simply
5748 emulate the instruction. */
5751 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5752 arm_displaced_step_closure
*dsc
)
5754 int inc
= dsc
->u
.block
.increment
;
5755 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5756 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5757 uint32_t regmask
= dsc
->u
.block
.regmask
;
5758 int regno
= inc
? 0 : 15;
5759 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5760 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5761 && (regmask
& 0x8000) != 0;
5762 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5763 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5764 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5769 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5770 sensible we can do here. Complain loudly. */
5771 if (exception_return
)
5772 error (_("Cannot single-step exception return"));
5774 /* We don't handle any stores here for now. */
5775 gdb_assert (dsc
->u
.block
.load
!= 0);
5777 if (debug_displaced
)
5778 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5779 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5780 dsc
->u
.block
.increment
? "inc" : "dec",
5781 dsc
->u
.block
.before
? "before" : "after");
5788 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5791 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5794 xfer_addr
+= bump_before
;
5796 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5797 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5799 xfer_addr
+= bump_after
;
5801 regmask
&= ~(1 << regno
);
5804 if (dsc
->u
.block
.writeback
)
5805 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5809 /* Clean up an STM which included the PC in the register list. */
5812 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5813 arm_displaced_step_closure
*dsc
)
5815 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5816 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5817 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5818 CORE_ADDR stm_insn_addr
;
5821 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5823 /* If condition code fails, there's nothing else to do. */
5824 if (!store_executed
)
5827 if (dsc
->u
.block
.increment
)
5829 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5831 if (dsc
->u
.block
.before
)
5836 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5838 if (dsc
->u
.block
.before
)
5842 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5843 stm_insn_addr
= dsc
->scratch_base
;
5844 offset
= pc_val
- stm_insn_addr
;
5846 if (debug_displaced
)
5847 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5848 "STM instruction\n", offset
);
5850 /* Rewrite the stored PC to the proper value for the non-displaced original
5852 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5853 dsc
->insn_addr
+ offset
);
5856 /* Clean up an LDM which includes the PC in the register list. We clumped all
5857 the registers in the transferred list into a contiguous range r0...rX (to
5858 avoid loading PC directly and losing control of the debugged program), so we
5859 must undo that here. */
5862 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5863 struct regcache
*regs
,
5864 arm_displaced_step_closure
*dsc
)
5866 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5867 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5868 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5869 unsigned int regs_loaded
= bitcount (mask
);
5870 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5872 /* The method employed here will fail if the register list is fully populated
5873 (we need to avoid loading PC directly). */
5874 gdb_assert (num_to_shuffle
< 16);
5879 clobbered
= (1 << num_to_shuffle
) - 1;
5881 while (num_to_shuffle
> 0)
5883 if ((mask
& (1 << write_reg
)) != 0)
5885 unsigned int read_reg
= num_to_shuffle
- 1;
5887 if (read_reg
!= write_reg
)
5889 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5890 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5891 if (debug_displaced
)
5892 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5893 "loaded register r%d to r%d\n"), read_reg
,
5896 else if (debug_displaced
)
5897 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5898 "r%d already in the right place\n"),
5901 clobbered
&= ~(1 << write_reg
);
5909 /* Restore any registers we scribbled over. */
5910 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
5912 if ((clobbered
& (1 << write_reg
)) != 0)
5914 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
5916 if (debug_displaced
)
5917 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
5918 "clobbered register r%d\n"), write_reg
);
5919 clobbered
&= ~(1 << write_reg
);
5923 /* Perform register writeback manually. */
5924 if (dsc
->u
.block
.writeback
)
5926 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
5928 if (dsc
->u
.block
.increment
)
5929 new_rn_val
+= regs_loaded
* 4;
5931 new_rn_val
-= regs_loaded
* 4;
5933 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
5938 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
5939 in user-level code (in particular exception return, ldm rn, {...pc}^). */
5942 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
5943 struct regcache
*regs
,
5944 arm_displaced_step_closure
*dsc
)
5946 int load
= bit (insn
, 20);
5947 int user
= bit (insn
, 22);
5948 int increment
= bit (insn
, 23);
5949 int before
= bit (insn
, 24);
5950 int writeback
= bit (insn
, 21);
5951 int rn
= bits (insn
, 16, 19);
5953 /* Block transfers which don't mention PC can be run directly
5955 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
5956 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
5958 if (rn
== ARM_PC_REGNUM
)
5960 warning (_("displaced: Unpredictable LDM or STM with "
5961 "base register r15"));
5962 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
5965 if (debug_displaced
)
5966 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
5967 "%.8lx\n", (unsigned long) insn
);
5969 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
5970 dsc
->u
.block
.rn
= rn
;
5972 dsc
->u
.block
.load
= load
;
5973 dsc
->u
.block
.user
= user
;
5974 dsc
->u
.block
.increment
= increment
;
5975 dsc
->u
.block
.before
= before
;
5976 dsc
->u
.block
.writeback
= writeback
;
5977 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
5979 dsc
->u
.block
.regmask
= insn
& 0xffff;
5983 if ((insn
& 0xffff) == 0xffff)
5985 /* LDM with a fully-populated register list. This case is
5986 particularly tricky. Implement for now by fully emulating the
5987 instruction (which might not behave perfectly in all cases, but
5988 these instructions should be rare enough for that not to matter
5990 dsc
->modinsn
[0] = ARM_NOP
;
5992 dsc
->cleanup
= &cleanup_block_load_all
;
5996 /* LDM of a list of registers which includes PC. Implement by
5997 rewriting the list of registers to be transferred into a
5998 contiguous chunk r0...rX before doing the transfer, then shuffling
5999 registers into the correct places in the cleanup routine. */
6000 unsigned int regmask
= insn
& 0xffff;
6001 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6004 for (i
= 0; i
< num_in_list
; i
++)
6005 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6007 /* Writeback makes things complicated. We need to avoid clobbering
6008 the base register with one of the registers in our modified
6009 register list, but just using a different register can't work in
6012 ldm r14!, {r0-r13,pc}
6014 which would need to be rewritten as:
6018 but that can't work, because there's no free register for N.
6020 Solve this by turning off the writeback bit, and emulating
6021 writeback manually in the cleanup routine. */
6026 new_regmask
= (1 << num_in_list
) - 1;
6028 if (debug_displaced
)
6029 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6030 "{..., pc}: original reg list %.4x, modified "
6031 "list %.4x\n"), rn
, writeback
? "!" : "",
6032 (int) insn
& 0xffff, new_regmask
);
6034 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6036 dsc
->cleanup
= &cleanup_block_load_pc
;
6041 /* STM of a list of registers which includes PC. Run the instruction
6042 as-is, but out of line: this will store the wrong value for the PC,
6043 so we must manually fix up the memory in the cleanup routine.
6044 Doing things this way has the advantage that we can auto-detect
6045 the offset of the PC write (which is architecture-dependent) in
6046 the cleanup routine. */
6047 dsc
->modinsn
[0] = insn
;
6049 dsc
->cleanup
= &cleanup_block_store_pc
;
6056 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6057 struct regcache
*regs
,
6058 arm_displaced_step_closure
*dsc
)
6060 int rn
= bits (insn1
, 0, 3);
6061 int load
= bit (insn1
, 4);
6062 int writeback
= bit (insn1
, 5);
6064 /* Block transfers which don't mention PC can be run directly
6066 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6067 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6069 if (rn
== ARM_PC_REGNUM
)
6071 warning (_("displaced: Unpredictable LDM or STM with "
6072 "base register r15"));
6073 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6074 "unpredictable ldm/stm", dsc
);
6077 if (debug_displaced
)
6078 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6079 "%.4x%.4x\n", insn1
, insn2
);
6081 /* Clear bit 13, since it should be always zero. */
6082 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6083 dsc
->u
.block
.rn
= rn
;
6085 dsc
->u
.block
.load
= load
;
6086 dsc
->u
.block
.user
= 0;
6087 dsc
->u
.block
.increment
= bit (insn1
, 7);
6088 dsc
->u
.block
.before
= bit (insn1
, 8);
6089 dsc
->u
.block
.writeback
= writeback
;
6090 dsc
->u
.block
.cond
= INST_AL
;
6091 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6095 if (dsc
->u
.block
.regmask
== 0xffff)
6097 /* This branch is impossible to happen. */
6102 unsigned int regmask
= dsc
->u
.block
.regmask
;
6103 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6106 for (i
= 0; i
< num_in_list
; i
++)
6107 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6112 new_regmask
= (1 << num_in_list
) - 1;
6114 if (debug_displaced
)
6115 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6116 "{..., pc}: original reg list %.4x, modified "
6117 "list %.4x\n"), rn
, writeback
? "!" : "",
6118 (int) dsc
->u
.block
.regmask
, new_regmask
);
6120 dsc
->modinsn
[0] = insn1
;
6121 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6124 dsc
->cleanup
= &cleanup_block_load_pc
;
6129 dsc
->modinsn
[0] = insn1
;
6130 dsc
->modinsn
[1] = insn2
;
6132 dsc
->cleanup
= &cleanup_block_store_pc
;
6137 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6138 This is used to avoid a dependency on BFD's bfd_endian enum. */
6141 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6144 return read_memory_unsigned_integer (memaddr
, len
,
6145 (enum bfd_endian
) byte_order
);
6148 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6151 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6154 return gdbarch_addr_bits_remove (self
->regcache
->arch (), val
);
6157 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6160 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6165 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6168 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6170 return arm_is_thumb (self
->regcache
);
6173 /* single_step() is called just before we want to resume the inferior,
6174 if we want to single-step it but there is no hardware or kernel
6175 single-step support. We find the target of the coming instructions
6176 and breakpoint them. */
6178 std::vector
<CORE_ADDR
>
6179 arm_software_single_step (struct regcache
*regcache
)
6181 struct gdbarch
*gdbarch
= regcache
->arch ();
6182 struct arm_get_next_pcs next_pcs_ctx
;
6184 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6185 &arm_get_next_pcs_ops
,
6186 gdbarch_byte_order (gdbarch
),
6187 gdbarch_byte_order_for_code (gdbarch
),
6191 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6193 for (CORE_ADDR
&pc_ref
: next_pcs
)
6194 pc_ref
= gdbarch_addr_bits_remove (gdbarch
, pc_ref
);
6199 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6200 for Linux, where some SVC instructions must be treated specially. */
6203 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6204 arm_displaced_step_closure
*dsc
)
6206 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6208 if (debug_displaced
)
6209 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6210 "%.8lx\n", (unsigned long) resume_addr
);
6212 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6216 /* Common copy routine for svc instruciton. */
6219 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6220 arm_displaced_step_closure
*dsc
)
6222 /* Preparation: none.
6223 Insn: unmodified svc.
6224 Cleanup: pc <- insn_addr + insn_size. */
6226 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6228 dsc
->wrote_to_pc
= 1;
6230 /* Allow OS-specific code to override SVC handling. */
6231 if (dsc
->u
.svc
.copy_svc_os
)
6232 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6235 dsc
->cleanup
= &cleanup_svc
;
6241 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6242 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6245 if (debug_displaced
)
6246 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6247 (unsigned long) insn
);
6249 dsc
->modinsn
[0] = insn
;
6251 return install_svc (gdbarch
, regs
, dsc
);
6255 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6256 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6259 if (debug_displaced
)
6260 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6263 dsc
->modinsn
[0] = insn
;
6265 return install_svc (gdbarch
, regs
, dsc
);
6268 /* Copy undefined instructions. */
6271 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6272 arm_displaced_step_closure
*dsc
)
6274 if (debug_displaced
)
6275 fprintf_unfiltered (gdb_stdlog
,
6276 "displaced: copying undefined insn %.8lx\n",
6277 (unsigned long) insn
);
6279 dsc
->modinsn
[0] = insn
;
6285 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6286 arm_displaced_step_closure
*dsc
)
6289 if (debug_displaced
)
6290 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6291 "%.4x %.4x\n", (unsigned short) insn1
,
6292 (unsigned short) insn2
);
6294 dsc
->modinsn
[0] = insn1
;
6295 dsc
->modinsn
[1] = insn2
;
6301 /* Copy unpredictable instructions. */
6304 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6305 arm_displaced_step_closure
*dsc
)
6307 if (debug_displaced
)
6308 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6309 "%.8lx\n", (unsigned long) insn
);
6311 dsc
->modinsn
[0] = insn
;
6316 /* The decode_* functions are instruction decoding helpers. They mostly follow
6317 the presentation in the ARM ARM. */
6320 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6321 struct regcache
*regs
,
6322 arm_displaced_step_closure
*dsc
)
6324 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6325 unsigned int rn
= bits (insn
, 16, 19);
6327 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0x1) == 0x0)
6328 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6329 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0x1) == 0x1)
6330 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6331 else if ((op1
& 0x60) == 0x20)
6332 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6333 else if ((op1
& 0x71) == 0x40)
6334 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6336 else if ((op1
& 0x77) == 0x41)
6337 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6338 else if ((op1
& 0x77) == 0x45)
6339 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6340 else if ((op1
& 0x77) == 0x51)
6343 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6345 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6347 else if ((op1
& 0x77) == 0x55)
6348 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6349 else if (op1
== 0x57)
6352 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6353 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6354 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6355 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6356 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6358 else if ((op1
& 0x63) == 0x43)
6359 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6360 else if ((op2
& 0x1) == 0x0)
6361 switch (op1
& ~0x80)
6364 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6366 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6367 case 0x71: case 0x75:
6369 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6370 case 0x63: case 0x67: case 0x73: case 0x77:
6371 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6373 return arm_copy_undef (gdbarch
, insn
, dsc
);
6376 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6380 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6381 struct regcache
*regs
,
6382 arm_displaced_step_closure
*dsc
)
6384 if (bit (insn
, 27) == 0)
6385 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6386 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6387 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6390 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6393 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6395 case 0x4: case 0x5: case 0x6: case 0x7:
6396 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6399 switch ((insn
& 0xe00000) >> 21)
6401 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6403 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6406 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6409 return arm_copy_undef (gdbarch
, insn
, dsc
);
6414 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6415 switch ((insn
& 0xe00000) >> 21)
6418 /* ldc/ldc2 imm (undefined for rn == pc). */
6419 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6420 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6423 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6425 case 0x4: case 0x5: case 0x6: case 0x7:
6426 /* ldc/ldc2 lit (undefined for rn != pc). */
6427 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6428 : arm_copy_undef (gdbarch
, insn
, dsc
);
6431 return arm_copy_undef (gdbarch
, insn
, dsc
);
6436 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6439 if (bits (insn
, 16, 19) == 0xf)
6441 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6443 return arm_copy_undef (gdbarch
, insn
, dsc
);
6447 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6449 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6453 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6455 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6458 return arm_copy_undef (gdbarch
, insn
, dsc
);
6462 /* Decode miscellaneous instructions in dp/misc encoding space. */
6465 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6466 struct regcache
*regs
,
6467 arm_displaced_step_closure
*dsc
)
6469 unsigned int op2
= bits (insn
, 4, 6);
6470 unsigned int op
= bits (insn
, 21, 22);
6475 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6478 if (op
== 0x1) /* bx. */
6479 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6481 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6483 return arm_copy_undef (gdbarch
, insn
, dsc
);
6487 /* Not really supported. */
6488 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6490 return arm_copy_undef (gdbarch
, insn
, dsc
);
6494 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6495 regs
, dsc
); /* blx register. */
6497 return arm_copy_undef (gdbarch
, insn
, dsc
);
6500 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6504 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6506 /* Not really supported. */
6507 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6511 return arm_copy_undef (gdbarch
, insn
, dsc
);
6516 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6517 struct regcache
*regs
,
6518 arm_displaced_step_closure
*dsc
)
6521 switch (bits (insn
, 20, 24))
6524 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6527 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6529 case 0x12: case 0x16:
6530 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6533 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6537 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6539 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6540 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6541 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6542 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6543 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6544 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6545 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6546 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6547 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6548 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6549 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6550 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6551 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6552 /* 2nd arg means "unprivileged". */
6553 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6557 /* Should be unreachable. */
6562 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6563 struct regcache
*regs
,
6564 arm_displaced_step_closure
*dsc
)
6566 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6567 uint32_t op1
= bits (insn
, 20, 24);
6569 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6570 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6571 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6572 else if ((!a
&& (op1
& 0x17) == 0x02)
6573 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6574 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6575 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6576 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6577 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6578 else if ((!a
&& (op1
& 0x17) == 0x03)
6579 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6580 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6581 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6582 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6583 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6584 else if ((!a
&& (op1
& 0x17) == 0x06)
6585 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6586 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6587 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6588 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6589 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6590 else if ((!a
&& (op1
& 0x17) == 0x07)
6591 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6592 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6594 /* Should be unreachable. */
6599 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6600 arm_displaced_step_closure
*dsc
)
6602 switch (bits (insn
, 20, 24))
6604 case 0x00: case 0x01: case 0x02: case 0x03:
6605 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6607 case 0x04: case 0x05: case 0x06: case 0x07:
6608 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6610 case 0x08: case 0x09: case 0x0a: case 0x0b:
6611 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6612 return arm_copy_unmodified (gdbarch
, insn
,
6613 "decode/pack/unpack/saturate/reverse", dsc
);
6616 if (bits (insn
, 5, 7) == 0) /* op2. */
6618 if (bits (insn
, 12, 15) == 0xf)
6619 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6621 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6624 return arm_copy_undef (gdbarch
, insn
, dsc
);
6626 case 0x1a: case 0x1b:
6627 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6628 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6630 return arm_copy_undef (gdbarch
, insn
, dsc
);
6632 case 0x1c: case 0x1d:
6633 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6635 if (bits (insn
, 0, 3) == 0xf)
6636 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6638 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6641 return arm_copy_undef (gdbarch
, insn
, dsc
);
6643 case 0x1e: case 0x1f:
6644 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6645 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6647 return arm_copy_undef (gdbarch
, insn
, dsc
);
6650 /* Should be unreachable. */
6655 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6656 struct regcache
*regs
,
6657 arm_displaced_step_closure
*dsc
)
6660 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6662 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6666 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6667 struct regcache
*regs
,
6668 arm_displaced_step_closure
*dsc
)
6670 unsigned int opcode
= bits (insn
, 20, 24);
6674 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6675 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6677 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6678 case 0x12: case 0x16:
6679 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6681 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6682 case 0x13: case 0x17:
6683 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6685 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6686 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6687 /* Note: no writeback for these instructions. Bit 25 will always be
6688 zero though (via caller), so the following works OK. */
6689 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6692 /* Should be unreachable. */
6696 /* Decode shifted register instructions. */
6699 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6700 uint16_t insn2
, struct regcache
*regs
,
6701 arm_displaced_step_closure
*dsc
)
6703 /* PC is only allowed to be used in instruction MOV. */
6705 unsigned int op
= bits (insn1
, 5, 8);
6706 unsigned int rn
= bits (insn1
, 0, 3);
6708 if (op
== 0x2 && rn
== 0xf) /* MOV */
6709 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6711 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6712 "dp (shift reg)", dsc
);
6716 /* Decode extension register load/store. Exactly the same as
6717 arm_decode_ext_reg_ld_st. */
6720 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6721 uint16_t insn2
, struct regcache
*regs
,
6722 arm_displaced_step_closure
*dsc
)
6724 unsigned int opcode
= bits (insn1
, 4, 8);
6728 case 0x04: case 0x05:
6729 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6730 "vfp/neon vmov", dsc
);
6732 case 0x08: case 0x0c: /* 01x00 */
6733 case 0x0a: case 0x0e: /* 01x10 */
6734 case 0x12: case 0x16: /* 10x10 */
6735 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6736 "vfp/neon vstm/vpush", dsc
);
6738 case 0x09: case 0x0d: /* 01x01 */
6739 case 0x0b: case 0x0f: /* 01x11 */
6740 case 0x13: case 0x17: /* 10x11 */
6741 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6742 "vfp/neon vldm/vpop", dsc
);
6744 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6745 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6747 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6748 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6751 /* Should be unreachable. */
6756 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6757 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6759 unsigned int op1
= bits (insn
, 20, 25);
6760 int op
= bit (insn
, 4);
6761 unsigned int coproc
= bits (insn
, 8, 11);
6763 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6764 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6765 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6766 && (coproc
& 0xe) != 0xa)
6768 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6769 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6770 && (coproc
& 0xe) != 0xa)
6771 /* ldc/ldc2 imm/lit. */
6772 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6773 else if ((op1
& 0x3e) == 0x00)
6774 return arm_copy_undef (gdbarch
, insn
, dsc
);
6775 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6776 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6777 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6778 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6779 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6780 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6781 else if ((op1
& 0x30) == 0x20 && !op
)
6783 if ((coproc
& 0xe) == 0xa)
6784 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6786 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6788 else if ((op1
& 0x30) == 0x20 && op
)
6789 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6790 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6791 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6792 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6793 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6794 else if ((op1
& 0x30) == 0x30)
6795 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6797 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6801 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6802 uint16_t insn2
, struct regcache
*regs
,
6803 arm_displaced_step_closure
*dsc
)
6805 unsigned int coproc
= bits (insn2
, 8, 11);
6806 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6807 unsigned int bit_9
= bit (insn1
, 9);
6808 unsigned int bit_4
= bit (insn1
, 4);
6813 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6814 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6816 else if (bit_5_8
== 0) /* UNDEFINED. */
6817 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6820 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6821 if ((coproc
& 0xe) == 0xa)
6822 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6824 else /* coproc is not 101x. */
6826 if (bit_4
== 0) /* STC/STC2. */
6827 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6829 else /* LDC/LDC2 {literal, immeidate}. */
6830 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6836 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6842 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6843 arm_displaced_step_closure
*dsc
, int rd
)
6849 Preparation: Rd <- PC
6855 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6856 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6860 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6861 arm_displaced_step_closure
*dsc
,
6862 int rd
, unsigned int imm
)
6865 /* Encoding T2: ADDS Rd, #imm */
6866 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6868 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6874 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6875 struct regcache
*regs
,
6876 arm_displaced_step_closure
*dsc
)
6878 unsigned int rd
= bits (insn
, 8, 10);
6879 unsigned int imm8
= bits (insn
, 0, 7);
6881 if (debug_displaced
)
6882 fprintf_unfiltered (gdb_stdlog
,
6883 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6886 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6890 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6891 uint16_t insn2
, struct regcache
*regs
,
6892 arm_displaced_step_closure
*dsc
)
6894 unsigned int rd
= bits (insn2
, 8, 11);
6895 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6896 extract raw immediate encoding rather than computing immediate. When
6897 generating ADD or SUB instruction, we can simply perform OR operation to
6898 set immediate into ADD. */
6899 unsigned int imm_3_8
= insn2
& 0x70ff;
6900 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
6902 if (debug_displaced
)
6903 fprintf_unfiltered (gdb_stdlog
,
6904 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
6905 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
6907 if (bit (insn1
, 7)) /* Encoding T2 */
6909 /* Encoding T3: SUB Rd, Rd, #imm */
6910 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
6911 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6913 else /* Encoding T3 */
6915 /* Encoding T3: ADD Rd, Rd, #imm */
6916 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
6917 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6921 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6927 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6928 struct regcache
*regs
,
6929 arm_displaced_step_closure
*dsc
)
6931 unsigned int rt
= bits (insn1
, 8, 10);
6933 int imm8
= (bits (insn1
, 0, 7) << 2);
6939 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
6941 Insn: LDR R0, [R2, R3];
6942 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
6944 if (debug_displaced
)
6945 fprintf_unfiltered (gdb_stdlog
,
6946 "displaced: copying thumb ldr r%d [pc #%d]\n"
6949 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6950 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6951 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6952 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6953 /* The assembler calculates the required value of the offset from the
6954 Align(PC,4) value of this instruction to the label. */
6955 pc
= pc
& 0xfffffffc;
6957 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
6958 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
6961 dsc
->u
.ldst
.xfersize
= 4;
6963 dsc
->u
.ldst
.immed
= 0;
6964 dsc
->u
.ldst
.writeback
= 0;
6965 dsc
->u
.ldst
.restore_r4
= 0;
6967 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
6969 dsc
->cleanup
= &cleanup_load
;
6974 /* Copy Thumb cbnz/cbz insruction. */
6977 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
6978 struct regcache
*regs
,
6979 arm_displaced_step_closure
*dsc
)
6981 int non_zero
= bit (insn1
, 11);
6982 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
6983 CORE_ADDR from
= dsc
->insn_addr
;
6984 int rn
= bits (insn1
, 0, 2);
6985 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6987 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
6988 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
6989 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
6990 condition is false, let it be, cleanup_branch will do nothing. */
6991 if (dsc
->u
.branch
.cond
)
6993 dsc
->u
.branch
.cond
= INST_AL
;
6994 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
6997 dsc
->u
.branch
.dest
= from
+ 2;
6999 dsc
->u
.branch
.link
= 0;
7000 dsc
->u
.branch
.exchange
= 0;
7002 if (debug_displaced
)
7003 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7004 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7005 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7007 dsc
->modinsn
[0] = THUMB_NOP
;
7009 dsc
->cleanup
= &cleanup_branch
;
7013 /* Copy Table Branch Byte/Halfword */
7015 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7016 uint16_t insn2
, struct regcache
*regs
,
7017 arm_displaced_step_closure
*dsc
)
7019 ULONGEST rn_val
, rm_val
;
7020 int is_tbh
= bit (insn2
, 4);
7021 CORE_ADDR halfwords
= 0;
7022 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7024 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7025 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7031 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7032 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7038 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7039 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7042 if (debug_displaced
)
7043 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7044 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7045 (unsigned int) rn_val
, (unsigned int) rm_val
,
7046 (unsigned int) halfwords
);
7048 dsc
->u
.branch
.cond
= INST_AL
;
7049 dsc
->u
.branch
.link
= 0;
7050 dsc
->u
.branch
.exchange
= 0;
7051 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7053 dsc
->cleanup
= &cleanup_branch
;
7059 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7060 arm_displaced_step_closure
*dsc
)
7063 int val
= displaced_read_reg (regs
, dsc
, 7);
7064 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7067 val
= displaced_read_reg (regs
, dsc
, 8);
7068 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7071 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7076 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7077 struct regcache
*regs
,
7078 arm_displaced_step_closure
*dsc
)
7080 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7082 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7085 (1) register list is full, that is, r0-r7 are used.
7086 Prepare: tmp[0] <- r8
7088 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7089 MOV r8, r7; Move value of r7 to r8;
7090 POP {r7}; Store PC value into r7.
7092 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7094 (2) register list is not full, supposing there are N registers in
7095 register list (except PC, 0 <= N <= 7).
7096 Prepare: for each i, 0 - N, tmp[i] <- ri.
7098 POP {r0, r1, ...., rN};
7100 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7101 from tmp[] properly.
7103 if (debug_displaced
)
7104 fprintf_unfiltered (gdb_stdlog
,
7105 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7106 dsc
->u
.block
.regmask
, insn1
);
7108 if (dsc
->u
.block
.regmask
== 0xff)
7110 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7112 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7113 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7114 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7117 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7121 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7123 unsigned int new_regmask
;
7125 for (i
= 0; i
< num_in_list
+ 1; i
++)
7126 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7128 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7130 if (debug_displaced
)
7131 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7132 "{..., pc}: original reg list %.4x,"
7133 " modified list %.4x\n"),
7134 (int) dsc
->u
.block
.regmask
, new_regmask
);
7136 dsc
->u
.block
.regmask
|= 0x8000;
7137 dsc
->u
.block
.writeback
= 0;
7138 dsc
->u
.block
.cond
= INST_AL
;
7140 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7142 dsc
->cleanup
= &cleanup_block_load_pc
;
7149 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7150 struct regcache
*regs
,
7151 arm_displaced_step_closure
*dsc
)
7153 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7154 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7157 /* 16-bit thumb instructions. */
7158 switch (op_bit_12_15
)
7160 /* Shift (imme), add, subtract, move and compare. */
7161 case 0: case 1: case 2: case 3:
7162 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7163 "shift/add/sub/mov/cmp",
7167 switch (op_bit_10_11
)
7169 case 0: /* Data-processing */
7170 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7174 case 1: /* Special data instructions and branch and exchange. */
7176 unsigned short op
= bits (insn1
, 7, 9);
7177 if (op
== 6 || op
== 7) /* BX or BLX */
7178 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7179 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7180 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7182 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7186 default: /* LDR (literal) */
7187 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7190 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7191 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7194 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7195 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7196 else /* Generate SP-relative address */
7197 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7199 case 11: /* Misc 16-bit instructions */
7201 switch (bits (insn1
, 8, 11))
7203 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7204 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7206 case 12: case 13: /* POP */
7207 if (bit (insn1
, 8)) /* PC is in register list. */
7208 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7210 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7212 case 15: /* If-Then, and hints */
7213 if (bits (insn1
, 0, 3))
7214 /* If-Then makes up to four following instructions conditional.
7215 IT instruction itself is not conditional, so handle it as a
7216 common unmodified instruction. */
7217 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7220 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7223 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7228 if (op_bit_10_11
< 2) /* Store multiple registers */
7229 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7230 else /* Load multiple registers */
7231 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7233 case 13: /* Conditional branch and supervisor call */
7234 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7235 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7237 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7239 case 14: /* Unconditional branch */
7240 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7247 internal_error (__FILE__
, __LINE__
,
7248 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7252 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7253 uint16_t insn1
, uint16_t insn2
,
7254 struct regcache
*regs
,
7255 arm_displaced_step_closure
*dsc
)
7257 int rt
= bits (insn2
, 12, 15);
7258 int rn
= bits (insn1
, 0, 3);
7259 int op1
= bits (insn1
, 7, 8);
7261 switch (bits (insn1
, 5, 6))
7263 case 0: /* Load byte and memory hints */
7264 if (rt
== 0xf) /* PLD/PLI */
7267 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7268 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7270 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7275 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7276 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7279 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7280 "ldrb{reg, immediate}/ldrbt",
7285 case 1: /* Load halfword and memory hints. */
7286 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7287 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7288 "pld/unalloc memhint", dsc
);
7292 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7295 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7299 case 2: /* Load word */
7301 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7304 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7305 else if (op1
== 0x1) /* Encoding T3 */
7306 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7308 else /* op1 == 0x0 */
7310 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7311 /* LDR (immediate) */
7312 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7313 dsc
, bit (insn2
, 8), 1);
7314 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7315 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7318 /* LDR (register) */
7319 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7325 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7332 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7333 uint16_t insn2
, struct regcache
*regs
,
7334 arm_displaced_step_closure
*dsc
)
7337 unsigned short op
= bit (insn2
, 15);
7338 unsigned int op1
= bits (insn1
, 11, 12);
7344 switch (bits (insn1
, 9, 10))
7349 /* Load/store {dual, execlusive}, table branch. */
7350 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7351 && bits (insn2
, 5, 7) == 0)
7352 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7355 /* PC is not allowed to use in load/store {dual, exclusive}
7357 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7358 "load/store dual/ex", dsc
);
7360 else /* load/store multiple */
7362 switch (bits (insn1
, 7, 8))
7364 case 0: case 3: /* SRS, RFE */
7365 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7368 case 1: case 2: /* LDM/STM/PUSH/POP */
7369 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7376 /* Data-processing (shift register). */
7377 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7380 default: /* Coprocessor instructions. */
7381 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7386 case 2: /* op1 = 2 */
7387 if (op
) /* Branch and misc control. */
7389 if (bit (insn2
, 14) /* BLX/BL */
7390 || bit (insn2
, 12) /* Unconditional branch */
7391 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7392 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7394 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7399 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7401 int dp_op
= bits (insn1
, 4, 8);
7402 int rn
= bits (insn1
, 0, 3);
7403 if ((dp_op
== 0 || dp_op
== 0xa) && rn
== 0xf)
7404 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7407 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7410 else /* Data processing (modified immeidate) */
7411 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7415 case 3: /* op1 = 3 */
7416 switch (bits (insn1
, 9, 10))
7420 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7422 else /* NEON Load/Store and Store single data item */
7423 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7424 "neon elt/struct load/store",
7427 case 1: /* op1 = 3, bits (9, 10) == 1 */
7428 switch (bits (insn1
, 7, 8))
7430 case 0: case 1: /* Data processing (register) */
7431 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7434 case 2: /* Multiply and absolute difference */
7435 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7436 "mul/mua/diff", dsc
);
7438 case 3: /* Long multiply and divide */
7439 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7444 default: /* Coprocessor instructions */
7445 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7454 internal_error (__FILE__
, __LINE__
,
7455 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7460 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7461 struct regcache
*regs
,
7462 arm_displaced_step_closure
*dsc
)
7464 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7466 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7468 if (debug_displaced
)
7469 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7470 "at %.8lx\n", insn1
, (unsigned long) from
);
7473 dsc
->insn_size
= thumb_insn_size (insn1
);
7474 if (thumb_insn_size (insn1
) == 4)
7477 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7478 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7481 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7485 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7486 CORE_ADDR to
, struct regcache
*regs
,
7487 arm_displaced_step_closure
*dsc
)
7490 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7493 /* Most displaced instructions use a 1-instruction scratch space, so set this
7494 here and override below if/when necessary. */
7496 dsc
->insn_addr
= from
;
7497 dsc
->scratch_base
= to
;
7498 dsc
->cleanup
= NULL
;
7499 dsc
->wrote_to_pc
= 0;
7501 if (!displaced_in_arm_mode (regs
))
7502 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7506 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7507 if (debug_displaced
)
7508 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7509 "at %.8lx\n", (unsigned long) insn
,
7510 (unsigned long) from
);
7512 if ((insn
& 0xf0000000) == 0xf0000000)
7513 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7514 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7516 case 0x0: case 0x1: case 0x2: case 0x3:
7517 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7520 case 0x4: case 0x5: case 0x6:
7521 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7525 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7528 case 0x8: case 0x9: case 0xa: case 0xb:
7529 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7532 case 0xc: case 0xd: case 0xe: case 0xf:
7533 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7538 internal_error (__FILE__
, __LINE__
,
7539 _("arm_process_displaced_insn: Instruction decode error"));
7542 /* Actually set up the scratch space for a displaced instruction. */
7545 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7546 CORE_ADDR to
, arm_displaced_step_closure
*dsc
)
7548 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7549 unsigned int i
, len
, offset
;
7550 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7551 int size
= dsc
->is_thumb
? 2 : 4;
7552 const gdb_byte
*bkp_insn
;
7555 /* Poke modified instruction(s). */
7556 for (i
= 0; i
< dsc
->numinsns
; i
++)
7558 if (debug_displaced
)
7560 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7562 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7565 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7566 (unsigned short)dsc
->modinsn
[i
]);
7568 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7569 (unsigned long) to
+ offset
);
7572 write_memory_unsigned_integer (to
+ offset
, size
,
7573 byte_order_for_code
,
7578 /* Choose the correct breakpoint instruction. */
7581 bkp_insn
= tdep
->thumb_breakpoint
;
7582 len
= tdep
->thumb_breakpoint_size
;
7586 bkp_insn
= tdep
->arm_breakpoint
;
7587 len
= tdep
->arm_breakpoint_size
;
7590 /* Put breakpoint afterwards. */
7591 write_memory (to
+ offset
, bkp_insn
, len
);
7593 if (debug_displaced
)
7594 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7595 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7598 /* Entry point for cleaning things up after a displaced instruction has been
7602 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7603 struct displaced_step_closure
*dsc_
,
7604 CORE_ADDR from
, CORE_ADDR to
,
7605 struct regcache
*regs
)
7607 arm_displaced_step_closure
*dsc
= (arm_displaced_step_closure
*) dsc_
;
7610 dsc
->cleanup (gdbarch
, regs
, dsc
);
7612 if (!dsc
->wrote_to_pc
)
7613 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7614 dsc
->insn_addr
+ dsc
->insn_size
);
7618 #include "bfd-in2.h"
7619 #include "libcoff.h"
7622 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7624 gdb_disassembler
*di
7625 = static_cast<gdb_disassembler
*>(info
->application_data
);
7626 struct gdbarch
*gdbarch
= di
->arch ();
7628 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7630 static asymbol
*asym
;
7631 static combined_entry_type ce
;
7632 static struct coff_symbol_struct csym
;
7633 static struct bfd fake_bfd
;
7634 static bfd_target fake_target
;
7636 if (csym
.native
== NULL
)
7638 /* Create a fake symbol vector containing a Thumb symbol.
7639 This is solely so that the code in print_insn_little_arm()
7640 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7641 the presence of a Thumb symbol and switch to decoding
7642 Thumb instructions. */
7644 fake_target
.flavour
= bfd_target_coff_flavour
;
7645 fake_bfd
.xvec
= &fake_target
;
7646 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7648 csym
.symbol
.the_bfd
= &fake_bfd
;
7649 csym
.symbol
.name
= "fake";
7650 asym
= (asymbol
*) & csym
;
7653 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7654 info
->symbols
= &asym
;
7657 info
->symbols
= NULL
;
7659 /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
7660 accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
7661 opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
7662 the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
7663 in default_print_insn. */
7664 if (exec_bfd
!= NULL
)
7665 info
->flags
|= USER_SPECIFIED_MACHINE_TYPE
;
7667 return default_print_insn (memaddr
, info
);
7670 /* The following define instruction sequences that will cause ARM
7671 cpu's to take an undefined instruction trap. These are used to
7672 signal a breakpoint to GDB.
7674 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7675 modes. A different instruction is required for each mode. The ARM
7676 cpu's can also be big or little endian. Thus four different
7677 instructions are needed to support all cases.
7679 Note: ARMv4 defines several new instructions that will take the
7680 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7681 not in fact add the new instructions. The new undefined
7682 instructions in ARMv4 are all instructions that had no defined
7683 behaviour in earlier chips. There is no guarantee that they will
7684 raise an exception, but may be treated as NOP's. In practice, it
7685 may only safe to rely on instructions matching:
7687 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7688 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7689 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7691 Even this may only true if the condition predicate is true. The
7692 following use a condition predicate of ALWAYS so it is always TRUE.
7694 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7695 and NetBSD all use a software interrupt rather than an undefined
7696 instruction to force a trap. This can be handled by by the
7697 abi-specific code during establishment of the gdbarch vector. */
7699 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7700 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7701 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7702 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7704 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7705 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7706 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7707 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7709 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7712 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7714 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7715 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7717 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7719 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7721 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7722 check whether we are replacing a 32-bit instruction. */
7723 if (tdep
->thumb2_breakpoint
!= NULL
)
7727 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7729 unsigned short inst1
;
7731 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7732 if (thumb_insn_size (inst1
) == 4)
7733 return ARM_BP_KIND_THUMB2
;
7737 return ARM_BP_KIND_THUMB
;
7740 return ARM_BP_KIND_ARM
;
7744 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7746 static const gdb_byte
*
7747 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7753 case ARM_BP_KIND_ARM
:
7754 *size
= tdep
->arm_breakpoint_size
;
7755 return tdep
->arm_breakpoint
;
7756 case ARM_BP_KIND_THUMB
:
7757 *size
= tdep
->thumb_breakpoint_size
;
7758 return tdep
->thumb_breakpoint
;
7759 case ARM_BP_KIND_THUMB2
:
7760 *size
= tdep
->thumb2_breakpoint_size
;
7761 return tdep
->thumb2_breakpoint
;
7763 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7767 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7770 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7771 struct regcache
*regcache
,
7776 /* Check the memory pointed by PC is readable. */
7777 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7779 struct arm_get_next_pcs next_pcs_ctx
;
7781 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7782 &arm_get_next_pcs_ops
,
7783 gdbarch_byte_order (gdbarch
),
7784 gdbarch_byte_order_for_code (gdbarch
),
7788 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7790 /* If MEMADDR is the next instruction of current pc, do the
7791 software single step computation, and get the thumb mode by
7792 the destination address. */
7793 for (CORE_ADDR pc
: next_pcs
)
7795 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7797 if (IS_THUMB_ADDR (pc
))
7799 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7800 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7803 return ARM_BP_KIND_ARM
;
7808 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7811 /* Extract from an array REGBUF containing the (raw) register state a
7812 function return value of type TYPE, and copy that, in virtual
7813 format, into VALBUF. */
7816 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7819 struct gdbarch
*gdbarch
= regs
->arch ();
7820 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7822 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7824 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7828 /* The value is in register F0 in internal format. We need to
7829 extract the raw value and then convert it to the desired
7831 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7833 regs
->cooked_read (ARM_F0_REGNUM
, tmpbuf
);
7834 target_float_convert (tmpbuf
, arm_ext_type (gdbarch
),
7839 case ARM_FLOAT_SOFT_FPA
:
7840 case ARM_FLOAT_SOFT_VFP
:
7841 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7842 not using the VFP ABI code. */
7844 regs
->cooked_read (ARM_A1_REGNUM
, valbuf
);
7845 if (TYPE_LENGTH (type
) > 4)
7846 regs
->cooked_read (ARM_A1_REGNUM
+ 1, valbuf
+ INT_REGISTER_SIZE
);
7850 internal_error (__FILE__
, __LINE__
,
7851 _("arm_extract_return_value: "
7852 "Floating point model not supported"));
7856 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7857 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7858 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7859 || TYPE_CODE (type
) == TYPE_CODE_PTR
7860 || TYPE_IS_REFERENCE (type
)
7861 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7863 /* If the type is a plain integer, then the access is
7864 straight-forward. Otherwise we have to play around a bit
7866 int len
= TYPE_LENGTH (type
);
7867 int regno
= ARM_A1_REGNUM
;
7872 /* By using store_unsigned_integer we avoid having to do
7873 anything special for small big-endian values. */
7874 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7875 store_unsigned_integer (valbuf
,
7876 (len
> INT_REGISTER_SIZE
7877 ? INT_REGISTER_SIZE
: len
),
7879 len
-= INT_REGISTER_SIZE
;
7880 valbuf
+= INT_REGISTER_SIZE
;
7885 /* For a structure or union the behaviour is as if the value had
7886 been stored to word-aligned memory and then loaded into
7887 registers with 32-bit load instruction(s). */
7888 int len
= TYPE_LENGTH (type
);
7889 int regno
= ARM_A1_REGNUM
;
7890 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7894 regs
->cooked_read (regno
++, tmpbuf
);
7895 memcpy (valbuf
, tmpbuf
,
7896 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7897 len
-= INT_REGISTER_SIZE
;
7898 valbuf
+= INT_REGISTER_SIZE
;
7904 /* Will a function return an aggregate type in memory or in a
7905 register? Return 0 if an aggregate type can be returned in a
7906 register, 1 if it must be returned in memory. */
7909 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7911 enum type_code code
;
7913 type
= check_typedef (type
);
7915 /* Simple, non-aggregate types (ie not including vectors and
7916 complex) are always returned in a register (or registers). */
7917 code
= TYPE_CODE (type
);
7918 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7919 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7922 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7924 /* Vector values should be returned using ARM registers if they
7925 are not over 16 bytes. */
7926 return (TYPE_LENGTH (type
) > 16);
7929 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7931 /* The AAPCS says all aggregates not larger than a word are returned
7933 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
7942 /* All aggregate types that won't fit in a register must be returned
7944 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
7947 /* In the ARM ABI, "integer" like aggregate types are returned in
7948 registers. For an aggregate type to be integer like, its size
7949 must be less than or equal to INT_REGISTER_SIZE and the
7950 offset of each addressable subfield must be zero. Note that bit
7951 fields are not addressable, and all addressable subfields of
7952 unions always start at offset zero.
7954 This function is based on the behaviour of GCC 2.95.1.
7955 See: gcc/arm.c: arm_return_in_memory() for details.
7957 Note: All versions of GCC before GCC 2.95.2 do not set up the
7958 parameters correctly for a function returning the following
7959 structure: struct { float f;}; This should be returned in memory,
7960 not a register. Richard Earnshaw sent me a patch, but I do not
7961 know of any way to detect if a function like the above has been
7962 compiled with the correct calling convention. */
7964 /* Assume all other aggregate types can be returned in a register.
7965 Run a check for structures, unions and arrays. */
7968 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
7971 /* Need to check if this struct/union is "integer" like. For
7972 this to be true, its size must be less than or equal to
7973 INT_REGISTER_SIZE and the offset of each addressable
7974 subfield must be zero. Note that bit fields are not
7975 addressable, and unions always start at offset zero. If any
7976 of the subfields is a floating point type, the struct/union
7977 cannot be an integer type. */
7979 /* For each field in the object, check:
7980 1) Is it FP? --> yes, nRc = 1;
7981 2) Is it addressable (bitpos != 0) and
7982 not packed (bitsize == 0)?
7986 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
7988 enum type_code field_type_code
;
7991 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
7994 /* Is it a floating point type field? */
7995 if (field_type_code
== TYPE_CODE_FLT
)
8001 /* If bitpos != 0, then we have to care about it. */
8002 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8004 /* Bitfields are not addressable. If the field bitsize is
8005 zero, then the field is not packed. Hence it cannot be
8006 a bitfield or any other packed type. */
8007 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8020 /* Write into appropriate registers a function return value of type
8021 TYPE, given in virtual format. */
8024 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8025 const gdb_byte
*valbuf
)
8027 struct gdbarch
*gdbarch
= regs
->arch ();
8028 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8030 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8032 gdb_byte buf
[FP_REGISTER_SIZE
];
8034 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8038 target_float_convert (valbuf
, type
, buf
, arm_ext_type (gdbarch
));
8039 regs
->cooked_write (ARM_F0_REGNUM
, buf
);
8042 case ARM_FLOAT_SOFT_FPA
:
8043 case ARM_FLOAT_SOFT_VFP
:
8044 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8045 not using the VFP ABI code. */
8047 regs
->cooked_write (ARM_A1_REGNUM
, valbuf
);
8048 if (TYPE_LENGTH (type
) > 4)
8049 regs
->cooked_write (ARM_A1_REGNUM
+ 1, valbuf
+ INT_REGISTER_SIZE
);
8053 internal_error (__FILE__
, __LINE__
,
8054 _("arm_store_return_value: Floating "
8055 "point model not supported"));
8059 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8060 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8061 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8062 || TYPE_CODE (type
) == TYPE_CODE_PTR
8063 || TYPE_IS_REFERENCE (type
)
8064 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8066 if (TYPE_LENGTH (type
) <= 4)
8068 /* Values of one word or less are zero/sign-extended and
8070 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8071 LONGEST val
= unpack_long (type
, valbuf
);
8073 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8074 regs
->cooked_write (ARM_A1_REGNUM
, tmpbuf
);
8078 /* Integral values greater than one word are stored in consecutive
8079 registers starting with r0. This will always be a multiple of
8080 the regiser size. */
8081 int len
= TYPE_LENGTH (type
);
8082 int regno
= ARM_A1_REGNUM
;
8086 regs
->cooked_write (regno
++, valbuf
);
8087 len
-= INT_REGISTER_SIZE
;
8088 valbuf
+= INT_REGISTER_SIZE
;
8094 /* For a structure or union the behaviour is as if the value had
8095 been stored to word-aligned memory and then loaded into
8096 registers with 32-bit load instruction(s). */
8097 int len
= TYPE_LENGTH (type
);
8098 int regno
= ARM_A1_REGNUM
;
8099 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8103 memcpy (tmpbuf
, valbuf
,
8104 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8105 regs
->cooked_write (regno
++, tmpbuf
);
8106 len
-= INT_REGISTER_SIZE
;
8107 valbuf
+= INT_REGISTER_SIZE
;
8113 /* Handle function return values. */
8115 static enum return_value_convention
8116 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8117 struct type
*valtype
, struct regcache
*regcache
,
8118 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8120 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8121 struct type
*func_type
= function
? value_type (function
) : NULL
;
8122 enum arm_vfp_cprc_base_type vfp_base_type
;
8125 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8126 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8128 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8129 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8131 for (i
= 0; i
< vfp_base_count
; i
++)
8133 if (reg_char
== 'q')
8136 arm_neon_quad_write (gdbarch
, regcache
, i
,
8137 writebuf
+ i
* unit_length
);
8140 arm_neon_quad_read (gdbarch
, regcache
, i
,
8141 readbuf
+ i
* unit_length
);
8148 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8149 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8152 regcache
->cooked_write (regnum
, writebuf
+ i
* unit_length
);
8154 regcache
->cooked_read (regnum
, readbuf
+ i
* unit_length
);
8157 return RETURN_VALUE_REGISTER_CONVENTION
;
8160 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8161 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8162 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8164 if (tdep
->struct_return
== pcc_struct_return
8165 || arm_return_in_memory (gdbarch
, valtype
))
8166 return RETURN_VALUE_STRUCT_CONVENTION
;
8168 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8170 if (arm_return_in_memory (gdbarch
, valtype
))
8171 return RETURN_VALUE_STRUCT_CONVENTION
;
8175 arm_store_return_value (valtype
, regcache
, writebuf
);
8178 arm_extract_return_value (valtype
, regcache
, readbuf
);
8180 return RETURN_VALUE_REGISTER_CONVENTION
;
8185 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8187 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8191 gdb_byte buf
[INT_REGISTER_SIZE
];
8193 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8195 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8199 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8203 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8204 return the target PC. Otherwise return 0. */
8207 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8211 CORE_ADDR start_addr
;
8213 /* Find the starting address and name of the function containing the PC. */
8214 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8216 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8218 start_addr
= arm_skip_bx_reg (frame
, pc
);
8219 if (start_addr
!= 0)
8225 /* If PC is in a Thumb call or return stub, return the address of the
8226 target PC, which is in a register. The thunk functions are called
8227 _call_via_xx, where x is the register name. The possible names
8228 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8229 functions, named __ARM_call_via_r[0-7]. */
8230 if (startswith (name
, "_call_via_")
8231 || startswith (name
, "__ARM_call_via_"))
8233 /* Use the name suffix to determine which register contains the
8235 static const char *table
[15] =
8236 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8237 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8240 int offset
= strlen (name
) - 2;
8242 for (regno
= 0; regno
<= 14; regno
++)
8243 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8244 return get_frame_register_unsigned (frame
, regno
);
8247 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8248 non-interworking calls to foo. We could decode the stubs
8249 to find the target but it's easier to use the symbol table. */
8250 namelen
= strlen (name
);
8251 if (name
[0] == '_' && name
[1] == '_'
8252 && ((namelen
> 2 + strlen ("_from_thumb")
8253 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8254 || (namelen
> 2 + strlen ("_from_arm")
8255 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8258 int target_len
= namelen
- 2;
8259 struct bound_minimal_symbol minsym
;
8260 struct objfile
*objfile
;
8261 struct obj_section
*sec
;
8263 if (name
[namelen
- 1] == 'b')
8264 target_len
-= strlen ("_from_thumb");
8266 target_len
-= strlen ("_from_arm");
8268 target_name
= (char *) alloca (target_len
+ 1);
8269 memcpy (target_name
, name
+ 2, target_len
);
8270 target_name
[target_len
] = '\0';
8272 sec
= find_pc_section (pc
);
8273 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8274 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8275 if (minsym
.minsym
!= NULL
)
8276 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8281 return 0; /* not a stub */
8285 set_arm_command (const char *args
, int from_tty
)
8287 printf_unfiltered (_("\
8288 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8289 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8293 show_arm_command (const char *args
, int from_tty
)
8295 cmd_show_list (showarmcmdlist
, from_tty
, "");
8299 arm_update_current_architecture (void)
8301 struct gdbarch_info info
;
8303 /* If the current architecture is not ARM, we have nothing to do. */
8304 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8307 /* Update the architecture. */
8308 gdbarch_info_init (&info
);
8310 if (!gdbarch_update_p (info
))
8311 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8315 set_fp_model_sfunc (const char *args
, int from_tty
,
8316 struct cmd_list_element
*c
)
8320 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8321 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8323 arm_fp_model
= (enum arm_float_model
) fp_model
;
8327 if (fp_model
== ARM_FLOAT_LAST
)
8328 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8331 arm_update_current_architecture ();
8335 show_fp_model (struct ui_file
*file
, int from_tty
,
8336 struct cmd_list_element
*c
, const char *value
)
8338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8340 if (arm_fp_model
== ARM_FLOAT_AUTO
8341 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8342 fprintf_filtered (file
, _("\
8343 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8344 fp_model_strings
[tdep
->fp_model
]);
8346 fprintf_filtered (file
, _("\
8347 The current ARM floating point model is \"%s\".\n"),
8348 fp_model_strings
[arm_fp_model
]);
8352 arm_set_abi (const char *args
, int from_tty
,
8353 struct cmd_list_element
*c
)
8357 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8358 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8360 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8364 if (arm_abi
== ARM_ABI_LAST
)
8365 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8368 arm_update_current_architecture ();
8372 arm_show_abi (struct ui_file
*file
, int from_tty
,
8373 struct cmd_list_element
*c
, const char *value
)
8375 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8377 if (arm_abi_global
== ARM_ABI_AUTO
8378 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8379 fprintf_filtered (file
, _("\
8380 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8381 arm_abi_strings
[tdep
->arm_abi
]);
8383 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8388 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8389 struct cmd_list_element
*c
, const char *value
)
8391 fprintf_filtered (file
,
8392 _("The current execution mode assumed "
8393 "(when symbols are unavailable) is \"%s\".\n"),
8394 arm_fallback_mode_string
);
8398 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8399 struct cmd_list_element
*c
, const char *value
)
8401 fprintf_filtered (file
,
8402 _("The current execution mode assumed "
8403 "(even when symbols are available) is \"%s\".\n"),
8404 arm_force_mode_string
);
8407 /* If the user changes the register disassembly style used for info
8408 register and other commands, we have to also switch the style used
8409 in opcodes for disassembly output. This function is run in the "set
8410 arm disassembly" command, and does that. */
8413 set_disassembly_style_sfunc (const char *args
, int from_tty
,
8414 struct cmd_list_element
*c
)
8416 /* Convert the short style name into the long style name (eg, reg-names-*)
8417 before calling the generic set_disassembler_options() function. */
8418 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
8419 set_disassembler_options (&long_name
[0]);
8423 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
8424 struct cmd_list_element
*c
, const char *value
)
8426 struct gdbarch
*gdbarch
= get_current_arch ();
8427 char *options
= get_disassembler_options (gdbarch
);
8428 const char *style
= "";
8432 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8433 if (CONST_STRNEQ (opt
, "reg-names-"))
8435 style
= &opt
[strlen ("reg-names-")];
8436 len
= strcspn (style
, ",");
8439 fprintf_unfiltered (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
8442 /* Return the ARM register name corresponding to register I. */
8444 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8446 const int num_regs
= gdbarch_num_regs (gdbarch
);
8448 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8449 && i
>= num_regs
&& i
< num_regs
+ 32)
8451 static const char *const vfp_pseudo_names
[] = {
8452 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8453 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8454 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8455 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8458 return vfp_pseudo_names
[i
- num_regs
];
8461 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8462 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8464 static const char *const neon_pseudo_names
[] = {
8465 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8466 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8469 return neon_pseudo_names
[i
- num_regs
- 32];
8472 if (i
>= ARRAY_SIZE (arm_register_names
))
8473 /* These registers are only supported on targets which supply
8474 an XML description. */
8477 return arm_register_names
[i
];
8480 /* Test whether the coff symbol specific value corresponds to a Thumb
8484 coff_sym_is_thumb (int val
)
8486 return (val
== C_THUMBEXT
8487 || val
== C_THUMBSTAT
8488 || val
== C_THUMBEXTFUNC
8489 || val
== C_THUMBSTATFUNC
8490 || val
== C_THUMBLABEL
);
8493 /* arm_coff_make_msymbol_special()
8494 arm_elf_make_msymbol_special()
8496 These functions test whether the COFF or ELF symbol corresponds to
8497 an address in thumb code, and set a "special" bit in a minimal
8498 symbol to indicate that it does. */
8501 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8503 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8505 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8506 == ST_BRANCH_TO_THUMB
)
8507 MSYMBOL_SET_SPECIAL (msym
);
8511 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8513 if (coff_sym_is_thumb (val
))
8514 MSYMBOL_SET_SPECIAL (msym
);
8518 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8520 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8526 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8529 const char *name
= bfd_asymbol_name (sym
);
8530 struct arm_per_objfile
*data
;
8531 struct arm_mapping_symbol new_map_sym
;
8533 gdb_assert (name
[0] == '$');
8534 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8537 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8538 arm_objfile_data_key
);
8541 data
= new arm_per_objfile (objfile
->obfd
->section_count
);
8542 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8544 arm_mapping_symbol_vec
&map
8545 = data
->section_maps
[bfd_get_section (sym
)->index
];
8547 new_map_sym
.value
= sym
->value
;
8548 new_map_sym
.type
= name
[1];
8550 /* Assume that most mapping symbols appear in order of increasing
8551 value. If they were randomly distributed, it would be faster to
8552 always push here and then sort at first use. */
8553 arm_mapping_symbol_vec::iterator it
8554 = std::lower_bound (map
.begin (), map
.end (), new_map_sym
);
8555 map
.insert (it
, new_map_sym
);
8559 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8561 struct gdbarch
*gdbarch
= regcache
->arch ();
8562 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8564 /* If necessary, set the T bit. */
8567 ULONGEST val
, t_bit
;
8568 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8569 t_bit
= arm_psr_thumb_bit (gdbarch
);
8570 if (arm_pc_is_thumb (gdbarch
, pc
))
8571 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8574 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8579 /* Read the contents of a NEON quad register, by reading from two
8580 double registers. This is used to implement the quad pseudo
8581 registers, and for argument passing in case the quad registers are
8582 missing; vectors are passed in quad registers when using the VFP
8583 ABI, even if a NEON unit is not present. REGNUM is the index of
8584 the quad register, in [0, 15]. */
8586 static enum register_status
8587 arm_neon_quad_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8588 int regnum
, gdb_byte
*buf
)
8591 gdb_byte reg_buf
[8];
8592 int offset
, double_regnum
;
8593 enum register_status status
;
8595 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8596 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8599 /* d0 is always the least significant half of q0. */
8600 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8605 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8606 if (status
!= REG_VALID
)
8608 memcpy (buf
+ offset
, reg_buf
, 8);
8610 offset
= 8 - offset
;
8611 status
= regcache
->raw_read (double_regnum
+ 1, reg_buf
);
8612 if (status
!= REG_VALID
)
8614 memcpy (buf
+ offset
, reg_buf
, 8);
8619 static enum register_status
8620 arm_pseudo_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8621 int regnum
, gdb_byte
*buf
)
8623 const int num_regs
= gdbarch_num_regs (gdbarch
);
8625 gdb_byte reg_buf
[8];
8626 int offset
, double_regnum
;
8628 gdb_assert (regnum
>= num_regs
);
8631 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8632 /* Quad-precision register. */
8633 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8636 enum register_status status
;
8638 /* Single-precision register. */
8639 gdb_assert (regnum
< 32);
8641 /* s0 is always the least significant half of d0. */
8642 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8643 offset
= (regnum
& 1) ? 0 : 4;
8645 offset
= (regnum
& 1) ? 4 : 0;
8647 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8648 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8651 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8652 if (status
== REG_VALID
)
8653 memcpy (buf
, reg_buf
+ offset
, 4);
8658 /* Store the contents of BUF to a NEON quad register, by writing to
8659 two double registers. This is used to implement the quad pseudo
8660 registers, and for argument passing in case the quad registers are
8661 missing; vectors are passed in quad registers when using the VFP
8662 ABI, even if a NEON unit is not present. REGNUM is the index
8663 of the quad register, in [0, 15]. */
8666 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8667 int regnum
, const gdb_byte
*buf
)
8670 int offset
, double_regnum
;
8672 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8673 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8676 /* d0 is always the least significant half of q0. */
8677 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8682 regcache
->raw_write (double_regnum
, buf
+ offset
);
8683 offset
= 8 - offset
;
8684 regcache
->raw_write (double_regnum
+ 1, buf
+ offset
);
8688 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8689 int regnum
, const gdb_byte
*buf
)
8691 const int num_regs
= gdbarch_num_regs (gdbarch
);
8693 gdb_byte reg_buf
[8];
8694 int offset
, double_regnum
;
8696 gdb_assert (regnum
>= num_regs
);
8699 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8700 /* Quad-precision register. */
8701 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8704 /* Single-precision register. */
8705 gdb_assert (regnum
< 32);
8707 /* s0 is always the least significant half of d0. */
8708 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8709 offset
= (regnum
& 1) ? 0 : 4;
8711 offset
= (regnum
& 1) ? 4 : 0;
8713 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8714 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8717 regcache
->raw_read (double_regnum
, reg_buf
);
8718 memcpy (reg_buf
+ offset
, buf
, 4);
8719 regcache
->raw_write (double_regnum
, reg_buf
);
8723 static struct value
*
8724 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8726 const int *reg_p
= (const int *) baton
;
8727 return value_of_register (*reg_p
, frame
);
8730 static enum gdb_osabi
8731 arm_elf_osabi_sniffer (bfd
*abfd
)
8733 unsigned int elfosabi
;
8734 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8736 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8738 if (elfosabi
== ELFOSABI_ARM
)
8739 /* GNU tools use this value. Check note sections in this case,
8741 bfd_map_over_sections (abfd
,
8742 generic_elf_osabi_sniff_abi_tag_sections
,
8745 /* Anything else will be handled by the generic ELF sniffer. */
8750 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8751 struct reggroup
*group
)
8753 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8754 this, FPS register belongs to save_regroup, restore_reggroup, and
8755 all_reggroup, of course. */
8756 if (regnum
== ARM_FPS_REGNUM
)
8757 return (group
== float_reggroup
8758 || group
== save_reggroup
8759 || group
== restore_reggroup
8760 || group
== all_reggroup
);
8762 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8766 /* For backward-compatibility we allow two 'g' packet lengths with
8767 the remote protocol depending on whether FPA registers are
8768 supplied. M-profile targets do not have FPA registers, but some
8769 stubs already exist in the wild which use a 'g' packet which
8770 supplies them albeit with dummy values. The packet format which
8771 includes FPA registers should be considered deprecated for
8772 M-profile targets. */
8775 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8777 if (gdbarch_tdep (gdbarch
)->is_m
)
8779 /* If we know from the executable this is an M-profile target,
8780 cater for remote targets whose register set layout is the
8781 same as the FPA layout. */
8782 register_remote_g_packet_guess (gdbarch
,
8783 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8784 (16 * INT_REGISTER_SIZE
)
8785 + (8 * FP_REGISTER_SIZE
)
8786 + (2 * INT_REGISTER_SIZE
),
8787 tdesc_arm_with_m_fpa_layout
);
8789 /* The regular M-profile layout. */
8790 register_remote_g_packet_guess (gdbarch
,
8791 /* r0-r12,sp,lr,pc; xpsr */
8792 (16 * INT_REGISTER_SIZE
)
8793 + INT_REGISTER_SIZE
,
8796 /* M-profile plus M4F VFP. */
8797 register_remote_g_packet_guess (gdbarch
,
8798 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8799 (16 * INT_REGISTER_SIZE
)
8800 + (16 * VFP_REGISTER_SIZE
)
8801 + (2 * INT_REGISTER_SIZE
),
8802 tdesc_arm_with_m_vfp_d16
);
8805 /* Otherwise we don't have a useful guess. */
8808 /* Implement the code_of_frame_writable gdbarch method. */
8811 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8813 if (gdbarch_tdep (gdbarch
)->is_m
8814 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8816 /* M-profile exception frames return to some magic PCs, where
8817 isn't writable at all. */
8825 /* Initialize the current architecture based on INFO. If possible,
8826 re-use an architecture from ARCHES, which is a list of
8827 architectures already created during this debugging session.
8829 Called e.g. at program startup, when reading a core file, and when
8830 reading a binary file. */
8832 static struct gdbarch
*
8833 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8835 struct gdbarch_tdep
*tdep
;
8836 struct gdbarch
*gdbarch
;
8837 struct gdbarch_list
*best_arch
;
8838 enum arm_abi_kind arm_abi
= arm_abi_global
;
8839 enum arm_float_model fp_model
= arm_fp_model
;
8840 struct tdesc_arch_data
*tdesc_data
= NULL
;
8842 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8843 int have_wmmx_registers
= 0;
8845 int have_fpa_registers
= 1;
8846 const struct target_desc
*tdesc
= info
.target_desc
;
8848 /* If we have an object to base this architecture on, try to determine
8851 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8853 int ei_osabi
, e_flags
;
8855 switch (bfd_get_flavour (info
.abfd
))
8857 case bfd_target_coff_flavour
:
8858 /* Assume it's an old APCS-style ABI. */
8860 arm_abi
= ARM_ABI_APCS
;
8863 case bfd_target_elf_flavour
:
8864 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8865 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8867 if (ei_osabi
== ELFOSABI_ARM
)
8869 /* GNU tools used to use this value, but do not for EABI
8870 objects. There's nowhere to tag an EABI version
8871 anyway, so assume APCS. */
8872 arm_abi
= ARM_ABI_APCS
;
8874 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8876 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8880 case EF_ARM_EABI_UNKNOWN
:
8881 /* Assume GNU tools. */
8882 arm_abi
= ARM_ABI_APCS
;
8885 case EF_ARM_EABI_VER4
:
8886 case EF_ARM_EABI_VER5
:
8887 arm_abi
= ARM_ABI_AAPCS
;
8888 /* EABI binaries default to VFP float ordering.
8889 They may also contain build attributes that can
8890 be used to identify if the VFP argument-passing
8892 if (fp_model
== ARM_FLOAT_AUTO
)
8895 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8899 case AEABI_VFP_args_base
:
8900 /* "The user intended FP parameter/result
8901 passing to conform to AAPCS, base
8903 fp_model
= ARM_FLOAT_SOFT_VFP
;
8905 case AEABI_VFP_args_vfp
:
8906 /* "The user intended FP parameter/result
8907 passing to conform to AAPCS, VFP
8909 fp_model
= ARM_FLOAT_VFP
;
8911 case AEABI_VFP_args_toolchain
:
8912 /* "The user intended FP parameter/result
8913 passing to conform to tool chain-specific
8914 conventions" - we don't know any such
8915 conventions, so leave it as "auto". */
8917 case AEABI_VFP_args_compatible
:
8918 /* "Code is compatible with both the base
8919 and VFP variants; the user did not permit
8920 non-variadic functions to pass FP
8921 parameters/results" - leave it as
8925 /* Attribute value not mentioned in the
8926 November 2012 ABI, so leave it as
8931 fp_model
= ARM_FLOAT_SOFT_VFP
;
8937 /* Leave it as "auto". */
8938 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
8943 /* Detect M-profile programs. This only works if the
8944 executable file includes build attributes; GCC does
8945 copy them to the executable, but e.g. RealView does
8948 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8951 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8952 Tag_CPU_arch_profile
);
8954 /* GCC specifies the profile for v6-M; RealView only
8955 specifies the profile for architectures starting with
8956 V7 (as opposed to architectures with a tag
8957 numerically greater than TAG_CPU_ARCH_V7). */
8958 if (!tdesc_has_registers (tdesc
)
8959 && (attr_arch
== TAG_CPU_ARCH_V6_M
8960 || attr_arch
== TAG_CPU_ARCH_V6S_M
8961 || attr_profile
== 'M'))
8966 if (fp_model
== ARM_FLOAT_AUTO
)
8968 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
8971 /* Leave it as "auto". Strictly speaking this case
8972 means FPA, but almost nobody uses that now, and
8973 many toolchains fail to set the appropriate bits
8974 for the floating-point model they use. */
8976 case EF_ARM_SOFT_FLOAT
:
8977 fp_model
= ARM_FLOAT_SOFT_FPA
;
8979 case EF_ARM_VFP_FLOAT
:
8980 fp_model
= ARM_FLOAT_VFP
;
8982 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
8983 fp_model
= ARM_FLOAT_SOFT_VFP
;
8988 if (e_flags
& EF_ARM_BE8
)
8989 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
8994 /* Leave it as "auto". */
8999 /* Check any target description for validity. */
9000 if (tdesc_has_registers (tdesc
))
9002 /* For most registers we require GDB's default names; but also allow
9003 the numeric names for sp / lr / pc, as a convenience. */
9004 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9005 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9006 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9008 const struct tdesc_feature
*feature
;
9011 feature
= tdesc_find_feature (tdesc
,
9012 "org.gnu.gdb.arm.core");
9013 if (feature
== NULL
)
9015 feature
= tdesc_find_feature (tdesc
,
9016 "org.gnu.gdb.arm.m-profile");
9017 if (feature
== NULL
)
9023 tdesc_data
= tdesc_data_alloc ();
9026 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9027 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9028 arm_register_names
[i
]);
9029 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9032 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9035 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9039 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9040 ARM_PS_REGNUM
, "xpsr");
9042 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9043 ARM_PS_REGNUM
, "cpsr");
9047 tdesc_data_cleanup (tdesc_data
);
9051 feature
= tdesc_find_feature (tdesc
,
9052 "org.gnu.gdb.arm.fpa");
9053 if (feature
!= NULL
)
9056 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9057 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9058 arm_register_names
[i
]);
9061 tdesc_data_cleanup (tdesc_data
);
9066 have_fpa_registers
= 0;
9068 feature
= tdesc_find_feature (tdesc
,
9069 "org.gnu.gdb.xscale.iwmmxt");
9070 if (feature
!= NULL
)
9072 static const char *const iwmmxt_names
[] = {
9073 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9074 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9075 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9076 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9080 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9082 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9083 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9085 /* Check for the control registers, but do not fail if they
9087 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9088 tdesc_numbered_register (feature
, tdesc_data
, i
,
9089 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9091 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9093 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9094 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9098 tdesc_data_cleanup (tdesc_data
);
9102 have_wmmx_registers
= 1;
9105 /* If we have a VFP unit, check whether the single precision registers
9106 are present. If not, then we will synthesize them as pseudo
9108 feature
= tdesc_find_feature (tdesc
,
9109 "org.gnu.gdb.arm.vfp");
9110 if (feature
!= NULL
)
9112 static const char *const vfp_double_names
[] = {
9113 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9114 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9115 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9116 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9119 /* Require the double precision registers. There must be either
9122 for (i
= 0; i
< 32; i
++)
9124 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9126 vfp_double_names
[i
]);
9130 if (!valid_p
&& i
== 16)
9133 /* Also require FPSCR. */
9134 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9135 ARM_FPSCR_REGNUM
, "fpscr");
9138 tdesc_data_cleanup (tdesc_data
);
9142 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9143 have_vfp_pseudos
= 1;
9145 vfp_register_count
= i
;
9147 /* If we have VFP, also check for NEON. The architecture allows
9148 NEON without VFP (integer vector operations only), but GDB
9149 does not support that. */
9150 feature
= tdesc_find_feature (tdesc
,
9151 "org.gnu.gdb.arm.neon");
9152 if (feature
!= NULL
)
9154 /* NEON requires 32 double-precision registers. */
9157 tdesc_data_cleanup (tdesc_data
);
9161 /* If there are quad registers defined by the stub, use
9162 their type; otherwise (normally) provide them with
9163 the default type. */
9164 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9165 have_neon_pseudos
= 1;
9172 /* If there is already a candidate, use it. */
9173 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9175 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9177 if (arm_abi
!= ARM_ABI_AUTO
9178 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9181 if (fp_model
!= ARM_FLOAT_AUTO
9182 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9185 /* There are various other properties in tdep that we do not
9186 need to check here: those derived from a target description,
9187 since gdbarches with a different target description are
9188 automatically disqualified. */
9190 /* Do check is_m, though, since it might come from the binary. */
9191 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9194 /* Found a match. */
9198 if (best_arch
!= NULL
)
9200 if (tdesc_data
!= NULL
)
9201 tdesc_data_cleanup (tdesc_data
);
9202 return best_arch
->gdbarch
;
9205 tdep
= XCNEW (struct gdbarch_tdep
);
9206 gdbarch
= gdbarch_alloc (&info
, tdep
);
9208 /* Record additional information about the architecture we are defining.
9209 These are gdbarch discriminators, like the OSABI. */
9210 tdep
->arm_abi
= arm_abi
;
9211 tdep
->fp_model
= fp_model
;
9213 tdep
->have_fpa_registers
= have_fpa_registers
;
9214 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9215 gdb_assert (vfp_register_count
== 0
9216 || vfp_register_count
== 16
9217 || vfp_register_count
== 32);
9218 tdep
->vfp_register_count
= vfp_register_count
;
9219 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9220 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9221 tdep
->have_neon
= have_neon
;
9223 arm_register_g_packet_guesses (gdbarch
);
9226 switch (info
.byte_order_for_code
)
9228 case BFD_ENDIAN_BIG
:
9229 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9230 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9231 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9232 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9236 case BFD_ENDIAN_LITTLE
:
9237 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9238 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9239 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9240 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9245 internal_error (__FILE__
, __LINE__
,
9246 _("arm_gdbarch_init: bad byte order for float format"));
9249 /* On ARM targets char defaults to unsigned. */
9250 set_gdbarch_char_signed (gdbarch
, 0);
9252 /* wchar_t is unsigned under the AAPCS. */
9253 if (tdep
->arm_abi
== ARM_ABI_AAPCS
)
9254 set_gdbarch_wchar_signed (gdbarch
, 0);
9256 set_gdbarch_wchar_signed (gdbarch
, 1);
9258 /* Compute type alignment. */
9259 set_gdbarch_type_align (gdbarch
, arm_type_align
);
9261 /* Note: for displaced stepping, this includes the breakpoint, and one word
9262 of additional scratch space. This setting isn't used for anything beside
9263 displaced stepping at present. */
9264 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9266 /* This should be low enough for everything. */
9267 tdep
->lowest_pc
= 0x20;
9268 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9270 /* The default, for both APCS and AAPCS, is to return small
9271 structures in registers. */
9272 tdep
->struct_return
= reg_struct_return
;
9274 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9275 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9278 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9280 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9282 frame_base_set_default (gdbarch
, &arm_normal_base
);
9284 /* Address manipulation. */
9285 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9287 /* Advance PC across function entry code. */
9288 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9290 /* Detect whether PC is at a point where the stack has been destroyed. */
9291 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9293 /* Skip trampolines. */
9294 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9296 /* The stack grows downward. */
9297 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9299 /* Breakpoint manipulation. */
9300 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9301 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9302 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9303 arm_breakpoint_kind_from_current_state
);
9305 /* Information about registers, etc. */
9306 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9307 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9308 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9309 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9310 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9312 /* This "info float" is FPA-specific. Use the generic version if we
9314 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9315 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9317 /* Internal <-> external register number maps. */
9318 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9319 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9321 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9323 /* Returning results. */
9324 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9327 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9329 /* Minsymbol frobbing. */
9330 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9331 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9332 arm_coff_make_msymbol_special
);
9333 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9335 /* Thumb-2 IT block support. */
9336 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9337 arm_adjust_breakpoint_address
);
9339 /* Virtual tables. */
9340 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9342 /* Hook in the ABI-specific overrides, if they have been registered. */
9343 gdbarch_init_osabi (info
, gdbarch
);
9345 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9347 /* Add some default predicates. */
9349 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9350 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9351 dwarf2_append_unwinders (gdbarch
);
9352 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9353 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9354 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9356 /* Now we have tuned the configuration, set a few final things,
9357 based on what the OS ABI has told us. */
9359 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9360 binaries are always marked. */
9361 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9362 tdep
->arm_abi
= ARM_ABI_APCS
;
9364 /* Watchpoints are not steppable. */
9365 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9367 /* We used to default to FPA for generic ARM, but almost nobody
9368 uses that now, and we now provide a way for the user to force
9369 the model. So default to the most useful variant. */
9370 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9371 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9373 if (tdep
->jb_pc
>= 0)
9374 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9376 /* Floating point sizes and format. */
9377 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9378 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9380 set_gdbarch_double_format
9381 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9382 set_gdbarch_long_double_format
9383 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9387 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9388 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9391 if (have_vfp_pseudos
)
9393 /* NOTE: These are the only pseudo registers used by
9394 the ARM target at the moment. If more are added, a
9395 little more care in numbering will be needed. */
9397 int num_pseudos
= 32;
9398 if (have_neon_pseudos
)
9400 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9401 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9402 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9407 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9409 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9411 /* Override tdesc_register_type to adjust the types of VFP
9412 registers for NEON. */
9413 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9416 /* Add standard register aliases. We add aliases even for those
9417 nanes which are used by the current architecture - it's simpler,
9418 and does no harm, since nothing ever lists user registers. */
9419 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9420 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9421 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9423 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
9424 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
9430 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9437 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9438 (unsigned long) tdep
->lowest_pc
);
9444 static void arm_record_test (void);
9449 _initialize_arm_tdep (void)
9453 char regdesc
[1024], *rdptr
= regdesc
;
9454 size_t rest
= sizeof (regdesc
);
9456 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9458 arm_objfile_data_key
9459 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9461 /* Add ourselves to objfile event chain. */
9462 gdb::observers::new_objfile
.attach (arm_exidx_new_objfile
);
9464 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9466 /* Register an ELF OS ABI sniffer for ARM binaries. */
9467 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9468 bfd_target_elf_flavour
,
9469 arm_elf_osabi_sniffer
);
9471 /* Initialize the standard target descriptions. */
9472 initialize_tdesc_arm_with_m ();
9473 initialize_tdesc_arm_with_m_fpa_layout ();
9474 initialize_tdesc_arm_with_m_vfp_d16 ();
9475 initialize_tdesc_arm_with_iwmmxt ();
9476 initialize_tdesc_arm_with_vfpv2 ();
9477 initialize_tdesc_arm_with_vfpv3 ();
9478 initialize_tdesc_arm_with_neon ();
9480 /* Add root prefix command for all "set arm"/"show arm" commands. */
9481 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9482 _("Various ARM-specific commands."),
9483 &setarmcmdlist
, "set arm ", 0, &setlist
);
9485 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9486 _("Various ARM-specific commands."),
9487 &showarmcmdlist
, "show arm ", 0, &showlist
);
9490 arm_disassembler_options
= xstrdup ("reg-names-std");
9491 const disasm_options_t
*disasm_options
9492 = &disassembler_options_arm ()->options
;
9493 int num_disassembly_styles
= 0;
9494 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9495 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9496 num_disassembly_styles
++;
9498 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9499 valid_disassembly_styles
= XNEWVEC (const char *,
9500 num_disassembly_styles
+ 1);
9501 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9502 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9504 size_t offset
= strlen ("reg-names-");
9505 const char *style
= disasm_options
->name
[i
];
9506 valid_disassembly_styles
[j
++] = &style
[offset
];
9507 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
9508 disasm_options
->description
[i
]);
9512 /* Mark the end of valid options. */
9513 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
9515 /* Create the help text. */
9516 std::string helptext
= string_printf ("%s%s%s",
9517 _("The valid values are:\n"),
9519 _("The default is \"std\"."));
9521 add_setshow_enum_cmd("disassembler", no_class
,
9522 valid_disassembly_styles
, &disassembly_style
,
9523 _("Set the disassembly style."),
9524 _("Show the disassembly style."),
9526 set_disassembly_style_sfunc
,
9527 show_disassembly_style_sfunc
,
9528 &setarmcmdlist
, &showarmcmdlist
);
9530 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9531 _("Set usage of ARM 32-bit mode."),
9532 _("Show usage of ARM 32-bit mode."),
9533 _("When off, a 26-bit PC will be used."),
9535 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9537 &setarmcmdlist
, &showarmcmdlist
);
9539 /* Add a command to allow the user to force the FPU model. */
9540 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9541 _("Set the floating point type."),
9542 _("Show the floating point type."),
9543 _("auto - Determine the FP typefrom the OS-ABI.\n\
9544 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9545 fpa - FPA co-processor (GCC compiled).\n\
9546 softvfp - Software FP with pure-endian doubles.\n\
9547 vfp - VFP co-processor."),
9548 set_fp_model_sfunc
, show_fp_model
,
9549 &setarmcmdlist
, &showarmcmdlist
);
9551 /* Add a command to allow the user to force the ABI. */
9552 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9555 NULL
, arm_set_abi
, arm_show_abi
,
9556 &setarmcmdlist
, &showarmcmdlist
);
9558 /* Add two commands to allow the user to force the assumed
9560 add_setshow_enum_cmd ("fallback-mode", class_support
,
9561 arm_mode_strings
, &arm_fallback_mode_string
,
9562 _("Set the mode assumed when symbols are unavailable."),
9563 _("Show the mode assumed when symbols are unavailable."),
9564 NULL
, NULL
, arm_show_fallback_mode
,
9565 &setarmcmdlist
, &showarmcmdlist
);
9566 add_setshow_enum_cmd ("force-mode", class_support
,
9567 arm_mode_strings
, &arm_force_mode_string
,
9568 _("Set the mode assumed even when symbols are available."),
9569 _("Show the mode assumed even when symbols are available."),
9570 NULL
, NULL
, arm_show_force_mode
,
9571 &setarmcmdlist
, &showarmcmdlist
);
9573 /* Debugging flag. */
9574 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9575 _("Set ARM debugging."),
9576 _("Show ARM debugging."),
9577 _("When on, arm-specific debugging is enabled."),
9579 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9580 &setdebuglist
, &showdebuglist
);
9583 selftests::register_test ("arm-record", selftests::arm_record_test
);
9588 /* ARM-reversible process record data structures. */
9590 #define ARM_INSN_SIZE_BYTES 4
9591 #define THUMB_INSN_SIZE_BYTES 2
9592 #define THUMB2_INSN_SIZE_BYTES 4
9595 /* Position of the bit within a 32-bit ARM instruction
9596 that defines whether the instruction is a load or store. */
9597 #define INSN_S_L_BIT_NUM 20
9599 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9602 unsigned int reg_len = LENGTH; \
9605 REGS = XNEWVEC (uint32_t, reg_len); \
9606 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9611 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9614 unsigned int mem_len = LENGTH; \
9617 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9618 memcpy(&MEMS->len, &RECORD_BUF[0], \
9619 sizeof(struct arm_mem_r) * LENGTH); \
9624 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9625 #define INSN_RECORDED(ARM_RECORD) \
9626 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9628 /* ARM memory record structure. */
9631 uint32_t len
; /* Record length. */
9632 uint32_t addr
; /* Memory address. */
9635 /* ARM instruction record contains opcode of current insn
9636 and execution state (before entry to decode_insn()),
9637 contains list of to-be-modified registers and
9638 memory blocks (on return from decode_insn()). */
9640 typedef struct insn_decode_record_t
9642 struct gdbarch
*gdbarch
;
9643 struct regcache
*regcache
;
9644 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9645 uint32_t arm_insn
; /* Should accommodate thumb. */
9646 uint32_t cond
; /* Condition code. */
9647 uint32_t opcode
; /* Insn opcode. */
9648 uint32_t decode
; /* Insn decode bits. */
9649 uint32_t mem_rec_count
; /* No of mem records. */
9650 uint32_t reg_rec_count
; /* No of reg records. */
9651 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9652 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9653 } insn_decode_record
;
9656 /* Checks ARM SBZ and SBO mandatory fields. */
9659 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9661 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9680 enum arm_record_result
9682 ARM_RECORD_SUCCESS
= 0,
9683 ARM_RECORD_FAILURE
= 1
9690 } arm_record_strx_t
;
9701 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9702 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9705 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9706 ULONGEST u_regval
[2]= {0};
9708 uint32_t reg_src1
= 0, reg_src2
= 0;
9709 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9711 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9712 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9714 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9716 /* 1) Handle misc store, immediate offset. */
9717 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9718 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9719 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9720 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9722 if (ARM_PC_REGNUM
== reg_src1
)
9724 /* If R15 was used as Rn, hence current PC+8. */
9725 u_regval
[0] = u_regval
[0] + 8;
9727 offset_8
= (immed_high
<< 4) | immed_low
;
9728 /* Calculate target store address. */
9729 if (14 == arm_insn_r
->opcode
)
9731 tgt_mem_addr
= u_regval
[0] + offset_8
;
9735 tgt_mem_addr
= u_regval
[0] - offset_8
;
9737 if (ARM_RECORD_STRH
== str_type
)
9739 record_buf_mem
[0] = 2;
9740 record_buf_mem
[1] = tgt_mem_addr
;
9741 arm_insn_r
->mem_rec_count
= 1;
9743 else if (ARM_RECORD_STRD
== str_type
)
9745 record_buf_mem
[0] = 4;
9746 record_buf_mem
[1] = tgt_mem_addr
;
9747 record_buf_mem
[2] = 4;
9748 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9749 arm_insn_r
->mem_rec_count
= 2;
9752 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9754 /* 2) Store, register offset. */
9756 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9758 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9759 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9760 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9763 /* If R15 was used as Rn, hence current PC+8. */
9764 u_regval
[0] = u_regval
[0] + 8;
9766 /* Calculate target store address, Rn +/- Rm, register offset. */
9767 if (12 == arm_insn_r
->opcode
)
9769 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9773 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9775 if (ARM_RECORD_STRH
== str_type
)
9777 record_buf_mem
[0] = 2;
9778 record_buf_mem
[1] = tgt_mem_addr
;
9779 arm_insn_r
->mem_rec_count
= 1;
9781 else if (ARM_RECORD_STRD
== str_type
)
9783 record_buf_mem
[0] = 4;
9784 record_buf_mem
[1] = tgt_mem_addr
;
9785 record_buf_mem
[2] = 4;
9786 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9787 arm_insn_r
->mem_rec_count
= 2;
9790 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9791 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9793 /* 3) Store, immediate pre-indexed. */
9794 /* 5) Store, immediate post-indexed. */
9795 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9796 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9797 offset_8
= (immed_high
<< 4) | immed_low
;
9798 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9799 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9800 /* Calculate target store address, Rn +/- Rm, register offset. */
9801 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9803 tgt_mem_addr
= u_regval
[0] + offset_8
;
9807 tgt_mem_addr
= u_regval
[0] - offset_8
;
9809 if (ARM_RECORD_STRH
== str_type
)
9811 record_buf_mem
[0] = 2;
9812 record_buf_mem
[1] = tgt_mem_addr
;
9813 arm_insn_r
->mem_rec_count
= 1;
9815 else if (ARM_RECORD_STRD
== str_type
)
9817 record_buf_mem
[0] = 4;
9818 record_buf_mem
[1] = tgt_mem_addr
;
9819 record_buf_mem
[2] = 4;
9820 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9821 arm_insn_r
->mem_rec_count
= 2;
9823 /* Record Rn also as it changes. */
9824 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9825 arm_insn_r
->reg_rec_count
= 1;
9827 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9828 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9830 /* 4) Store, register pre-indexed. */
9831 /* 6) Store, register post -indexed. */
9832 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9833 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9834 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9835 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9836 /* Calculate target store address, Rn +/- Rm, register offset. */
9837 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9839 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9843 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9845 if (ARM_RECORD_STRH
== str_type
)
9847 record_buf_mem
[0] = 2;
9848 record_buf_mem
[1] = tgt_mem_addr
;
9849 arm_insn_r
->mem_rec_count
= 1;
9851 else if (ARM_RECORD_STRD
== str_type
)
9853 record_buf_mem
[0] = 4;
9854 record_buf_mem
[1] = tgt_mem_addr
;
9855 record_buf_mem
[2] = 4;
9856 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9857 arm_insn_r
->mem_rec_count
= 2;
9859 /* Record Rn also as it changes. */
9860 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9861 arm_insn_r
->reg_rec_count
= 1;
9866 /* Handling ARM extension space insns. */
9869 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9871 int ret
= 0; /* Return value: -1:record failure ; 0:success */
9872 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9873 uint32_t record_buf
[8], record_buf_mem
[8];
9874 uint32_t reg_src1
= 0;
9875 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9876 ULONGEST u_regval
= 0;
9878 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9879 /* Handle unconditional insn extension space. */
9881 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9882 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9883 if (arm_insn_r
->cond
)
9885 /* PLD has no affect on architectural state, it just affects
9887 if (5 == ((opcode1
& 0xE0) >> 5))
9890 record_buf
[0] = ARM_PS_REGNUM
;
9891 record_buf
[1] = ARM_LR_REGNUM
;
9892 arm_insn_r
->reg_rec_count
= 2;
9894 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9898 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9899 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9902 /* Undefined instruction on ARM V5; need to handle if later
9903 versions define it. */
9906 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9907 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9908 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9910 /* Handle arithmetic insn extension space. */
9911 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
9912 && !INSN_RECORDED(arm_insn_r
))
9914 /* Handle MLA(S) and MUL(S). */
9915 if (in_inclusive_range (insn_op1
, 0U, 3U))
9917 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9918 record_buf
[1] = ARM_PS_REGNUM
;
9919 arm_insn_r
->reg_rec_count
= 2;
9921 else if (in_inclusive_range (insn_op1
, 4U, 15U))
9923 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9924 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
9925 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9926 record_buf
[2] = ARM_PS_REGNUM
;
9927 arm_insn_r
->reg_rec_count
= 3;
9931 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
9932 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
9933 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
9935 /* Handle control insn extension space. */
9937 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
9938 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
9940 if (!bit (arm_insn_r
->arm_insn
,25))
9942 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
9944 if ((0 == insn_op1
) || (2 == insn_op1
))
9947 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9948 arm_insn_r
->reg_rec_count
= 1;
9950 else if (1 == insn_op1
)
9952 /* CSPR is going to be changed. */
9953 record_buf
[0] = ARM_PS_REGNUM
;
9954 arm_insn_r
->reg_rec_count
= 1;
9956 else if (3 == insn_op1
)
9958 /* SPSR is going to be changed. */
9959 /* We need to get SPSR value, which is yet to be done. */
9963 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
9968 record_buf
[0] = ARM_PS_REGNUM
;
9969 arm_insn_r
->reg_rec_count
= 1;
9971 else if (3 == insn_op1
)
9974 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9975 arm_insn_r
->reg_rec_count
= 1;
9978 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
9981 record_buf
[0] = ARM_PS_REGNUM
;
9982 record_buf
[1] = ARM_LR_REGNUM
;
9983 arm_insn_r
->reg_rec_count
= 2;
9985 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
9987 /* QADD, QSUB, QDADD, QDSUB */
9988 record_buf
[0] = ARM_PS_REGNUM
;
9989 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9990 arm_insn_r
->reg_rec_count
= 2;
9992 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
9995 record_buf
[0] = ARM_PS_REGNUM
;
9996 record_buf
[1] = ARM_LR_REGNUM
;
9997 arm_insn_r
->reg_rec_count
= 2;
9999 /* Save SPSR also;how? */
10002 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10003 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10004 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10005 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10008 if (0 == insn_op1
|| 1 == insn_op1
)
10010 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10011 /* We dont do optimization for SMULW<y> where we
10013 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10014 record_buf
[1] = ARM_PS_REGNUM
;
10015 arm_insn_r
->reg_rec_count
= 2;
10017 else if (2 == insn_op1
)
10020 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10021 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10022 arm_insn_r
->reg_rec_count
= 2;
10024 else if (3 == insn_op1
)
10027 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10028 arm_insn_r
->reg_rec_count
= 1;
10034 /* MSR : immediate form. */
10037 /* CSPR is going to be changed. */
10038 record_buf
[0] = ARM_PS_REGNUM
;
10039 arm_insn_r
->reg_rec_count
= 1;
10041 else if (3 == insn_op1
)
10043 /* SPSR is going to be changed. */
10044 /* we need to get SPSR value, which is yet to be done */
10050 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10051 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10052 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10054 /* Handle load/store insn extension space. */
10056 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10057 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10058 && !INSN_RECORDED(arm_insn_r
))
10063 /* These insn, changes register and memory as well. */
10064 /* SWP or SWPB insn. */
10065 /* Get memory address given by Rn. */
10066 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10067 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10068 /* SWP insn ?, swaps word. */
10069 if (8 == arm_insn_r
->opcode
)
10071 record_buf_mem
[0] = 4;
10075 /* SWPB insn, swaps only byte. */
10076 record_buf_mem
[0] = 1;
10078 record_buf_mem
[1] = u_regval
;
10079 arm_insn_r
->mem_rec_count
= 1;
10080 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10081 arm_insn_r
->reg_rec_count
= 1;
10083 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10086 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10089 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10092 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10093 record_buf
[1] = record_buf
[0] + 1;
10094 arm_insn_r
->reg_rec_count
= 2;
10096 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10099 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10102 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10104 /* LDRH, LDRSB, LDRSH. */
10105 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10106 arm_insn_r
->reg_rec_count
= 1;
10111 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10112 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10113 && !INSN_RECORDED(arm_insn_r
))
10116 /* Handle coprocessor insn extension space. */
10119 /* To be done for ARMv5 and later; as of now we return -1. */
10123 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10124 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10129 /* Handling opcode 000 insns. */
10132 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10134 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10135 uint32_t record_buf
[8], record_buf_mem
[8];
10136 ULONGEST u_regval
[2] = {0};
10138 uint32_t reg_src1
= 0;
10139 uint32_t opcode1
= 0;
10141 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10142 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10143 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10145 if (!((opcode1
& 0x19) == 0x10))
10147 /* Data-processing (register) and Data-processing (register-shifted
10149 /* Out of 11 shifter operands mode, all the insn modifies destination
10150 register, which is specified by 13-16 decode. */
10151 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10152 record_buf
[1] = ARM_PS_REGNUM
;
10153 arm_insn_r
->reg_rec_count
= 2;
10155 else if ((arm_insn_r
->decode
< 8) && ((opcode1
& 0x19) == 0x10))
10157 /* Miscellaneous instructions */
10159 if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10160 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10162 /* Handle BLX, branch and link/exchange. */
10163 if (9 == arm_insn_r
->opcode
)
10165 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10166 and R14 stores the return address. */
10167 record_buf
[0] = ARM_PS_REGNUM
;
10168 record_buf
[1] = ARM_LR_REGNUM
;
10169 arm_insn_r
->reg_rec_count
= 2;
10172 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10174 /* Handle enhanced software breakpoint insn, BKPT. */
10175 /* CPSR is changed to be executed in ARM state, disabling normal
10176 interrupts, entering abort mode. */
10177 /* According to high vector configuration PC is set. */
10178 /* user hit breakpoint and type reverse, in
10179 that case, we need to go back with previous CPSR and
10180 Program Counter. */
10181 record_buf
[0] = ARM_PS_REGNUM
;
10182 record_buf
[1] = ARM_LR_REGNUM
;
10183 arm_insn_r
->reg_rec_count
= 2;
10185 /* Save SPSR also; how? */
10188 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10189 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10191 /* Handle BX, branch and link/exchange. */
10192 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10193 record_buf
[0] = ARM_PS_REGNUM
;
10194 arm_insn_r
->reg_rec_count
= 1;
10196 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10197 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10198 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10200 /* Count leading zeros: CLZ. */
10201 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10202 arm_insn_r
->reg_rec_count
= 1;
10204 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10205 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10206 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10207 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0))
10209 /* Handle MRS insn. */
10210 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10211 arm_insn_r
->reg_rec_count
= 1;
10214 else if (9 == arm_insn_r
->decode
&& opcode1
< 0x10)
10216 /* Multiply and multiply-accumulate */
10218 /* Handle multiply instructions. */
10219 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10220 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10222 /* Handle MLA and MUL. */
10223 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10224 record_buf
[1] = ARM_PS_REGNUM
;
10225 arm_insn_r
->reg_rec_count
= 2;
10227 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10229 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10230 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10231 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10232 record_buf
[2] = ARM_PS_REGNUM
;
10233 arm_insn_r
->reg_rec_count
= 3;
10236 else if (9 == arm_insn_r
->decode
&& opcode1
> 0x10)
10238 /* Synchronization primitives */
10240 /* Handling SWP, SWPB. */
10241 /* These insn, changes register and memory as well. */
10242 /* SWP or SWPB insn. */
10244 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10245 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10246 /* SWP insn ?, swaps word. */
10247 if (8 == arm_insn_r
->opcode
)
10249 record_buf_mem
[0] = 4;
10253 /* SWPB insn, swaps only byte. */
10254 record_buf_mem
[0] = 1;
10256 record_buf_mem
[1] = u_regval
[0];
10257 arm_insn_r
->mem_rec_count
= 1;
10258 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10259 arm_insn_r
->reg_rec_count
= 1;
10261 else if (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
10262 || 15 == arm_insn_r
->decode
)
10264 if ((opcode1
& 0x12) == 2)
10266 /* Extra load/store (unprivileged) */
10271 /* Extra load/store */
10272 switch (bits (arm_insn_r
->arm_insn
, 5, 6))
10275 if ((opcode1
& 0x05) == 0x0 || (opcode1
& 0x05) == 0x4)
10277 /* STRH (register), STRH (immediate) */
10278 arm_record_strx (arm_insn_r
, &record_buf
[0],
10279 &record_buf_mem
[0], ARM_RECORD_STRH
);
10281 else if ((opcode1
& 0x05) == 0x1)
10283 /* LDRH (register) */
10284 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10285 arm_insn_r
->reg_rec_count
= 1;
10287 if (bit (arm_insn_r
->arm_insn
, 21))
10289 /* Write back to Rn. */
10290 record_buf
[arm_insn_r
->reg_rec_count
++]
10291 = bits (arm_insn_r
->arm_insn
, 16, 19);
10294 else if ((opcode1
& 0x05) == 0x5)
10296 /* LDRH (immediate), LDRH (literal) */
10297 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10299 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10300 arm_insn_r
->reg_rec_count
= 1;
10304 /*LDRH (immediate) */
10305 if (bit (arm_insn_r
->arm_insn
, 21))
10307 /* Write back to Rn. */
10308 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10316 if ((opcode1
& 0x05) == 0x0)
10318 /* LDRD (register) */
10319 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10320 record_buf
[1] = record_buf
[0] + 1;
10321 arm_insn_r
->reg_rec_count
= 2;
10323 if (bit (arm_insn_r
->arm_insn
, 21))
10325 /* Write back to Rn. */
10326 record_buf
[arm_insn_r
->reg_rec_count
++]
10327 = bits (arm_insn_r
->arm_insn
, 16, 19);
10330 else if ((opcode1
& 0x05) == 0x1)
10332 /* LDRSB (register) */
10333 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10334 arm_insn_r
->reg_rec_count
= 1;
10336 if (bit (arm_insn_r
->arm_insn
, 21))
10338 /* Write back to Rn. */
10339 record_buf
[arm_insn_r
->reg_rec_count
++]
10340 = bits (arm_insn_r
->arm_insn
, 16, 19);
10343 else if ((opcode1
& 0x05) == 0x4 || (opcode1
& 0x05) == 0x5)
10345 /* LDRD (immediate), LDRD (literal), LDRSB (immediate),
10347 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10349 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10350 arm_insn_r
->reg_rec_count
= 1;
10354 /*LDRD (immediate), LDRSB (immediate) */
10355 if (bit (arm_insn_r
->arm_insn
, 21))
10357 /* Write back to Rn. */
10358 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10366 if ((opcode1
& 0x05) == 0x0)
10368 /* STRD (register) */
10369 arm_record_strx (arm_insn_r
, &record_buf
[0],
10370 &record_buf_mem
[0], ARM_RECORD_STRD
);
10372 else if ((opcode1
& 0x05) == 0x1)
10374 /* LDRSH (register) */
10375 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10376 arm_insn_r
->reg_rec_count
= 1;
10378 if (bit (arm_insn_r
->arm_insn
, 21))
10380 /* Write back to Rn. */
10381 record_buf
[arm_insn_r
->reg_rec_count
++]
10382 = bits (arm_insn_r
->arm_insn
, 16, 19);
10385 else if ((opcode1
& 0x05) == 0x4)
10387 /* STRD (immediate) */
10388 arm_record_strx (arm_insn_r
, &record_buf
[0],
10389 &record_buf_mem
[0], ARM_RECORD_STRD
);
10391 else if ((opcode1
& 0x05) == 0x5)
10393 /* LDRSH (immediate), LDRSH (literal) */
10394 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10395 arm_insn_r
->reg_rec_count
= 1;
10397 if (bit (arm_insn_r
->arm_insn
, 21))
10399 /* Write back to Rn. */
10400 record_buf
[arm_insn_r
->reg_rec_count
++]
10401 = bits (arm_insn_r
->arm_insn
, 16, 19);
10417 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10418 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10422 /* Handling opcode 001 insns. */
10425 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10427 uint32_t record_buf
[8], record_buf_mem
[8];
10429 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10430 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10432 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10433 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10434 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10437 /* Handle MSR insn. */
10438 if (9 == arm_insn_r
->opcode
)
10440 /* CSPR is going to be changed. */
10441 record_buf
[0] = ARM_PS_REGNUM
;
10442 arm_insn_r
->reg_rec_count
= 1;
10446 /* SPSR is going to be changed. */
10449 else if (arm_insn_r
->opcode
<= 15)
10451 /* Normal data processing insns. */
10452 /* Out of 11 shifter operands mode, all the insn modifies destination
10453 register, which is specified by 13-16 decode. */
10454 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10455 record_buf
[1] = ARM_PS_REGNUM
;
10456 arm_insn_r
->reg_rec_count
= 2;
10463 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10464 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10469 arm_record_media (insn_decode_record
*arm_insn_r
)
10471 uint32_t record_buf
[8];
10473 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10476 /* Parallel addition and subtraction, signed */
10478 /* Parallel addition and subtraction, unsigned */
10481 /* Packing, unpacking, saturation and reversal */
10483 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10485 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10491 /* Signed multiplies */
10493 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10494 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10496 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10498 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10499 else if (op1
== 0x4)
10500 record_buf
[arm_insn_r
->reg_rec_count
++]
10501 = bits (arm_insn_r
->arm_insn
, 12, 15);
10507 if (bit (arm_insn_r
->arm_insn
, 21)
10508 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10511 record_buf
[arm_insn_r
->reg_rec_count
++]
10512 = bits (arm_insn_r
->arm_insn
, 12, 15);
10514 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10515 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10517 /* USAD8 and USADA8 */
10518 record_buf
[arm_insn_r
->reg_rec_count
++]
10519 = bits (arm_insn_r
->arm_insn
, 16, 19);
10526 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10527 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10529 /* Permanently UNDEFINED */
10534 /* BFC, BFI and UBFX */
10535 record_buf
[arm_insn_r
->reg_rec_count
++]
10536 = bits (arm_insn_r
->arm_insn
, 12, 15);
10545 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10550 /* Handle ARM mode instructions with opcode 010. */
10553 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10555 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10557 uint32_t reg_base
, reg_dest
;
10558 uint32_t offset_12
, tgt_mem_addr
;
10559 uint32_t record_buf
[8], record_buf_mem
[8];
10560 unsigned char wback
;
10563 /* Calculate wback. */
10564 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10565 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10567 arm_insn_r
->reg_rec_count
= 0;
10568 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10570 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10572 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10575 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10576 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10578 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10579 preceeds a LDR instruction having R15 as reg_base, it
10580 emulates a branch and link instruction, and hence we need to save
10581 CPSR and PC as well. */
10582 if (ARM_PC_REGNUM
== reg_dest
)
10583 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10585 /* If wback is true, also save the base register, which is going to be
10588 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10592 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10594 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10595 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10597 /* Handle bit U. */
10598 if (bit (arm_insn_r
->arm_insn
, 23))
10600 /* U == 1: Add the offset. */
10601 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10605 /* U == 0: subtract the offset. */
10606 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10609 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10611 if (bit (arm_insn_r
->arm_insn
, 22))
10613 /* STRB and STRBT: 1 byte. */
10614 record_buf_mem
[0] = 1;
10618 /* STR and STRT: 4 bytes. */
10619 record_buf_mem
[0] = 4;
10622 /* Handle bit P. */
10623 if (bit (arm_insn_r
->arm_insn
, 24))
10624 record_buf_mem
[1] = tgt_mem_addr
;
10626 record_buf_mem
[1] = (uint32_t) u_regval
;
10628 arm_insn_r
->mem_rec_count
= 1;
10630 /* If wback is true, also save the base register, which is going to be
10633 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10636 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10637 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10641 /* Handling opcode 011 insns. */
10644 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10646 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10648 uint32_t shift_imm
= 0;
10649 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10650 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10651 uint32_t record_buf
[8], record_buf_mem
[8];
10654 ULONGEST u_regval
[2];
10656 if (bit (arm_insn_r
->arm_insn
, 4))
10657 return arm_record_media (arm_insn_r
);
10659 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10660 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10662 /* Handle enhanced store insns and LDRD DSP insn,
10663 order begins according to addressing modes for store insns
10667 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10669 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10670 /* LDR insn has a capability to do branching, if
10671 MOV LR, PC is precedded by LDR insn having Rn as R15
10672 in that case, it emulates branch and link insn, and hence we
10673 need to save CSPR and PC as well. */
10674 if (15 != reg_dest
)
10676 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10677 arm_insn_r
->reg_rec_count
= 1;
10681 record_buf
[0] = reg_dest
;
10682 record_buf
[1] = ARM_PS_REGNUM
;
10683 arm_insn_r
->reg_rec_count
= 2;
10688 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10690 /* Store insn, register offset and register pre-indexed,
10691 register post-indexed. */
10693 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10695 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10696 regcache_raw_read_unsigned (reg_cache
, reg_src1
10698 regcache_raw_read_unsigned (reg_cache
, reg_src2
10700 if (15 == reg_src2
)
10702 /* If R15 was used as Rn, hence current PC+8. */
10703 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10704 u_regval
[0] = u_regval
[0] + 8;
10706 /* Calculate target store address, Rn +/- Rm, register offset. */
10708 if (bit (arm_insn_r
->arm_insn
, 23))
10710 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10714 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10717 switch (arm_insn_r
->opcode
)
10731 record_buf_mem
[0] = 4;
10746 record_buf_mem
[0] = 1;
10750 gdb_assert_not_reached ("no decoding pattern found");
10753 record_buf_mem
[1] = tgt_mem_addr
;
10754 arm_insn_r
->mem_rec_count
= 1;
10756 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10757 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10758 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10759 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10760 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10761 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10764 /* Rn is going to be changed in pre-indexed mode and
10765 post-indexed mode as well. */
10766 record_buf
[0] = reg_src2
;
10767 arm_insn_r
->reg_rec_count
= 1;
10772 /* Store insn, scaled register offset; scaled pre-indexed. */
10773 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10775 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10777 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10778 /* Get shift_imm. */
10779 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10780 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10781 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10782 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10783 /* Offset_12 used as shift. */
10787 /* Offset_12 used as index. */
10788 offset_12
= u_regval
[0] << shift_imm
;
10792 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10798 if (bit (u_regval
[0], 31))
10800 offset_12
= 0xFFFFFFFF;
10809 /* This is arithmetic shift. */
10810 offset_12
= s_word
>> shift_imm
;
10817 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10819 /* Get C flag value and shift it by 31. */
10820 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10821 | (u_regval
[0]) >> 1);
10825 offset_12
= (u_regval
[0] >> shift_imm
) \
10827 (sizeof(uint32_t) - shift_imm
));
10832 gdb_assert_not_reached ("no decoding pattern found");
10836 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10838 if (bit (arm_insn_r
->arm_insn
, 23))
10840 tgt_mem_addr
= u_regval
[1] + offset_12
;
10844 tgt_mem_addr
= u_regval
[1] - offset_12
;
10847 switch (arm_insn_r
->opcode
)
10861 record_buf_mem
[0] = 4;
10876 record_buf_mem
[0] = 1;
10880 gdb_assert_not_reached ("no decoding pattern found");
10883 record_buf_mem
[1] = tgt_mem_addr
;
10884 arm_insn_r
->mem_rec_count
= 1;
10886 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10887 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10888 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10889 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10890 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10891 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10894 /* Rn is going to be changed in register scaled pre-indexed
10895 mode,and scaled post indexed mode. */
10896 record_buf
[0] = reg_src2
;
10897 arm_insn_r
->reg_rec_count
= 1;
10902 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10903 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10907 /* Handle ARM mode instructions with opcode 100. */
10910 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10912 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10913 uint32_t register_count
= 0, register_bits
;
10914 uint32_t reg_base
, addr_mode
;
10915 uint32_t record_buf
[24], record_buf_mem
[48];
10919 /* Fetch the list of registers. */
10920 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10921 arm_insn_r
->reg_rec_count
= 0;
10923 /* Fetch the base register that contains the address we are loading data
10925 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10927 /* Calculate wback. */
10928 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10930 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10932 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10934 /* Find out which registers are going to be loaded from memory. */
10935 while (register_bits
)
10937 if (register_bits
& 0x00000001)
10938 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10939 register_bits
= register_bits
>> 1;
10944 /* If wback is true, also save the base register, which is going to be
10947 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10949 /* Save the CPSR register. */
10950 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10954 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10956 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10958 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10960 /* Find out how many registers are going to be stored to memory. */
10961 while (register_bits
)
10963 if (register_bits
& 0x00000001)
10965 register_bits
= register_bits
>> 1;
10970 /* STMDA (STMED): Decrement after. */
10972 record_buf_mem
[1] = (uint32_t) u_regval
10973 - register_count
* INT_REGISTER_SIZE
+ 4;
10975 /* STM (STMIA, STMEA): Increment after. */
10977 record_buf_mem
[1] = (uint32_t) u_regval
;
10979 /* STMDB (STMFD): Decrement before. */
10981 record_buf_mem
[1] = (uint32_t) u_regval
10982 - register_count
* INT_REGISTER_SIZE
;
10984 /* STMIB (STMFA): Increment before. */
10986 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
10989 gdb_assert_not_reached ("no decoding pattern found");
10993 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
10994 arm_insn_r
->mem_rec_count
= 1;
10996 /* If wback is true, also save the base register, which is going to be
10999 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11002 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11003 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11007 /* Handling opcode 101 insns. */
11010 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11012 uint32_t record_buf
[8];
11014 /* Handle B, BL, BLX(1) insns. */
11015 /* B simply branches so we do nothing here. */
11016 /* Note: BLX(1) doesnt fall here but instead it falls into
11017 extension space. */
11018 if (bit (arm_insn_r
->arm_insn
, 24))
11020 record_buf
[0] = ARM_LR_REGNUM
;
11021 arm_insn_r
->reg_rec_count
= 1;
11024 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11030 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11032 printf_unfiltered (_("Process record does not support instruction "
11033 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11034 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11039 /* Record handler for vector data transfer instructions. */
11042 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11044 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11045 uint32_t record_buf
[4];
11047 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11048 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11049 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11050 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11051 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11053 /* Handle VMOV instruction. */
11054 if (bit_l
&& bit_c
)
11056 record_buf
[0] = reg_t
;
11057 arm_insn_r
->reg_rec_count
= 1;
11059 else if (bit_l
&& !bit_c
)
11061 /* Handle VMOV instruction. */
11062 if (bits_a
== 0x00)
11064 record_buf
[0] = reg_t
;
11065 arm_insn_r
->reg_rec_count
= 1;
11067 /* Handle VMRS instruction. */
11068 else if (bits_a
== 0x07)
11071 reg_t
= ARM_PS_REGNUM
;
11073 record_buf
[0] = reg_t
;
11074 arm_insn_r
->reg_rec_count
= 1;
11077 else if (!bit_l
&& !bit_c
)
11079 /* Handle VMOV instruction. */
11080 if (bits_a
== 0x00)
11082 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11084 arm_insn_r
->reg_rec_count
= 1;
11086 /* Handle VMSR instruction. */
11087 else if (bits_a
== 0x07)
11089 record_buf
[0] = ARM_FPSCR_REGNUM
;
11090 arm_insn_r
->reg_rec_count
= 1;
11093 else if (!bit_l
&& bit_c
)
11095 /* Handle VMOV instruction. */
11096 if (!(bits_a
& 0x04))
11098 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11100 arm_insn_r
->reg_rec_count
= 1;
11102 /* Handle VDUP instruction. */
11105 if (bit (arm_insn_r
->arm_insn
, 21))
11107 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11108 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11109 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11110 arm_insn_r
->reg_rec_count
= 2;
11114 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11115 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11116 arm_insn_r
->reg_rec_count
= 1;
11121 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11125 /* Record handler for extension register load/store instructions. */
11128 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11130 uint32_t opcode
, single_reg
;
11131 uint8_t op_vldm_vstm
;
11132 uint32_t record_buf
[8], record_buf_mem
[128];
11133 ULONGEST u_regval
= 0;
11135 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11137 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11138 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11139 op_vldm_vstm
= opcode
& 0x1b;
11141 /* Handle VMOV instructions. */
11142 if ((opcode
& 0x1e) == 0x04)
11144 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11146 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11147 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11148 arm_insn_r
->reg_rec_count
= 2;
11152 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11153 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11157 /* The first S register number m is REG_M:M (M is bit 5),
11158 the corresponding D register number is REG_M:M / 2, which
11160 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11161 /* The second S register number is REG_M:M + 1, the
11162 corresponding D register number is (REG_M:M + 1) / 2.
11163 IOW, if bit M is 1, the first and second S registers
11164 are mapped to different D registers, otherwise, they are
11165 in the same D register. */
11168 record_buf
[arm_insn_r
->reg_rec_count
++]
11169 = ARM_D0_REGNUM
+ reg_m
+ 1;
11174 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11175 arm_insn_r
->reg_rec_count
= 1;
11179 /* Handle VSTM and VPUSH instructions. */
11180 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11181 || op_vldm_vstm
== 0x12)
11183 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11184 uint32_t memory_index
= 0;
11186 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11187 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11188 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11189 imm_off32
= imm_off8
<< 2;
11190 memory_count
= imm_off8
;
11192 if (bit (arm_insn_r
->arm_insn
, 23))
11193 start_address
= u_regval
;
11195 start_address
= u_regval
- imm_off32
;
11197 if (bit (arm_insn_r
->arm_insn
, 21))
11199 record_buf
[0] = reg_rn
;
11200 arm_insn_r
->reg_rec_count
= 1;
11203 while (memory_count
> 0)
11207 record_buf_mem
[memory_index
] = 4;
11208 record_buf_mem
[memory_index
+ 1] = start_address
;
11209 start_address
= start_address
+ 4;
11210 memory_index
= memory_index
+ 2;
11214 record_buf_mem
[memory_index
] = 4;
11215 record_buf_mem
[memory_index
+ 1] = start_address
;
11216 record_buf_mem
[memory_index
+ 2] = 4;
11217 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11218 start_address
= start_address
+ 8;
11219 memory_index
= memory_index
+ 4;
11223 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11225 /* Handle VLDM instructions. */
11226 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11227 || op_vldm_vstm
== 0x13)
11229 uint32_t reg_count
, reg_vd
;
11230 uint32_t reg_index
= 0;
11231 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11233 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11234 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11236 /* REG_VD is the first D register number. If the instruction
11237 loads memory to S registers (SINGLE_REG is TRUE), the register
11238 number is (REG_VD << 1 | bit D), so the corresponding D
11239 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11241 reg_vd
= reg_vd
| (bit_d
<< 4);
11243 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11244 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11246 /* If the instruction loads memory to D register, REG_COUNT should
11247 be divided by 2, according to the ARM Architecture Reference
11248 Manual. If the instruction loads memory to S register, divide by
11249 2 as well because two S registers are mapped to D register. */
11250 reg_count
= reg_count
/ 2;
11251 if (single_reg
&& bit_d
)
11253 /* Increase the register count if S register list starts from
11254 an odd number (bit d is one). */
11258 while (reg_count
> 0)
11260 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11263 arm_insn_r
->reg_rec_count
= reg_index
;
11265 /* VSTR Vector store register. */
11266 else if ((opcode
& 0x13) == 0x10)
11268 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11269 uint32_t memory_index
= 0;
11271 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11272 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11273 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11274 imm_off32
= imm_off8
<< 2;
11276 if (bit (arm_insn_r
->arm_insn
, 23))
11277 start_address
= u_regval
+ imm_off32
;
11279 start_address
= u_regval
- imm_off32
;
11283 record_buf_mem
[memory_index
] = 4;
11284 record_buf_mem
[memory_index
+ 1] = start_address
;
11285 arm_insn_r
->mem_rec_count
= 1;
11289 record_buf_mem
[memory_index
] = 4;
11290 record_buf_mem
[memory_index
+ 1] = start_address
;
11291 record_buf_mem
[memory_index
+ 2] = 4;
11292 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11293 arm_insn_r
->mem_rec_count
= 2;
11296 /* VLDR Vector load register. */
11297 else if ((opcode
& 0x13) == 0x11)
11299 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11303 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11304 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11308 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11309 /* Record register D rather than pseudo register S. */
11310 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11312 arm_insn_r
->reg_rec_count
= 1;
11315 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11316 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11320 /* Record handler for arm/thumb mode VFP data processing instructions. */
11323 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11325 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11326 uint32_t record_buf
[4];
11327 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11328 enum insn_types curr_insn_type
= INSN_INV
;
11330 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11331 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11332 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11333 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11334 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11335 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11336 /* Mask off the "D" bit. */
11337 opc1
= opc1
& ~0x04;
11339 /* Handle VMLA, VMLS. */
11342 if (bit (arm_insn_r
->arm_insn
, 10))
11344 if (bit (arm_insn_r
->arm_insn
, 6))
11345 curr_insn_type
= INSN_T0
;
11347 curr_insn_type
= INSN_T1
;
11352 curr_insn_type
= INSN_T1
;
11354 curr_insn_type
= INSN_T2
;
11357 /* Handle VNMLA, VNMLS, VNMUL. */
11358 else if (opc1
== 0x01)
11361 curr_insn_type
= INSN_T1
;
11363 curr_insn_type
= INSN_T2
;
11366 else if (opc1
== 0x02 && !(opc3
& 0x01))
11368 if (bit (arm_insn_r
->arm_insn
, 10))
11370 if (bit (arm_insn_r
->arm_insn
, 6))
11371 curr_insn_type
= INSN_T0
;
11373 curr_insn_type
= INSN_T1
;
11378 curr_insn_type
= INSN_T1
;
11380 curr_insn_type
= INSN_T2
;
11383 /* Handle VADD, VSUB. */
11384 else if (opc1
== 0x03)
11386 if (!bit (arm_insn_r
->arm_insn
, 9))
11388 if (bit (arm_insn_r
->arm_insn
, 6))
11389 curr_insn_type
= INSN_T0
;
11391 curr_insn_type
= INSN_T1
;
11396 curr_insn_type
= INSN_T1
;
11398 curr_insn_type
= INSN_T2
;
11402 else if (opc1
== 0x08)
11405 curr_insn_type
= INSN_T1
;
11407 curr_insn_type
= INSN_T2
;
11409 /* Handle all other vfp data processing instructions. */
11410 else if (opc1
== 0x0b)
11413 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11415 if (bit (arm_insn_r
->arm_insn
, 4))
11417 if (bit (arm_insn_r
->arm_insn
, 6))
11418 curr_insn_type
= INSN_T0
;
11420 curr_insn_type
= INSN_T1
;
11425 curr_insn_type
= INSN_T1
;
11427 curr_insn_type
= INSN_T2
;
11430 /* Handle VNEG and VABS. */
11431 else if ((opc2
== 0x01 && opc3
== 0x01)
11432 || (opc2
== 0x00 && opc3
== 0x03))
11434 if (!bit (arm_insn_r
->arm_insn
, 11))
11436 if (bit (arm_insn_r
->arm_insn
, 6))
11437 curr_insn_type
= INSN_T0
;
11439 curr_insn_type
= INSN_T1
;
11444 curr_insn_type
= INSN_T1
;
11446 curr_insn_type
= INSN_T2
;
11449 /* Handle VSQRT. */
11450 else if (opc2
== 0x01 && opc3
== 0x03)
11453 curr_insn_type
= INSN_T1
;
11455 curr_insn_type
= INSN_T2
;
11458 else if (opc2
== 0x07 && opc3
== 0x03)
11461 curr_insn_type
= INSN_T1
;
11463 curr_insn_type
= INSN_T2
;
11465 else if (opc3
& 0x01)
11468 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11470 if (!bit (arm_insn_r
->arm_insn
, 18))
11471 curr_insn_type
= INSN_T2
;
11475 curr_insn_type
= INSN_T1
;
11477 curr_insn_type
= INSN_T2
;
11481 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11484 curr_insn_type
= INSN_T1
;
11486 curr_insn_type
= INSN_T2
;
11488 /* Handle VCVTB, VCVTT. */
11489 else if ((opc2
& 0x0e) == 0x02)
11490 curr_insn_type
= INSN_T2
;
11491 /* Handle VCMP, VCMPE. */
11492 else if ((opc2
& 0x0e) == 0x04)
11493 curr_insn_type
= INSN_T3
;
11497 switch (curr_insn_type
)
11500 reg_vd
= reg_vd
| (bit_d
<< 4);
11501 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11502 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11503 arm_insn_r
->reg_rec_count
= 2;
11507 reg_vd
= reg_vd
| (bit_d
<< 4);
11508 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11509 arm_insn_r
->reg_rec_count
= 1;
11513 reg_vd
= (reg_vd
<< 1) | bit_d
;
11514 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11515 arm_insn_r
->reg_rec_count
= 1;
11519 record_buf
[0] = ARM_FPSCR_REGNUM
;
11520 arm_insn_r
->reg_rec_count
= 1;
11524 gdb_assert_not_reached ("no decoding pattern found");
11528 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11532 /* Handling opcode 110 insns. */
11535 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11537 uint32_t op1
, op1_ebit
, coproc
;
11539 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11540 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11541 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11543 if ((coproc
& 0x0e) == 0x0a)
11545 /* Handle extension register ld/st instructions. */
11547 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11549 /* 64-bit transfers between arm core and extension registers. */
11550 if ((op1
& 0x3e) == 0x04)
11551 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11555 /* Handle coprocessor ld/st instructions. */
11560 return arm_record_unsupported_insn (arm_insn_r
);
11563 return arm_record_unsupported_insn (arm_insn_r
);
11566 /* Move to coprocessor from two arm core registers. */
11568 return arm_record_unsupported_insn (arm_insn_r
);
11570 /* Move to two arm core registers from coprocessor. */
11575 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11576 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11577 arm_insn_r
->reg_rec_count
= 2;
11579 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11583 return arm_record_unsupported_insn (arm_insn_r
);
11586 /* Handling opcode 111 insns. */
11589 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11591 uint32_t op
, op1_ebit
, coproc
, bits_24_25
;
11592 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11593 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11595 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11596 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11597 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11598 op
= bit (arm_insn_r
->arm_insn
, 4);
11599 bits_24_25
= bits (arm_insn_r
->arm_insn
, 24, 25);
11601 /* Handle arm SWI/SVC system call instructions. */
11602 if (bits_24_25
== 0x3)
11604 if (tdep
->arm_syscall_record
!= NULL
)
11606 ULONGEST svc_operand
, svc_number
;
11608 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11610 if (svc_operand
) /* OABI. */
11611 svc_number
= svc_operand
- 0x900000;
11613 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11615 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11619 printf_unfiltered (_("no syscall record support\n"));
11623 else if (bits_24_25
== 0x02)
11627 if ((coproc
& 0x0e) == 0x0a)
11629 /* 8, 16, and 32-bit transfer */
11630 return arm_record_vdata_transfer_insn (arm_insn_r
);
11637 uint32_t record_buf
[1];
11639 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11640 if (record_buf
[0] == 15)
11641 record_buf
[0] = ARM_PS_REGNUM
;
11643 arm_insn_r
->reg_rec_count
= 1;
11644 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11657 if ((coproc
& 0x0e) == 0x0a)
11659 /* VFP data-processing instructions. */
11660 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11671 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11675 if ((coproc
& 0x0e) != 0x0a)
11681 else if (op1
== 4 || op1
== 5)
11683 if ((coproc
& 0x0e) == 0x0a)
11685 /* 64-bit transfers between ARM core and extension */
11694 else if (op1
== 0 || op1
== 1)
11701 if ((coproc
& 0x0e) == 0x0a)
11703 /* Extension register load/store */
11707 /* STC, STC2, LDC, LDC2 */
11716 /* Handling opcode 000 insns. */
11719 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11721 uint32_t record_buf
[8];
11722 uint32_t reg_src1
= 0;
11724 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11726 record_buf
[0] = ARM_PS_REGNUM
;
11727 record_buf
[1] = reg_src1
;
11728 thumb_insn_r
->reg_rec_count
= 2;
11730 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11736 /* Handling opcode 001 insns. */
11739 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11741 uint32_t record_buf
[8];
11742 uint32_t reg_src1
= 0;
11744 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11746 record_buf
[0] = ARM_PS_REGNUM
;
11747 record_buf
[1] = reg_src1
;
11748 thumb_insn_r
->reg_rec_count
= 2;
11750 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11755 /* Handling opcode 010 insns. */
11758 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11760 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11761 uint32_t record_buf
[8], record_buf_mem
[8];
11763 uint32_t reg_src1
= 0, reg_src2
= 0;
11764 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11766 ULONGEST u_regval
[2] = {0};
11768 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11770 if (bit (thumb_insn_r
->arm_insn
, 12))
11772 /* Handle load/store register offset. */
11773 uint32_t opB
= bits (thumb_insn_r
->arm_insn
, 9, 11);
11775 if (in_inclusive_range (opB
, 4U, 7U))
11777 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11778 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11779 record_buf
[0] = reg_src1
;
11780 thumb_insn_r
->reg_rec_count
= 1;
11782 else if (in_inclusive_range (opB
, 0U, 2U))
11784 /* STR(2), STRB(2), STRH(2) . */
11785 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11786 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11787 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11788 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11790 record_buf_mem
[0] = 4; /* STR (2). */
11792 record_buf_mem
[0] = 1; /* STRB (2). */
11794 record_buf_mem
[0] = 2; /* STRH (2). */
11795 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11796 thumb_insn_r
->mem_rec_count
= 1;
11799 else if (bit (thumb_insn_r
->arm_insn
, 11))
11801 /* Handle load from literal pool. */
11803 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11804 record_buf
[0] = reg_src1
;
11805 thumb_insn_r
->reg_rec_count
= 1;
11809 /* Special data instructions and branch and exchange */
11810 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11811 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11812 if ((3 == opcode2
) && (!opcode3
))
11814 /* Branch with exchange. */
11815 record_buf
[0] = ARM_PS_REGNUM
;
11816 thumb_insn_r
->reg_rec_count
= 1;
11820 /* Format 8; special data processing insns. */
11821 record_buf
[0] = ARM_PS_REGNUM
;
11822 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11823 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11824 thumb_insn_r
->reg_rec_count
= 2;
11829 /* Format 5; data processing insns. */
11830 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11831 if (bit (thumb_insn_r
->arm_insn
, 7))
11833 reg_src1
= reg_src1
+ 8;
11835 record_buf
[0] = ARM_PS_REGNUM
;
11836 record_buf
[1] = reg_src1
;
11837 thumb_insn_r
->reg_rec_count
= 2;
11840 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11841 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11847 /* Handling opcode 001 insns. */
11850 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11852 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11853 uint32_t record_buf
[8], record_buf_mem
[8];
11855 uint32_t reg_src1
= 0;
11856 uint32_t opcode
= 0, immed_5
= 0;
11858 ULONGEST u_regval
= 0;
11860 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11865 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11866 record_buf
[0] = reg_src1
;
11867 thumb_insn_r
->reg_rec_count
= 1;
11872 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11873 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11874 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11875 record_buf_mem
[0] = 4;
11876 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11877 thumb_insn_r
->mem_rec_count
= 1;
11880 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11881 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11887 /* Handling opcode 100 insns. */
11890 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11892 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11893 uint32_t record_buf
[8], record_buf_mem
[8];
11895 uint32_t reg_src1
= 0;
11896 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11898 ULONGEST u_regval
= 0;
11900 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11905 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11906 record_buf
[0] = reg_src1
;
11907 thumb_insn_r
->reg_rec_count
= 1;
11909 else if (1 == opcode
)
11912 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11913 record_buf
[0] = reg_src1
;
11914 thumb_insn_r
->reg_rec_count
= 1;
11916 else if (2 == opcode
)
11919 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11920 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11921 record_buf_mem
[0] = 4;
11922 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11923 thumb_insn_r
->mem_rec_count
= 1;
11925 else if (0 == opcode
)
11928 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11929 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11930 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11931 record_buf_mem
[0] = 2;
11932 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11933 thumb_insn_r
->mem_rec_count
= 1;
11936 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11937 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11943 /* Handling opcode 101 insns. */
11946 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11948 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11950 uint32_t opcode
= 0;
11951 uint32_t register_bits
= 0, register_count
= 0;
11952 uint32_t index
= 0, start_address
= 0;
11953 uint32_t record_buf
[24], record_buf_mem
[48];
11956 ULONGEST u_regval
= 0;
11958 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11960 if (opcode
== 0 || opcode
== 1)
11962 /* ADR and ADD (SP plus immediate) */
11964 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11965 record_buf
[0] = reg_src1
;
11966 thumb_insn_r
->reg_rec_count
= 1;
11970 /* Miscellaneous 16-bit instructions */
11971 uint32_t opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 11);
11976 /* SETEND and CPS */
11979 /* ADD/SUB (SP plus immediate) */
11980 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11981 record_buf
[0] = ARM_SP_REGNUM
;
11982 thumb_insn_r
->reg_rec_count
= 1;
11984 case 1: /* fall through */
11985 case 3: /* fall through */
11986 case 9: /* fall through */
11991 /* SXTH, SXTB, UXTH, UXTB */
11992 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
11993 thumb_insn_r
->reg_rec_count
= 1;
11995 case 4: /* fall through */
11998 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11999 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12000 while (register_bits
)
12002 if (register_bits
& 0x00000001)
12004 register_bits
= register_bits
>> 1;
12006 start_address
= u_regval
- \
12007 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12008 thumb_insn_r
->mem_rec_count
= register_count
;
12009 while (register_count
)
12011 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12012 record_buf_mem
[(register_count
* 2) - 2] = 4;
12013 start_address
= start_address
+ 4;
12016 record_buf
[0] = ARM_SP_REGNUM
;
12017 thumb_insn_r
->reg_rec_count
= 1;
12020 /* REV, REV16, REVSH */
12021 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
12022 thumb_insn_r
->reg_rec_count
= 1;
12024 case 12: /* fall through */
12027 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12028 while (register_bits
)
12030 if (register_bits
& 0x00000001)
12031 record_buf
[index
++] = register_count
;
12032 register_bits
= register_bits
>> 1;
12035 record_buf
[index
++] = ARM_PS_REGNUM
;
12036 record_buf
[index
++] = ARM_SP_REGNUM
;
12037 thumb_insn_r
->reg_rec_count
= index
;
12041 /* Handle enhanced software breakpoint insn, BKPT. */
12042 /* CPSR is changed to be executed in ARM state, disabling normal
12043 interrupts, entering abort mode. */
12044 /* According to high vector configuration PC is set. */
12045 /* User hits breakpoint and type reverse, in that case, we need to go back with
12046 previous CPSR and Program Counter. */
12047 record_buf
[0] = ARM_PS_REGNUM
;
12048 record_buf
[1] = ARM_LR_REGNUM
;
12049 thumb_insn_r
->reg_rec_count
= 2;
12050 /* We need to save SPSR value, which is not yet done. */
12051 printf_unfiltered (_("Process record does not support instruction "
12052 "0x%0x at address %s.\n"),
12053 thumb_insn_r
->arm_insn
,
12054 paddress (thumb_insn_r
->gdbarch
,
12055 thumb_insn_r
->this_addr
));
12059 /* If-Then, and hints */
12066 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12067 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12073 /* Handling opcode 110 insns. */
12076 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12078 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12079 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12081 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12082 uint32_t reg_src1
= 0;
12083 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12084 uint32_t index
= 0, start_address
= 0;
12085 uint32_t record_buf
[24], record_buf_mem
[48];
12087 ULONGEST u_regval
= 0;
12089 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12090 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12096 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12098 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12099 while (register_bits
)
12101 if (register_bits
& 0x00000001)
12102 record_buf
[index
++] = register_count
;
12103 register_bits
= register_bits
>> 1;
12106 record_buf
[index
++] = reg_src1
;
12107 thumb_insn_r
->reg_rec_count
= index
;
12109 else if (0 == opcode2
)
12111 /* It handles both STMIA. */
12112 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12114 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12115 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12116 while (register_bits
)
12118 if (register_bits
& 0x00000001)
12120 register_bits
= register_bits
>> 1;
12122 start_address
= u_regval
;
12123 thumb_insn_r
->mem_rec_count
= register_count
;
12124 while (register_count
)
12126 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12127 record_buf_mem
[(register_count
* 2) - 2] = 4;
12128 start_address
= start_address
+ 4;
12132 else if (0x1F == opcode1
)
12134 /* Handle arm syscall insn. */
12135 if (tdep
->arm_syscall_record
!= NULL
)
12137 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12138 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12142 printf_unfiltered (_("no syscall record support\n"));
12147 /* B (1), conditional branch is automatically taken care in process_record,
12148 as PC is saved there. */
12150 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12151 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12157 /* Handling opcode 111 insns. */
12160 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12162 uint32_t record_buf
[8];
12163 uint32_t bits_h
= 0;
12165 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12167 if (2 == bits_h
|| 3 == bits_h
)
12170 record_buf
[0] = ARM_LR_REGNUM
;
12171 thumb_insn_r
->reg_rec_count
= 1;
12173 else if (1 == bits_h
)
12176 record_buf
[0] = ARM_PS_REGNUM
;
12177 record_buf
[1] = ARM_LR_REGNUM
;
12178 thumb_insn_r
->reg_rec_count
= 2;
12181 /* B(2) is automatically taken care in process_record, as PC is
12184 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12189 /* Handler for thumb2 load/store multiple instructions. */
12192 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12194 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12196 uint32_t reg_rn
, op
;
12197 uint32_t register_bits
= 0, register_count
= 0;
12198 uint32_t index
= 0, start_address
= 0;
12199 uint32_t record_buf
[24], record_buf_mem
[48];
12201 ULONGEST u_regval
= 0;
12203 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12204 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12206 if (0 == op
|| 3 == op
)
12208 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12210 /* Handle RFE instruction. */
12211 record_buf
[0] = ARM_PS_REGNUM
;
12212 thumb2_insn_r
->reg_rec_count
= 1;
12216 /* Handle SRS instruction after reading banked SP. */
12217 return arm_record_unsupported_insn (thumb2_insn_r
);
12220 else if (1 == op
|| 2 == op
)
12222 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12224 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12225 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12226 while (register_bits
)
12228 if (register_bits
& 0x00000001)
12229 record_buf
[index
++] = register_count
;
12232 register_bits
= register_bits
>> 1;
12234 record_buf
[index
++] = reg_rn
;
12235 record_buf
[index
++] = ARM_PS_REGNUM
;
12236 thumb2_insn_r
->reg_rec_count
= index
;
12240 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12241 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12242 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12243 while (register_bits
)
12245 if (register_bits
& 0x00000001)
12248 register_bits
= register_bits
>> 1;
12253 /* Start address calculation for LDMDB/LDMEA. */
12254 start_address
= u_regval
;
12258 /* Start address calculation for LDMDB/LDMEA. */
12259 start_address
= u_regval
- register_count
* 4;
12262 thumb2_insn_r
->mem_rec_count
= register_count
;
12263 while (register_count
)
12265 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12266 record_buf_mem
[register_count
* 2 - 2] = 4;
12267 start_address
= start_address
+ 4;
12270 record_buf
[0] = reg_rn
;
12271 record_buf
[1] = ARM_PS_REGNUM
;
12272 thumb2_insn_r
->reg_rec_count
= 2;
12276 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12278 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12280 return ARM_RECORD_SUCCESS
;
12283 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12287 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12289 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12291 uint32_t reg_rd
, reg_rn
, offset_imm
;
12292 uint32_t reg_dest1
, reg_dest2
;
12293 uint32_t address
, offset_addr
;
12294 uint32_t record_buf
[8], record_buf_mem
[8];
12295 uint32_t op1
, op2
, op3
;
12297 ULONGEST u_regval
[2];
12299 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12300 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12301 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12303 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12305 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12307 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12308 record_buf
[0] = reg_dest1
;
12309 record_buf
[1] = ARM_PS_REGNUM
;
12310 thumb2_insn_r
->reg_rec_count
= 2;
12313 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12315 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12316 record_buf
[2] = reg_dest2
;
12317 thumb2_insn_r
->reg_rec_count
= 3;
12322 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12323 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12325 if (0 == op1
&& 0 == op2
)
12327 /* Handle STREX. */
12328 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12329 address
= u_regval
[0] + (offset_imm
* 4);
12330 record_buf_mem
[0] = 4;
12331 record_buf_mem
[1] = address
;
12332 thumb2_insn_r
->mem_rec_count
= 1;
12333 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12334 record_buf
[0] = reg_rd
;
12335 thumb2_insn_r
->reg_rec_count
= 1;
12337 else if (1 == op1
&& 0 == op2
)
12339 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12340 record_buf
[0] = reg_rd
;
12341 thumb2_insn_r
->reg_rec_count
= 1;
12342 address
= u_regval
[0];
12343 record_buf_mem
[1] = address
;
12347 /* Handle STREXB. */
12348 record_buf_mem
[0] = 1;
12349 thumb2_insn_r
->mem_rec_count
= 1;
12353 /* Handle STREXH. */
12354 record_buf_mem
[0] = 2 ;
12355 thumb2_insn_r
->mem_rec_count
= 1;
12359 /* Handle STREXD. */
12360 address
= u_regval
[0];
12361 record_buf_mem
[0] = 4;
12362 record_buf_mem
[2] = 4;
12363 record_buf_mem
[3] = address
+ 4;
12364 thumb2_insn_r
->mem_rec_count
= 2;
12369 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12371 if (bit (thumb2_insn_r
->arm_insn
, 24))
12373 if (bit (thumb2_insn_r
->arm_insn
, 23))
12374 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12376 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12378 address
= offset_addr
;
12381 address
= u_regval
[0];
12383 record_buf_mem
[0] = 4;
12384 record_buf_mem
[1] = address
;
12385 record_buf_mem
[2] = 4;
12386 record_buf_mem
[3] = address
+ 4;
12387 thumb2_insn_r
->mem_rec_count
= 2;
12388 record_buf
[0] = reg_rn
;
12389 thumb2_insn_r
->reg_rec_count
= 1;
12393 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12395 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12397 return ARM_RECORD_SUCCESS
;
12400 /* Handler for thumb2 data processing (shift register and modified immediate)
12404 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12406 uint32_t reg_rd
, op
;
12407 uint32_t record_buf
[8];
12409 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12410 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12412 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12414 record_buf
[0] = ARM_PS_REGNUM
;
12415 thumb2_insn_r
->reg_rec_count
= 1;
12419 record_buf
[0] = reg_rd
;
12420 record_buf
[1] = ARM_PS_REGNUM
;
12421 thumb2_insn_r
->reg_rec_count
= 2;
12424 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12426 return ARM_RECORD_SUCCESS
;
12429 /* Generic handler for thumb2 instructions which effect destination and PS
12433 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12436 uint32_t record_buf
[8];
12438 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12440 record_buf
[0] = reg_rd
;
12441 record_buf
[1] = ARM_PS_REGNUM
;
12442 thumb2_insn_r
->reg_rec_count
= 2;
12444 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12446 return ARM_RECORD_SUCCESS
;
12449 /* Handler for thumb2 branch and miscellaneous control instructions. */
12452 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12454 uint32_t op
, op1
, op2
;
12455 uint32_t record_buf
[8];
12457 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12458 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12459 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12461 /* Handle MSR insn. */
12462 if (!(op1
& 0x2) && 0x38 == op
)
12466 /* CPSR is going to be changed. */
12467 record_buf
[0] = ARM_PS_REGNUM
;
12468 thumb2_insn_r
->reg_rec_count
= 1;
12472 arm_record_unsupported_insn(thumb2_insn_r
);
12476 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12479 record_buf
[0] = ARM_PS_REGNUM
;
12480 record_buf
[1] = ARM_LR_REGNUM
;
12481 thumb2_insn_r
->reg_rec_count
= 2;
12484 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12486 return ARM_RECORD_SUCCESS
;
12489 /* Handler for thumb2 store single data item instructions. */
12492 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12494 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12496 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12497 uint32_t address
, offset_addr
;
12498 uint32_t record_buf
[8], record_buf_mem
[8];
12501 ULONGEST u_regval
[2];
12503 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12504 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12505 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12506 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12508 if (bit (thumb2_insn_r
->arm_insn
, 23))
12511 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12512 offset_addr
= u_regval
[0] + offset_imm
;
12513 address
= offset_addr
;
12518 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12520 /* Handle STRB (register). */
12521 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12522 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12523 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12524 offset_addr
= u_regval
[1] << shift_imm
;
12525 address
= u_regval
[0] + offset_addr
;
12529 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12530 if (bit (thumb2_insn_r
->arm_insn
, 10))
12532 if (bit (thumb2_insn_r
->arm_insn
, 9))
12533 offset_addr
= u_regval
[0] + offset_imm
;
12535 offset_addr
= u_regval
[0] - offset_imm
;
12537 address
= offset_addr
;
12540 address
= u_regval
[0];
12546 /* Store byte instructions. */
12549 record_buf_mem
[0] = 1;
12551 /* Store half word instructions. */
12554 record_buf_mem
[0] = 2;
12556 /* Store word instructions. */
12559 record_buf_mem
[0] = 4;
12563 gdb_assert_not_reached ("no decoding pattern found");
12567 record_buf_mem
[1] = address
;
12568 thumb2_insn_r
->mem_rec_count
= 1;
12569 record_buf
[0] = reg_rn
;
12570 thumb2_insn_r
->reg_rec_count
= 1;
12572 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12574 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12576 return ARM_RECORD_SUCCESS
;
12579 /* Handler for thumb2 load memory hints instructions. */
12582 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12584 uint32_t record_buf
[8];
12585 uint32_t reg_rt
, reg_rn
;
12587 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12588 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12590 if (ARM_PC_REGNUM
!= reg_rt
)
12592 record_buf
[0] = reg_rt
;
12593 record_buf
[1] = reg_rn
;
12594 record_buf
[2] = ARM_PS_REGNUM
;
12595 thumb2_insn_r
->reg_rec_count
= 3;
12597 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12599 return ARM_RECORD_SUCCESS
;
12602 return ARM_RECORD_FAILURE
;
12605 /* Handler for thumb2 load word instructions. */
12608 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12610 uint32_t record_buf
[8];
12612 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12613 record_buf
[1] = ARM_PS_REGNUM
;
12614 thumb2_insn_r
->reg_rec_count
= 2;
12616 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12618 return ARM_RECORD_SUCCESS
;
12621 /* Handler for thumb2 long multiply, long multiply accumulate, and
12622 divide instructions. */
12625 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12627 uint32_t opcode1
= 0, opcode2
= 0;
12628 uint32_t record_buf
[8];
12630 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12631 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12633 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12635 /* Handle SMULL, UMULL, SMULAL. */
12636 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12637 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12638 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12639 record_buf
[2] = ARM_PS_REGNUM
;
12640 thumb2_insn_r
->reg_rec_count
= 3;
12642 else if (1 == opcode1
|| 3 == opcode2
)
12644 /* Handle SDIV and UDIV. */
12645 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12646 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12647 record_buf
[2] = ARM_PS_REGNUM
;
12648 thumb2_insn_r
->reg_rec_count
= 3;
12651 return ARM_RECORD_FAILURE
;
12653 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12655 return ARM_RECORD_SUCCESS
;
12658 /* Record handler for thumb32 coprocessor instructions. */
12661 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12663 if (bit (thumb2_insn_r
->arm_insn
, 25))
12664 return arm_record_coproc_data_proc (thumb2_insn_r
);
12666 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12669 /* Record handler for advance SIMD structure load/store instructions. */
12672 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12674 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12675 uint32_t l_bit
, a_bit
, b_bits
;
12676 uint32_t record_buf
[128], record_buf_mem
[128];
12677 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12678 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12681 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12682 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12683 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12684 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12685 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12686 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12687 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12688 f_elem
= 8 / f_ebytes
;
12692 ULONGEST u_regval
= 0;
12693 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12694 address
= u_regval
;
12699 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12701 if (b_bits
== 0x07)
12703 else if (b_bits
== 0x0a)
12705 else if (b_bits
== 0x06)
12707 else if (b_bits
== 0x02)
12712 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12714 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12716 record_buf_mem
[index_m
++] = f_ebytes
;
12717 record_buf_mem
[index_m
++] = address
;
12718 address
= address
+ f_ebytes
;
12719 thumb2_insn_r
->mem_rec_count
+= 1;
12724 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12726 if (b_bits
== 0x09 || b_bits
== 0x08)
12728 else if (b_bits
== 0x03)
12733 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12734 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12736 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12738 record_buf_mem
[index_m
++] = f_ebytes
;
12739 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12740 thumb2_insn_r
->mem_rec_count
+= 1;
12742 address
= address
+ (2 * f_ebytes
);
12746 else if ((b_bits
& 0x0e) == 0x04)
12748 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12750 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12752 record_buf_mem
[index_m
++] = f_ebytes
;
12753 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12754 thumb2_insn_r
->mem_rec_count
+= 1;
12756 address
= address
+ (3 * f_ebytes
);
12760 else if (!(b_bits
& 0x0e))
12762 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12764 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12766 record_buf_mem
[index_m
++] = f_ebytes
;
12767 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12768 thumb2_insn_r
->mem_rec_count
+= 1;
12770 address
= address
+ (4 * f_ebytes
);
12776 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12778 if (bft_size
== 0x00)
12780 else if (bft_size
== 0x01)
12782 else if (bft_size
== 0x02)
12788 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12789 thumb2_insn_r
->mem_rec_count
= 1;
12791 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12792 thumb2_insn_r
->mem_rec_count
= 2;
12794 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12795 thumb2_insn_r
->mem_rec_count
= 3;
12797 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12798 thumb2_insn_r
->mem_rec_count
= 4;
12800 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12802 record_buf_mem
[index_m
] = f_ebytes
;
12803 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12812 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12813 thumb2_insn_r
->reg_rec_count
= 1;
12815 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12816 thumb2_insn_r
->reg_rec_count
= 2;
12818 else if ((b_bits
& 0x0e) == 0x04)
12819 thumb2_insn_r
->reg_rec_count
= 3;
12821 else if (!(b_bits
& 0x0e))
12822 thumb2_insn_r
->reg_rec_count
= 4;
12827 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12828 thumb2_insn_r
->reg_rec_count
= 1;
12830 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12831 thumb2_insn_r
->reg_rec_count
= 2;
12833 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12834 thumb2_insn_r
->reg_rec_count
= 3;
12836 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12837 thumb2_insn_r
->reg_rec_count
= 4;
12839 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12840 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12844 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12846 record_buf
[index_r
] = reg_rn
;
12847 thumb2_insn_r
->reg_rec_count
+= 1;
12850 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12852 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12857 /* Decodes thumb2 instruction type and invokes its record handler. */
12859 static unsigned int
12860 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12862 uint32_t op
, op1
, op2
;
12864 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12865 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12866 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12870 if (!(op2
& 0x64 ))
12872 /* Load/store multiple instruction. */
12873 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12875 else if ((op2
& 0x64) == 0x4)
12877 /* Load/store (dual/exclusive) and table branch instruction. */
12878 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12880 else if ((op2
& 0x60) == 0x20)
12882 /* Data-processing (shifted register). */
12883 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12885 else if (op2
& 0x40)
12887 /* Co-processor instructions. */
12888 return thumb2_record_coproc_insn (thumb2_insn_r
);
12891 else if (op1
== 0x02)
12895 /* Branches and miscellaneous control instructions. */
12896 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12898 else if (op2
& 0x20)
12900 /* Data-processing (plain binary immediate) instruction. */
12901 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12905 /* Data-processing (modified immediate). */
12906 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12909 else if (op1
== 0x03)
12911 if (!(op2
& 0x71 ))
12913 /* Store single data item. */
12914 return thumb2_record_str_single_data (thumb2_insn_r
);
12916 else if (!((op2
& 0x71) ^ 0x10))
12918 /* Advanced SIMD or structure load/store instructions. */
12919 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12921 else if (!((op2
& 0x67) ^ 0x01))
12923 /* Load byte, memory hints instruction. */
12924 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12926 else if (!((op2
& 0x67) ^ 0x03))
12928 /* Load halfword, memory hints instruction. */
12929 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12931 else if (!((op2
& 0x67) ^ 0x05))
12933 /* Load word instruction. */
12934 return thumb2_record_ld_word (thumb2_insn_r
);
12936 else if (!((op2
& 0x70) ^ 0x20))
12938 /* Data-processing (register) instruction. */
12939 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12941 else if (!((op2
& 0x78) ^ 0x30))
12943 /* Multiply, multiply accumulate, abs diff instruction. */
12944 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12946 else if (!((op2
& 0x78) ^ 0x38))
12948 /* Long multiply, long multiply accumulate, and divide. */
12949 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12951 else if (op2
& 0x40)
12953 /* Co-processor instructions. */
12954 return thumb2_record_coproc_insn (thumb2_insn_r
);
12962 /* Abstract memory reader. */
12964 class abstract_memory_reader
12967 /* Read LEN bytes of target memory at address MEMADDR, placing the
12968 results in GDB's memory at BUF. Return true on success. */
12970 virtual bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) = 0;
12973 /* Instruction reader from real target. */
12975 class instruction_reader
: public abstract_memory_reader
12978 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
12980 if (target_read_memory (memaddr
, buf
, len
))
12989 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12990 and positive val on fauilure. */
12993 extract_arm_insn (abstract_memory_reader
& reader
,
12994 insn_decode_record
*insn_record
, uint32_t insn_size
)
12996 gdb_byte buf
[insn_size
];
12998 memset (&buf
[0], 0, insn_size
);
13000 if (!reader
.read (insn_record
->this_addr
, buf
, insn_size
))
13002 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13004 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13008 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13010 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13014 decode_insn (abstract_memory_reader
&reader
, insn_decode_record
*arm_record
,
13015 record_type_t record_type
, uint32_t insn_size
)
13018 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
13020 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13022 arm_record_data_proc_misc_ld_str
, /* 000. */
13023 arm_record_data_proc_imm
, /* 001. */
13024 arm_record_ld_st_imm_offset
, /* 010. */
13025 arm_record_ld_st_reg_offset
, /* 011. */
13026 arm_record_ld_st_multiple
, /* 100. */
13027 arm_record_b_bl
, /* 101. */
13028 arm_record_asimd_vfp_coproc
, /* 110. */
13029 arm_record_coproc_data_proc
/* 111. */
13032 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
13034 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13036 thumb_record_shift_add_sub
, /* 000. */
13037 thumb_record_add_sub_cmp_mov
, /* 001. */
13038 thumb_record_ld_st_reg_offset
, /* 010. */
13039 thumb_record_ld_st_imm_offset
, /* 011. */
13040 thumb_record_ld_st_stack
, /* 100. */
13041 thumb_record_misc
, /* 101. */
13042 thumb_record_ldm_stm_swi
, /* 110. */
13043 thumb_record_branch
/* 111. */
13046 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13047 uint32_t insn_id
= 0;
13049 if (extract_arm_insn (reader
, arm_record
, insn_size
))
13053 printf_unfiltered (_("Process record: error reading memory at "
13054 "addr %s len = %d.\n"),
13055 paddress (arm_record
->gdbarch
,
13056 arm_record
->this_addr
), insn_size
);
13060 else if (ARM_RECORD
== record_type
)
13062 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13063 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13065 if (arm_record
->cond
== 0xf)
13066 ret
= arm_record_extension_space (arm_record
);
13069 /* If this insn has fallen into extension space
13070 then we need not decode it anymore. */
13071 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13073 if (ret
!= ARM_RECORD_SUCCESS
)
13075 arm_record_unsupported_insn (arm_record
);
13079 else if (THUMB_RECORD
== record_type
)
13081 /* As thumb does not have condition codes, we set negative. */
13082 arm_record
->cond
= -1;
13083 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13084 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13085 if (ret
!= ARM_RECORD_SUCCESS
)
13087 arm_record_unsupported_insn (arm_record
);
13091 else if (THUMB2_RECORD
== record_type
)
13093 /* As thumb does not have condition codes, we set negative. */
13094 arm_record
->cond
= -1;
13096 /* Swap first half of 32bit thumb instruction with second half. */
13097 arm_record
->arm_insn
13098 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13100 ret
= thumb2_record_decode_insn_handler (arm_record
);
13102 if (ret
!= ARM_RECORD_SUCCESS
)
13104 arm_record_unsupported_insn (arm_record
);
13110 /* Throw assertion. */
13111 gdb_assert_not_reached ("not a valid instruction, could not decode");
13118 namespace selftests
{
13120 /* Provide both 16-bit and 32-bit thumb instructions. */
13122 class instruction_reader_thumb
: public abstract_memory_reader
13125 template<size_t SIZE
>
13126 instruction_reader_thumb (enum bfd_endian endian
,
13127 const uint16_t (&insns
)[SIZE
])
13128 : m_endian (endian
), m_insns (insns
), m_insns_size (SIZE
)
13131 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
13133 SELF_CHECK (len
== 4 || len
== 2);
13134 SELF_CHECK (memaddr
% 2 == 0);
13135 SELF_CHECK ((memaddr
/ 2) < m_insns_size
);
13137 store_unsigned_integer (buf
, 2, m_endian
, m_insns
[memaddr
/ 2]);
13140 store_unsigned_integer (&buf
[2], 2, m_endian
,
13141 m_insns
[memaddr
/ 2 + 1]);
13147 enum bfd_endian m_endian
;
13148 const uint16_t *m_insns
;
13149 size_t m_insns_size
;
13153 arm_record_test (void)
13155 struct gdbarch_info info
;
13156 gdbarch_info_init (&info
);
13157 info
.bfd_arch_info
= bfd_scan_arch ("arm");
13159 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
13161 SELF_CHECK (gdbarch
!= NULL
);
13163 /* 16-bit Thumb instructions. */
13165 insn_decode_record arm_record
;
13167 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13168 arm_record
.gdbarch
= gdbarch
;
13170 static const uint16_t insns
[] = {
13171 /* db b2 uxtb r3, r3 */
13173 /* cd 58 ldr r5, [r1, r3] */
13177 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13178 instruction_reader_thumb
reader (endian
, insns
);
13179 int ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13180 THUMB_INSN_SIZE_BYTES
);
13182 SELF_CHECK (ret
== 0);
13183 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13184 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13185 SELF_CHECK (arm_record
.arm_regs
[0] == 3);
13187 arm_record
.this_addr
+= 2;
13188 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13189 THUMB_INSN_SIZE_BYTES
);
13191 SELF_CHECK (ret
== 0);
13192 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13193 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13194 SELF_CHECK (arm_record
.arm_regs
[0] == 5);
13197 /* 32-bit Thumb-2 instructions. */
13199 insn_decode_record arm_record
;
13201 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13202 arm_record
.gdbarch
= gdbarch
;
13204 static const uint16_t insns
[] = {
13205 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
13209 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13210 instruction_reader_thumb
reader (endian
, insns
);
13211 int ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13212 THUMB2_INSN_SIZE_BYTES
);
13214 SELF_CHECK (ret
== 0);
13215 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13216 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13217 SELF_CHECK (arm_record
.arm_regs
[0] == 7);
13220 } // namespace selftests
13221 #endif /* GDB_SELF_TEST */
13223 /* Cleans up local record registers and memory allocations. */
13226 deallocate_reg_mem (insn_decode_record
*record
)
13228 xfree (record
->arm_regs
);
13229 xfree (record
->arm_mems
);
13233 /* Parse the current instruction and record the values of the registers and
13234 memory that will be changed in current instruction to record_arch_list".
13235 Return -1 if something is wrong. */
13238 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13239 CORE_ADDR insn_addr
)
13242 uint32_t no_of_rec
= 0;
13243 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13244 ULONGEST t_bit
= 0, insn_id
= 0;
13246 ULONGEST u_regval
= 0;
13248 insn_decode_record arm_record
;
13250 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13251 arm_record
.regcache
= regcache
;
13252 arm_record
.this_addr
= insn_addr
;
13253 arm_record
.gdbarch
= gdbarch
;
13256 if (record_debug
> 1)
13258 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13260 paddress (gdbarch
, arm_record
.this_addr
));
13263 instruction_reader reader
;
13264 if (extract_arm_insn (reader
, &arm_record
, 2))
13268 printf_unfiltered (_("Process record: error reading memory at "
13269 "addr %s len = %d.\n"),
13270 paddress (arm_record
.gdbarch
,
13271 arm_record
.this_addr
), 2);
13276 /* Check the insn, whether it is thumb or arm one. */
13278 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13279 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13282 if (!(u_regval
& t_bit
))
13284 /* We are decoding arm insn. */
13285 ret
= decode_insn (reader
, &arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13289 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13290 /* is it thumb2 insn? */
13291 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13293 ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13294 THUMB2_INSN_SIZE_BYTES
);
13298 /* We are decoding thumb insn. */
13299 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13300 THUMB_INSN_SIZE_BYTES
);
13306 /* Record registers. */
13307 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13308 if (arm_record
.arm_regs
)
13310 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13312 if (record_full_arch_list_add_reg
13313 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13317 /* Record memories. */
13318 if (arm_record
.arm_mems
)
13320 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13322 if (record_full_arch_list_add_mem
13323 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13324 arm_record
.arm_mems
[no_of_rec
].len
))
13329 if (record_full_arch_list_add_end ())
13334 deallocate_reg_mem (&arm_record
);