1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002-2015 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Forward declarations. */
27 /* Register numbers of various important registers. */
30 ARM_A1_REGNUM
= 0, /* first integer-like argument */
31 ARM_A4_REGNUM
= 3, /* last integer-like argument */
34 ARM_SP_REGNUM
= 13, /* Contains address of top of stack */
35 ARM_LR_REGNUM
= 14, /* address to return to from a function call */
36 ARM_PC_REGNUM
= 15, /* Contains program counter */
37 ARM_F0_REGNUM
= 16, /* first floating point register */
38 ARM_F3_REGNUM
= 19, /* last floating point argument register */
39 ARM_F7_REGNUM
= 23, /* last floating point register */
40 ARM_FPS_REGNUM
= 24, /* floating point status register */
41 ARM_PS_REGNUM
= 25, /* Contains processor status */
42 ARM_WR0_REGNUM
, /* WMMX data registers. */
43 ARM_WR15_REGNUM
= ARM_WR0_REGNUM
+ 15,
44 ARM_WC0_REGNUM
, /* WMMX control registers. */
45 ARM_WCSSF_REGNUM
= ARM_WC0_REGNUM
+ 2,
46 ARM_WCASF_REGNUM
= ARM_WC0_REGNUM
+ 3,
47 ARM_WC7_REGNUM
= ARM_WC0_REGNUM
+ 7,
48 ARM_WCGR0_REGNUM
, /* WMMX general purpose registers. */
49 ARM_WCGR3_REGNUM
= ARM_WCGR0_REGNUM
+ 3,
50 ARM_WCGR7_REGNUM
= ARM_WCGR0_REGNUM
+ 7,
51 ARM_D0_REGNUM
, /* VFP double-precision registers. */
52 ARM_D31_REGNUM
= ARM_D0_REGNUM
+ 31,
57 /* Other useful registers. */
58 ARM_FP_REGNUM
= 11, /* Frame register in ARM code, if used. */
59 THUMB_FP_REGNUM
= 7, /* Frame register in Thumb code, if used. */
61 ARM_LAST_ARG_REGNUM
= ARM_A4_REGNUM
,
62 ARM_NUM_FP_ARG_REGS
= 4,
63 ARM_LAST_FP_ARG_REGNUM
= ARM_F3_REGNUM
66 /* Size of integer registers. */
67 #define INT_REGISTER_SIZE 4
69 /* Say how long FP registers are. Used for documentation purposes and
70 code readability in this header. IEEE extended doubles are 80
71 bits. DWORD aligned they use 96 bits. */
72 #define FP_REGISTER_SIZE 12
74 /* Say how long VFP double precision registers are. Used for documentation
75 purposes and code readability. These are fixed at 64 bits. */
76 #define VFP_REGISTER_SIZE 8
78 /* Number of machine registers. The only define actually required
79 is gdbarch_num_regs. The other definitions are used for documentation
80 purposes and code readability. */
81 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
82 (and called PS for processor status) so the status bits can be cleared
83 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
85 #define NUM_FREGS 8 /* Number of floating point registers. */
86 #define NUM_SREGS 2 /* Number of status registers. */
87 #define NUM_GREGS 16 /* Number of general purpose registers. */
90 /* Instruction condition field values. */
108 #define FLAG_N 0x80000000
109 #define FLAG_Z 0x40000000
110 #define FLAG_C 0x20000000
111 #define FLAG_V 0x10000000
115 #define XPSR_T 0x01000000
117 /* Type of floating-point code in use by inferior. There are really 3 models
118 that are traditionally supported (plus the endianness issue), but gcc can
119 only generate 2 of those. The third is APCS_FLOAT, where arguments to
120 functions are passed in floating-point registers.
122 In addition to the traditional models, VFP adds two more.
124 If you update this enum, don't forget to update fp_model_strings in
129 ARM_FLOAT_AUTO
, /* Automatic detection. Do not set in tdep. */
130 ARM_FLOAT_SOFT_FPA
, /* Traditional soft-float (mixed-endian on LE ARM). */
131 ARM_FLOAT_FPA
, /* FPA co-processor. GCC calling convention. */
132 ARM_FLOAT_SOFT_VFP
, /* Soft-float with pure-endian doubles. */
133 ARM_FLOAT_VFP
, /* Full VFP calling convention. */
134 ARM_FLOAT_LAST
/* Keep at end. */
137 /* ABI used by the inferior. */
146 /* Convention for returning structures. */
150 pcc_struct_return
, /* Return "short" structures in memory. */
151 reg_struct_return
/* Return "short" structures in registers. */
154 /* Target-dependent structure in gdbarch. */
157 /* The ABI for this architecture. It should never be set to
159 enum arm_abi_kind arm_abi
;
161 enum arm_float_model fp_model
; /* Floating point calling conventions. */
163 int have_fpa_registers
; /* Does the target report the FPA registers? */
164 /* The number of VFP registers reported by the target. It is zero
165 if VFP registers are not supported. */
166 int vfp_register_count
;
167 int have_vfp_pseudos
; /* Are we synthesizing the single precision
169 int have_neon_pseudos
; /* Are we synthesizing the quad precision
170 NEON registers? Requires
172 int have_neon
; /* Do we have a NEON unit? */
174 int is_m
; /* Does the target follow the "M" profile. */
175 CORE_ADDR lowest_pc
; /* Lowest address at which instructions
178 const gdb_byte
*arm_breakpoint
; /* Breakpoint pattern for an ARM insn. */
179 int arm_breakpoint_size
; /* And its size. */
180 const gdb_byte
*thumb_breakpoint
; /* Breakpoint pattern for a Thumb insn. */
181 int thumb_breakpoint_size
; /* And its size. */
183 /* If the Thumb breakpoint is an undefined instruction (which is
184 affected by IT blocks) rather than a BKPT instruction (which is
185 not), then we need a 32-bit Thumb breakpoint to preserve the
186 instruction count in IT blocks. */
187 const gdb_byte
*thumb2_breakpoint
;
188 int thumb2_breakpoint_size
;
190 int jb_pc
; /* Offset to PC value in jump buffer.
191 If this is negative, longjmp support
193 size_t jb_elt_size
; /* And the size of each entry in the buf. */
195 /* Convention for returning structures. */
196 enum struct_return struct_return
;
198 /* ISA-specific data types. */
199 struct type
*arm_ext_type
;
200 struct type
*neon_double_type
;
201 struct type
*neon_quad_type
;
203 /* Return the expected next PC if FRAME is stopped at a syscall
205 CORE_ADDR (*syscall_next_pc
) (struct frame_info
*frame
);
207 /* syscall record. */
208 int (*arm_syscall_record
) (struct regcache
*regcache
, unsigned long svc_number
);
211 /* Structures used for displaced stepping. */
213 /* The maximum number of temporaries available for displaced instructions. */
214 #define DISPLACED_TEMPS 16
215 /* The maximum number of modified instructions generated for one single-stepped
216 instruction, including the breakpoint (usually at the end of the instruction
217 sequence) and any scratch words, etc. */
218 #define DISPLACED_MODIFIED_INSNS 8
220 struct displaced_step_closure
222 ULONGEST tmp
[DISPLACED_TEMPS
];
230 int rn
; /* Writeback register. */
231 unsigned int immed
: 1; /* Offset is immediate. */
232 unsigned int writeback
: 1; /* Perform base-register writeback. */
233 unsigned int restore_r4
: 1; /* Used r4 as scratch. */
239 unsigned int link
: 1;
240 unsigned int exchange
: 1;
241 unsigned int cond
: 4;
246 unsigned int regmask
;
249 unsigned int load
: 1;
250 unsigned int user
: 1;
251 unsigned int increment
: 1;
252 unsigned int before
: 1;
253 unsigned int writeback
: 1;
254 unsigned int cond
: 4;
259 unsigned int immed
: 1;
264 /* If non-NULL, override generic SVC handling (e.g. for a particular
266 int (*copy_svc_os
) (struct gdbarch
*gdbarch
, struct regcache
*regs
,
267 struct displaced_step_closure
*dsc
);
271 /* The size of original instruction, 2 or 4. */
272 unsigned int insn_size
;
273 /* True if the original insn (and thus all replacement insns) are Thumb
275 unsigned int is_thumb
;
277 /* The slots in the array is used in this way below,
278 - ARM instruction occupies one slot,
279 - Thumb 16 bit instruction occupies one slot,
280 - Thumb 32-bit instruction occupies *two* slots, one part for each. */
281 unsigned long modinsn
[DISPLACED_MODIFIED_INSNS
];
284 CORE_ADDR scratch_base
;
285 void (*cleanup
) (struct gdbarch
*, struct regcache
*,
286 struct displaced_step_closure
*);
289 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
290 write may write to the PC, specifies the way the CPSR T bit, etc. is
291 modified by the instruction. */
303 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
304 CORE_ADDR to
, struct regcache
*regs
,
305 struct displaced_step_closure
*dsc
);
307 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
308 CORE_ADDR to
, struct displaced_step_closure
*dsc
);
310 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
313 displaced_write_reg (struct regcache
*regs
,
314 struct displaced_step_closure
*dsc
, int regno
,
315 ULONGEST val
, enum pc_write_style write_pc
);
317 CORE_ADDR
arm_skip_stub (struct frame_info
*, CORE_ADDR
);
318 CORE_ADDR
arm_get_next_pc (struct frame_info
*, CORE_ADDR
);
319 void arm_insert_single_step_breakpoint (struct gdbarch
*,
320 struct address_space
*, CORE_ADDR
);
321 int arm_deal_with_atomic_sequence (struct frame_info
*);
322 int arm_software_single_step (struct frame_info
*);
323 int arm_frame_is_thumb (struct frame_info
*frame
);
325 extern struct displaced_step_closure
*
326 arm_displaced_step_copy_insn (struct gdbarch
*, CORE_ADDR
, CORE_ADDR
,
328 extern void arm_displaced_step_fixup (struct gdbarch
*,
329 struct displaced_step_closure
*,
330 CORE_ADDR
, CORE_ADDR
, struct regcache
*);
332 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
333 extern int arm_psr_thumb_bit (struct gdbarch
*);
335 /* Is the instruction at the given memory address a Thumb or ARM
337 extern int arm_pc_is_thumb (struct gdbarch
*, CORE_ADDR
);
339 extern int arm_process_record (struct gdbarch
*gdbarch
,
340 struct regcache
*regcache
, CORE_ADDR addr
);
341 /* Functions exported from armbsd-tdep.h. */
343 /* Return the appropriate register set for the core section identified
344 by SECT_NAME and SECT_SIZE. */
347 armbsd_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
348 iterate_over_regset_sections_cb
*cb
,
350 const struct regcache
*regcache
);
352 /* Target descriptions. */
353 extern struct target_desc
*tdesc_arm_with_m
;
354 extern struct target_desc
*tdesc_arm_with_iwmmxt
;
355 extern struct target_desc
*tdesc_arm_with_vfpv2
;
356 extern struct target_desc
*tdesc_arm_with_vfpv3
;
357 extern struct target_desc
*tdesc_arm_with_neon
;
359 #endif /* arm-tdep.h */