gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef ARM_TDEP_H
  21 #define ARM_TDEP_H
  22
  23 /* Forward declarations.  */
  24 struct gdbarch;
  25 struct regset;
  26
  27 /* Register numbers of various important registers.  */
  28
  29 enum gdb_regnum {
  30   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  31   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  32   ARM_AP_REGNUM = 11,
  33   ARM_IP_REGNUM = 12,
  34   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  35   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  36   ARM_PC_REGNUM = 15,           /* Contains program counter */
  37   ARM_F0_REGNUM = 16,           /* first floating point register */
  38   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  39   ARM_F7_REGNUM = 23,           /* last floating point register */
  40   ARM_FPS_REGNUM = 24,          /* floating point status register */
  41   ARM_PS_REGNUM = 25,           /* Contains processor status */
  42   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  43   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  44   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  45   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  46   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  47   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  48   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  49   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  50   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  51   ARM_D0_REGNUM,                /* VFP double-precision registers.  */
  52   ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  53   ARM_FPSCR_REGNUM,
  54
  55   ARM_NUM_REGS,
  56
  57   /* Other useful registers.  */
  58   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  59   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  60   ARM_NUM_ARG_REGS = 4,
  61   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  62   ARM_NUM_FP_ARG_REGS = 4,
  63   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  64 };
  65
  66 /* Size of integer registers.  */
  67 #define INT_REGISTER_SIZE               4
  68
  69 /* Say how long FP registers are.  Used for documentation purposes and
  70    code readability in this header.  IEEE extended doubles are 80
  71    bits.  DWORD aligned they use 96 bits.  */
  72 #define FP_REGISTER_SIZE        12
  73
  74 /* Number of machine registers.  The only define actually required
  75    is gdbarch_num_regs.  The other definitions are used for documentation
  76    purposes and code readability.  */
  77 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  78    (and called PS for processor status) so the status bits can be cleared
  79    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  80    in PS.  */
  81 #define NUM_FREGS       8       /* Number of floating point registers.  */
  82 #define NUM_SREGS       2       /* Number of status registers.  */
  83 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  84
  85
  86 /* Instruction condition field values.  */
  87 #define INST_EQ         0x0
  88 #define INST_NE         0x1
  89 #define INST_CS         0x2
  90 #define INST_CC         0x3
  91 #define INST_MI         0x4
  92 #define INST_PL         0x5
  93 #define INST_VS         0x6
  94 #define INST_VC         0x7
  95 #define INST_HI         0x8
  96 #define INST_LS         0x9
  97 #define INST_GE         0xa
  98 #define INST_LT         0xb
  99 #define INST_GT         0xc
 100 #define INST_LE         0xd
 101 #define INST_AL         0xe
 102 #define INST_NV         0xf
 103
 104 #define FLAG_N          0x80000000
 105 #define FLAG_Z          0x40000000
 106 #define FLAG_C          0x20000000
 107 #define FLAG_V          0x10000000
 108
 109 #define CPSR_T          0x20
 110
 111 #define XPSR_T          0x01000000
 112
 113 /* Type of floating-point code in use by inferior.  There are really 3 models
 114    that are traditionally supported (plus the endianness issue), but gcc can
 115    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 116    functions are passed in floating-point registers.
 117
 118    In addition to the traditional models, VFP adds two more.
 119
 120    If you update this enum, don't forget to update fp_model_strings in
 121    arm-tdep.c.  */
 122
 123 enum arm_float_model
 124 {
 125   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 126   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 127   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 128   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 129   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 130   ARM_FLOAT_LAST        /* Keep at end.  */
 131 };
 132
 133 /* ABI used by the inferior.  */
 134 enum arm_abi_kind
 135 {
 136   ARM_ABI_AUTO,
 137   ARM_ABI_APCS,
 138   ARM_ABI_AAPCS,
 139   ARM_ABI_LAST
 140 };
 141
 142 /* Convention for returning structures.  */
 143
 144 enum struct_return
 145 {
 146   pcc_struct_return,            /* Return "short" structures in memory.  */
 147   reg_struct_return             /* Return "short" structures in registers.  */
 148 };
 149
 150 /* Target-dependent structure in gdbarch.  */
 151 struct gdbarch_tdep
 152 {
 153   /* The ABI for this architecture.  It should never be set to
 154      ARM_ABI_AUTO.  */
 155   enum arm_abi_kind arm_abi;
 156
 157   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 158
 159   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 160   int have_vfp_registers;       /* Does the target report the VFP registers?  */
 161   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 162                                    VFP registers?  */
 163   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 164                                    NEON registers?  Requires
 165                                    have_vfp_pseudos.  */
 166   int have_neon;                /* Do we have a NEON unit?  */
 167
 168   int is_m;                     /* Does the target follow the "M" profile.  */
 169   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 170                                    will appear.  */
 171
 172   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 173   int arm_breakpoint_size;      /* And its size.  */
 174   const char *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn.  */
 175   int thumb_breakpoint_size;    /* And its size.  */
 176
 177   /* If the Thumb breakpoint is an undefined instruction (which is
 178      affected by IT blocks) rather than a BKPT instruction (which is
 179      not), then we need a 32-bit Thumb breakpoint to preserve the
 180      instruction count in IT blocks.  */
 181   const char *thumb2_breakpoint;
 182   int thumb2_breakpoint_size;
 183
 184   int jb_pc;                    /* Offset to PC value in jump buffer.
 185                                    If this is negative, longjmp support
 186                                    will be disabled.  */
 187   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 188
 189   /* Convention for returning structures.  */
 190   enum struct_return struct_return;
 191
 192   /* Cached core file helpers.  */
 193   struct regset *gregset, *fpregset;
 194
 195   /* ISA-specific data types.  */
 196   struct type *arm_ext_type;
 197   struct type *neon_double_type;
 198   struct type *neon_quad_type;
 199
 200   /* Return the expected next PC if FRAME is stopped at a syscall
 201      instruction.  */
 202   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 203 };
 204
 205 /* Structures used for displaced stepping.  */
 206
 207 /* The maximum number of temporaries available for displaced instructions.  */
 208 #define DISPLACED_TEMPS                 16
 209 /* The maximum number of modified instructions generated for one single-stepped
 210    instruction, including the breakpoint (usually at the end of the instruction
 211    sequence) and any scratch words, etc.  */
 212 #define DISPLACED_MODIFIED_INSNS        8
 213
 214 struct displaced_step_closure
 215 {
 216   ULONGEST tmp[DISPLACED_TEMPS];
 217   int rd;
 218   int wrote_to_pc;
 219   union
 220   {
 221     struct
 222     {
 223       int xfersize;
 224       int rn;                      /* Writeback register.  */
 225       unsigned int immed : 1;      /* Offset is immediate.  */
 226       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 227       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 228     } ldst;
 229
 230     struct
 231     {
 232       unsigned long dest;
 233       unsigned int link : 1;
 234       unsigned int exchange : 1;
 235       unsigned int cond : 4;
 236     } branch;
 237
 238     struct
 239     {
 240       unsigned int regmask;
 241       int rn;
 242       CORE_ADDR xfer_addr;
 243       unsigned int load : 1;
 244       unsigned int user : 1;
 245       unsigned int increment : 1;
 246       unsigned int before : 1;
 247       unsigned int writeback : 1;
 248       unsigned int cond : 4;
 249     } block;
 250
 251     struct
 252     {
 253       unsigned int immed : 1;
 254     } preload;
 255
 256     struct
 257     {
 258       /* If non-NULL, override generic SVC handling (e.g. for a particular
 259          OS).  */
 260       int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
 261                           struct regcache *regs,
 262                           struct displaced_step_closure *dsc);
 263     } svc;
 264   } u;
 265   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 266   int numinsns;
 267   CORE_ADDR insn_addr;
 268   CORE_ADDR scratch_base;
 269   void (*cleanup) (struct gdbarch *, struct regcache *,
 270                    struct displaced_step_closure *);
 271 };
 272
 273 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 274    write may write to the PC, specifies the way the CPSR T bit, etc. is
 275    modified by the instruction.  */
 276
 277 enum pc_write_style
 278 {
 279   BRANCH_WRITE_PC,
 280   BX_WRITE_PC,
 281   LOAD_WRITE_PC,
 282   ALU_WRITE_PC,
 283   CANNOT_WRITE_PC
 284 };
 285
 286 extern void
 287   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 288                               CORE_ADDR to, struct regcache *regs,
 289                               struct displaced_step_closure *dsc);
 290 extern void
 291   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 292                               CORE_ADDR to, struct displaced_step_closure *dsc);
 293 extern ULONGEST
 294   displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
 295 extern void
 296   displaced_write_reg (struct regcache *regs,
 297                        struct displaced_step_closure *dsc, int regno,
 298                        ULONGEST val, enum pc_write_style write_pc);
 299
 300 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 301 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 302 int arm_software_single_step (struct frame_info *);
 303 int arm_frame_is_thumb (struct frame_info *frame);
 304
 305 extern struct displaced_step_closure *
 306   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 307                                 struct regcache *);
 308 extern void arm_displaced_step_fixup (struct gdbarch *,
 309                                       struct displaced_step_closure *,
 310                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 311
 312 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 313 extern int arm_psr_thumb_bit (struct gdbarch *);
 314
 315 /* Is the instruction at the given memory address a Thumb or ARM
 316    instruction?  */
 317 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 318
 319 /* Functions exported from armbsd-tdep.h.  */
 320
 321 /* Return the appropriate register set for the core section identified
 322    by SECT_NAME and SECT_SIZE.  */
 323
 324 extern const struct regset *
 325   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 326                                    const char *sect_name, size_t sect_size);
 327
 328 #endif /* arm-tdep.h */