gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002-2017 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25 struct address_space;
  26 struct get_next_pcs;
  27 struct arm_get_next_pcs;
  28 struct gdb_get_next_pcs;
  29
  30 #include "arch/arm.h"
  31
  32 /* Say how long FP registers are.  Used for documentation purposes and
  33    code readability in this header.  IEEE extended doubles are 80
  34    bits.  DWORD aligned they use 96 bits.  */
  35 #define FP_REGISTER_SIZE        12
  36
  37 /* Say how long VFP double precision registers are.  Used for documentation
  38    purposes and code readability.  These are fixed at 64 bits.  */
  39 #define VFP_REGISTER_SIZE       8
  40
  41 /* Number of machine registers.  The only define actually required
  42    is gdbarch_num_regs.  The other definitions are used for documentation
  43    purposes and code readability.  */
  44 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  45    (and called PS for processor status) so the status bits can be cleared
  46    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  47    in PS.  */
  48 #define NUM_FREGS       8       /* Number of floating point registers.  */
  49 #define NUM_SREGS       2       /* Number of status registers.  */
  50 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  51
  52
  53
  54 /* Type of floating-point code in use by inferior.  There are really 3 models
  55    that are traditionally supported (plus the endianness issue), but gcc can
  56    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
  57    functions are passed in floating-point registers.
  58
  59    In addition to the traditional models, VFP adds two more.
  60
  61    If you update this enum, don't forget to update fp_model_strings in
  62    arm-tdep.c.  */
  63
  64 enum arm_float_model
  65 {
  66   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
  67   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
  68   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
  69   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
  70   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
  71   ARM_FLOAT_LAST        /* Keep at end.  */
  72 };
  73
  74 /* ABI used by the inferior.  */
  75 enum arm_abi_kind
  76 {
  77   ARM_ABI_AUTO,
  78   ARM_ABI_APCS,
  79   ARM_ABI_AAPCS,
  80   ARM_ABI_LAST
  81 };
  82
  83 /* Convention for returning structures.  */
  84
  85 enum struct_return
  86 {
  87   pcc_struct_return,            /* Return "short" structures in memory.  */
  88   reg_struct_return             /* Return "short" structures in registers.  */
  89 };
  90
  91 /* Target-dependent structure in gdbarch.  */
  92 struct gdbarch_tdep
  93 {
  94   /* The ABI for this architecture.  It should never be set to
  95      ARM_ABI_AUTO.  */
  96   enum arm_abi_kind arm_abi;
  97
  98   enum arm_float_model fp_model; /* Floating point calling conventions.  */
  99
 100   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 101   int have_wmmx_registers;      /* Does the target report the WMMX registers?  */
 102   /* The number of VFP registers reported by the target.  It is zero
 103      if VFP registers are not supported.  */
 104   int vfp_register_count;
 105   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 106                                    VFP registers?  */
 107   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 108                                    NEON registers?  Requires
 109                                    have_vfp_pseudos.  */
 110   int have_neon;                /* Do we have a NEON unit?  */
 111
 112   int is_m;                     /* Does the target follow the "M" profile.  */
 113   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 114                                    will appear.  */
 115
 116   const gdb_byte *arm_breakpoint;       /* Breakpoint pattern for an ARM insn.  */
 117   int arm_breakpoint_size;      /* And its size.  */
 118   const gdb_byte *thumb_breakpoint;     /* Breakpoint pattern for a Thumb insn.  */
 119   int thumb_breakpoint_size;    /* And its size.  */
 120
 121   /* If the Thumb breakpoint is an undefined instruction (which is
 122      affected by IT blocks) rather than a BKPT instruction (which is
 123      not), then we need a 32-bit Thumb breakpoint to preserve the
 124      instruction count in IT blocks.  */
 125   const gdb_byte *thumb2_breakpoint;
 126   int thumb2_breakpoint_size;
 127
 128   int jb_pc;                    /* Offset to PC value in jump buffer.
 129                                    If this is negative, longjmp support
 130                                    will be disabled.  */
 131   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 132
 133   /* Convention for returning structures.  */
 134   enum struct_return struct_return;
 135
 136   /* ISA-specific data types.  */
 137   struct type *arm_ext_type;
 138   struct type *neon_double_type;
 139   struct type *neon_quad_type;
 140
 141    /* syscall record.  */
 142   int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 143 };
 144
 145 /* Structures used for displaced stepping.  */
 146
 147 /* The maximum number of temporaries available for displaced instructions.  */
 148 #define DISPLACED_TEMPS                 16
 149 /* The maximum number of modified instructions generated for one single-stepped
 150    instruction, including the breakpoint (usually at the end of the instruction
 151    sequence) and any scratch words, etc.  */
 152 #define DISPLACED_MODIFIED_INSNS        8
 153
 154 struct displaced_step_closure
 155 {
 156   ULONGEST tmp[DISPLACED_TEMPS];
 157   int rd;
 158   int wrote_to_pc;
 159   union
 160   {
 161     struct
 162     {
 163       int xfersize;
 164       int rn;                      /* Writeback register.  */
 165       unsigned int immed : 1;      /* Offset is immediate.  */
 166       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 167       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 168     } ldst;
 169
 170     struct
 171     {
 172       unsigned long dest;
 173       unsigned int link : 1;
 174       unsigned int exchange : 1;
 175       unsigned int cond : 4;
 176     } branch;
 177
 178     struct
 179     {
 180       unsigned int regmask;
 181       int rn;
 182       CORE_ADDR xfer_addr;
 183       unsigned int load : 1;
 184       unsigned int user : 1;
 185       unsigned int increment : 1;
 186       unsigned int before : 1;
 187       unsigned int writeback : 1;
 188       unsigned int cond : 4;
 189     } block;
 190
 191     struct
 192     {
 193       unsigned int immed : 1;
 194     } preload;
 195
 196     struct
 197     {
 198       /* If non-NULL, override generic SVC handling (e.g. for a particular
 199          OS).  */
 200       int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
 201                           struct displaced_step_closure *dsc);
 202     } svc;
 203   } u;
 204
 205   /* The size of original instruction, 2 or 4.  */
 206   unsigned int insn_size;
 207   /* True if the original insn (and thus all replacement insns) are Thumb
 208      instead of ARM.   */
 209   unsigned int is_thumb;
 210
 211   /* The slots in the array is used in this way below,
 212      - ARM instruction occupies one slot,
 213      - Thumb 16 bit instruction occupies one slot,
 214      - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
 215   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 216   int numinsns;
 217   CORE_ADDR insn_addr;
 218   CORE_ADDR scratch_base;
 219   void (*cleanup) (struct gdbarch *, struct regcache *,
 220                    struct displaced_step_closure *);
 221 };
 222
 223 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 224    write may write to the PC, specifies the way the CPSR T bit, etc. is
 225    modified by the instruction.  */
 226
 227 enum pc_write_style
 228 {
 229   BRANCH_WRITE_PC,
 230   BX_WRITE_PC,
 231   LOAD_WRITE_PC,
 232   ALU_WRITE_PC,
 233   CANNOT_WRITE_PC
 234 };
 235
 236 extern void
 237   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 238                               CORE_ADDR to, struct regcache *regs,
 239                               struct displaced_step_closure *dsc);
 240 extern void
 241   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 242                               CORE_ADDR to, struct displaced_step_closure *dsc);
 243 extern ULONGEST
 244   displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
 245                       int regno);
 246 extern void
 247   displaced_write_reg (struct regcache *regs,
 248                        struct displaced_step_closure *dsc, int regno,
 249                        ULONGEST val, enum pc_write_style write_pc);
 250
 251 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 252
 253 ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
 254                                                         int len,
 255                                                         int byte_order);
 256
 257 CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
 258                                              CORE_ADDR val);
 259
 260 int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
 261
 262 VEC (CORE_ADDR) *arm_software_single_step (struct regcache *);
 263 int arm_is_thumb (struct regcache *regcache);
 264 int arm_frame_is_thumb (struct frame_info *frame);
 265
 266 extern void arm_displaced_step_fixup (struct gdbarch *,
 267                                       struct displaced_step_closure *,
 268                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 269
 270 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 271 extern int arm_psr_thumb_bit (struct gdbarch *);
 272
 273 /* Is the instruction at the given memory address a Thumb or ARM
 274    instruction?  */
 275 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 276
 277 extern int arm_process_record (struct gdbarch *gdbarch,
 278                                struct regcache *regcache, CORE_ADDR addr);
 279 /* Functions exported from arm-bsd-tdep.h.  */
 280
 281 /* Return the appropriate register set for the core section identified
 282    by SECT_NAME and SECT_SIZE.  */
 283
 284 extern void
 285   armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
 286                                        iterate_over_regset_sections_cb *cb,
 287                                        void *cb_data,
 288                                        const struct regcache *regcache);
 289
 290 /* Target descriptions.  */
 291 extern struct target_desc *tdesc_arm_with_m;
 292 extern struct target_desc *tdesc_arm_with_iwmmxt;
 293 extern struct target_desc *tdesc_arm_with_vfpv2;
 294 extern struct target_desc *tdesc_arm_with_vfpv3;
 295 extern struct target_desc *tdesc_arm_with_neon;
 296
 297 #endif /* arm-tdep.h */