gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25 struct address_space;
  26
  27 /* Register numbers of various important registers.  */
  28
  29 enum gdb_regnum {
  30   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  31   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  32   ARM_AP_REGNUM = 11,
  33   ARM_IP_REGNUM = 12,
  34   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  35   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  36   ARM_PC_REGNUM = 15,           /* Contains program counter */
  37   ARM_F0_REGNUM = 16,           /* first floating point register */
  38   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  39   ARM_F7_REGNUM = 23,           /* last floating point register */
  40   ARM_FPS_REGNUM = 24,          /* floating point status register */
  41   ARM_PS_REGNUM = 25,           /* Contains processor status */
  42   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  43   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  44   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  45   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  46   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  47   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  48   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  49   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  50   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  51   ARM_D0_REGNUM,                /* VFP double-precision registers.  */
  52   ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  53   ARM_FPSCR_REGNUM,
  54
  55   ARM_NUM_REGS,
  56
  57   /* Other useful registers.  */
  58   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  59   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  60   ARM_NUM_ARG_REGS = 4,
  61   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  62   ARM_NUM_FP_ARG_REGS = 4,
  63   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  64 };
  65
  66 /* Size of integer registers.  */
  67 #define INT_REGISTER_SIZE               4
  68
  69 /* Say how long FP registers are.  Used for documentation purposes and
  70    code readability in this header.  IEEE extended doubles are 80
  71    bits.  DWORD aligned they use 96 bits.  */
  72 #define FP_REGISTER_SIZE        12
  73
  74 /* Number of machine registers.  The only define actually required
  75    is gdbarch_num_regs.  The other definitions are used for documentation
  76    purposes and code readability.  */
  77 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  78    (and called PS for processor status) so the status bits can be cleared
  79    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  80    in PS.  */
  81 #define NUM_FREGS       8       /* Number of floating point registers.  */
  82 #define NUM_SREGS       2       /* Number of status registers.  */
  83 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  84
  85
  86 /* Instruction condition field values.  */
  87 #define INST_EQ         0x0
  88 #define INST_NE         0x1
  89 #define INST_CS         0x2
  90 #define INST_CC         0x3
  91 #define INST_MI         0x4
  92 #define INST_PL         0x5
  93 #define INST_VS         0x6
  94 #define INST_VC         0x7
  95 #define INST_HI         0x8
  96 #define INST_LS         0x9
  97 #define INST_GE         0xa
  98 #define INST_LT         0xb
  99 #define INST_GT         0xc
 100 #define INST_LE         0xd
 101 #define INST_AL         0xe
 102 #define INST_NV         0xf
 103
 104 #define FLAG_N          0x80000000
 105 #define FLAG_Z          0x40000000
 106 #define FLAG_C          0x20000000
 107 #define FLAG_V          0x10000000
 108
 109 #define CPSR_T          0x20
 110
 111 #define XPSR_T          0x01000000
 112
 113 /* Type of floating-point code in use by inferior.  There are really 3 models
 114    that are traditionally supported (plus the endianness issue), but gcc can
 115    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 116    functions are passed in floating-point registers.
 117
 118    In addition to the traditional models, VFP adds two more.
 119
 120    If you update this enum, don't forget to update fp_model_strings in
 121    arm-tdep.c.  */
 122
 123 enum arm_float_model
 124 {
 125   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 126   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 127   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 128   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 129   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 130   ARM_FLOAT_LAST        /* Keep at end.  */
 131 };
 132
 133 /* ABI used by the inferior.  */
 134 enum arm_abi_kind
 135 {
 136   ARM_ABI_AUTO,
 137   ARM_ABI_APCS,
 138   ARM_ABI_AAPCS,
 139   ARM_ABI_LAST
 140 };
 141
 142 /* Convention for returning structures.  */
 143
 144 enum struct_return
 145 {
 146   pcc_struct_return,            /* Return "short" structures in memory.  */
 147   reg_struct_return             /* Return "short" structures in registers.  */
 148 };
 149
 150 /* Target-dependent structure in gdbarch.  */
 151 struct gdbarch_tdep
 152 {
 153   /* The ABI for this architecture.  It should never be set to
 154      ARM_ABI_AUTO.  */
 155   enum arm_abi_kind arm_abi;
 156
 157   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 158
 159   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 160   int have_vfp_registers;       /* Does the target report the VFP registers?  */
 161   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 162                                    VFP registers?  */
 163   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 164                                    NEON registers?  Requires
 165                                    have_vfp_pseudos.  */
 166   int have_neon;                /* Do we have a NEON unit?  */
 167
 168   int is_m;                     /* Does the target follow the "M" profile.  */
 169   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 170                                    will appear.  */
 171
 172   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 173   int arm_breakpoint_size;      /* And its size.  */
 174   const char *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn.  */
 175   int thumb_breakpoint_size;    /* And its size.  */
 176
 177   /* If the Thumb breakpoint is an undefined instruction (which is
 178      affected by IT blocks) rather than a BKPT instruction (which is
 179      not), then we need a 32-bit Thumb breakpoint to preserve the
 180      instruction count in IT blocks.  */
 181   const char *thumb2_breakpoint;
 182   int thumb2_breakpoint_size;
 183
 184   int jb_pc;                    /* Offset to PC value in jump buffer.
 185                                    If this is negative, longjmp support
 186                                    will be disabled.  */
 187   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 188
 189   /* Convention for returning structures.  */
 190   enum struct_return struct_return;
 191
 192   /* Cached core file helpers.  */
 193   struct regset *gregset, *fpregset, *vfpregset;
 194
 195   /* ISA-specific data types.  */
 196   struct type *arm_ext_type;
 197   struct type *neon_double_type;
 198   struct type *neon_quad_type;
 199
 200   /* Return the expected next PC if FRAME is stopped at a syscall
 201      instruction.  */
 202   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 203
 204    /* Parse swi insn args, sycall record.  */
 205   int (*arm_swi_record) (struct regcache *regcache);
 206 };
 207
 208 /* Structures used for displaced stepping.  */
 209
 210 /* The maximum number of temporaries available for displaced instructions.  */
 211 #define DISPLACED_TEMPS                 16
 212 /* The maximum number of modified instructions generated for one single-stepped
 213    instruction, including the breakpoint (usually at the end of the instruction
 214    sequence) and any scratch words, etc.  */
 215 #define DISPLACED_MODIFIED_INSNS        8
 216
 217 struct displaced_step_closure
 218 {
 219   ULONGEST tmp[DISPLACED_TEMPS];
 220   int rd;
 221   int wrote_to_pc;
 222   union
 223   {
 224     struct
 225     {
 226       int xfersize;
 227       int rn;                      /* Writeback register.  */
 228       unsigned int immed : 1;      /* Offset is immediate.  */
 229       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 230       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 231     } ldst;
 232
 233     struct
 234     {
 235       unsigned long dest;
 236       unsigned int link : 1;
 237       unsigned int exchange : 1;
 238       unsigned int cond : 4;
 239     } branch;
 240
 241     struct
 242     {
 243       unsigned int regmask;
 244       int rn;
 245       CORE_ADDR xfer_addr;
 246       unsigned int load : 1;
 247       unsigned int user : 1;
 248       unsigned int increment : 1;
 249       unsigned int before : 1;
 250       unsigned int writeback : 1;
 251       unsigned int cond : 4;
 252     } block;
 253
 254     struct
 255     {
 256       unsigned int immed : 1;
 257     } preload;
 258
 259     struct
 260     {
 261       /* If non-NULL, override generic SVC handling (e.g. for a particular
 262          OS).  */
 263       int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
 264                           struct displaced_step_closure *dsc);
 265     } svc;
 266   } u;
 267
 268   /* The size of original instruction, 2 or 4.  */
 269   unsigned int insn_size;
 270   /* True if the original insn (and thus all replacement insns) are Thumb
 271      instead of ARM.   */
 272   unsigned int is_thumb;
 273
 274   /* The slots in the array is used in this way below,
 275      - ARM instruction occupies one slot,
 276      - Thumb 16 bit instruction occupies one slot,
 277      - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
 278   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 279   int numinsns;
 280   CORE_ADDR insn_addr;
 281   CORE_ADDR scratch_base;
 282   void (*cleanup) (struct gdbarch *, struct regcache *,
 283                    struct displaced_step_closure *);
 284 };
 285
 286 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 287    write may write to the PC, specifies the way the CPSR T bit, etc. is
 288    modified by the instruction.  */
 289
 290 enum pc_write_style
 291 {
 292   BRANCH_WRITE_PC,
 293   BX_WRITE_PC,
 294   LOAD_WRITE_PC,
 295   ALU_WRITE_PC,
 296   CANNOT_WRITE_PC
 297 };
 298
 299 extern void
 300   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 301                               CORE_ADDR to, struct regcache *regs,
 302                               struct displaced_step_closure *dsc);
 303 extern void
 304   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 305                               CORE_ADDR to, struct displaced_step_closure *dsc);
 306 extern ULONGEST
 307   displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
 308                       int regno);
 309 extern void
 310   displaced_write_reg (struct regcache *regs,
 311                        struct displaced_step_closure *dsc, int regno,
 312                        ULONGEST val, enum pc_write_style write_pc);
 313
 314 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 315 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 316 void arm_insert_single_step_breakpoint (struct gdbarch *,
 317                                         struct address_space *, CORE_ADDR);
 318 int arm_deal_with_atomic_sequence (struct frame_info *);
 319 int arm_software_single_step (struct frame_info *);
 320 int arm_frame_is_thumb (struct frame_info *frame);
 321
 322 extern struct displaced_step_closure *
 323   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 324                                 struct regcache *);
 325 extern void arm_displaced_step_fixup (struct gdbarch *,
 326                                       struct displaced_step_closure *,
 327                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 328
 329 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 330 extern int arm_psr_thumb_bit (struct gdbarch *);
 331
 332 /* Is the instruction at the given memory address a Thumb or ARM
 333    instruction?  */
 334 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 335
 336 extern int arm_process_record (struct gdbarch *gdbarch,
 337                                struct regcache *regcache, CORE_ADDR addr);
 338 /* Functions exported from armbsd-tdep.h.  */
 339
 340 /* Return the appropriate register set for the core section identified
 341    by SECT_NAME and SECT_SIZE.  */
 342
 343 extern const struct regset *
 344   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 345                                    const char *sect_name, size_t sect_size);
 346
 347 /* Target descriptions.  */
 348 extern struct target_desc *tdesc_arm_with_m;
 349 extern struct target_desc *tdesc_arm_with_iwmmxt;
 350 extern struct target_desc *tdesc_arm_with_vfpv2;
 351 extern struct target_desc *tdesc_arm_with_vfpv3;
 352 extern struct target_desc *tdesc_arm_with_neon;
 353
 354 #endif /* arm-tdep.h */