gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002-2014 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25 struct address_space;
  26
  27 /* Register numbers of various important registers.  */
  28
  29 enum gdb_regnum {
  30   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  31   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  32   ARM_AP_REGNUM = 11,
  33   ARM_IP_REGNUM = 12,
  34   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  35   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  36   ARM_PC_REGNUM = 15,           /* Contains program counter */
  37   ARM_F0_REGNUM = 16,           /* first floating point register */
  38   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  39   ARM_F7_REGNUM = 23,           /* last floating point register */
  40   ARM_FPS_REGNUM = 24,          /* floating point status register */
  41   ARM_PS_REGNUM = 25,           /* Contains processor status */
  42   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  43   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  44   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  45   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  46   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  47   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  48   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  49   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  50   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  51   ARM_D0_REGNUM,                /* VFP double-precision registers.  */
  52   ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  53   ARM_FPSCR_REGNUM,
  54
  55   ARM_NUM_REGS,
  56
  57   /* Other useful registers.  */
  58   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  59   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  60   ARM_NUM_ARG_REGS = 4,
  61   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  62   ARM_NUM_FP_ARG_REGS = 4,
  63   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  64 };
  65
  66 /* Size of integer registers.  */
  67 #define INT_REGISTER_SIZE               4
  68
  69 /* Say how long FP registers are.  Used for documentation purposes and
  70    code readability in this header.  IEEE extended doubles are 80
  71    bits.  DWORD aligned they use 96 bits.  */
  72 #define FP_REGISTER_SIZE        12
  73
  74 /* Say how long VFP double precision registers are.  Used for documentation
  75    purposes and code readability.  These are fixed at 64 bits.  */
  76 #define VFP_REGISTER_SIZE       8
  77
  78 /* Number of machine registers.  The only define actually required
  79    is gdbarch_num_regs.  The other definitions are used for documentation
  80    purposes and code readability.  */
  81 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  82    (and called PS for processor status) so the status bits can be cleared
  83    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  84    in PS.  */
  85 #define NUM_FREGS       8       /* Number of floating point registers.  */
  86 #define NUM_SREGS       2       /* Number of status registers.  */
  87 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  88
  89
  90 /* Instruction condition field values.  */
  91 #define INST_EQ         0x0
  92 #define INST_NE         0x1
  93 #define INST_CS         0x2
  94 #define INST_CC         0x3
  95 #define INST_MI         0x4
  96 #define INST_PL         0x5
  97 #define INST_VS         0x6
  98 #define INST_VC         0x7
  99 #define INST_HI         0x8
 100 #define INST_LS         0x9
 101 #define INST_GE         0xa
 102 #define INST_LT         0xb
 103 #define INST_GT         0xc
 104 #define INST_LE         0xd
 105 #define INST_AL         0xe
 106 #define INST_NV         0xf
 107
 108 #define FLAG_N          0x80000000
 109 #define FLAG_Z          0x40000000
 110 #define FLAG_C          0x20000000
 111 #define FLAG_V          0x10000000
 112
 113 #define CPSR_T          0x20
 114
 115 #define XPSR_T          0x01000000
 116
 117 /* Type of floating-point code in use by inferior.  There are really 3 models
 118    that are traditionally supported (plus the endianness issue), but gcc can
 119    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 120    functions are passed in floating-point registers.
 121
 122    In addition to the traditional models, VFP adds two more.
 123
 124    If you update this enum, don't forget to update fp_model_strings in
 125    arm-tdep.c.  */
 126
 127 enum arm_float_model
 128 {
 129   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 130   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 131   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 132   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 133   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 134   ARM_FLOAT_LAST        /* Keep at end.  */
 135 };
 136
 137 /* ABI used by the inferior.  */
 138 enum arm_abi_kind
 139 {
 140   ARM_ABI_AUTO,
 141   ARM_ABI_APCS,
 142   ARM_ABI_AAPCS,
 143   ARM_ABI_LAST
 144 };
 145
 146 /* Convention for returning structures.  */
 147
 148 enum struct_return
 149 {
 150   pcc_struct_return,            /* Return "short" structures in memory.  */
 151   reg_struct_return             /* Return "short" structures in registers.  */
 152 };
 153
 154 /* Target-dependent structure in gdbarch.  */
 155 struct gdbarch_tdep
 156 {
 157   /* The ABI for this architecture.  It should never be set to
 158      ARM_ABI_AUTO.  */
 159   enum arm_abi_kind arm_abi;
 160
 161   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 162
 163   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 164   int have_vfp_registers;       /* Does the target report the VFP registers?  */
 165   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 166                                    VFP registers?  */
 167   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 168                                    NEON registers?  Requires
 169                                    have_vfp_pseudos.  */
 170   int have_neon;                /* Do we have a NEON unit?  */
 171
 172   int is_m;                     /* Does the target follow the "M" profile.  */
 173   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 174                                    will appear.  */
 175
 176   const gdb_byte *arm_breakpoint;       /* Breakpoint pattern for an ARM insn.  */
 177   int arm_breakpoint_size;      /* And its size.  */
 178   const gdb_byte *thumb_breakpoint;     /* Breakpoint pattern for a Thumb insn.  */
 179   int thumb_breakpoint_size;    /* And its size.  */
 180
 181   /* If the Thumb breakpoint is an undefined instruction (which is
 182      affected by IT blocks) rather than a BKPT instruction (which is
 183      not), then we need a 32-bit Thumb breakpoint to preserve the
 184      instruction count in IT blocks.  */
 185   const gdb_byte *thumb2_breakpoint;
 186   int thumb2_breakpoint_size;
 187
 188   int jb_pc;                    /* Offset to PC value in jump buffer.
 189                                    If this is negative, longjmp support
 190                                    will be disabled.  */
 191   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 192
 193   /* Convention for returning structures.  */
 194   enum struct_return struct_return;
 195
 196   /* ISA-specific data types.  */
 197   struct type *arm_ext_type;
 198   struct type *neon_double_type;
 199   struct type *neon_quad_type;
 200
 201   /* Return the expected next PC if FRAME is stopped at a syscall
 202      instruction.  */
 203   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 204
 205    /* syscall record.  */
 206   int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 207 };
 208
 209 /* Structures used for displaced stepping.  */
 210
 211 /* The maximum number of temporaries available for displaced instructions.  */
 212 #define DISPLACED_TEMPS                 16
 213 /* The maximum number of modified instructions generated for one single-stepped
 214    instruction, including the breakpoint (usually at the end of the instruction
 215    sequence) and any scratch words, etc.  */
 216 #define DISPLACED_MODIFIED_INSNS        8
 217
 218 struct displaced_step_closure
 219 {
 220   ULONGEST tmp[DISPLACED_TEMPS];
 221   int rd;
 222   int wrote_to_pc;
 223   union
 224   {
 225     struct
 226     {
 227       int xfersize;
 228       int rn;                      /* Writeback register.  */
 229       unsigned int immed : 1;      /* Offset is immediate.  */
 230       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 231       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 232     } ldst;
 233
 234     struct
 235     {
 236       unsigned long dest;
 237       unsigned int link : 1;
 238       unsigned int exchange : 1;
 239       unsigned int cond : 4;
 240     } branch;
 241
 242     struct
 243     {
 244       unsigned int regmask;
 245       int rn;
 246       CORE_ADDR xfer_addr;
 247       unsigned int load : 1;
 248       unsigned int user : 1;
 249       unsigned int increment : 1;
 250       unsigned int before : 1;
 251       unsigned int writeback : 1;
 252       unsigned int cond : 4;
 253     } block;
 254
 255     struct
 256     {
 257       unsigned int immed : 1;
 258     } preload;
 259
 260     struct
 261     {
 262       /* If non-NULL, override generic SVC handling (e.g. for a particular
 263          OS).  */
 264       int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
 265                           struct displaced_step_closure *dsc);
 266     } svc;
 267   } u;
 268
 269   /* The size of original instruction, 2 or 4.  */
 270   unsigned int insn_size;
 271   /* True if the original insn (and thus all replacement insns) are Thumb
 272      instead of ARM.   */
 273   unsigned int is_thumb;
 274
 275   /* The slots in the array is used in this way below,
 276      - ARM instruction occupies one slot,
 277      - Thumb 16 bit instruction occupies one slot,
 278      - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
 279   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 280   int numinsns;
 281   CORE_ADDR insn_addr;
 282   CORE_ADDR scratch_base;
 283   void (*cleanup) (struct gdbarch *, struct regcache *,
 284                    struct displaced_step_closure *);
 285 };
 286
 287 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 288    write may write to the PC, specifies the way the CPSR T bit, etc. is
 289    modified by the instruction.  */
 290
 291 enum pc_write_style
 292 {
 293   BRANCH_WRITE_PC,
 294   BX_WRITE_PC,
 295   LOAD_WRITE_PC,
 296   ALU_WRITE_PC,
 297   CANNOT_WRITE_PC
 298 };
 299
 300 extern void
 301   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 302                               CORE_ADDR to, struct regcache *regs,
 303                               struct displaced_step_closure *dsc);
 304 extern void
 305   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 306                               CORE_ADDR to, struct displaced_step_closure *dsc);
 307 extern ULONGEST
 308   displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
 309                       int regno);
 310 extern void
 311   displaced_write_reg (struct regcache *regs,
 312                        struct displaced_step_closure *dsc, int regno,
 313                        ULONGEST val, enum pc_write_style write_pc);
 314
 315 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 316 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 317 void arm_insert_single_step_breakpoint (struct gdbarch *,
 318                                         struct address_space *, CORE_ADDR);
 319 int arm_deal_with_atomic_sequence (struct frame_info *);
 320 int arm_software_single_step (struct frame_info *);
 321 int arm_frame_is_thumb (struct frame_info *frame);
 322
 323 extern struct displaced_step_closure *
 324   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 325                                 struct regcache *);
 326 extern void arm_displaced_step_fixup (struct gdbarch *,
 327                                       struct displaced_step_closure *,
 328                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 329
 330 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 331 extern int arm_psr_thumb_bit (struct gdbarch *);
 332
 333 /* Is the instruction at the given memory address a Thumb or ARM
 334    instruction?  */
 335 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 336
 337 extern int arm_process_record (struct gdbarch *gdbarch,
 338                                struct regcache *regcache, CORE_ADDR addr);
 339 /* Functions exported from armbsd-tdep.h.  */
 340
 341 /* Return the appropriate register set for the core section identified
 342    by SECT_NAME and SECT_SIZE.  */
 343
 344 extern const struct regset *
 345   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 346                                    const char *sect_name, size_t sect_size);
 347
 348 /* Target descriptions.  */
 349 extern struct target_desc *tdesc_arm_with_m;
 350 extern struct target_desc *tdesc_arm_with_iwmmxt;
 351 extern struct target_desc *tdesc_arm_with_vfpv2;
 352 extern struct target_desc *tdesc_arm_with_vfpv3;
 353 extern struct target_desc *tdesc_arm_with_neon;
 354
 355 #endif /* arm-tdep.h */