gdb/bfin-tdep.c

   1 /* Target-dependent code for Analog Devices Blackfin processor, for GDB.
   2
   3    Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    Contributed by Analog Devices, Inc.
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  22
  23 #include "defs.h"
  24 #include "gdb_string.h"
  25 #include "inferior.h"
  26 #include "gdbcore.h"
  27 #include "arch-utils.h"
  28 #include "regcache.h"
  29 #include "frame.h"
  30 #include "frame-unwind.h"
  31 #include "frame-base.h"
  32 #include "trad-frame.h"
  33 #include "dis-asm.h"
  34 #include "gdb_assert.h"
  35 #include "sim-regno.h"
  36 #include "gdb/sim-bfin.h"
  37 #include "dwarf2-frame.h"
  38 #include "symtab.h"
  39 #include "elf-bfd.h"
  40 #include "elf/bfin.h"
  41 #include "osabi.h"
  42 #include "infcall.h"
  43 #include "xml-syscall.h"
  44 #include "bfin-tdep.h"
  45
  46 /* Macros used by prologue functions.  */
  47 #define P_LINKAGE                       0xE800
  48 #define P_MINUS_SP1                     0x0140
  49 #define P_MINUS_SP2                     0x05C0
  50 #define P_MINUS_SP3                     0x0540
  51 #define P_MINUS_SP4                     0x04C0
  52 #define P_SP_PLUS                       0x6C06
  53 #define P_P2_LOW                        0xE10A
  54 #define P_P2_HIGH                       0XE14A
  55 #define P_SP_EQ_SP_PLUS_P2              0X5BB2
  56 #define P_SP_EQ_P2_PLUS_SP              0x5B96
  57 #define P_MINUS_MINUS_SP_EQ_RETS        0x0167
  58
  59 /* Macros used for program flow control.  */
  60 /* 16 bit instruction, max  */
  61 #define P_16_BIT_INSR_MAX               0xBFFF
  62 /* 32 bit instruction, min  */
  63 #define P_32_BIT_INSR_MIN               0xC000
  64 /* 32 bit instruction, max  */
  65 #define P_32_BIT_INSR_MAX               0xE801
  66 /* jump (preg), 16-bit, min  */
  67 #define P_JUMP_PREG_MIN                 0x0050
  68 /* jump (preg), 16-bit, max  */
  69 #define P_JUMP_PREG_MAX                 0x0057
  70 /* jump (pc+preg), 16-bit, min  */
  71 #define P_JUMP_PC_PLUS_PREG_MIN         0x0080
  72 /* jump (pc+preg), 16-bit, max  */
  73 #define P_JUMP_PC_PLUS_PREG_MAX         0x0087
  74 /* jump.s pcrel13m2, 16-bit, min  */
  75 #define P_JUMP_S_MIN                    0x2000
  76 /* jump.s pcrel13m2, 16-bit, max  */
  77 #define P_JUMP_S_MAX                    0x2FFF
  78 /* jump.l pcrel25m2, 32-bit, min  */
  79 #define P_JUMP_L_MIN                    0xE200
  80 /* jump.l pcrel25m2, 32-bit, max  */
  81 #define P_JUMP_L_MAX                    0xE2FF
  82 /* conditional jump pcrel11m2, 16-bit, min  */
  83 #define P_IF_CC_JUMP_MIN                0x1800
  84 /* conditional jump pcrel11m2, 16-bit, max  */
  85 #define P_IF_CC_JUMP_MAX                0x1BFF
  86 /* conditional jump(bp) pcrel11m2, 16-bit, min  */
  87 #define P_IF_CC_JUMP_BP_MIN             0x1C00
  88 /* conditional jump(bp) pcrel11m2, 16-bit, max  */
  89 #define P_IF_CC_JUMP_BP_MAX             0x1FFF
  90 /* conditional !jump pcrel11m2, 16-bit, min  */
  91 #define P_IF_NOT_CC_JUMP_MIN            0x1000
  92 /* conditional !jump pcrel11m2, 16-bit, max  */
  93 #define P_IF_NOT_CC_JUMP_MAX            0x13FF
  94 /* conditional jump(bp) pcrel11m2, 16-bit, min  */
  95 #define P_IF_NOT_CC_JUMP_BP_MIN         0x1400
  96 /* conditional jump(bp) pcrel11m2, 16-bit, max  */
  97 #define P_IF_NOT_CC_JUMP_BP_MAX         0x17FF
  98 /* call (preg), 16-bit, min  */
  99 #define P_CALL_PREG_MIN                 0x0060
 100 /* call (preg), 16-bit, max  */
 101 #define P_CALL_PREG_MAX                 0x0067
 102 /* call (pc+preg), 16-bit, min  */
 103 #define P_CALL_PC_PLUS_PREG_MIN         0x0070
 104 /* call (pc+preg), 16-bit, max  */
 105 #define P_CALL_PC_PLUS_PREG_MAX         0x0077
 106 /* call pcrel25m2, 32-bit, min  */
 107 #define P_CALL_MIN                      0xE300
 108 /* call pcrel25m2, 32-bit, max  */
 109 #define P_CALL_MAX                      0xE3FF
 110 /* RTS  */
 111 #define P_RTS                           0x0010
 112 /* MNOP  */
 113 #define P_MNOP                          0xC803
 114 /* EXCPT, 16-bit, min  */
 115 #define P_EXCPT_MIN                     0x00A0
 116 /* EXCPT, 16-bit, max  */
 117 #define P_EXCPT_MAX                     0x00AF
 118 /* multi instruction mask 1, 16-bit  */
 119 #define P_BIT_MULTI_INS_1               0xC000
 120 /* multi instruction mask 2, 16-bit  */
 121 #define P_BIT_MULTI_INS_2               0x0800
 122
 123 /* The maximum bytes we search to skip the prologue.  */
 124 #define UPPER_LIMIT                     40
 125
 126 /* ASTAT bits  */
 127 #define ASTAT_CC_POS                    5
 128 #define ASTAT_CC                        (1 << ASTAT_CC_POS)
 129
 130 /* Initial value: Register names used in BFIN's ISA documentation.  */
 131
 132 static const char * const bfin_register_name_strings[] =
 133 {
 134   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 135   "p0", "p1", "p2", "p3", "p4", "p5", "sp", "fp",
 136   "i0", "i1", "i2", "i3", "m0", "m1", "m2", "m3",
 137   "b0", "b1", "b2", "b3", "l0", "l1", "l2", "l3",
 138   "a0x", "a0w", "a1x", "a1w", "astat", "rets",
 139   "lc0", "lt0", "lb0", "lc1", "lt1", "lb1", "cycles", "cycles2",
 140   "usp", "seqstat", "syscfg", "reti", "retx", "retn", "rete",
 141   "pc", "cc",
 142 };
 143
 144 #define NUM_BFIN_REGNAMES ARRAY_SIZE (bfin_register_name_strings)
 145
 146
 147 /* In this diagram successive memory locations increase downwards or the
 148    stack grows upwards with negative indices.  (PUSH analogy for stack.)
 149
 150    The top frame is the "frame" of the current function being executed.
 151
 152      +--------------+ SP    -
 153      |  local vars  |       ^
 154      +--------------+       |
 155      |  save regs   |       |
 156      +--------------+ FP    |
 157      |   old FP    -|--    top
 158      +--------------+  |  frame
 159      |    RETS      |  |    |
 160      +--------------+  |    |
 161      |   param 1    |  |    |
 162      |   param 2    |  |    |
 163      |    ...       |  |    V
 164      +--------------+  |    -
 165      |  local vars  |  |    ^
 166      +--------------+  |    |
 167      |  save regs   |  |    |
 168      +--------------+<-     |
 169      |   old FP    -|--   next
 170      +--------------+  |  frame
 171      |    RETS      |  |    |
 172      +--------------+  |    |
 173      |   param 1    |  |    |
 174      |   param 2    |  |    |
 175      |    ...       |  |    V
 176      +--------------+  |    -
 177      |  local vars  |  |    ^
 178      +--------------+  |    |
 179      |  save regs   |  |    |
 180      +--------------+<-  next frame
 181      |   old FP     |       |
 182      +--------------+       |
 183      |    RETS      |       V
 184      +--------------+       -
 185
 186    The frame chain is formed as following:
 187
 188      FP has the topmost frame.
 189      FP + 4 has the previous FP and so on.  */
 190
 191
 192 /* Map from DWARF2 register number to GDB register number.  */
 193
 194 static const int map_gcc_gdb[] =
 195 {
 196   BFIN_R0_REGNUM,
 197   BFIN_R1_REGNUM,
 198   BFIN_R2_REGNUM,
 199   BFIN_R3_REGNUM,
 200   BFIN_R4_REGNUM,
 201   BFIN_R5_REGNUM,
 202   BFIN_R6_REGNUM,
 203   BFIN_R7_REGNUM,
 204   BFIN_P0_REGNUM,
 205   BFIN_P1_REGNUM,
 206   BFIN_P2_REGNUM,
 207   BFIN_P3_REGNUM,
 208   BFIN_P4_REGNUM,
 209   BFIN_P5_REGNUM,
 210   BFIN_SP_REGNUM,
 211   BFIN_FP_REGNUM,
 212   BFIN_I0_REGNUM,
 213   BFIN_I1_REGNUM,
 214   BFIN_I2_REGNUM,
 215   BFIN_I3_REGNUM,
 216   BFIN_B0_REGNUM,
 217   BFIN_B1_REGNUM,
 218   BFIN_B2_REGNUM,
 219   BFIN_B3_REGNUM,
 220   BFIN_L0_REGNUM,
 221   BFIN_L1_REGNUM,
 222   BFIN_L2_REGNUM,
 223   BFIN_L3_REGNUM,
 224   BFIN_M0_REGNUM,
 225   BFIN_M1_REGNUM,
 226   BFIN_M2_REGNUM,
 227   BFIN_M3_REGNUM,
 228   BFIN_A0_DOT_X_REGNUM,
 229   BFIN_A1_DOT_X_REGNUM,
 230   BFIN_CC_REGNUM,
 231   BFIN_RETS_REGNUM,
 232   BFIN_RETI_REGNUM,
 233   BFIN_RETX_REGNUM,
 234   BFIN_RETN_REGNUM,
 235   BFIN_RETE_REGNUM,
 236   BFIN_ASTAT_REGNUM,
 237   BFIN_SEQSTAT_REGNUM,
 238   BFIN_USP_REGNUM,
 239   BFIN_LT0_REGNUM,
 240   BFIN_LT1_REGNUM,
 241   BFIN_LC0_REGNUM,
 242   BFIN_LC1_REGNUM,
 243   BFIN_LB0_REGNUM,
 244   BFIN_LB1_REGNUM
 245 };
 246
 247
 248 struct bfin_frame_cache
 249 {
 250   /* Base address.  */
 251   CORE_ADDR base;
 252   CORE_ADDR sp_offset;
 253   CORE_ADDR pc;
 254   int frameless_pc_value;
 255
 256   /* Saved registers.  */
 257   CORE_ADDR saved_regs[BFIN_NUM_REGS];
 258   CORE_ADDR saved_sp;
 259
 260   /* Stack space reserved for local variables.  */
 261   long locals;
 262 };
 263
 264 /* Allocate and initialize a frame cache.  */
 265
 266 static struct bfin_frame_cache *
 267 bfin_alloc_frame_cache (void)
 268 {
 269   struct bfin_frame_cache *cache;
 270   int i;
 271
 272   cache = FRAME_OBSTACK_ZALLOC (struct bfin_frame_cache);
 273
 274   /* Base address.  */
 275   cache->base = 0;
 276   cache->sp_offset = -4;
 277   cache->pc = 0;
 278   cache->frameless_pc_value = 0;
 279
 280   /* Saved registers.  We initialize these to -1 since zero is a valid
 281      offset (that's where fp is supposed to be stored).  */
 282   for (i = 0; i < BFIN_NUM_REGS; i++)
 283     cache->saved_regs[i] = -1;
 284
 285   /* Frameless until proven otherwise.  */
 286   cache->locals = -1;
 287
 288   return cache;
 289 }
 290
 291 static struct bfin_frame_cache *
 292 bfin_frame_cache (struct frame_info *this_frame, void **this_cache)
 293 {
 294   struct bfin_frame_cache *cache;
 295   int i;
 296
 297   if (*this_cache)
 298     return *this_cache;
 299
 300   cache = bfin_alloc_frame_cache ();
 301   *this_cache = cache;
 302
 303   cache->base = get_frame_register_unsigned (this_frame, BFIN_FP_REGNUM);
 304   if (cache->base == 0)
 305     return cache;
 306
 307   /* For normal frames, PC is stored at [FP + 4].  */
 308   cache->saved_regs[BFIN_PC_REGNUM] = 4;
 309   cache->saved_regs[BFIN_FP_REGNUM] = 0;
 310
 311   /* Adjust all the saved registers such that they contain addresses
 312      instead of offsets.  */
 313   for (i = 0; i < BFIN_NUM_REGS; i++)
 314     if (cache->saved_regs[i] != -1)
 315       cache->saved_regs[i] += cache->base;
 316
 317   cache->pc = get_frame_func (this_frame) ;
 318   if (cache->pc == 0 || cache->pc == get_frame_pc (this_frame))
 319     {
 320       /* Either there is no prologue (frameless function) or we are at
 321          the start of a function.  In short we do not have a frame.
 322          PC is stored in rets register.  FP points to previous frame.  */
 323
 324       cache->saved_regs[BFIN_PC_REGNUM] =
 325         get_frame_register_unsigned (this_frame, BFIN_RETS_REGNUM);
 326       cache->frameless_pc_value = 1;
 327       cache->base = get_frame_register_unsigned (this_frame, BFIN_FP_REGNUM);
 328       cache->saved_regs[BFIN_FP_REGNUM] = cache->base;
 329       cache->saved_sp = cache->base;
 330     }
 331   else
 332     {
 333       cache->frameless_pc_value = 0;
 334
 335       /* Now that we have the base address for the stack frame we can
 336          calculate the value of SP in the calling frame.  */
 337       cache->saved_sp = cache->base + 8;
 338     }
 339
 340   return cache;
 341 }
 342
 343 static void
 344 bfin_frame_this_id (struct frame_info *this_frame,
 345                     void **this_cache,
 346                     struct frame_id *this_id)
 347 {
 348   struct bfin_frame_cache *cache = bfin_frame_cache (this_frame, this_cache);
 349
 350   /* This marks the outermost frame.  */
 351   if (cache->base == 0)
 352     return;
 353
 354   /* See the end of bfin_push_dummy_call.  */
 355   *this_id = frame_id_build (cache->base + 8, cache->pc);
 356 }
 357
 358 static struct value *
 359 bfin_frame_prev_register (struct frame_info *this_frame,
 360                           void **this_cache,
 361                           int regnum)
 362 {
 363   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 364   struct bfin_frame_cache *cache = bfin_frame_cache (this_frame, this_cache);
 365
 366   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
 367     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
 368
 369   if (regnum < BFIN_NUM_REGS && cache->saved_regs[regnum] != -1)
 370     return frame_unwind_got_memory (this_frame, regnum,
 371                                     cache->saved_regs[regnum]);
 372
 373   return frame_unwind_got_register (this_frame, regnum, regnum);
 374 }
 375
 376 static const struct frame_unwind bfin_frame_unwind =
 377 {
 378   NORMAL_FRAME,
 379   default_frame_unwind_stop_reason,
 380   bfin_frame_this_id,
 381   bfin_frame_prev_register,
 382   NULL,
 383   default_frame_sniffer
 384 };
 385
 386 /* Check for "[--SP] = <reg>;" insns.  These are appear in function
 387    prologues to save misc registers onto the stack.  */
 388
 389 static int
 390 is_minus_minus_sp (int op)
 391 {
 392   op &= 0xFFC0;
 393
 394   if ((op == P_MINUS_SP1) || (op == P_MINUS_SP2)
 395       || (op == P_MINUS_SP3) || (op == P_MINUS_SP4))
 396     return 1;
 397
 398   return 0;
 399 }
 400
 401 /* Skip all the insns that appear in generated function prologues.  */
 402
 403 static CORE_ADDR
 404 bfin_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 405 {
 406   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 407   int op = read_memory_unsigned_integer (pc, 2, byte_order);
 408   CORE_ADDR orig_pc = pc;
 409   int done = 0;
 410
 411   /* The new gcc prologue generates the register saves BEFORE the link
 412      or RETS saving instruction.
 413      So, our job is to stop either at those instructions or some upper
 414      limit saying there is no frame!  */
 415
 416   while (!done)
 417     {
 418       if (is_minus_minus_sp (op))
 419         {
 420           while (is_minus_minus_sp (op))
 421             {
 422               pc += 2;
 423               op = read_memory_unsigned_integer (pc, 2, byte_order);
 424             }
 425
 426           if (op == P_LINKAGE)
 427             pc += 4;
 428
 429           done = 1;
 430         }
 431       else if (op == P_LINKAGE)
 432         {
 433           pc += 4;
 434           done = 1;
 435         }
 436       else if (op == P_MINUS_MINUS_SP_EQ_RETS)
 437         {
 438           pc += 2;
 439           done = 1;
 440         }
 441       else if (op == P_RTS)
 442         {
 443           done = 1;
 444         }
 445       else if ((op >= P_JUMP_PREG_MIN && op <= P_JUMP_PREG_MAX)
 446                || (op >= P_JUMP_PC_PLUS_PREG_MIN
 447                    && op <= P_JUMP_PC_PLUS_PREG_MAX)
 448                || (op == P_JUMP_S_MIN && op <= P_JUMP_S_MAX))
 449         {
 450           done = 1;
 451         }
 452       else if (pc - orig_pc >= UPPER_LIMIT)
 453         {
 454           warning (_("Function Prologue not recognised; "
 455                      "pc will point to ENTRY_POINT of the function"));
 456           pc = orig_pc + 2;
 457           done = 1;
 458         }
 459       else
 460         {
 461           pc += 2; /* Not a terminating instruction go on.  */
 462           op = read_memory_unsigned_integer (pc, 2, byte_order);
 463         }
 464     }
 465
 466    /* TODO:
 467       Dwarf2 uses entry point value AFTER some register initializations.
 468       We should perhaps skip such asssignments as well (R6 = R1, ...).  */
 469
 470   return pc;
 471 }
 472
 473 /* Return the GDB type object for the "standard" data type of data in
 474    register N.  This should be void pointer for P0-P5, SP, FP;
 475    void pointer to function for PC; int otherwise.  */
 476
 477 static struct type *
 478 bfin_register_type (struct gdbarch *gdbarch, int regnum)
 479 {
 480   if ((regnum >= BFIN_P0_REGNUM && regnum <= BFIN_FP_REGNUM)
 481       || regnum == BFIN_USP_REGNUM)
 482     return builtin_type (gdbarch)->builtin_data_ptr;
 483
 484   if (regnum == BFIN_PC_REGNUM || regnum == BFIN_RETS_REGNUM
 485       || regnum == BFIN_RETI_REGNUM || regnum == BFIN_RETX_REGNUM
 486       || regnum == BFIN_RETN_REGNUM || regnum == BFIN_RETE_REGNUM
 487       || regnum == BFIN_LT0_REGNUM || regnum == BFIN_LB0_REGNUM
 488       || regnum == BFIN_LT1_REGNUM || regnum == BFIN_LB1_REGNUM)
 489     return builtin_type (gdbarch)->builtin_func_ptr;
 490
 491   return builtin_type (gdbarch)->builtin_int32;
 492 }
 493
 494 static CORE_ADDR
 495 bfin_push_dummy_call (struct gdbarch *gdbarch,
 496                       struct value *function,
 497                       struct regcache *regcache,
 498                       CORE_ADDR bp_addr,
 499                       int nargs,
 500                       struct value **args,
 501                       CORE_ADDR sp,
 502                       int struct_return,
 503                       CORE_ADDR struct_addr)
 504 {
 505   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 506   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
 507   char buf[4];
 508   int i;
 509   long reg_r0, reg_r1, reg_r2;
 510   int total_len = 0;
 511   enum bfin_abi abi = bfin_abi (gdbarch);
 512   CORE_ADDR func_addr = find_function_addr (function, NULL);
 513
 514   for (i = nargs - 1; i >= 0; i--)
 515     {
 516       struct type *value_type = value_enclosing_type (args[i]);
 517       int len = TYPE_LENGTH (value_type);
 518
 519       total_len += (len + 3) & ~3;
 520     }
 521
 522   /* At least twelve bytes of stack space must be allocated for the function's
 523      arguments, even for functions that have less than 12 bytes of argument
 524      data.  */
 525
 526   if (total_len < 12)
 527     sp -= 12 - total_len;
 528
 529   /* Push arguments in reverse order.  */
 530
 531   for (i = nargs - 1; i >= 0; i--)
 532     {
 533       struct type *value_type = value_enclosing_type (args[i]);
 534       struct type *arg_type = check_typedef (value_type);
 535       int len = TYPE_LENGTH (value_type);
 536       int container_len = (len + 3) & ~3;
 537
 538       sp -= container_len;
 539       write_memory (sp, value_contents_writeable (args[i]), container_len);
 540     }
 541
 542   /* Initialize R0, R1, and R2 to the first 3 words of parameters.  */
 543
 544   reg_r0 = read_memory_integer (sp, 4, byte_order);
 545   regcache_cooked_write_unsigned (regcache, BFIN_R0_REGNUM, reg_r0);
 546   reg_r1 = read_memory_integer (sp + 4, 4, byte_order);
 547   regcache_cooked_write_unsigned (regcache, BFIN_R1_REGNUM, reg_r1);
 548   reg_r2 = read_memory_integer (sp + 8, 4, byte_order);
 549   regcache_cooked_write_unsigned (regcache, BFIN_R2_REGNUM, reg_r2);
 550
 551   /* Store struct value address.  */
 552
 553   if (struct_return)
 554     regcache_cooked_write_unsigned (regcache, BFIN_P0_REGNUM, struct_addr);
 555
 556   /* Set the dummy return value to bp_addr.
 557      A dummy breakpoint will be setup to execute the call.  */
 558
 559   regcache_cooked_write_unsigned (regcache, BFIN_RETS_REGNUM, bp_addr);
 560
 561   /* Finally, update the stack pointer.  */
 562
 563   regcache_cooked_write_unsigned (regcache, BFIN_SP_REGNUM, sp);
 564
 565   return sp;
 566 }
 567
 568 /* Convert DWARF2 register number REG to the appropriate register number
 569    used by GDB.  */
 570
 571 static int
 572 bfin_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 573 {
 574   if (reg > ARRAY_SIZE (map_gcc_gdb))
 575     return 0;
 576
 577   return map_gcc_gdb[reg];
 578 }
 579
 580 /* This function implements the BREAKPOINT_FROM_PC macro.  It returns
 581    a pointer to a string of bytes that encode a breakpoint instruction,
 582    stores the length of the string to *lenptr, and adjusts the program
 583    counter (if necessary) to point to the actual memory location where
 584    the breakpoint should be inserted.  */
 585
 586 static const unsigned char *
 587 bfin_breakpoint_from_pc (struct gdbarch *gdbarch,
 588                          CORE_ADDR *pcptr, int *lenptr)
 589 {
 590   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 591   unsigned short iw;
 592   static unsigned char bfin_breakpoint[] = {0xa1, 0x00, 0x00, 0x00};
 593   static unsigned char bfin_sim_breakpoint[] = {0x25, 0x00, 0x00, 0x00};
 594
 595   iw = read_memory_unsigned_integer (*pcptr, 2, byte_order);
 596
 597   if ((iw & 0xf000) >= 0xc000)
 598     /* 32-bit instruction.  */
 599     *lenptr = 4;
 600   else
 601     *lenptr = 2;
 602
 603   if (strcmp (target_shortname, "sim") == 0)
 604     return bfin_sim_breakpoint;
 605   else
 606     return bfin_breakpoint;
 607 }
 608
 609 static void
 610 bfin_extract_return_value (struct type *type,
 611                            struct regcache *regs,
 612                            gdb_byte *dst)
 613 {
 614   struct gdbarch *gdbarch = get_regcache_arch (regs);
 615   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 616   bfd_byte *valbuf = dst;
 617   int len = TYPE_LENGTH (type);
 618   ULONGEST tmp;
 619   int regno = BFIN_R0_REGNUM;
 620
 621   gdb_assert (len <= 8);
 622
 623   while (len > 0)
 624     {
 625       regcache_cooked_read_unsigned (regs, regno++, &tmp);
 626       store_unsigned_integer (valbuf, (len > 4 ? 4 : len), tmp, byte_order);
 627       len -= 4;
 628       valbuf += 4;
 629     }
 630 }
 631
 632 /* Write into appropriate registers a function return value of type
 633    TYPE, given in virtual format.  */
 634
 635 static void
 636 bfin_store_return_value (struct type *type,
 637                          struct regcache *regs,
 638                          const gdb_byte *src)
 639 {
 640   const bfd_byte *valbuf = src;
 641
 642   /* Integral values greater than one word are stored in consecutive
 643      registers starting with R0.  This will always be a multiple of
 644      the register size.  */
 645
 646   int len = TYPE_LENGTH (type);
 647   int regno = BFIN_R0_REGNUM;
 648
 649   gdb_assert (len <= 8);
 650
 651   while (len > 0)
 652     {
 653       regcache_cooked_write (regs, regno++, valbuf);
 654       len -= 4;
 655       valbuf += 4;
 656     }
 657 }
 658
 659 /* Determine, for architecture GDBARCH, how a return value of TYPE
 660    should be returned.  If it is supposed to be returned in registers,
 661    and READBUF is nonzero, read the appropriate value from REGCACHE,
 662    and copy it into READBUF.  If WRITEBUF is nonzero, write the value
 663    from WRITEBUF into REGCACHE.  */
 664
 665 static enum return_value_convention
 666 bfin_return_value (struct gdbarch *gdbarch,
 667                    struct type *func_type,
 668                    struct type *type,
 669                    struct regcache *regcache,
 670                    gdb_byte *readbuf,
 671                    const gdb_byte *writebuf)
 672 {
 673   if (TYPE_LENGTH (type) > 8)
 674     return RETURN_VALUE_STRUCT_CONVENTION;
 675
 676   if (readbuf)
 677     bfin_extract_return_value (type, regcache, readbuf);
 678
 679   if (writebuf)
 680     bfin_store_return_value (type, regcache, writebuf);
 681
 682   return RETURN_VALUE_REGISTER_CONVENTION;
 683 }
 684
 685 /* Return the BFIN register name corresponding to register I.  */
 686
 687 static const char *
 688 bfin_register_name (struct gdbarch *gdbarch, int i)
 689 {
 690   return bfin_register_name_strings[i];
 691 }
 692
 693 static enum register_status
 694 bfin_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
 695                            int regnum, gdb_byte *buffer)
 696 {
 697   gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
 698   enum register_status status;
 699
 700   if (regnum != BFIN_CC_REGNUM)
 701     internal_error (__FILE__, __LINE__,
 702                     _("invalid register number %d"), regnum);
 703
 704   /* Extract the CC bit from the ASTAT register.  */
 705   status = regcache_raw_read (regcache, BFIN_ASTAT_REGNUM, buf);
 706   if (status == REG_VALID)
 707     {
 708       buffer[1] = buffer[2] = buffer[3] = 0;
 709       buffer[0] = !!(buf[0] & ASTAT_CC);
 710     }
 711   return status;
 712 }
 713
 714 static void
 715 bfin_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
 716                             int regnum, const gdb_byte *buffer)
 717 {
 718   gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
 719
 720   if (regnum != BFIN_CC_REGNUM)
 721     internal_error (__FILE__, __LINE__,
 722                     _("invalid register number %d"), regnum);
 723
 724   /* Overlay the CC bit in the ASTAT register.  */
 725   regcache_raw_read (regcache, BFIN_ASTAT_REGNUM, buf);
 726   buf[0] = (buf[0] & ~ASTAT_CC) | ((buffer[0] & 1) << ASTAT_CC_POS);
 727   regcache_raw_write (regcache, BFIN_ASTAT_REGNUM, buf);
 728 }
 729
 730 static CORE_ADDR
 731 bfin_frame_base_address (struct frame_info *this_frame, void **this_cache)
 732 {
 733   struct bfin_frame_cache *cache = bfin_frame_cache (this_frame, this_cache);
 734
 735   return cache->base;
 736 }
 737
 738 static CORE_ADDR
 739 bfin_frame_local_address (struct frame_info *this_frame, void **this_cache)
 740 {
 741   struct bfin_frame_cache *cache = bfin_frame_cache (this_frame, this_cache);
 742
 743   return cache->base - 4;
 744 }
 745
 746 static CORE_ADDR
 747 bfin_frame_args_address (struct frame_info *this_frame, void **this_cache)
 748 {
 749   struct bfin_frame_cache *cache = bfin_frame_cache (this_frame, this_cache);
 750
 751   return cache->base + 8;
 752 }
 753
 754 static const struct frame_base bfin_frame_base =
 755 {
 756   &bfin_frame_unwind,
 757   bfin_frame_base_address,
 758   bfin_frame_local_address,
 759   bfin_frame_args_address
 760 };
 761
 762 static struct frame_id
 763 bfin_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
 764 {
 765   CORE_ADDR sp;
 766
 767   sp = get_frame_register_unsigned (this_frame, BFIN_SP_REGNUM);
 768
 769   return frame_id_build (sp, get_frame_pc (this_frame));
 770 }
 771
 772 static CORE_ADDR
 773 bfin_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 774 {
 775   return frame_unwind_register_unsigned (next_frame, BFIN_PC_REGNUM);
 776 }
 777
 778 static CORE_ADDR
 779 bfin_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
 780 {
 781   return (address & ~0x3);
 782 }
 783
 784 enum bfin_abi
 785 bfin_abi (struct gdbarch *gdbarch)
 786 {
 787   return gdbarch_tdep (gdbarch)->bfin_abi;
 788 }
 789
 790 /* Initialize the current architecture based on INFO.  If possible,
 791    re-use an architecture from ARCHES, which is a list of
 792    architectures already created during this debugging session.
 793
 794    Called e.g. at program startup, when reading a core file, and when
 795    reading a binary file.  */
 796
 797 static struct gdbarch *
 798 bfin_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 799 {
 800   struct gdbarch_tdep *tdep;
 801   struct gdbarch *gdbarch;
 802   int elf_flags;
 803   enum bfin_abi abi;
 804
 805   /* Extract the ELF flags, if available.  */
 806   if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
 807     elf_flags = elf_elfheader (info.abfd)->e_flags;
 808   else
 809     elf_flags = 0;
 810
 811   abi = BFIN_ABI_FLAT;
 812
 813   /* If there is already a candidate, use it.  */
 814
 815   for (arches = gdbarch_list_lookup_by_info (arches, &info);
 816        arches != NULL;
 817        arches = gdbarch_list_lookup_by_info (arches->next, &info))
 818     {
 819       if (gdbarch_tdep (arches->gdbarch)->bfin_abi != abi)
 820         continue;
 821       return arches->gdbarch;
 822     }
 823
 824   tdep = XMALLOC (struct gdbarch_tdep);
 825   gdbarch = gdbarch_alloc (&info, tdep);
 826
 827   tdep->bfin_abi = abi;
 828
 829   set_gdbarch_num_regs (gdbarch, BFIN_NUM_REGS);
 830   set_gdbarch_pseudo_register_read (gdbarch, bfin_pseudo_register_read);
 831   set_gdbarch_pseudo_register_write (gdbarch, bfin_pseudo_register_write);
 832   set_gdbarch_num_pseudo_regs (gdbarch, BFIN_NUM_PSEUDO_REGS);
 833   set_gdbarch_sp_regnum (gdbarch, BFIN_SP_REGNUM);
 834   set_gdbarch_pc_regnum (gdbarch, BFIN_PC_REGNUM);
 835   set_gdbarch_ps_regnum (gdbarch, BFIN_ASTAT_REGNUM);
 836   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, bfin_reg_to_regnum);
 837   set_gdbarch_register_name (gdbarch, bfin_register_name);
 838   set_gdbarch_register_type (gdbarch, bfin_register_type);
 839   set_gdbarch_dummy_id (gdbarch, bfin_dummy_id);
 840   set_gdbarch_push_dummy_call (gdbarch, bfin_push_dummy_call);
 841   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
 842   set_gdbarch_return_value (gdbarch, bfin_return_value);
 843   set_gdbarch_skip_prologue (gdbarch, bfin_skip_prologue);
 844   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 845   set_gdbarch_breakpoint_from_pc (gdbarch, bfin_breakpoint_from_pc);
 846   set_gdbarch_decr_pc_after_break (gdbarch, 2);
 847   set_gdbarch_frame_args_skip (gdbarch, 8);
 848   set_gdbarch_unwind_pc (gdbarch, bfin_unwind_pc);
 849   set_gdbarch_frame_align (gdbarch, bfin_frame_align);
 850   set_gdbarch_print_insn (gdbarch, print_insn_bfin);
 851
 852   /* Hook in ABI-specific overrides, if they have been registered.  */
 853   gdbarch_init_osabi (info, gdbarch);
 854
 855   dwarf2_append_unwinders (gdbarch);
 856
 857   frame_base_set_default (gdbarch, &bfin_frame_base);
 858
 859   frame_unwind_append_unwinder (gdbarch, &bfin_frame_unwind);
 860
 861   return gdbarch;
 862 }
 863
 864 /* Provide a prototype to silence -Wmissing-prototypes.  */
 865 extern initialize_file_ftype _initialize_bfin_tdep;
 866
 867 void
 868 _initialize_bfin_tdep (void)
 869 {
 870   register_gdbarch_init (bfd_arch_bfin, bfin_gdbarch_init);
 871 }