1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "exceptions.h"
48 #include "i386-tdep.h"
49 #include "i387-tdep.h"
50 #include "x86-xstate.h"
53 #include "record-full.h"
56 #include "features/i386/i386.c"
57 #include "features/i386/i386-avx.c"
58 #include "features/i386/i386-mpx.c"
59 #include "features/i386/i386-avx512.c"
60 #include "features/i386/i386-mmx.c"
65 #include "stap-probe.h"
66 #include "user-regs.h"
67 #include "cli/cli-utils.h"
68 #include "expression.h"
69 #include "parser-defs.h"
74 static const char *i386_register_names
[] =
76 "eax", "ecx", "edx", "ebx",
77 "esp", "ebp", "esi", "edi",
78 "eip", "eflags", "cs", "ss",
79 "ds", "es", "fs", "gs",
80 "st0", "st1", "st2", "st3",
81 "st4", "st5", "st6", "st7",
82 "fctrl", "fstat", "ftag", "fiseg",
83 "fioff", "foseg", "fooff", "fop",
84 "xmm0", "xmm1", "xmm2", "xmm3",
85 "xmm4", "xmm5", "xmm6", "xmm7",
89 static const char *i386_zmm_names
[] =
91 "zmm0", "zmm1", "zmm2", "zmm3",
92 "zmm4", "zmm5", "zmm6", "zmm7"
95 static const char *i386_zmmh_names
[] =
97 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
98 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
101 static const char *i386_k_names
[] =
103 "k0", "k1", "k2", "k3",
104 "k4", "k5", "k6", "k7"
107 static const char *i386_ymm_names
[] =
109 "ymm0", "ymm1", "ymm2", "ymm3",
110 "ymm4", "ymm5", "ymm6", "ymm7",
113 static const char *i386_ymmh_names
[] =
115 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
116 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
119 static const char *i386_mpx_names
[] =
121 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
124 /* Register names for MPX pseudo-registers. */
126 static const char *i386_bnd_names
[] =
128 "bnd0", "bnd1", "bnd2", "bnd3"
131 /* Register names for MMX pseudo-registers. */
133 static const char *i386_mmx_names
[] =
135 "mm0", "mm1", "mm2", "mm3",
136 "mm4", "mm5", "mm6", "mm7"
139 /* Register names for byte pseudo-registers. */
141 static const char *i386_byte_names
[] =
143 "al", "cl", "dl", "bl",
144 "ah", "ch", "dh", "bh"
147 /* Register names for word pseudo-registers. */
149 static const char *i386_word_names
[] =
151 "ax", "cx", "dx", "bx",
155 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
156 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
157 we have 16 upper ZMM regs that have to be handled differently. */
159 const int num_lower_zmm_regs
= 16;
164 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int mm0_regnum
= tdep
->mm0_regnum
;
172 regnum
-= mm0_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
179 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
183 regnum
-= tdep
->al_regnum
;
184 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
190 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
192 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 regnum
-= tdep
->ax_regnum
;
195 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
198 /* Dword register? */
201 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
203 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
204 int eax_regnum
= tdep
->eax_regnum
;
209 regnum
-= eax_regnum
;
210 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
213 /* AVX512 register? */
216 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
219 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
221 if (zmm0h_regnum
< 0)
224 regnum
-= zmm0h_regnum
;
225 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
229 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
232 int zmm0_regnum
= tdep
->zmm0_regnum
;
237 regnum
-= zmm0_regnum
;
238 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
242 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 int k0_regnum
= tdep
->k0_regnum
;
251 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
255 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
258 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
260 if (ymm0h_regnum
< 0)
263 regnum
-= ymm0h_regnum
;
264 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
270 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
273 int ymm0_regnum
= tdep
->ymm0_regnum
;
278 regnum
-= ymm0_regnum
;
279 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
283 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
286 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
288 if (ymm16h_regnum
< 0)
291 regnum
-= ymm16h_regnum
;
292 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
296 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
299 int ymm16_regnum
= tdep
->ymm16_regnum
;
301 if (ymm16_regnum
< 0)
304 regnum
-= ymm16_regnum
;
305 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
311 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
314 int bnd0_regnum
= tdep
->bnd0_regnum
;
319 regnum
-= bnd0_regnum
;
320 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
326 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
328 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
329 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
331 if (num_xmm_regs
== 0)
334 regnum
-= I387_XMM0_REGNUM (tdep
);
335 return regnum
>= 0 && regnum
< num_xmm_regs
;
338 /* XMM_512 register? */
341 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
343 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
344 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
346 if (num_xmm_avx512_regs
== 0)
349 regnum
-= I387_XMM16_REGNUM (tdep
);
350 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
354 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
358 if (I387_NUM_XMM_REGS (tdep
) == 0)
361 return (regnum
== I387_MXCSR_REGNUM (tdep
));
367 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
371 if (I387_ST0_REGNUM (tdep
) < 0)
374 return (I387_ST0_REGNUM (tdep
) <= regnum
375 && regnum
< I387_FCTRL_REGNUM (tdep
));
379 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
381 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
383 if (I387_ST0_REGNUM (tdep
) < 0)
386 return (I387_FCTRL_REGNUM (tdep
) <= regnum
387 && regnum
< I387_XMM0_REGNUM (tdep
));
390 /* BNDr (raw) register? */
393 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
397 if (I387_BND0R_REGNUM (tdep
) < 0)
400 regnum
-= tdep
->bnd0r_regnum
;
401 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
404 /* BND control register? */
407 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
409 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
411 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
414 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
415 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
418 /* Return the name of register REGNUM, or the empty string if it is
419 an anonymous register. */
422 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
424 /* Hide the upper YMM registers. */
425 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
428 /* Hide the upper YMM16-31 registers. */
429 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
432 /* Hide the upper ZMM registers. */
433 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
436 return tdesc_register_name (gdbarch
, regnum
);
439 /* Return the name of register REGNUM. */
442 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
444 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
445 if (i386_bnd_regnum_p (gdbarch
, regnum
))
446 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
447 if (i386_mmx_regnum_p (gdbarch
, regnum
))
448 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
449 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
450 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
451 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
452 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
453 else if (i386_byte_regnum_p (gdbarch
, regnum
))
454 return i386_byte_names
[regnum
- tdep
->al_regnum
];
455 else if (i386_word_regnum_p (gdbarch
, regnum
))
456 return i386_word_names
[regnum
- tdep
->ax_regnum
];
458 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
461 /* Convert a dbx register number REG to the appropriate register
462 number used by GDB. */
465 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 /* This implements what GCC calls the "default" register map
470 (dbx_register_map[]). */
472 if (reg
>= 0 && reg
<= 7)
474 /* General-purpose registers. The debug info calls %ebp
475 register 4, and %esp register 5. */
482 else if (reg
>= 12 && reg
<= 19)
484 /* Floating-point registers. */
485 return reg
- 12 + I387_ST0_REGNUM (tdep
);
487 else if (reg
>= 21 && reg
<= 28)
490 int ymm0_regnum
= tdep
->ymm0_regnum
;
493 && i386_xmm_regnum_p (gdbarch
, reg
))
494 return reg
- 21 + ymm0_regnum
;
496 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
498 else if (reg
>= 29 && reg
<= 36)
501 return reg
- 29 + I387_MM0_REGNUM (tdep
);
504 /* This will hopefully provoke a warning. */
505 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
508 /* Convert SVR4 register number REG to the appropriate register number
512 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 /* This implements the GCC register map that tries to be compatible
517 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
519 /* The SVR4 register numbering includes %eip and %eflags, and
520 numbers the floating point registers differently. */
521 if (reg
>= 0 && reg
<= 9)
523 /* General-purpose registers. */
526 else if (reg
>= 11 && reg
<= 18)
528 /* Floating-point registers. */
529 return reg
- 11 + I387_ST0_REGNUM (tdep
);
531 else if (reg
>= 21 && reg
<= 36)
533 /* The SSE and MMX registers have the same numbers as with dbx. */
534 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
539 case 37: return I387_FCTRL_REGNUM (tdep
);
540 case 38: return I387_FSTAT_REGNUM (tdep
);
541 case 39: return I387_MXCSR_REGNUM (tdep
);
542 case 40: return I386_ES_REGNUM
;
543 case 41: return I386_CS_REGNUM
;
544 case 42: return I386_SS_REGNUM
;
545 case 43: return I386_DS_REGNUM
;
546 case 44: return I386_FS_REGNUM
;
547 case 45: return I386_GS_REGNUM
;
550 /* This will hopefully provoke a warning. */
551 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
556 /* This is the variable that is set with "set disassembly-flavor", and
557 its legitimate values. */
558 static const char att_flavor
[] = "att";
559 static const char intel_flavor
[] = "intel";
560 static const char *const valid_flavors
[] =
566 static const char *disassembly_flavor
= att_flavor
;
569 /* Use the program counter to determine the contents and size of a
570 breakpoint instruction. Return a pointer to a string of bytes that
571 encode a breakpoint instruction, store the length of the string in
572 *LEN and optionally adjust *PC to point to the correct memory
573 location for inserting the breakpoint.
575 On the i386 we have a single breakpoint that fits in a single byte
576 and can be inserted anywhere.
578 This function is 64-bit safe. */
580 static const gdb_byte
*
581 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
583 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
585 *len
= sizeof (break_insn
);
589 /* Displaced instruction handling. */
591 /* Skip the legacy instruction prefixes in INSN.
592 Not all prefixes are valid for any particular insn
593 but we needn't care, the insn will fault if it's invalid.
594 The result is a pointer to the first opcode byte,
595 or NULL if we run off the end of the buffer. */
598 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
600 gdb_byte
*end
= insn
+ max_len
;
606 case DATA_PREFIX_OPCODE
:
607 case ADDR_PREFIX_OPCODE
:
608 case CS_PREFIX_OPCODE
:
609 case DS_PREFIX_OPCODE
:
610 case ES_PREFIX_OPCODE
:
611 case FS_PREFIX_OPCODE
:
612 case GS_PREFIX_OPCODE
:
613 case SS_PREFIX_OPCODE
:
614 case LOCK_PREFIX_OPCODE
:
615 case REPE_PREFIX_OPCODE
:
616 case REPNE_PREFIX_OPCODE
:
628 i386_absolute_jmp_p (const gdb_byte
*insn
)
630 /* jmp far (absolute address in operand). */
636 /* jump near, absolute indirect (/4). */
637 if ((insn
[1] & 0x38) == 0x20)
640 /* jump far, absolute indirect (/5). */
641 if ((insn
[1] & 0x38) == 0x28)
648 /* Return non-zero if INSN is a jump, zero otherwise. */
651 i386_jmp_p (const gdb_byte
*insn
)
653 /* jump short, relative. */
657 /* jump near, relative. */
661 return i386_absolute_jmp_p (insn
);
665 i386_absolute_call_p (const gdb_byte
*insn
)
667 /* call far, absolute. */
673 /* Call near, absolute indirect (/2). */
674 if ((insn
[1] & 0x38) == 0x10)
677 /* Call far, absolute indirect (/3). */
678 if ((insn
[1] & 0x38) == 0x18)
686 i386_ret_p (const gdb_byte
*insn
)
690 case 0xc2: /* ret near, pop N bytes. */
691 case 0xc3: /* ret near */
692 case 0xca: /* ret far, pop N bytes. */
693 case 0xcb: /* ret far */
694 case 0xcf: /* iret */
703 i386_call_p (const gdb_byte
*insn
)
705 if (i386_absolute_call_p (insn
))
708 /* call near, relative. */
715 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
716 length in bytes. Otherwise, return zero. */
719 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
721 /* Is it 'int $0x80'? */
722 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
723 /* Or is it 'sysenter'? */
724 || (insn
[0] == 0x0f && insn
[1] == 0x34)
725 /* Or is it 'syscall'? */
726 || (insn
[0] == 0x0f && insn
[1] == 0x05))
735 /* The gdbarch insn_is_call method. */
738 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
740 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
742 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
743 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
745 return i386_call_p (insn
);
748 /* The gdbarch insn_is_ret method. */
751 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
753 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
755 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
756 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
758 return i386_ret_p (insn
);
761 /* The gdbarch insn_is_jump method. */
764 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
766 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
768 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
769 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
771 return i386_jmp_p (insn
);
774 /* Some kernels may run one past a syscall insn, so we have to cope.
775 Otherwise this is just simple_displaced_step_copy_insn. */
777 struct displaced_step_closure
*
778 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
779 CORE_ADDR from
, CORE_ADDR to
,
780 struct regcache
*regs
)
782 size_t len
= gdbarch_max_insn_length (gdbarch
);
783 gdb_byte
*buf
= xmalloc (len
);
785 read_memory (from
, buf
, len
);
787 /* GDB may get control back after the insn after the syscall.
788 Presumably this is a kernel bug.
789 If this is a syscall, make sure there's a nop afterwards. */
794 insn
= i386_skip_prefixes (buf
, len
);
795 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
796 insn
[syscall_length
] = NOP_OPCODE
;
799 write_memory (to
, buf
, len
);
803 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
804 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
805 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
808 return (struct displaced_step_closure
*) buf
;
811 /* Fix up the state of registers and memory after having single-stepped
812 a displaced instruction. */
815 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
816 struct displaced_step_closure
*closure
,
817 CORE_ADDR from
, CORE_ADDR to
,
818 struct regcache
*regs
)
820 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
822 /* The offset we applied to the instruction's address.
823 This could well be negative (when viewed as a signed 32-bit
824 value), but ULONGEST won't reflect that, so take care when
826 ULONGEST insn_offset
= to
- from
;
828 /* Since we use simple_displaced_step_copy_insn, our closure is a
829 copy of the instruction. */
830 gdb_byte
*insn
= (gdb_byte
*) closure
;
831 /* The start of the insn, needed in case we see some prefixes. */
832 gdb_byte
*insn_start
= insn
;
835 fprintf_unfiltered (gdb_stdlog
,
836 "displaced: fixup (%s, %s), "
837 "insn = 0x%02x 0x%02x ...\n",
838 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
841 /* The list of issues to contend with here is taken from
842 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
843 Yay for Free Software! */
845 /* Relocate the %eip, if necessary. */
847 /* The instruction recognizers we use assume any leading prefixes
848 have been skipped. */
850 /* This is the size of the buffer in closure. */
851 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
852 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
853 /* If there are too many prefixes, just ignore the insn.
854 It will fault when run. */
859 /* Except in the case of absolute or indirect jump or call
860 instructions, or a return instruction, the new eip is relative to
861 the displaced instruction; make it relative. Well, signal
862 handler returns don't need relocation either, but we use the
863 value of %eip to recognize those; see below. */
864 if (! i386_absolute_jmp_p (insn
)
865 && ! i386_absolute_call_p (insn
)
866 && ! i386_ret_p (insn
))
871 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
873 /* A signal trampoline system call changes the %eip, resuming
874 execution of the main program after the signal handler has
875 returned. That makes them like 'return' instructions; we
876 shouldn't relocate %eip.
878 But most system calls don't, and we do need to relocate %eip.
880 Our heuristic for distinguishing these cases: if stepping
881 over the system call instruction left control directly after
882 the instruction, the we relocate --- control almost certainly
883 doesn't belong in the displaced copy. Otherwise, we assume
884 the instruction has put control where it belongs, and leave
885 it unrelocated. Goodness help us if there are PC-relative
887 if (i386_syscall_p (insn
, &insn_len
)
888 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
889 /* GDB can get control back after the insn after the syscall.
890 Presumably this is a kernel bug.
891 i386_displaced_step_copy_insn ensures its a nop,
892 we add one to the length for it. */
893 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
896 fprintf_unfiltered (gdb_stdlog
,
897 "displaced: syscall changed %%eip; "
902 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
904 /* If we just stepped over a breakpoint insn, we don't backup
905 the pc on purpose; this is to match behaviour without
908 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
911 fprintf_unfiltered (gdb_stdlog
,
913 "relocated %%eip from %s to %s\n",
914 paddress (gdbarch
, orig_eip
),
915 paddress (gdbarch
, eip
));
919 /* If the instruction was PUSHFL, then the TF bit will be set in the
920 pushed value, and should be cleared. We'll leave this for later,
921 since GDB already messes up the TF flag when stepping over a
924 /* If the instruction was a call, the return address now atop the
925 stack is the address following the copied instruction. We need
926 to make it the address following the original instruction. */
927 if (i386_call_p (insn
))
931 const ULONGEST retaddr_len
= 4;
933 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
934 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
935 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
936 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
939 fprintf_unfiltered (gdb_stdlog
,
940 "displaced: relocated return addr at %s to %s\n",
941 paddress (gdbarch
, esp
),
942 paddress (gdbarch
, retaddr
));
947 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
949 target_write_memory (*to
, buf
, len
);
954 i386_relocate_instruction (struct gdbarch
*gdbarch
,
955 CORE_ADDR
*to
, CORE_ADDR oldloc
)
957 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
958 gdb_byte buf
[I386_MAX_INSN_LEN
];
959 int offset
= 0, rel32
, newrel
;
961 gdb_byte
*insn
= buf
;
963 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
965 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
966 I386_MAX_INSN_LEN
, oldloc
);
968 /* Get past the prefixes. */
969 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
971 /* Adjust calls with 32-bit relative addresses as push/jump, with
972 the address pushed being the location where the original call in
973 the user program would return to. */
976 gdb_byte push_buf
[16];
977 unsigned int ret_addr
;
979 /* Where "ret" in the original code will return to. */
980 ret_addr
= oldloc
+ insn_length
;
981 push_buf
[0] = 0x68; /* pushq $... */
982 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
984 append_insns (to
, 5, push_buf
);
986 /* Convert the relative call to a relative jump. */
989 /* Adjust the destination offset. */
990 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
991 newrel
= (oldloc
- *to
) + rel32
;
992 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
995 fprintf_unfiltered (gdb_stdlog
,
996 "Adjusted insn rel32=%s at %s to"
998 hex_string (rel32
), paddress (gdbarch
, oldloc
),
999 hex_string (newrel
), paddress (gdbarch
, *to
));
1001 /* Write the adjusted jump into its displaced location. */
1002 append_insns (to
, 5, insn
);
1006 /* Adjust jumps with 32-bit relative addresses. Calls are already
1008 if (insn
[0] == 0xe9)
1010 /* Adjust conditional jumps. */
1011 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1016 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1017 newrel
= (oldloc
- *to
) + rel32
;
1018 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1019 if (debug_displaced
)
1020 fprintf_unfiltered (gdb_stdlog
,
1021 "Adjusted insn rel32=%s at %s to"
1022 " rel32=%s at %s\n",
1023 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1024 hex_string (newrel
), paddress (gdbarch
, *to
));
1027 /* Write the adjusted instructions into their displaced
1029 append_insns (to
, insn_length
, buf
);
1033 #ifdef I386_REGNO_TO_SYMMETRY
1034 #error "The Sequent Symmetry is no longer supported."
1037 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1038 and %esp "belong" to the calling function. Therefore these
1039 registers should be saved if they're going to be modified. */
1041 /* The maximum number of saved registers. This should include all
1042 registers mentioned above, and %eip. */
1043 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1045 struct i386_frame_cache
1053 /* Saved registers. */
1054 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1059 /* Stack space reserved for local variables. */
1063 /* Allocate and initialize a frame cache. */
1065 static struct i386_frame_cache
*
1066 i386_alloc_frame_cache (void)
1068 struct i386_frame_cache
*cache
;
1071 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1076 cache
->sp_offset
= -4;
1079 /* Saved registers. We initialize these to -1 since zero is a valid
1080 offset (that's where %ebp is supposed to be stored). */
1081 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1082 cache
->saved_regs
[i
] = -1;
1083 cache
->saved_sp
= 0;
1084 cache
->saved_sp_reg
= -1;
1085 cache
->pc_in_eax
= 0;
1087 /* Frameless until proven otherwise. */
1093 /* If the instruction at PC is a jump, return the address of its
1094 target. Otherwise, return PC. */
1097 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1099 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1104 if (target_read_code (pc
, &op
, 1))
1111 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1117 /* Relative jump: if data16 == 0, disp32, else disp16. */
1120 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1122 /* Include the size of the jmp instruction (including the
1128 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1130 /* Include the size of the jmp instruction. */
1135 /* Relative jump, disp8 (ignore data16). */
1136 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1138 delta
+= data16
+ 2;
1145 /* Check whether PC points at a prologue for a function returning a
1146 structure or union. If so, it updates CACHE and returns the
1147 address of the first instruction after the code sequence that
1148 removes the "hidden" argument from the stack or CURRENT_PC,
1149 whichever is smaller. Otherwise, return PC. */
1152 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1153 struct i386_frame_cache
*cache
)
1155 /* Functions that return a structure or union start with:
1158 xchgl %eax, (%esp) 0x87 0x04 0x24
1159 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1161 (the System V compiler puts out the second `xchg' instruction,
1162 and the assembler doesn't try to optimize it, so the 'sib' form
1163 gets generated). This sequence is used to get the address of the
1164 return buffer for a function that returns a structure. */
1165 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1166 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1170 if (current_pc
<= pc
)
1173 if (target_read_code (pc
, &op
, 1))
1176 if (op
!= 0x58) /* popl %eax */
1179 if (target_read_code (pc
+ 1, buf
, 4))
1182 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1185 if (current_pc
== pc
)
1187 cache
->sp_offset
+= 4;
1191 if (current_pc
== pc
+ 1)
1193 cache
->pc_in_eax
= 1;
1197 if (buf
[1] == proto1
[1])
1204 i386_skip_probe (CORE_ADDR pc
)
1206 /* A function may start with
1220 if (target_read_code (pc
, &op
, 1))
1223 if (op
== 0x68 || op
== 0x6a)
1227 /* Skip past the `pushl' instruction; it has either a one-byte or a
1228 four-byte operand, depending on the opcode. */
1234 /* Read the following 8 bytes, which should be `call _probe' (6
1235 bytes) followed by `addl $4,%esp' (2 bytes). */
1236 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1237 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1238 pc
+= delta
+ sizeof (buf
);
1244 /* GCC 4.1 and later, can put code in the prologue to realign the
1245 stack pointer. Check whether PC points to such code, and update
1246 CACHE accordingly. Return the first instruction after the code
1247 sequence or CURRENT_PC, whichever is smaller. If we don't
1248 recognize the code, return PC. */
1251 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1252 struct i386_frame_cache
*cache
)
1254 /* There are 2 code sequences to re-align stack before the frame
1257 1. Use a caller-saved saved register:
1263 2. Use a callee-saved saved register:
1270 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1272 0x83 0xe4 0xf0 andl $-16, %esp
1273 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1278 int offset
, offset_and
;
1279 static int regnums
[8] = {
1280 I386_EAX_REGNUM
, /* %eax */
1281 I386_ECX_REGNUM
, /* %ecx */
1282 I386_EDX_REGNUM
, /* %edx */
1283 I386_EBX_REGNUM
, /* %ebx */
1284 I386_ESP_REGNUM
, /* %esp */
1285 I386_EBP_REGNUM
, /* %ebp */
1286 I386_ESI_REGNUM
, /* %esi */
1287 I386_EDI_REGNUM
/* %edi */
1290 if (target_read_code (pc
, buf
, sizeof buf
))
1293 /* Check caller-saved saved register. The first instruction has
1294 to be "leal 4(%esp), %reg". */
1295 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1297 /* MOD must be binary 10 and R/M must be binary 100. */
1298 if ((buf
[1] & 0xc7) != 0x44)
1301 /* REG has register number. */
1302 reg
= (buf
[1] >> 3) & 7;
1307 /* Check callee-saved saved register. The first instruction
1308 has to be "pushl %reg". */
1309 if ((buf
[0] & 0xf8) != 0x50)
1315 /* The next instruction has to be "leal 8(%esp), %reg". */
1316 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1319 /* MOD must be binary 10 and R/M must be binary 100. */
1320 if ((buf
[2] & 0xc7) != 0x44)
1323 /* REG has register number. Registers in pushl and leal have to
1325 if (reg
!= ((buf
[2] >> 3) & 7))
1331 /* Rigister can't be %esp nor %ebp. */
1332 if (reg
== 4 || reg
== 5)
1335 /* The next instruction has to be "andl $-XXX, %esp". */
1336 if (buf
[offset
+ 1] != 0xe4
1337 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1340 offset_and
= offset
;
1341 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1343 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1344 0xfc. REG must be binary 110 and MOD must be binary 01. */
1345 if (buf
[offset
] != 0xff
1346 || buf
[offset
+ 2] != 0xfc
1347 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1350 /* R/M has register. Registers in leal and pushl have to be the
1352 if (reg
!= (buf
[offset
+ 1] & 7))
1355 if (current_pc
> pc
+ offset_and
)
1356 cache
->saved_sp_reg
= regnums
[reg
];
1358 return min (pc
+ offset
+ 3, current_pc
);
1361 /* Maximum instruction length we need to handle. */
1362 #define I386_MAX_MATCHED_INSN_LEN 6
1364 /* Instruction description. */
1368 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1369 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1372 /* Return whether instruction at PC matches PATTERN. */
1375 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1379 if (target_read_code (pc
, &op
, 1))
1382 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1384 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1385 int insn_matched
= 1;
1388 gdb_assert (pattern
.len
> 1);
1389 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1391 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1394 for (i
= 1; i
< pattern
.len
; i
++)
1396 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1399 return insn_matched
;
1404 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1405 the first instruction description that matches. Otherwise, return
1408 static struct i386_insn
*
1409 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1411 struct i386_insn
*pattern
;
1413 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1415 if (i386_match_pattern (pc
, *pattern
))
1422 /* Return whether PC points inside a sequence of instructions that
1423 matches INSN_PATTERNS. */
1426 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1428 CORE_ADDR current_pc
;
1430 struct i386_insn
*insn
;
1432 insn
= i386_match_insn (pc
, insn_patterns
);
1437 ix
= insn
- insn_patterns
;
1438 for (i
= ix
- 1; i
>= 0; i
--)
1440 current_pc
-= insn_patterns
[i
].len
;
1442 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1446 current_pc
= pc
+ insn
->len
;
1447 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1449 if (!i386_match_pattern (current_pc
, *insn
))
1452 current_pc
+= insn
->len
;
1458 /* Some special instructions that might be migrated by GCC into the
1459 part of the prologue that sets up the new stack frame. Because the
1460 stack frame hasn't been setup yet, no registers have been saved
1461 yet, and only the scratch registers %eax, %ecx and %edx can be
1464 struct i386_insn i386_frame_setup_skip_insns
[] =
1466 /* Check for `movb imm8, r' and `movl imm32, r'.
1468 ??? Should we handle 16-bit operand-sizes here? */
1470 /* `movb imm8, %al' and `movb imm8, %ah' */
1471 /* `movb imm8, %cl' and `movb imm8, %ch' */
1472 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1473 /* `movb imm8, %dl' and `movb imm8, %dh' */
1474 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1475 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1476 { 5, { 0xb8 }, { 0xfe } },
1477 /* `movl imm32, %edx' */
1478 { 5, { 0xba }, { 0xff } },
1480 /* Check for `mov imm32, r32'. Note that there is an alternative
1481 encoding for `mov m32, %eax'.
1483 ??? Should we handle SIB adressing here?
1484 ??? Should we handle 16-bit operand-sizes here? */
1486 /* `movl m32, %eax' */
1487 { 5, { 0xa1 }, { 0xff } },
1488 /* `movl m32, %eax' and `mov; m32, %ecx' */
1489 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1490 /* `movl m32, %edx' */
1491 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1493 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1494 Because of the symmetry, there are actually two ways to encode
1495 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1496 opcode bytes 0x31 and 0x33 for `xorl'. */
1498 /* `subl %eax, %eax' */
1499 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1500 /* `subl %ecx, %ecx' */
1501 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1502 /* `subl %edx, %edx' */
1503 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1504 /* `xorl %eax, %eax' */
1505 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1506 /* `xorl %ecx, %ecx' */
1507 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1508 /* `xorl %edx, %edx' */
1509 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1514 /* Check whether PC points to a no-op instruction. */
1516 i386_skip_noop (CORE_ADDR pc
)
1521 if (target_read_code (pc
, &op
, 1))
1527 /* Ignore `nop' instruction. */
1531 if (target_read_code (pc
, &op
, 1))
1535 /* Ignore no-op instruction `mov %edi, %edi'.
1536 Microsoft system dlls often start with
1537 a `mov %edi,%edi' instruction.
1538 The 5 bytes before the function start are
1539 filled with `nop' instructions.
1540 This pattern can be used for hot-patching:
1541 The `mov %edi, %edi' instruction can be replaced by a
1542 near jump to the location of the 5 `nop' instructions
1543 which can be replaced by a 32-bit jump to anywhere
1544 in the 32-bit address space. */
1546 else if (op
== 0x8b)
1548 if (target_read_code (pc
+ 1, &op
, 1))
1554 if (target_read_code (pc
, &op
, 1))
1564 /* Check whether PC points at a code that sets up a new stack frame.
1565 If so, it updates CACHE and returns the address of the first
1566 instruction after the sequence that sets up the frame or LIMIT,
1567 whichever is smaller. If we don't recognize the code, return PC. */
1570 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1571 CORE_ADDR pc
, CORE_ADDR limit
,
1572 struct i386_frame_cache
*cache
)
1574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1575 struct i386_insn
*insn
;
1582 if (target_read_code (pc
, &op
, 1))
1585 if (op
== 0x55) /* pushl %ebp */
1587 /* Take into account that we've executed the `pushl %ebp' that
1588 starts this instruction sequence. */
1589 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1590 cache
->sp_offset
+= 4;
1593 /* If that's all, return now. */
1597 /* Check for some special instructions that might be migrated by
1598 GCC into the prologue and skip them. At this point in the
1599 prologue, code should only touch the scratch registers %eax,
1600 %ecx and %edx, so while the number of posibilities is sheer,
1603 Make sure we only skip these instructions if we later see the
1604 `movl %esp, %ebp' that actually sets up the frame. */
1605 while (pc
+ skip
< limit
)
1607 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1614 /* If that's all, return now. */
1615 if (limit
<= pc
+ skip
)
1618 if (target_read_code (pc
+ skip
, &op
, 1))
1621 /* The i386 prologue looks like
1627 and a different prologue can be generated for atom.
1631 lea -0x10(%esp),%esp
1633 We handle both of them here. */
1637 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1639 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1645 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1650 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1651 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1660 /* OK, we actually have a frame. We just don't know how large
1661 it is yet. Set its size to zero. We'll adjust it if
1662 necessary. We also now commit to skipping the special
1663 instructions mentioned before. */
1666 /* If that's all, return now. */
1670 /* Check for stack adjustment
1676 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1677 reg, so we don't have to worry about a data16 prefix. */
1678 if (target_read_code (pc
, &op
, 1))
1682 /* `subl' with 8-bit immediate. */
1683 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1684 /* Some instruction starting with 0x83 other than `subl'. */
1687 /* `subl' with signed 8-bit immediate (though it wouldn't
1688 make sense to be negative). */
1689 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1692 else if (op
== 0x81)
1694 /* Maybe it is `subl' with a 32-bit immediate. */
1695 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1696 /* Some instruction starting with 0x81 other than `subl'. */
1699 /* It is `subl' with a 32-bit immediate. */
1700 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1703 else if (op
== 0x8d)
1705 /* The ModR/M byte is 0x64. */
1706 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1708 /* 'lea' with 8-bit displacement. */
1709 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1714 /* Some instruction other than `subl' nor 'lea'. */
1718 else if (op
== 0xc8) /* enter */
1720 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1727 /* Check whether PC points at code that saves registers on the stack.
1728 If so, it updates CACHE and returns the address of the first
1729 instruction after the register saves or CURRENT_PC, whichever is
1730 smaller. Otherwise, return PC. */
1733 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1734 struct i386_frame_cache
*cache
)
1736 CORE_ADDR offset
= 0;
1740 if (cache
->locals
> 0)
1741 offset
-= cache
->locals
;
1742 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1744 if (target_read_code (pc
, &op
, 1))
1746 if (op
< 0x50 || op
> 0x57)
1750 cache
->saved_regs
[op
- 0x50] = offset
;
1751 cache
->sp_offset
+= 4;
1758 /* Do a full analysis of the prologue at PC and update CACHE
1759 accordingly. Bail out early if CURRENT_PC is reached. Return the
1760 address where the analysis stopped.
1762 We handle these cases:
1764 The startup sequence can be at the start of the function, or the
1765 function can start with a branch to startup code at the end.
1767 %ebp can be set up with either the 'enter' instruction, or "pushl
1768 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1769 once used in the System V compiler).
1771 Local space is allocated just below the saved %ebp by either the
1772 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1773 16-bit unsigned argument for space to allocate, and the 'addl'
1774 instruction could have either a signed byte, or 32-bit immediate.
1776 Next, the registers used by this function are pushed. With the
1777 System V compiler they will always be in the order: %edi, %esi,
1778 %ebx (and sometimes a harmless bug causes it to also save but not
1779 restore %eax); however, the code below is willing to see the pushes
1780 in any order, and will handle up to 8 of them.
1782 If the setup sequence is at the end of the function, then the next
1783 instruction will be a branch back to the start. */
1786 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1787 CORE_ADDR pc
, CORE_ADDR current_pc
,
1788 struct i386_frame_cache
*cache
)
1790 pc
= i386_skip_noop (pc
);
1791 pc
= i386_follow_jump (gdbarch
, pc
);
1792 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1793 pc
= i386_skip_probe (pc
);
1794 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1795 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1796 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1799 /* Return PC of first real instruction. */
1802 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1804 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1806 static gdb_byte pic_pat
[6] =
1808 0xe8, 0, 0, 0, 0, /* call 0x0 */
1809 0x5b, /* popl %ebx */
1811 struct i386_frame_cache cache
;
1815 CORE_ADDR func_addr
;
1817 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1819 CORE_ADDR post_prologue_pc
1820 = skip_prologue_using_sal (gdbarch
, func_addr
);
1821 struct symtab
*s
= find_pc_symtab (func_addr
);
1823 /* Clang always emits a line note before the prologue and another
1824 one after. We trust clang to emit usable line notes. */
1825 if (post_prologue_pc
1827 && s
->producer
!= NULL
1828 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1829 return max (start_pc
, post_prologue_pc
);
1833 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1834 if (cache
.locals
< 0)
1837 /* Found valid frame setup. */
1839 /* The native cc on SVR4 in -K PIC mode inserts the following code
1840 to get the address of the global offset table (GOT) into register
1845 movl %ebx,x(%ebp) (optional)
1848 This code is with the rest of the prologue (at the end of the
1849 function), so we have to skip it to get to the first real
1850 instruction at the start of the function. */
1852 for (i
= 0; i
< 6; i
++)
1854 if (target_read_code (pc
+ i
, &op
, 1))
1857 if (pic_pat
[i
] != op
)
1864 if (target_read_code (pc
+ delta
, &op
, 1))
1867 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1869 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1871 if (op
== 0x5d) /* One byte offset from %ebp. */
1873 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1875 else /* Unexpected instruction. */
1878 if (target_read_code (pc
+ delta
, &op
, 1))
1883 if (delta
> 0 && op
== 0x81
1884 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1891 /* If the function starts with a branch (to startup code at the end)
1892 the last instruction should bring us back to the first
1893 instruction of the real code. */
1894 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1895 pc
= i386_follow_jump (gdbarch
, pc
);
1900 /* Check that the code pointed to by PC corresponds to a call to
1901 __main, skip it if so. Return PC otherwise. */
1904 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1906 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1909 if (target_read_code (pc
, &op
, 1))
1915 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1917 /* Make sure address is computed correctly as a 32bit
1918 integer even if CORE_ADDR is 64 bit wide. */
1919 struct bound_minimal_symbol s
;
1920 CORE_ADDR call_dest
;
1922 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1923 call_dest
= call_dest
& 0xffffffffU
;
1924 s
= lookup_minimal_symbol_by_pc (call_dest
);
1925 if (s
.minsym
!= NULL
1926 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1927 && strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1935 /* This function is 64-bit safe. */
1938 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1942 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1943 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1947 /* Normal frames. */
1950 i386_frame_cache_1 (struct frame_info
*this_frame
,
1951 struct i386_frame_cache
*cache
)
1953 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1954 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1958 cache
->pc
= get_frame_func (this_frame
);
1960 /* In principle, for normal frames, %ebp holds the frame pointer,
1961 which holds the base address for the current stack frame.
1962 However, for functions that don't need it, the frame pointer is
1963 optional. For these "frameless" functions the frame pointer is
1964 actually the frame pointer of the calling frame. Signal
1965 trampolines are just a special case of a "frameless" function.
1966 They (usually) share their frame pointer with the frame that was
1967 in progress when the signal occurred. */
1969 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1970 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1971 if (cache
->base
== 0)
1977 /* For normal frames, %eip is stored at 4(%ebp). */
1978 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1981 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1984 if (cache
->locals
< 0)
1986 /* We didn't find a valid frame, which means that CACHE->base
1987 currently holds the frame pointer for our calling frame. If
1988 we're at the start of a function, or somewhere half-way its
1989 prologue, the function's frame probably hasn't been fully
1990 setup yet. Try to reconstruct the base address for the stack
1991 frame by looking at the stack pointer. For truly "frameless"
1992 functions this might work too. */
1994 if (cache
->saved_sp_reg
!= -1)
1996 /* Saved stack pointer has been saved. */
1997 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1998 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2000 /* We're halfway aligning the stack. */
2001 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2002 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2004 /* This will be added back below. */
2005 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2007 else if (cache
->pc
!= 0
2008 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2010 /* We're in a known function, but did not find a frame
2011 setup. Assume that the function does not use %ebp.
2012 Alternatively, we may have jumped to an invalid
2013 address; in that case there is definitely no new
2015 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2016 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2020 /* We're in an unknown function. We could not find the start
2021 of the function to analyze the prologue; our best option is
2022 to assume a typical frame layout with the caller's %ebp
2024 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2027 if (cache
->saved_sp_reg
!= -1)
2029 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2030 register may be unavailable). */
2031 if (cache
->saved_sp
== 0
2032 && deprecated_frame_register_read (this_frame
,
2033 cache
->saved_sp_reg
, buf
))
2034 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2036 /* Now that we have the base address for the stack frame we can
2037 calculate the value of %esp in the calling frame. */
2038 else if (cache
->saved_sp
== 0)
2039 cache
->saved_sp
= cache
->base
+ 8;
2041 /* Adjust all the saved registers such that they contain addresses
2042 instead of offsets. */
2043 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2044 if (cache
->saved_regs
[i
] != -1)
2045 cache
->saved_regs
[i
] += cache
->base
;
2050 static struct i386_frame_cache
*
2051 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2053 volatile struct gdb_exception ex
;
2054 struct i386_frame_cache
*cache
;
2059 cache
= i386_alloc_frame_cache ();
2060 *this_cache
= cache
;
2062 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2064 i386_frame_cache_1 (this_frame
, cache
);
2066 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2067 throw_exception (ex
);
2073 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2074 struct frame_id
*this_id
)
2076 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2079 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2080 else if (cache
->base
== 0)
2082 /* This marks the outermost frame. */
2086 /* See the end of i386_push_dummy_call. */
2087 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2091 static enum unwind_stop_reason
2092 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2095 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2098 return UNWIND_UNAVAILABLE
;
2100 /* This marks the outermost frame. */
2101 if (cache
->base
== 0)
2102 return UNWIND_OUTERMOST
;
2104 return UNWIND_NO_REASON
;
2107 static struct value
*
2108 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2111 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2113 gdb_assert (regnum
>= 0);
2115 /* The System V ABI says that:
2117 "The flags register contains the system flags, such as the
2118 direction flag and the carry flag. The direction flag must be
2119 set to the forward (that is, zero) direction before entry and
2120 upon exit from a function. Other user flags have no specified
2121 role in the standard calling sequence and are not preserved."
2123 To guarantee the "upon exit" part of that statement we fake a
2124 saved flags register that has its direction flag cleared.
2126 Note that GCC doesn't seem to rely on the fact that the direction
2127 flag is cleared after a function return; it always explicitly
2128 clears the flag before operations where it matters.
2130 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2131 right thing to do. The way we fake the flags register here makes
2132 it impossible to change it. */
2134 if (regnum
== I386_EFLAGS_REGNUM
)
2138 val
= get_frame_register_unsigned (this_frame
, regnum
);
2140 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2143 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2144 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2146 if (regnum
== I386_ESP_REGNUM
2147 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2149 /* If the SP has been saved, but we don't know where, then this
2150 means that SAVED_SP_REG register was found unavailable back
2151 when we built the cache. */
2152 if (cache
->saved_sp
== 0)
2153 return frame_unwind_got_register (this_frame
, regnum
,
2154 cache
->saved_sp_reg
);
2156 return frame_unwind_got_constant (this_frame
, regnum
,
2160 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2161 return frame_unwind_got_memory (this_frame
, regnum
,
2162 cache
->saved_regs
[regnum
]);
2164 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2167 static const struct frame_unwind i386_frame_unwind
=
2170 i386_frame_unwind_stop_reason
,
2172 i386_frame_prev_register
,
2174 default_frame_sniffer
2177 /* Normal frames, but in a function epilogue. */
2179 /* The epilogue is defined here as the 'ret' instruction, which will
2180 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2181 the function's stack frame. */
2184 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2187 struct symtab
*symtab
;
2189 symtab
= find_pc_symtab (pc
);
2190 if (symtab
&& symtab
->epilogue_unwind_valid
)
2193 if (target_read_memory (pc
, &insn
, 1))
2194 return 0; /* Can't read memory at pc. */
2196 if (insn
!= 0xc3) /* 'ret' instruction. */
2203 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2204 struct frame_info
*this_frame
,
2205 void **this_prologue_cache
)
2207 if (frame_relative_level (this_frame
) == 0)
2208 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
2209 get_frame_pc (this_frame
));
2214 static struct i386_frame_cache
*
2215 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2217 volatile struct gdb_exception ex
;
2218 struct i386_frame_cache
*cache
;
2224 cache
= i386_alloc_frame_cache ();
2225 *this_cache
= cache
;
2227 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2229 cache
->pc
= get_frame_func (this_frame
);
2231 /* At this point the stack looks as if we just entered the
2232 function, with the return address at the top of the
2234 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2235 cache
->base
= sp
+ cache
->sp_offset
;
2236 cache
->saved_sp
= cache
->base
+ 8;
2237 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2241 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2242 throw_exception (ex
);
2247 static enum unwind_stop_reason
2248 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2251 struct i386_frame_cache
*cache
=
2252 i386_epilogue_frame_cache (this_frame
, this_cache
);
2255 return UNWIND_UNAVAILABLE
;
2257 return UNWIND_NO_REASON
;
2261 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2263 struct frame_id
*this_id
)
2265 struct i386_frame_cache
*cache
=
2266 i386_epilogue_frame_cache (this_frame
, this_cache
);
2269 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2271 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2274 static struct value
*
2275 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2276 void **this_cache
, int regnum
)
2278 /* Make sure we've initialized the cache. */
2279 i386_epilogue_frame_cache (this_frame
, this_cache
);
2281 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2284 static const struct frame_unwind i386_epilogue_frame_unwind
=
2287 i386_epilogue_frame_unwind_stop_reason
,
2288 i386_epilogue_frame_this_id
,
2289 i386_epilogue_frame_prev_register
,
2291 i386_epilogue_frame_sniffer
2295 /* Stack-based trampolines. */
2297 /* These trampolines are used on cross x86 targets, when taking the
2298 address of a nested function. When executing these trampolines,
2299 no stack frame is set up, so we are in a similar situation as in
2300 epilogues and i386_epilogue_frame_this_id can be re-used. */
2302 /* Static chain passed in register. */
2304 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2306 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2307 { 5, { 0xb8 }, { 0xfe } },
2310 { 5, { 0xe9 }, { 0xff } },
2315 /* Static chain passed on stack (when regparm=3). */
2317 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2320 { 5, { 0x68 }, { 0xff } },
2323 { 5, { 0xe9 }, { 0xff } },
2328 /* Return whether PC points inside a stack trampoline. */
2331 i386_in_stack_tramp_p (CORE_ADDR pc
)
2336 /* A stack trampoline is detected if no name is associated
2337 to the current pc and if it points inside a trampoline
2340 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2344 if (target_read_memory (pc
, &insn
, 1))
2347 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2348 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2355 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2356 struct frame_info
*this_frame
,
2359 if (frame_relative_level (this_frame
) == 0)
2360 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2365 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2368 i386_epilogue_frame_unwind_stop_reason
,
2369 i386_epilogue_frame_this_id
,
2370 i386_epilogue_frame_prev_register
,
2372 i386_stack_tramp_frame_sniffer
2375 /* Generate a bytecode expression to get the value of the saved PC. */
2378 i386_gen_return_address (struct gdbarch
*gdbarch
,
2379 struct agent_expr
*ax
, struct axs_value
*value
,
2382 /* The following sequence assumes the traditional use of the base
2384 ax_reg (ax
, I386_EBP_REGNUM
);
2386 ax_simple (ax
, aop_add
);
2387 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2388 value
->kind
= axs_lvalue_memory
;
2392 /* Signal trampolines. */
2394 static struct i386_frame_cache
*
2395 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2397 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2399 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2400 volatile struct gdb_exception ex
;
2401 struct i386_frame_cache
*cache
;
2408 cache
= i386_alloc_frame_cache ();
2410 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2412 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2413 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2415 addr
= tdep
->sigcontext_addr (this_frame
);
2416 if (tdep
->sc_reg_offset
)
2420 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2422 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2423 if (tdep
->sc_reg_offset
[i
] != -1)
2424 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2428 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2429 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2434 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2435 throw_exception (ex
);
2437 *this_cache
= cache
;
2441 static enum unwind_stop_reason
2442 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2445 struct i386_frame_cache
*cache
=
2446 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2449 return UNWIND_UNAVAILABLE
;
2451 return UNWIND_NO_REASON
;
2455 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2456 struct frame_id
*this_id
)
2458 struct i386_frame_cache
*cache
=
2459 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2462 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2465 /* See the end of i386_push_dummy_call. */
2466 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2470 static struct value
*
2471 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2472 void **this_cache
, int regnum
)
2474 /* Make sure we've initialized the cache. */
2475 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2477 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2481 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2482 struct frame_info
*this_frame
,
2483 void **this_prologue_cache
)
2485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2487 /* We shouldn't even bother if we don't have a sigcontext_addr
2489 if (tdep
->sigcontext_addr
== NULL
)
2492 if (tdep
->sigtramp_p
!= NULL
)
2494 if (tdep
->sigtramp_p (this_frame
))
2498 if (tdep
->sigtramp_start
!= 0)
2500 CORE_ADDR pc
= get_frame_pc (this_frame
);
2502 gdb_assert (tdep
->sigtramp_end
!= 0);
2503 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2510 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2513 i386_sigtramp_frame_unwind_stop_reason
,
2514 i386_sigtramp_frame_this_id
,
2515 i386_sigtramp_frame_prev_register
,
2517 i386_sigtramp_frame_sniffer
2522 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2524 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2529 static const struct frame_base i386_frame_base
=
2532 i386_frame_base_address
,
2533 i386_frame_base_address
,
2534 i386_frame_base_address
2537 static struct frame_id
2538 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2542 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2544 /* See the end of i386_push_dummy_call. */
2545 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2548 /* _Decimal128 function return values need 16-byte alignment on the
2552 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2554 return sp
& -(CORE_ADDR
)16;
2558 /* Figure out where the longjmp will land. Slurp the args out of the
2559 stack. We expect the first arg to be a pointer to the jmp_buf
2560 structure from which we extract the address that we will land at.
2561 This address is copied into PC. This routine returns non-zero on
2565 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2568 CORE_ADDR sp
, jb_addr
;
2569 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2570 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2571 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2573 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2574 longjmp will land. */
2575 if (jb_pc_offset
== -1)
2578 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2579 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2580 if (target_read_memory (sp
+ 4, buf
, 4))
2583 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2584 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2587 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2592 /* Check whether TYPE must be 16-byte-aligned when passed as a
2593 function argument. 16-byte vectors, _Decimal128 and structures or
2594 unions containing such types must be 16-byte-aligned; other
2595 arguments are 4-byte-aligned. */
2598 i386_16_byte_align_p (struct type
*type
)
2600 type
= check_typedef (type
);
2601 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2602 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2603 && TYPE_LENGTH (type
) == 16)
2605 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2606 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2607 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2608 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2611 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2613 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2620 /* Implementation for set_gdbarch_push_dummy_code. */
2623 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2624 struct value
**args
, int nargs
, struct type
*value_type
,
2625 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2626 struct regcache
*regcache
)
2628 /* Use 0xcc breakpoint - 1 byte. */
2632 /* Keep the stack aligned. */
2637 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2638 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2639 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2640 CORE_ADDR struct_addr
)
2642 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2648 /* Determine the total space required for arguments and struct
2649 return address in a first pass (allowing for 16-byte-aligned
2650 arguments), then push arguments in a second pass. */
2652 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2654 int args_space_used
= 0;
2660 /* Push value address. */
2661 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2662 write_memory (sp
, buf
, 4);
2663 args_space_used
+= 4;
2669 for (i
= 0; i
< nargs
; i
++)
2671 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2675 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2676 args_space_used
= align_up (args_space_used
, 16);
2678 write_memory (sp
+ args_space_used
,
2679 value_contents_all (args
[i
]), len
);
2680 /* The System V ABI says that:
2682 "An argument's size is increased, if necessary, to make it a
2683 multiple of [32-bit] words. This may require tail padding,
2684 depending on the size of the argument."
2686 This makes sure the stack stays word-aligned. */
2687 args_space_used
+= align_up (len
, 4);
2691 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2692 args_space
= align_up (args_space
, 16);
2693 args_space
+= align_up (len
, 4);
2701 /* The original System V ABI only requires word alignment,
2702 but modern incarnations need 16-byte alignment in order
2703 to support SSE. Since wasting a few bytes here isn't
2704 harmful we unconditionally enforce 16-byte alignment. */
2709 /* Store return address. */
2711 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2712 write_memory (sp
, buf
, 4);
2714 /* Finally, update the stack pointer... */
2715 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2716 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2718 /* ...and fake a frame pointer. */
2719 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2721 /* MarkK wrote: This "+ 8" is all over the place:
2722 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2723 i386_dummy_id). It's there, since all frame unwinders for
2724 a given target have to agree (within a certain margin) on the
2725 definition of the stack address of a frame. Otherwise frame id
2726 comparison might not work correctly. Since DWARF2/GCC uses the
2727 stack address *before* the function call as a frame's CFA. On
2728 the i386, when %ebp is used as a frame pointer, the offset
2729 between the contents %ebp and the CFA as defined by GCC. */
2733 /* These registers are used for returning integers (and on some
2734 targets also for returning `struct' and `union' values when their
2735 size and alignment match an integer type). */
2736 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2737 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2739 /* Read, for architecture GDBARCH, a function return value of TYPE
2740 from REGCACHE, and copy that into VALBUF. */
2743 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2744 struct regcache
*regcache
, gdb_byte
*valbuf
)
2746 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2747 int len
= TYPE_LENGTH (type
);
2748 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2750 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2752 if (tdep
->st0_regnum
< 0)
2754 warning (_("Cannot find floating-point return value."));
2755 memset (valbuf
, 0, len
);
2759 /* Floating-point return values can be found in %st(0). Convert
2760 its contents to the desired type. This is probably not
2761 exactly how it would happen on the target itself, but it is
2762 the best we can do. */
2763 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2764 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2768 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2769 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2771 if (len
<= low_size
)
2773 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2774 memcpy (valbuf
, buf
, len
);
2776 else if (len
<= (low_size
+ high_size
))
2778 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2779 memcpy (valbuf
, buf
, low_size
);
2780 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2781 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2784 internal_error (__FILE__
, __LINE__
,
2785 _("Cannot extract return value of %d bytes long."),
2790 /* Write, for architecture GDBARCH, a function return value of TYPE
2791 from VALBUF into REGCACHE. */
2794 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2795 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2798 int len
= TYPE_LENGTH (type
);
2800 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2803 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2805 if (tdep
->st0_regnum
< 0)
2807 warning (_("Cannot set floating-point return value."));
2811 /* Returning floating-point values is a bit tricky. Apart from
2812 storing the return value in %st(0), we have to simulate the
2813 state of the FPU at function return point. */
2815 /* Convert the value found in VALBUF to the extended
2816 floating-point format used by the FPU. This is probably
2817 not exactly how it would happen on the target itself, but
2818 it is the best we can do. */
2819 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2820 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2822 /* Set the top of the floating-point register stack to 7. The
2823 actual value doesn't really matter, but 7 is what a normal
2824 function return would end up with if the program started out
2825 with a freshly initialized FPU. */
2826 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2828 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2830 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2831 the floating-point register stack to 7, the appropriate value
2832 for the tag word is 0x3fff. */
2833 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2837 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2838 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2840 if (len
<= low_size
)
2841 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2842 else if (len
<= (low_size
+ high_size
))
2844 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2845 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2846 len
- low_size
, valbuf
+ low_size
);
2849 internal_error (__FILE__
, __LINE__
,
2850 _("Cannot store return value of %d bytes long."), len
);
2855 /* This is the variable that is set with "set struct-convention", and
2856 its legitimate values. */
2857 static const char default_struct_convention
[] = "default";
2858 static const char pcc_struct_convention
[] = "pcc";
2859 static const char reg_struct_convention
[] = "reg";
2860 static const char *const valid_conventions
[] =
2862 default_struct_convention
,
2863 pcc_struct_convention
,
2864 reg_struct_convention
,
2867 static const char *struct_convention
= default_struct_convention
;
2869 /* Return non-zero if TYPE, which is assumed to be a structure,
2870 a union type, or an array type, should be returned in registers
2871 for architecture GDBARCH. */
2874 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2877 enum type_code code
= TYPE_CODE (type
);
2878 int len
= TYPE_LENGTH (type
);
2880 gdb_assert (code
== TYPE_CODE_STRUCT
2881 || code
== TYPE_CODE_UNION
2882 || code
== TYPE_CODE_ARRAY
);
2884 if (struct_convention
== pcc_struct_convention
2885 || (struct_convention
== default_struct_convention
2886 && tdep
->struct_return
== pcc_struct_return
))
2889 /* Structures consisting of a single `float', `double' or 'long
2890 double' member are returned in %st(0). */
2891 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2893 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2894 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2895 return (len
== 4 || len
== 8 || len
== 12);
2898 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2901 /* Determine, for architecture GDBARCH, how a return value of TYPE
2902 should be returned. If it is supposed to be returned in registers,
2903 and READBUF is non-zero, read the appropriate value from REGCACHE,
2904 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2905 from WRITEBUF into REGCACHE. */
2907 static enum return_value_convention
2908 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2909 struct type
*type
, struct regcache
*regcache
,
2910 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2912 enum type_code code
= TYPE_CODE (type
);
2914 if (((code
== TYPE_CODE_STRUCT
2915 || code
== TYPE_CODE_UNION
2916 || code
== TYPE_CODE_ARRAY
)
2917 && !i386_reg_struct_return_p (gdbarch
, type
))
2918 /* Complex double and long double uses the struct return covention. */
2919 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2920 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2921 /* 128-bit decimal float uses the struct return convention. */
2922 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2924 /* The System V ABI says that:
2926 "A function that returns a structure or union also sets %eax
2927 to the value of the original address of the caller's area
2928 before it returns. Thus when the caller receives control
2929 again, the address of the returned object resides in register
2930 %eax and can be used to access the object."
2932 So the ABI guarantees that we can always find the return
2933 value just after the function has returned. */
2935 /* Note that the ABI doesn't mention functions returning arrays,
2936 which is something possible in certain languages such as Ada.
2937 In this case, the value is returned as if it was wrapped in
2938 a record, so the convention applied to records also applies
2945 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2946 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2949 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2952 /* This special case is for structures consisting of a single
2953 `float', `double' or 'long double' member. These structures are
2954 returned in %st(0). For these structures, we call ourselves
2955 recursively, changing TYPE into the type of the first member of
2956 the structure. Since that should work for all structures that
2957 have only one member, we don't bother to check the member's type
2959 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2961 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2962 return i386_return_value (gdbarch
, function
, type
, regcache
,
2967 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2969 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2971 return RETURN_VALUE_REGISTER_CONVENTION
;
2976 i387_ext_type (struct gdbarch
*gdbarch
)
2978 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2980 if (!tdep
->i387_ext_type
)
2982 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2983 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2986 return tdep
->i387_ext_type
;
2989 /* Construct type for pseudo BND registers. We can't use
2990 tdesc_find_type since a complement of one value has to be used
2991 to describe the upper bound. */
2993 static struct type
*
2994 i386_bnd_type (struct gdbarch
*gdbarch
)
2996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2999 if (!tdep
->i386_bnd_type
)
3001 struct type
*t
, *bound_t
;
3002 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3004 /* The type we're building is described bellow: */
3009 void *ubound
; /* One complement of raw ubound field. */
3013 t
= arch_composite_type (gdbarch
,
3014 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3016 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3017 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3019 TYPE_NAME (t
) = "builtin_type_bound128";
3020 tdep
->i386_bnd_type
= t
;
3023 return tdep
->i386_bnd_type
;
3026 /* Construct vector type for pseudo ZMM registers. We can't use
3027 tdesc_find_type since ZMM isn't described in target description. */
3029 static struct type
*
3030 i386_zmm_type (struct gdbarch
*gdbarch
)
3032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3034 if (!tdep
->i386_zmm_type
)
3036 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3038 /* The type we're building is this: */
3040 union __gdb_builtin_type_vec512i
3042 int128_t uint128
[4];
3043 int64_t v4_int64
[8];
3044 int32_t v8_int32
[16];
3045 int16_t v16_int16
[32];
3046 int8_t v32_int8
[64];
3047 double v4_double
[8];
3054 t
= arch_composite_type (gdbarch
,
3055 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3056 append_composite_type_field (t
, "v16_float",
3057 init_vector_type (bt
->builtin_float
, 16));
3058 append_composite_type_field (t
, "v8_double",
3059 init_vector_type (bt
->builtin_double
, 8));
3060 append_composite_type_field (t
, "v64_int8",
3061 init_vector_type (bt
->builtin_int8
, 64));
3062 append_composite_type_field (t
, "v32_int16",
3063 init_vector_type (bt
->builtin_int16
, 32));
3064 append_composite_type_field (t
, "v16_int32",
3065 init_vector_type (bt
->builtin_int32
, 16));
3066 append_composite_type_field (t
, "v8_int64",
3067 init_vector_type (bt
->builtin_int64
, 8));
3068 append_composite_type_field (t
, "v4_int128",
3069 init_vector_type (bt
->builtin_int128
, 4));
3071 TYPE_VECTOR (t
) = 1;
3072 TYPE_NAME (t
) = "builtin_type_vec512i";
3073 tdep
->i386_zmm_type
= t
;
3076 return tdep
->i386_zmm_type
;
3079 /* Construct vector type for pseudo YMM registers. We can't use
3080 tdesc_find_type since YMM isn't described in target description. */
3082 static struct type
*
3083 i386_ymm_type (struct gdbarch
*gdbarch
)
3085 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3087 if (!tdep
->i386_ymm_type
)
3089 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3091 /* The type we're building is this: */
3093 union __gdb_builtin_type_vec256i
3095 int128_t uint128
[2];
3096 int64_t v2_int64
[4];
3097 int32_t v4_int32
[8];
3098 int16_t v8_int16
[16];
3099 int8_t v16_int8
[32];
3100 double v2_double
[4];
3107 t
= arch_composite_type (gdbarch
,
3108 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3109 append_composite_type_field (t
, "v8_float",
3110 init_vector_type (bt
->builtin_float
, 8));
3111 append_composite_type_field (t
, "v4_double",
3112 init_vector_type (bt
->builtin_double
, 4));
3113 append_composite_type_field (t
, "v32_int8",
3114 init_vector_type (bt
->builtin_int8
, 32));
3115 append_composite_type_field (t
, "v16_int16",
3116 init_vector_type (bt
->builtin_int16
, 16));
3117 append_composite_type_field (t
, "v8_int32",
3118 init_vector_type (bt
->builtin_int32
, 8));
3119 append_composite_type_field (t
, "v4_int64",
3120 init_vector_type (bt
->builtin_int64
, 4));
3121 append_composite_type_field (t
, "v2_int128",
3122 init_vector_type (bt
->builtin_int128
, 2));
3124 TYPE_VECTOR (t
) = 1;
3125 TYPE_NAME (t
) = "builtin_type_vec256i";
3126 tdep
->i386_ymm_type
= t
;
3129 return tdep
->i386_ymm_type
;
3132 /* Construct vector type for MMX registers. */
3133 static struct type
*
3134 i386_mmx_type (struct gdbarch
*gdbarch
)
3136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3138 if (!tdep
->i386_mmx_type
)
3140 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3142 /* The type we're building is this: */
3144 union __gdb_builtin_type_vec64i
3147 int32_t v2_int32
[2];
3148 int16_t v4_int16
[4];
3155 t
= arch_composite_type (gdbarch
,
3156 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3158 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3159 append_composite_type_field (t
, "v2_int32",
3160 init_vector_type (bt
->builtin_int32
, 2));
3161 append_composite_type_field (t
, "v4_int16",
3162 init_vector_type (bt
->builtin_int16
, 4));
3163 append_composite_type_field (t
, "v8_int8",
3164 init_vector_type (bt
->builtin_int8
, 8));
3166 TYPE_VECTOR (t
) = 1;
3167 TYPE_NAME (t
) = "builtin_type_vec64i";
3168 tdep
->i386_mmx_type
= t
;
3171 return tdep
->i386_mmx_type
;
3174 /* Return the GDB type object for the "standard" data type of data in
3178 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3180 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3181 return i386_bnd_type (gdbarch
);
3182 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3183 return i386_mmx_type (gdbarch
);
3184 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3185 return i386_ymm_type (gdbarch
);
3186 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3187 return i386_ymm_type (gdbarch
);
3188 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3189 return i386_zmm_type (gdbarch
);
3192 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3193 if (i386_byte_regnum_p (gdbarch
, regnum
))
3194 return bt
->builtin_int8
;
3195 else if (i386_word_regnum_p (gdbarch
, regnum
))
3196 return bt
->builtin_int16
;
3197 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3198 return bt
->builtin_int32
;
3199 else if (i386_k_regnum_p (gdbarch
, regnum
))
3200 return bt
->builtin_int64
;
3203 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3206 /* Map a cooked register onto a raw register or memory. For the i386,
3207 the MMX registers need to be mapped onto floating point registers. */
3210 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
3212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
3217 mmxreg
= regnum
- tdep
->mm0_regnum
;
3218 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
3219 tos
= (fstat
>> 11) & 0x7;
3220 fpreg
= (mmxreg
+ tos
) % 8;
3222 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3225 /* A helper function for us by i386_pseudo_register_read_value and
3226 amd64_pseudo_register_read_value. It does all the work but reads
3227 the data into an already-allocated value. */
3230 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3231 struct regcache
*regcache
,
3233 struct value
*result_value
)
3235 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3236 enum register_status status
;
3237 gdb_byte
*buf
= value_contents_raw (result_value
);
3239 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3241 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3243 /* Extract (always little endian). */
3244 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3245 if (status
!= REG_VALID
)
3246 mark_value_bytes_unavailable (result_value
, 0,
3247 TYPE_LENGTH (value_type (result_value
)));
3249 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3253 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3254 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3256 regnum
-= tdep
->bnd0_regnum
;
3258 /* Extract (always little endian). Read lower 128bits. */
3259 status
= regcache_raw_read (regcache
,
3260 I387_BND0R_REGNUM (tdep
) + regnum
,
3262 if (status
!= REG_VALID
)
3263 mark_value_bytes_unavailable (result_value
, 0, 16);
3266 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3267 LONGEST upper
, lower
;
3268 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3270 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3271 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3274 memcpy (buf
, &lower
, size
);
3275 memcpy (buf
+ size
, &upper
, size
);
3278 else if (i386_k_regnum_p (gdbarch
, regnum
))
3280 regnum
-= tdep
->k0_regnum
;
3282 /* Extract (always little endian). */
3283 status
= regcache_raw_read (regcache
,
3284 tdep
->k0_regnum
+ regnum
,
3286 if (status
!= REG_VALID
)
3287 mark_value_bytes_unavailable (result_value
, 0, 8);
3289 memcpy (buf
, raw_buf
, 8);
3291 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3293 regnum
-= tdep
->zmm0_regnum
;
3295 if (regnum
< num_lower_zmm_regs
)
3297 /* Extract (always little endian). Read lower 128bits. */
3298 status
= regcache_raw_read (regcache
,
3299 I387_XMM0_REGNUM (tdep
) + regnum
,
3301 if (status
!= REG_VALID
)
3302 mark_value_bytes_unavailable (result_value
, 0, 16);
3304 memcpy (buf
, raw_buf
, 16);
3306 /* Extract (always little endian). Read upper 128bits. */
3307 status
= regcache_raw_read (regcache
,
3308 tdep
->ymm0h_regnum
+ regnum
,
3310 if (status
!= REG_VALID
)
3311 mark_value_bytes_unavailable (result_value
, 16, 16);
3313 memcpy (buf
+ 16, raw_buf
, 16);
3317 /* Extract (always little endian). Read lower 128bits. */
3318 status
= regcache_raw_read (regcache
,
3319 I387_XMM16_REGNUM (tdep
) + regnum
3320 - num_lower_zmm_regs
,
3322 if (status
!= REG_VALID
)
3323 mark_value_bytes_unavailable (result_value
, 0, 16);
3325 memcpy (buf
, raw_buf
, 16);
3327 /* Extract (always little endian). Read upper 128bits. */
3328 status
= regcache_raw_read (regcache
,
3329 I387_YMM16H_REGNUM (tdep
) + regnum
3330 - num_lower_zmm_regs
,
3332 if (status
!= REG_VALID
)
3333 mark_value_bytes_unavailable (result_value
, 16, 16);
3335 memcpy (buf
+ 16, raw_buf
, 16);
3338 /* Read upper 256bits. */
3339 status
= regcache_raw_read (regcache
,
3340 tdep
->zmm0h_regnum
+ regnum
,
3342 if (status
!= REG_VALID
)
3343 mark_value_bytes_unavailable (result_value
, 32, 32);
3345 memcpy (buf
+ 32, raw_buf
, 32);
3347 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3349 regnum
-= tdep
->ymm0_regnum
;
3351 /* Extract (always little endian). Read lower 128bits. */
3352 status
= regcache_raw_read (regcache
,
3353 I387_XMM0_REGNUM (tdep
) + regnum
,
3355 if (status
!= REG_VALID
)
3356 mark_value_bytes_unavailable (result_value
, 0, 16);
3358 memcpy (buf
, raw_buf
, 16);
3359 /* Read upper 128bits. */
3360 status
= regcache_raw_read (regcache
,
3361 tdep
->ymm0h_regnum
+ regnum
,
3363 if (status
!= REG_VALID
)
3364 mark_value_bytes_unavailable (result_value
, 16, 32);
3366 memcpy (buf
+ 16, raw_buf
, 16);
3368 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3370 regnum
-= tdep
->ymm16_regnum
;
3371 /* Extract (always little endian). Read lower 128bits. */
3372 status
= regcache_raw_read (regcache
,
3373 I387_XMM16_REGNUM (tdep
) + regnum
,
3375 if (status
!= REG_VALID
)
3376 mark_value_bytes_unavailable (result_value
, 0, 16);
3378 memcpy (buf
, raw_buf
, 16);
3379 /* Read upper 128bits. */
3380 status
= regcache_raw_read (regcache
,
3381 tdep
->ymm16h_regnum
+ regnum
,
3383 if (status
!= REG_VALID
)
3384 mark_value_bytes_unavailable (result_value
, 16, 16);
3386 memcpy (buf
+ 16, raw_buf
, 16);
3388 else if (i386_word_regnum_p (gdbarch
, regnum
))
3390 int gpnum
= regnum
- tdep
->ax_regnum
;
3392 /* Extract (always little endian). */
3393 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3394 if (status
!= REG_VALID
)
3395 mark_value_bytes_unavailable (result_value
, 0,
3396 TYPE_LENGTH (value_type (result_value
)));
3398 memcpy (buf
, raw_buf
, 2);
3400 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3402 /* Check byte pseudo registers last since this function will
3403 be called from amd64_pseudo_register_read, which handles
3404 byte pseudo registers differently. */
3405 int gpnum
= regnum
- tdep
->al_regnum
;
3407 /* Extract (always little endian). We read both lower and
3409 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3410 if (status
!= REG_VALID
)
3411 mark_value_bytes_unavailable (result_value
, 0,
3412 TYPE_LENGTH (value_type (result_value
)));
3413 else if (gpnum
>= 4)
3414 memcpy (buf
, raw_buf
+ 1, 1);
3416 memcpy (buf
, raw_buf
, 1);
3419 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3423 static struct value
*
3424 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3425 struct regcache
*regcache
,
3428 struct value
*result
;
3430 result
= allocate_value (register_type (gdbarch
, regnum
));
3431 VALUE_LVAL (result
) = lval_register
;
3432 VALUE_REGNUM (result
) = regnum
;
3434 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3440 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3441 int regnum
, const gdb_byte
*buf
)
3443 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3445 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3447 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3450 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3451 /* ... Modify ... (always little endian). */
3452 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3454 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3460 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3462 ULONGEST upper
, lower
;
3463 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3464 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3466 /* New values from input value. */
3467 regnum
-= tdep
->bnd0_regnum
;
3468 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3469 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3471 /* Fetching register buffer. */
3472 regcache_raw_read (regcache
,
3473 I387_BND0R_REGNUM (tdep
) + regnum
,
3478 /* Set register bits. */
3479 memcpy (raw_buf
, &lower
, 8);
3480 memcpy (raw_buf
+ 8, &upper
, 8);
3483 regcache_raw_write (regcache
,
3484 I387_BND0R_REGNUM (tdep
) + regnum
,
3487 else if (i386_k_regnum_p (gdbarch
, regnum
))
3489 regnum
-= tdep
->k0_regnum
;
3491 regcache_raw_write (regcache
,
3492 tdep
->k0_regnum
+ regnum
,
3495 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3497 regnum
-= tdep
->zmm0_regnum
;
3499 if (regnum
< num_lower_zmm_regs
)
3501 /* Write lower 128bits. */
3502 regcache_raw_write (regcache
,
3503 I387_XMM0_REGNUM (tdep
) + regnum
,
3505 /* Write upper 128bits. */
3506 regcache_raw_write (regcache
,
3507 I387_YMM0_REGNUM (tdep
) + regnum
,
3512 /* Write lower 128bits. */
3513 regcache_raw_write (regcache
,
3514 I387_XMM16_REGNUM (tdep
) + regnum
3515 - num_lower_zmm_regs
,
3517 /* Write upper 128bits. */
3518 regcache_raw_write (regcache
,
3519 I387_YMM16H_REGNUM (tdep
) + regnum
3520 - num_lower_zmm_regs
,
3523 /* Write upper 256bits. */
3524 regcache_raw_write (regcache
,
3525 tdep
->zmm0h_regnum
+ regnum
,
3528 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3530 regnum
-= tdep
->ymm0_regnum
;
3532 /* ... Write lower 128bits. */
3533 regcache_raw_write (regcache
,
3534 I387_XMM0_REGNUM (tdep
) + regnum
,
3536 /* ... Write upper 128bits. */
3537 regcache_raw_write (regcache
,
3538 tdep
->ymm0h_regnum
+ regnum
,
3541 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3543 regnum
-= tdep
->ymm16_regnum
;
3545 /* ... Write lower 128bits. */
3546 regcache_raw_write (regcache
,
3547 I387_XMM16_REGNUM (tdep
) + regnum
,
3549 /* ... Write upper 128bits. */
3550 regcache_raw_write (regcache
,
3551 tdep
->ymm16h_regnum
+ regnum
,
3554 else if (i386_word_regnum_p (gdbarch
, regnum
))
3556 int gpnum
= regnum
- tdep
->ax_regnum
;
3559 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3560 /* ... Modify ... (always little endian). */
3561 memcpy (raw_buf
, buf
, 2);
3563 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3565 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3567 /* Check byte pseudo registers last since this function will
3568 be called from amd64_pseudo_register_read, which handles
3569 byte pseudo registers differently. */
3570 int gpnum
= regnum
- tdep
->al_regnum
;
3572 /* Read ... We read both lower and upper registers. */
3573 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3574 /* ... Modify ... (always little endian). */
3576 memcpy (raw_buf
+ 1, buf
, 1);
3578 memcpy (raw_buf
, buf
, 1);
3580 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3583 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3588 /* Return the register number of the register allocated by GCC after
3589 REGNUM, or -1 if there is no such register. */
3592 i386_next_regnum (int regnum
)
3594 /* GCC allocates the registers in the order:
3596 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3598 Since storing a variable in %esp doesn't make any sense we return
3599 -1 for %ebp and for %esp itself. */
3600 static int next_regnum
[] =
3602 I386_EDX_REGNUM
, /* Slot for %eax. */
3603 I386_EBX_REGNUM
, /* Slot for %ecx. */
3604 I386_ECX_REGNUM
, /* Slot for %edx. */
3605 I386_ESI_REGNUM
, /* Slot for %ebx. */
3606 -1, -1, /* Slots for %esp and %ebp. */
3607 I386_EDI_REGNUM
, /* Slot for %esi. */
3608 I386_EBP_REGNUM
/* Slot for %edi. */
3611 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3612 return next_regnum
[regnum
];
3617 /* Return nonzero if a value of type TYPE stored in register REGNUM
3618 needs any special handling. */
3621 i386_convert_register_p (struct gdbarch
*gdbarch
,
3622 int regnum
, struct type
*type
)
3624 int len
= TYPE_LENGTH (type
);
3626 /* Values may be spread across multiple registers. Most debugging
3627 formats aren't expressive enough to specify the locations, so
3628 some heuristics is involved. Right now we only handle types that
3629 have a length that is a multiple of the word size, since GCC
3630 doesn't seem to put any other types into registers. */
3631 if (len
> 4 && len
% 4 == 0)
3633 int last_regnum
= regnum
;
3637 last_regnum
= i386_next_regnum (last_regnum
);
3641 if (last_regnum
!= -1)
3645 return i387_convert_register_p (gdbarch
, regnum
, type
);
3648 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3649 return its contents in TO. */
3652 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3653 struct type
*type
, gdb_byte
*to
,
3654 int *optimizedp
, int *unavailablep
)
3656 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3657 int len
= TYPE_LENGTH (type
);
3659 if (i386_fp_regnum_p (gdbarch
, regnum
))
3660 return i387_register_to_value (frame
, regnum
, type
, to
,
3661 optimizedp
, unavailablep
);
3663 /* Read a value spread across multiple registers. */
3665 gdb_assert (len
> 4 && len
% 4 == 0);
3669 gdb_assert (regnum
!= -1);
3670 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3672 if (!get_frame_register_bytes (frame
, regnum
, 0,
3673 register_size (gdbarch
, regnum
),
3674 to
, optimizedp
, unavailablep
))
3677 regnum
= i386_next_regnum (regnum
);
3682 *optimizedp
= *unavailablep
= 0;
3686 /* Write the contents FROM of a value of type TYPE into register
3687 REGNUM in frame FRAME. */
3690 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3691 struct type
*type
, const gdb_byte
*from
)
3693 int len
= TYPE_LENGTH (type
);
3695 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3697 i387_value_to_register (frame
, regnum
, type
, from
);
3701 /* Write a value spread across multiple registers. */
3703 gdb_assert (len
> 4 && len
% 4 == 0);
3707 gdb_assert (regnum
!= -1);
3708 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3710 put_frame_register (frame
, regnum
, from
);
3711 regnum
= i386_next_regnum (regnum
);
3717 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3718 in the general-purpose register set REGSET to register cache
3719 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3722 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3723 int regnum
, const void *gregs
, size_t len
)
3725 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3726 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3727 const gdb_byte
*regs
= gregs
;
3730 gdb_assert (len
== tdep
->sizeof_gregset
);
3732 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3734 if ((regnum
== i
|| regnum
== -1)
3735 && tdep
->gregset_reg_offset
[i
] != -1)
3736 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3740 /* Collect register REGNUM from the register cache REGCACHE and store
3741 it in the buffer specified by GREGS and LEN as described by the
3742 general-purpose register set REGSET. If REGNUM is -1, do this for
3743 all registers in REGSET. */
3746 i386_collect_gregset (const struct regset
*regset
,
3747 const struct regcache
*regcache
,
3748 int regnum
, void *gregs
, size_t len
)
3750 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3751 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3752 gdb_byte
*regs
= gregs
;
3755 gdb_assert (len
== tdep
->sizeof_gregset
);
3757 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3759 if ((regnum
== i
|| regnum
== -1)
3760 && tdep
->gregset_reg_offset
[i
] != -1)
3761 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3765 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3766 in the floating-point register set REGSET to register cache
3767 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3770 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3771 int regnum
, const void *fpregs
, size_t len
)
3773 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3774 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3776 if (len
== I387_SIZEOF_FXSAVE
)
3778 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3782 gdb_assert (len
== tdep
->sizeof_fpregset
);
3783 i387_supply_fsave (regcache
, regnum
, fpregs
);
3786 /* Collect register REGNUM from the register cache REGCACHE and store
3787 it in the buffer specified by FPREGS and LEN as described by the
3788 floating-point register set REGSET. If REGNUM is -1, do this for
3789 all registers in REGSET. */
3792 i386_collect_fpregset (const struct regset
*regset
,
3793 const struct regcache
*regcache
,
3794 int regnum
, void *fpregs
, size_t len
)
3796 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3797 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3799 if (len
== I387_SIZEOF_FXSAVE
)
3801 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3805 gdb_assert (len
== tdep
->sizeof_fpregset
);
3806 i387_collect_fsave (regcache
, regnum
, fpregs
);
3809 /* Register set definitions. */
3811 const struct regset i386_gregset
=
3813 NULL
, i386_supply_gregset
, i386_collect_gregset
3816 const struct regset i386_fpregset
=
3818 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3821 /* Default iterator over core file register note sections. */
3824 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3825 iterate_over_regset_sections_cb
*cb
,
3827 const struct regcache
*regcache
)
3829 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3831 cb (".reg", tdep
->sizeof_gregset
, &i386_gregset
, NULL
, cb_data
);
3832 if (tdep
->sizeof_fpregset
)
3833 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
3837 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3840 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3841 CORE_ADDR pc
, char *name
)
3843 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3847 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3849 unsigned long indirect
=
3850 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3851 struct minimal_symbol
*indsym
=
3852 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3853 const char *symname
= indsym
? MSYMBOL_LINKAGE_NAME (indsym
) : 0;
3857 if (strncmp (symname
, "__imp_", 6) == 0
3858 || strncmp (symname
, "_imp_", 5) == 0)
3860 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3863 return 0; /* Not a trampoline. */
3867 /* Return whether the THIS_FRAME corresponds to a sigtramp
3871 i386_sigtramp_p (struct frame_info
*this_frame
)
3873 CORE_ADDR pc
= get_frame_pc (this_frame
);
3876 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3877 return (name
&& strcmp ("_sigtramp", name
) == 0);
3881 /* We have two flavours of disassembly. The machinery on this page
3882 deals with switching between those. */
3885 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3887 gdb_assert (disassembly_flavor
== att_flavor
3888 || disassembly_flavor
== intel_flavor
);
3890 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3891 constified, cast to prevent a compiler warning. */
3892 info
->disassembler_options
= (char *) disassembly_flavor
;
3894 return print_insn_i386 (pc
, info
);
3898 /* There are a few i386 architecture variants that differ only
3899 slightly from the generic i386 target. For now, we don't give them
3900 their own source file, but include them here. As a consequence,
3901 they'll always be included. */
3903 /* System V Release 4 (SVR4). */
3905 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3909 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3911 CORE_ADDR pc
= get_frame_pc (this_frame
);
3914 /* The origin of these symbols is currently unknown. */
3915 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3916 return (name
&& (strcmp ("_sigreturn", name
) == 0
3917 || strcmp ("sigvechandler", name
) == 0));
3920 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3921 address of the associated sigcontext (ucontext) structure. */
3924 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3926 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3931 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3932 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3934 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3939 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3943 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3945 return (*s
== '$' /* Literal number. */
3946 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3947 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3948 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3951 /* Helper function for i386_stap_parse_special_token.
3953 This function parses operands of the form `-8+3+1(%rbp)', which
3954 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3956 Return 1 if the operand was parsed successfully, zero
3960 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
3961 struct stap_parse_info
*p
)
3963 const char *s
= p
->arg
;
3965 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3969 long displacements
[3];
3985 if (!isdigit ((unsigned char) *s
))
3988 displacements
[0] = strtol (s
, &endp
, 10);
3991 if (*s
!= '+' && *s
!= '-')
3993 /* We are not dealing with a triplet. */
4006 if (!isdigit ((unsigned char) *s
))
4009 displacements
[1] = strtol (s
, &endp
, 10);
4012 if (*s
!= '+' && *s
!= '-')
4014 /* We are not dealing with a triplet. */
4027 if (!isdigit ((unsigned char) *s
))
4030 displacements
[2] = strtol (s
, &endp
, 10);
4033 if (*s
!= '(' || s
[1] != '%')
4039 while (isalnum (*s
))
4045 len
= s
- start
- 1;
4046 regname
= alloca (len
+ 1);
4048 strncpy (regname
, start
, len
);
4049 regname
[len
] = '\0';
4051 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4052 error (_("Invalid register name `%s' on expression `%s'."),
4053 regname
, p
->saved_arg
);
4055 for (i
= 0; i
< 3; i
++)
4057 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4059 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4060 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4061 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4063 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4066 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4069 write_exp_string (&p
->pstate
, str
);
4070 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4072 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4073 write_exp_elt_type (&p
->pstate
,
4074 builtin_type (gdbarch
)->builtin_data_ptr
);
4075 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4077 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4078 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4079 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4081 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4082 write_exp_elt_type (&p
->pstate
,
4083 lookup_pointer_type (p
->arg_type
));
4084 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4086 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4096 /* Helper function for i386_stap_parse_special_token.
4098 This function parses operands of the form `register base +
4099 (register index * size) + offset', as represented in
4100 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4102 Return 1 if the operand was parsed successfully, zero
4106 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4107 struct stap_parse_info
*p
)
4109 const char *s
= p
->arg
;
4111 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4113 int offset_minus
= 0;
4122 struct stoken base_token
, index_token
;
4132 if (offset_minus
&& !isdigit (*s
))
4139 offset
= strtol (s
, &endp
, 10);
4143 if (*s
!= '(' || s
[1] != '%')
4149 while (isalnum (*s
))
4152 if (*s
!= ',' || s
[1] != '%')
4155 len_base
= s
- start
;
4156 base
= alloca (len_base
+ 1);
4157 strncpy (base
, start
, len_base
);
4158 base
[len_base
] = '\0';
4160 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4161 error (_("Invalid register name `%s' on expression `%s'."),
4162 base
, p
->saved_arg
);
4167 while (isalnum (*s
))
4170 len_index
= s
- start
;
4171 index
= alloca (len_index
+ 1);
4172 strncpy (index
, start
, len_index
);
4173 index
[len_index
] = '\0';
4175 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4176 error (_("Invalid register name `%s' on expression `%s'."),
4177 index
, p
->saved_arg
);
4179 if (*s
!= ',' && *s
!= ')')
4195 size
= strtol (s
, &endp
, 10);
4206 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4207 write_exp_elt_type (&p
->pstate
,
4208 builtin_type (gdbarch
)->builtin_long
);
4209 write_exp_elt_longcst (&p
->pstate
, offset
);
4210 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4212 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4215 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4216 base_token
.ptr
= base
;
4217 base_token
.length
= len_base
;
4218 write_exp_string (&p
->pstate
, base_token
);
4219 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4222 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4224 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4225 index_token
.ptr
= index
;
4226 index_token
.length
= len_index
;
4227 write_exp_string (&p
->pstate
, index_token
);
4228 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4232 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4233 write_exp_elt_type (&p
->pstate
,
4234 builtin_type (gdbarch
)->builtin_long
);
4235 write_exp_elt_longcst (&p
->pstate
, size
);
4236 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4238 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4239 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4242 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4244 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4245 write_exp_elt_type (&p
->pstate
,
4246 lookup_pointer_type (p
->arg_type
));
4247 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4249 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4259 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4263 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4264 struct stap_parse_info
*p
)
4266 /* In order to parse special tokens, we use a state-machine that go
4267 through every known token and try to get a match. */
4271 THREE_ARG_DISPLACEMENT
,
4275 current_state
= TRIPLET
;
4277 /* The special tokens to be parsed here are:
4279 - `register base + (register index * size) + offset', as represented
4280 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4282 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4283 `*(-8 + 3 - 1 + (void *) $eax)'. */
4285 while (current_state
!= DONE
)
4287 switch (current_state
)
4290 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4294 case THREE_ARG_DISPLACEMENT
:
4295 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4300 /* Advancing to the next state. */
4312 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4314 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4315 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4316 static const char *const stap_register_indirection_prefixes
[] = { "(",
4318 static const char *const stap_register_indirection_suffixes
[] = { ")",
4321 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4322 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4324 /* Registering SystemTap handlers. */
4325 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4326 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4327 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4328 stap_register_indirection_prefixes
);
4329 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4330 stap_register_indirection_suffixes
);
4331 set_gdbarch_stap_is_single_operand (gdbarch
,
4332 i386_stap_is_single_operand
);
4333 set_gdbarch_stap_parse_special_token (gdbarch
,
4334 i386_stap_parse_special_token
);
4337 /* System V Release 4 (SVR4). */
4340 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4344 /* System V Release 4 uses ELF. */
4345 i386_elf_init_abi (info
, gdbarch
);
4347 /* System V Release 4 has shared libraries. */
4348 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4350 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4351 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4352 tdep
->sc_pc_offset
= 36 + 14 * 4;
4353 tdep
->sc_sp_offset
= 36 + 17 * 4;
4355 tdep
->jb_pc_offset
= 20;
4361 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4365 /* DJGPP doesn't have any special frames for signal handlers. */
4366 tdep
->sigtramp_p
= NULL
;
4368 tdep
->jb_pc_offset
= 36;
4370 /* DJGPP does not support the SSE registers. */
4371 if (! tdesc_has_registers (info
.target_desc
))
4372 tdep
->tdesc
= tdesc_i386_mmx
;
4374 /* Native compiler is GCC, which uses the SVR4 register numbering
4375 even in COFF and STABS. See the comment in i386_gdbarch_init,
4376 before the calls to set_gdbarch_stab_reg_to_regnum and
4377 set_gdbarch_sdb_reg_to_regnum. */
4378 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4379 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4381 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
4385 /* i386 register groups. In addition to the normal groups, add "mmx"
4388 static struct reggroup
*i386_sse_reggroup
;
4389 static struct reggroup
*i386_mmx_reggroup
;
4392 i386_init_reggroups (void)
4394 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4395 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4399 i386_add_reggroups (struct gdbarch
*gdbarch
)
4401 reggroup_add (gdbarch
, i386_sse_reggroup
);
4402 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4403 reggroup_add (gdbarch
, general_reggroup
);
4404 reggroup_add (gdbarch
, float_reggroup
);
4405 reggroup_add (gdbarch
, all_reggroup
);
4406 reggroup_add (gdbarch
, save_reggroup
);
4407 reggroup_add (gdbarch
, restore_reggroup
);
4408 reggroup_add (gdbarch
, vector_reggroup
);
4409 reggroup_add (gdbarch
, system_reggroup
);
4413 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4414 struct reggroup
*group
)
4416 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4417 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4418 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4419 bndr_regnum_p
, bnd_regnum_p
, k_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4420 zmm_avx512_regnum_p
, mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4421 avx512_p
, avx_p
, sse_p
;
4423 /* Don't include pseudo registers, except for MMX, in any register
4425 if (i386_byte_regnum_p (gdbarch
, regnum
))
4428 if (i386_word_regnum_p (gdbarch
, regnum
))
4431 if (i386_dword_regnum_p (gdbarch
, regnum
))
4434 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4435 if (group
== i386_mmx_reggroup
)
4436 return mmx_regnum_p
;
4438 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4439 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4440 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4441 if (group
== i386_sse_reggroup
)
4442 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4444 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4445 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4446 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4448 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4449 == X86_XSTATE_AVX512_MASK
);
4450 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4451 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4452 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4453 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4455 if (group
== vector_reggroup
)
4456 return (mmx_regnum_p
4457 || (zmm_regnum_p
&& avx512_p
)
4458 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4459 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4462 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4463 || i386_fpc_regnum_p (gdbarch
, regnum
));
4464 if (group
== float_reggroup
)
4467 /* For "info reg all", don't include upper YMM registers nor XMM
4468 registers when AVX is supported. */
4469 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4470 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4471 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4472 if (group
== all_reggroup
4473 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4474 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4476 || ymmh_avx512_regnum_p
4480 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4481 if (group
== all_reggroup
4482 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4483 return bnd_regnum_p
;
4485 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4486 if (group
== all_reggroup
4487 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4490 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4491 if (group
== all_reggroup
4492 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4493 return mpx_ctrl_regnum_p
;
4495 if (group
== general_reggroup
)
4496 return (!fp_regnum_p
4500 && !xmm_avx512_regnum_p
4503 && !ymm_avx512_regnum_p
4504 && !ymmh_avx512_regnum_p
4507 && !mpx_ctrl_regnum_p
4511 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4515 /* Get the ARGIth function argument for the current function. */
4518 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4521 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4522 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4523 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4524 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4528 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
4530 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
4532 /* On i386, breakpoint is exactly 1 byte long, so we just
4533 adjust the PC in the regcache. */
4535 regcache_write_pc (regcache
, current_pc
);
4539 #define PREFIX_REPZ 0x01
4540 #define PREFIX_REPNZ 0x02
4541 #define PREFIX_LOCK 0x04
4542 #define PREFIX_DATA 0x08
4543 #define PREFIX_ADDR 0x10
4555 /* i386 arith/logic operations */
4568 struct i386_record_s
4570 struct gdbarch
*gdbarch
;
4571 struct regcache
*regcache
;
4572 CORE_ADDR orig_addr
;
4578 uint8_t mod
, reg
, rm
;
4587 /* Parse the "modrm" part of the memory address irp->addr points at.
4588 Returns -1 if something goes wrong, 0 otherwise. */
4591 i386_record_modrm (struct i386_record_s
*irp
)
4593 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4595 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4599 irp
->mod
= (irp
->modrm
>> 6) & 3;
4600 irp
->reg
= (irp
->modrm
>> 3) & 7;
4601 irp
->rm
= irp
->modrm
& 7;
4606 /* Extract the memory address that the current instruction writes to,
4607 and return it in *ADDR. Return -1 if something goes wrong. */
4610 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4612 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4613 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4618 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4625 uint8_t base
= irp
->rm
;
4630 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4633 scale
= (byte
>> 6) & 3;
4634 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4642 if ((base
& 7) == 5)
4645 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4648 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4649 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4650 *addr
+= irp
->addr
+ irp
->rip_offset
;
4654 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4657 *addr
= (int8_t) buf
[0];
4660 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4662 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4670 if (base
== 4 && irp
->popl_esp_hack
)
4671 *addr
+= irp
->popl_esp_hack
;
4672 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4675 if (irp
->aflag
== 2)
4680 *addr
= (uint32_t) (offset64
+ *addr
);
4682 if (havesib
&& (index
!= 4 || scale
!= 0))
4684 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4686 if (irp
->aflag
== 2)
4687 *addr
+= offset64
<< scale
;
4689 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4694 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4695 address from 32-bit to 64-bit. */
4696 *addr
= (uint32_t) *addr
;
4707 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4710 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4716 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4719 *addr
= (int8_t) buf
[0];
4722 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4725 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4732 regcache_raw_read_unsigned (irp
->regcache
,
4733 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4735 *addr
= (uint32_t) (*addr
+ offset64
);
4736 regcache_raw_read_unsigned (irp
->regcache
,
4737 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4739 *addr
= (uint32_t) (*addr
+ offset64
);
4742 regcache_raw_read_unsigned (irp
->regcache
,
4743 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4745 *addr
= (uint32_t) (*addr
+ offset64
);
4746 regcache_raw_read_unsigned (irp
->regcache
,
4747 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4749 *addr
= (uint32_t) (*addr
+ offset64
);
4752 regcache_raw_read_unsigned (irp
->regcache
,
4753 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4755 *addr
= (uint32_t) (*addr
+ offset64
);
4756 regcache_raw_read_unsigned (irp
->regcache
,
4757 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4759 *addr
= (uint32_t) (*addr
+ offset64
);
4762 regcache_raw_read_unsigned (irp
->regcache
,
4763 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4765 *addr
= (uint32_t) (*addr
+ offset64
);
4766 regcache_raw_read_unsigned (irp
->regcache
,
4767 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4769 *addr
= (uint32_t) (*addr
+ offset64
);
4772 regcache_raw_read_unsigned (irp
->regcache
,
4773 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4775 *addr
= (uint32_t) (*addr
+ offset64
);
4778 regcache_raw_read_unsigned (irp
->regcache
,
4779 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4781 *addr
= (uint32_t) (*addr
+ offset64
);
4784 regcache_raw_read_unsigned (irp
->regcache
,
4785 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4787 *addr
= (uint32_t) (*addr
+ offset64
);
4790 regcache_raw_read_unsigned (irp
->regcache
,
4791 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4793 *addr
= (uint32_t) (*addr
+ offset64
);
4803 /* Record the address and contents of the memory that will be changed
4804 by the current instruction. Return -1 if something goes wrong, 0
4808 i386_record_lea_modrm (struct i386_record_s
*irp
)
4810 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4813 if (irp
->override
>= 0)
4815 if (record_full_memory_query
)
4819 target_terminal_ours ();
4821 Process record ignores the memory change of instruction at address %s\n\
4822 because it can't get the value of the segment register.\n\
4823 Do you want to stop the program?"),
4824 paddress (gdbarch
, irp
->orig_addr
));
4825 target_terminal_inferior ();
4833 if (i386_record_lea_modrm_addr (irp
, &addr
))
4836 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4842 /* Record the effects of a push operation. Return -1 if something
4843 goes wrong, 0 otherwise. */
4846 i386_record_push (struct i386_record_s
*irp
, int size
)
4850 if (record_full_arch_list_add_reg (irp
->regcache
,
4851 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4853 regcache_raw_read_unsigned (irp
->regcache
,
4854 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4856 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4863 /* Defines contents to record. */
4864 #define I386_SAVE_FPU_REGS 0xfffd
4865 #define I386_SAVE_FPU_ENV 0xfffe
4866 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4868 /* Record the values of the floating point registers which will be
4869 changed by the current instruction. Returns -1 if something is
4870 wrong, 0 otherwise. */
4872 static int i386_record_floats (struct gdbarch
*gdbarch
,
4873 struct i386_record_s
*ir
,
4876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4879 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4880 happen. Currently we store st0-st7 registers, but we need not store all
4881 registers all the time, in future we use ftag register and record only
4882 those who are not marked as an empty. */
4884 if (I386_SAVE_FPU_REGS
== iregnum
)
4886 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4888 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4892 else if (I386_SAVE_FPU_ENV
== iregnum
)
4894 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4896 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4900 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4902 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4904 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4908 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4909 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4911 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4916 /* Parameter error. */
4919 if(I386_SAVE_FPU_ENV
!= iregnum
)
4921 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4923 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4930 /* Parse the current instruction, and record the values of the
4931 registers and memory that will be changed by the current
4932 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4934 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4935 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4938 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4939 CORE_ADDR input_addr
)
4941 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4947 gdb_byte buf
[MAX_REGISTER_SIZE
];
4948 struct i386_record_s ir
;
4949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4953 memset (&ir
, 0, sizeof (struct i386_record_s
));
4954 ir
.regcache
= regcache
;
4955 ir
.addr
= input_addr
;
4956 ir
.orig_addr
= input_addr
;
4960 ir
.popl_esp_hack
= 0;
4961 ir
.regmap
= tdep
->record_regmap
;
4962 ir
.gdbarch
= gdbarch
;
4964 if (record_debug
> 1)
4965 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4967 paddress (gdbarch
, ir
.addr
));
4972 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4975 switch (opcode8
) /* Instruction prefixes */
4977 case REPE_PREFIX_OPCODE
:
4978 prefixes
|= PREFIX_REPZ
;
4980 case REPNE_PREFIX_OPCODE
:
4981 prefixes
|= PREFIX_REPNZ
;
4983 case LOCK_PREFIX_OPCODE
:
4984 prefixes
|= PREFIX_LOCK
;
4986 case CS_PREFIX_OPCODE
:
4987 ir
.override
= X86_RECORD_CS_REGNUM
;
4989 case SS_PREFIX_OPCODE
:
4990 ir
.override
= X86_RECORD_SS_REGNUM
;
4992 case DS_PREFIX_OPCODE
:
4993 ir
.override
= X86_RECORD_DS_REGNUM
;
4995 case ES_PREFIX_OPCODE
:
4996 ir
.override
= X86_RECORD_ES_REGNUM
;
4998 case FS_PREFIX_OPCODE
:
4999 ir
.override
= X86_RECORD_FS_REGNUM
;
5001 case GS_PREFIX_OPCODE
:
5002 ir
.override
= X86_RECORD_GS_REGNUM
;
5004 case DATA_PREFIX_OPCODE
:
5005 prefixes
|= PREFIX_DATA
;
5007 case ADDR_PREFIX_OPCODE
:
5008 prefixes
|= PREFIX_ADDR
;
5010 case 0x40: /* i386 inc %eax */
5011 case 0x41: /* i386 inc %ecx */
5012 case 0x42: /* i386 inc %edx */
5013 case 0x43: /* i386 inc %ebx */
5014 case 0x44: /* i386 inc %esp */
5015 case 0x45: /* i386 inc %ebp */
5016 case 0x46: /* i386 inc %esi */
5017 case 0x47: /* i386 inc %edi */
5018 case 0x48: /* i386 dec %eax */
5019 case 0x49: /* i386 dec %ecx */
5020 case 0x4a: /* i386 dec %edx */
5021 case 0x4b: /* i386 dec %ebx */
5022 case 0x4c: /* i386 dec %esp */
5023 case 0x4d: /* i386 dec %ebp */
5024 case 0x4e: /* i386 dec %esi */
5025 case 0x4f: /* i386 dec %edi */
5026 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5029 rex_w
= (opcode8
>> 3) & 1;
5030 rex_r
= (opcode8
& 0x4) << 1;
5031 ir
.rex_x
= (opcode8
& 0x2) << 2;
5032 ir
.rex_b
= (opcode8
& 0x1) << 3;
5034 else /* 32 bit target */
5043 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5049 if (prefixes
& PREFIX_DATA
)
5052 if (prefixes
& PREFIX_ADDR
)
5054 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5057 /* Now check op code. */
5058 opcode
= (uint32_t) opcode8
;
5063 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5066 opcode
= (uint32_t) opcode8
| 0x0f00;
5070 case 0x00: /* arith & logic */
5118 if (((opcode
>> 3) & 7) != OP_CMPL
)
5120 if ((opcode
& 1) == 0)
5123 ir
.ot
= ir
.dflag
+ OT_WORD
;
5125 switch ((opcode
>> 1) & 3)
5127 case 0: /* OP Ev, Gv */
5128 if (i386_record_modrm (&ir
))
5132 if (i386_record_lea_modrm (&ir
))
5138 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5140 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5143 case 1: /* OP Gv, Ev */
5144 if (i386_record_modrm (&ir
))
5147 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5149 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5151 case 2: /* OP A, Iv */
5152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5156 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5159 case 0x80: /* GRP1 */
5163 if (i386_record_modrm (&ir
))
5166 if (ir
.reg
!= OP_CMPL
)
5168 if ((opcode
& 1) == 0)
5171 ir
.ot
= ir
.dflag
+ OT_WORD
;
5178 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5179 if (i386_record_lea_modrm (&ir
))
5183 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5185 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5188 case 0x40: /* inc */
5197 case 0x48: /* dec */
5206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5207 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5210 case 0xf6: /* GRP3 */
5212 if ((opcode
& 1) == 0)
5215 ir
.ot
= ir
.dflag
+ OT_WORD
;
5216 if (i386_record_modrm (&ir
))
5219 if (ir
.mod
!= 3 && ir
.reg
== 0)
5220 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5225 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5231 if (i386_record_lea_modrm (&ir
))
5237 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5241 if (ir
.reg
== 3) /* neg */
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5249 if (ir
.ot
!= OT_BYTE
)
5250 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5255 opcode
= opcode
<< 8 | ir
.modrm
;
5261 case 0xfe: /* GRP4 */
5262 case 0xff: /* GRP5 */
5263 if (i386_record_modrm (&ir
))
5265 if (ir
.reg
>= 2 && opcode
== 0xfe)
5268 opcode
= opcode
<< 8 | ir
.modrm
;
5275 if ((opcode
& 1) == 0)
5278 ir
.ot
= ir
.dflag
+ OT_WORD
;
5281 if (i386_record_lea_modrm (&ir
))
5287 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5291 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5294 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5296 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5298 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5301 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5302 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5311 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5313 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5318 opcode
= opcode
<< 8 | ir
.modrm
;
5324 case 0x84: /* test */
5328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5331 case 0x98: /* CWDE/CBW */
5332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5335 case 0x99: /* CDQ/CWD */
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5337 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5340 case 0x0faf: /* imul */
5343 ir
.ot
= ir
.dflag
+ OT_WORD
;
5344 if (i386_record_modrm (&ir
))
5347 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5348 else if (opcode
== 0x6b)
5351 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5353 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5357 case 0x0fc0: /* xadd */
5359 if ((opcode
& 1) == 0)
5362 ir
.ot
= ir
.dflag
+ OT_WORD
;
5363 if (i386_record_modrm (&ir
))
5368 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5371 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5373 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5377 if (i386_record_lea_modrm (&ir
))
5379 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5386 case 0x0fb0: /* cmpxchg */
5388 if ((opcode
& 1) == 0)
5391 ir
.ot
= ir
.dflag
+ OT_WORD
;
5392 if (i386_record_modrm (&ir
))
5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5398 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5405 if (i386_record_lea_modrm (&ir
))
5408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5411 case 0x0fc7: /* cmpxchg8b */
5412 if (i386_record_modrm (&ir
))
5417 opcode
= opcode
<< 8 | ir
.modrm
;
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5422 if (i386_record_lea_modrm (&ir
))
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5427 case 0x50: /* push */
5437 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5439 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5443 case 0x06: /* push es */
5444 case 0x0e: /* push cs */
5445 case 0x16: /* push ss */
5446 case 0x1e: /* push ds */
5447 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5452 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5456 case 0x0fa0: /* push fs */
5457 case 0x0fa8: /* push gs */
5458 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5463 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5467 case 0x60: /* pusha */
5468 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5473 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5477 case 0x58: /* pop */
5485 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5486 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5489 case 0x61: /* popa */
5490 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5495 for (regnum
= X86_RECORD_REAX_REGNUM
;
5496 regnum
<= X86_RECORD_REDI_REGNUM
;
5498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5501 case 0x8f: /* pop */
5502 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5503 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5505 ir
.ot
= ir
.dflag
+ OT_WORD
;
5506 if (i386_record_modrm (&ir
))
5509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5512 ir
.popl_esp_hack
= 1 << ir
.ot
;
5513 if (i386_record_lea_modrm (&ir
))
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5519 case 0xc8: /* enter */
5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5521 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5523 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5527 case 0xc9: /* leave */
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5532 case 0x07: /* pop es */
5533 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5543 case 0x17: /* pop ss */
5544 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5554 case 0x1f: /* pop ds */
5555 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5565 case 0x0fa1: /* pop fs */
5566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5571 case 0x0fa9: /* pop gs */
5572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5577 case 0x88: /* mov */
5581 if ((opcode
& 1) == 0)
5584 ir
.ot
= ir
.dflag
+ OT_WORD
;
5586 if (i386_record_modrm (&ir
))
5591 if (opcode
== 0xc6 || opcode
== 0xc7)
5592 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5593 if (i386_record_lea_modrm (&ir
))
5598 if (opcode
== 0xc6 || opcode
== 0xc7)
5600 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5602 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5606 case 0x8a: /* mov */
5608 if ((opcode
& 1) == 0)
5611 ir
.ot
= ir
.dflag
+ OT_WORD
;
5612 if (i386_record_modrm (&ir
))
5615 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5620 case 0x8c: /* mov seg */
5621 if (i386_record_modrm (&ir
))
5626 opcode
= opcode
<< 8 | ir
.modrm
;
5631 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5635 if (i386_record_lea_modrm (&ir
))
5640 case 0x8e: /* mov seg */
5641 if (i386_record_modrm (&ir
))
5646 regnum
= X86_RECORD_ES_REGNUM
;
5649 regnum
= X86_RECORD_SS_REGNUM
;
5652 regnum
= X86_RECORD_DS_REGNUM
;
5655 regnum
= X86_RECORD_FS_REGNUM
;
5658 regnum
= X86_RECORD_GS_REGNUM
;
5662 opcode
= opcode
<< 8 | ir
.modrm
;
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5670 case 0x0fb6: /* movzbS */
5671 case 0x0fb7: /* movzwS */
5672 case 0x0fbe: /* movsbS */
5673 case 0x0fbf: /* movswS */
5674 if (i386_record_modrm (&ir
))
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5679 case 0x8d: /* lea */
5680 if (i386_record_modrm (&ir
))
5685 opcode
= opcode
<< 8 | ir
.modrm
;
5690 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5695 case 0xa0: /* mov EAX */
5698 case 0xd7: /* xlat */
5699 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5702 case 0xa2: /* mov EAX */
5704 if (ir
.override
>= 0)
5706 if (record_full_memory_query
)
5710 target_terminal_ours ();
5712 Process record ignores the memory change of instruction at address %s\n\
5713 because it can't get the value of the segment register.\n\
5714 Do you want to stop the program?"),
5715 paddress (gdbarch
, ir
.orig_addr
));
5716 target_terminal_inferior ();
5723 if ((opcode
& 1) == 0)
5726 ir
.ot
= ir
.dflag
+ OT_WORD
;
5729 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5732 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5736 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5739 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5743 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5746 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5748 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5753 case 0xb0: /* mov R, Ib */
5761 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5762 ? ((opcode
& 0x7) | ir
.rex_b
)
5763 : ((opcode
& 0x7) & 0x3));
5766 case 0xb8: /* mov R, Iv */
5774 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5777 case 0x91: /* xchg R, EAX */
5784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5788 case 0x86: /* xchg Ev, Gv */
5790 if ((opcode
& 1) == 0)
5793 ir
.ot
= ir
.dflag
+ OT_WORD
;
5794 if (i386_record_modrm (&ir
))
5799 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5801 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5805 if (i386_record_lea_modrm (&ir
))
5809 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5811 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5814 case 0xc4: /* les Gv */
5815 case 0xc5: /* lds Gv */
5816 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5822 case 0x0fb2: /* lss Gv */
5823 case 0x0fb4: /* lfs Gv */
5824 case 0x0fb5: /* lgs Gv */
5825 if (i386_record_modrm (&ir
))
5833 opcode
= opcode
<< 8 | ir
.modrm
;
5838 case 0xc4: /* les Gv */
5839 regnum
= X86_RECORD_ES_REGNUM
;
5841 case 0xc5: /* lds Gv */
5842 regnum
= X86_RECORD_DS_REGNUM
;
5844 case 0x0fb2: /* lss Gv */
5845 regnum
= X86_RECORD_SS_REGNUM
;
5847 case 0x0fb4: /* lfs Gv */
5848 regnum
= X86_RECORD_FS_REGNUM
;
5850 case 0x0fb5: /* lgs Gv */
5851 regnum
= X86_RECORD_GS_REGNUM
;
5854 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5855 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5856 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5859 case 0xc0: /* shifts */
5865 if ((opcode
& 1) == 0)
5868 ir
.ot
= ir
.dflag
+ OT_WORD
;
5869 if (i386_record_modrm (&ir
))
5871 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5873 if (i386_record_lea_modrm (&ir
))
5879 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5881 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5883 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5890 if (i386_record_modrm (&ir
))
5894 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5899 if (i386_record_lea_modrm (&ir
))
5904 case 0xd8: /* Floats. */
5912 if (i386_record_modrm (&ir
))
5914 ir
.reg
|= ((opcode
& 7) << 3);
5920 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5928 /* For fcom, ficom nothing to do. */
5934 /* For fcomp, ficomp pop FPU stack, store all. */
5935 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5962 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5963 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5964 of code, always affects st(0) register. */
5965 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5989 /* Handling fld, fild. */
5990 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5994 switch (ir
.reg
>> 4)
5997 if (record_full_arch_list_add_mem (addr64
, 4))
6001 if (record_full_arch_list_add_mem (addr64
, 8))
6007 if (record_full_arch_list_add_mem (addr64
, 2))
6013 switch (ir
.reg
>> 4)
6016 if (record_full_arch_list_add_mem (addr64
, 4))
6018 if (3 == (ir
.reg
& 7))
6020 /* For fstp m32fp. */
6021 if (i386_record_floats (gdbarch
, &ir
,
6022 I386_SAVE_FPU_REGS
))
6027 if (record_full_arch_list_add_mem (addr64
, 4))
6029 if ((3 == (ir
.reg
& 7))
6030 || (5 == (ir
.reg
& 7))
6031 || (7 == (ir
.reg
& 7)))
6033 /* For fstp insn. */
6034 if (i386_record_floats (gdbarch
, &ir
,
6035 I386_SAVE_FPU_REGS
))
6040 if (record_full_arch_list_add_mem (addr64
, 8))
6042 if (3 == (ir
.reg
& 7))
6044 /* For fstp m64fp. */
6045 if (i386_record_floats (gdbarch
, &ir
,
6046 I386_SAVE_FPU_REGS
))
6051 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6053 /* For fistp, fbld, fild, fbstp. */
6054 if (i386_record_floats (gdbarch
, &ir
,
6055 I386_SAVE_FPU_REGS
))
6060 if (record_full_arch_list_add_mem (addr64
, 2))
6069 if (i386_record_floats (gdbarch
, &ir
,
6070 I386_SAVE_FPU_ENV_REG_STACK
))
6075 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6080 if (i386_record_floats (gdbarch
, &ir
,
6081 I386_SAVE_FPU_ENV_REG_STACK
))
6087 if (record_full_arch_list_add_mem (addr64
, 28))
6092 if (record_full_arch_list_add_mem (addr64
, 14))
6098 if (record_full_arch_list_add_mem (addr64
, 2))
6100 /* Insn fstp, fbstp. */
6101 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6106 if (record_full_arch_list_add_mem (addr64
, 10))
6112 if (record_full_arch_list_add_mem (addr64
, 28))
6118 if (record_full_arch_list_add_mem (addr64
, 14))
6122 if (record_full_arch_list_add_mem (addr64
, 80))
6125 if (i386_record_floats (gdbarch
, &ir
,
6126 I386_SAVE_FPU_ENV_REG_STACK
))
6130 if (record_full_arch_list_add_mem (addr64
, 8))
6133 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6138 opcode
= opcode
<< 8 | ir
.modrm
;
6143 /* Opcode is an extension of modR/M byte. */
6149 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6153 if (0x0c == (ir
.modrm
>> 4))
6155 if ((ir
.modrm
& 0x0f) <= 7)
6157 if (i386_record_floats (gdbarch
, &ir
,
6158 I386_SAVE_FPU_REGS
))
6163 if (i386_record_floats (gdbarch
, &ir
,
6164 I387_ST0_REGNUM (tdep
)))
6166 /* If only st(0) is changing, then we have already
6168 if ((ir
.modrm
& 0x0f) - 0x08)
6170 if (i386_record_floats (gdbarch
, &ir
,
6171 I387_ST0_REGNUM (tdep
) +
6172 ((ir
.modrm
& 0x0f) - 0x08)))
6190 if (i386_record_floats (gdbarch
, &ir
,
6191 I387_ST0_REGNUM (tdep
)))
6209 if (i386_record_floats (gdbarch
, &ir
,
6210 I386_SAVE_FPU_REGS
))
6214 if (i386_record_floats (gdbarch
, &ir
,
6215 I387_ST0_REGNUM (tdep
)))
6217 if (i386_record_floats (gdbarch
, &ir
,
6218 I387_ST0_REGNUM (tdep
) + 1))
6225 if (0xe9 == ir
.modrm
)
6227 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6230 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6232 if (i386_record_floats (gdbarch
, &ir
,
6233 I387_ST0_REGNUM (tdep
)))
6235 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6237 if (i386_record_floats (gdbarch
, &ir
,
6238 I387_ST0_REGNUM (tdep
) +
6242 else if ((ir
.modrm
& 0x0f) - 0x08)
6244 if (i386_record_floats (gdbarch
, &ir
,
6245 I387_ST0_REGNUM (tdep
) +
6246 ((ir
.modrm
& 0x0f) - 0x08)))
6252 if (0xe3 == ir
.modrm
)
6254 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6257 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6259 if (i386_record_floats (gdbarch
, &ir
,
6260 I387_ST0_REGNUM (tdep
)))
6262 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6264 if (i386_record_floats (gdbarch
, &ir
,
6265 I387_ST0_REGNUM (tdep
) +
6269 else if ((ir
.modrm
& 0x0f) - 0x08)
6271 if (i386_record_floats (gdbarch
, &ir
,
6272 I387_ST0_REGNUM (tdep
) +
6273 ((ir
.modrm
& 0x0f) - 0x08)))
6279 if ((0x0c == ir
.modrm
>> 4)
6280 || (0x0d == ir
.modrm
>> 4)
6281 || (0x0f == ir
.modrm
>> 4))
6283 if ((ir
.modrm
& 0x0f) <= 7)
6285 if (i386_record_floats (gdbarch
, &ir
,
6286 I387_ST0_REGNUM (tdep
) +
6292 if (i386_record_floats (gdbarch
, &ir
,
6293 I387_ST0_REGNUM (tdep
) +
6294 ((ir
.modrm
& 0x0f) - 0x08)))
6300 if (0x0c == ir
.modrm
>> 4)
6302 if (i386_record_floats (gdbarch
, &ir
,
6303 I387_FTAG_REGNUM (tdep
)))
6306 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6308 if ((ir
.modrm
& 0x0f) <= 7)
6310 if (i386_record_floats (gdbarch
, &ir
,
6311 I387_ST0_REGNUM (tdep
) +
6317 if (i386_record_floats (gdbarch
, &ir
,
6318 I386_SAVE_FPU_REGS
))
6324 if ((0x0c == ir
.modrm
>> 4)
6325 || (0x0e == ir
.modrm
>> 4)
6326 || (0x0f == ir
.modrm
>> 4)
6327 || (0xd9 == ir
.modrm
))
6329 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6334 if (0xe0 == ir
.modrm
)
6336 if (record_full_arch_list_add_reg (ir
.regcache
,
6340 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6342 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6350 case 0xa4: /* movsS */
6352 case 0xaa: /* stosS */
6354 case 0x6c: /* insS */
6356 regcache_raw_read_unsigned (ir
.regcache
,
6357 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6363 if ((opcode
& 1) == 0)
6366 ir
.ot
= ir
.dflag
+ OT_WORD
;
6367 regcache_raw_read_unsigned (ir
.regcache
,
6368 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6371 regcache_raw_read_unsigned (ir
.regcache
,
6372 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6374 regcache_raw_read_unsigned (ir
.regcache
,
6375 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6377 if (ir
.aflag
&& (es
!= ds
))
6379 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6380 if (record_full_memory_query
)
6384 target_terminal_ours ();
6386 Process record ignores the memory change of instruction at address %s\n\
6387 because it can't get the value of the segment register.\n\
6388 Do you want to stop the program?"),
6389 paddress (gdbarch
, ir
.orig_addr
));
6390 target_terminal_inferior ();
6397 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6401 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6402 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6403 if (opcode
== 0xa4 || opcode
== 0xa5)
6404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6405 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6406 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6410 case 0xa6: /* cmpsS */
6412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6413 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6414 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6416 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6419 case 0xac: /* lodsS */
6421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6423 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6428 case 0xae: /* scasS */
6430 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6431 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6436 case 0x6e: /* outsS */
6438 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6439 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6444 case 0xe4: /* port I/O */
6448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6459 case 0xc2: /* ret im */
6460 case 0xc3: /* ret */
6461 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6462 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6465 case 0xca: /* lret im */
6466 case 0xcb: /* lret */
6467 case 0xcf: /* iret */
6468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6473 case 0xe8: /* call im */
6474 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6476 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6480 case 0x9a: /* lcall im */
6481 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6487 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6491 case 0xe9: /* jmp im */
6492 case 0xea: /* ljmp im */
6493 case 0xeb: /* jmp Jb */
6494 case 0x70: /* jcc Jb */
6510 case 0x0f80: /* jcc Jv */
6528 case 0x0f90: /* setcc Gv */
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6546 if (i386_record_modrm (&ir
))
6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6553 if (i386_record_lea_modrm (&ir
))
6558 case 0x0f40: /* cmov Gv, Ev */
6574 if (i386_record_modrm (&ir
))
6577 if (ir
.dflag
== OT_BYTE
)
6579 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6583 case 0x9c: /* pushf */
6584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6585 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6587 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6591 case 0x9d: /* popf */
6592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6596 case 0x9e: /* sahf */
6597 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6603 case 0xf5: /* cmc */
6604 case 0xf8: /* clc */
6605 case 0xf9: /* stc */
6606 case 0xfc: /* cld */
6607 case 0xfd: /* std */
6608 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6611 case 0x9f: /* lahf */
6612 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6621 /* bit operations */
6622 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6623 ir
.ot
= ir
.dflag
+ OT_WORD
;
6624 if (i386_record_modrm (&ir
))
6629 opcode
= opcode
<< 8 | ir
.modrm
;
6635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6638 if (i386_record_lea_modrm (&ir
))
6642 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6645 case 0x0fa3: /* bt Gv, Ev */
6646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6649 case 0x0fab: /* bts */
6650 case 0x0fb3: /* btr */
6651 case 0x0fbb: /* btc */
6652 ir
.ot
= ir
.dflag
+ OT_WORD
;
6653 if (i386_record_modrm (&ir
))
6656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6660 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6662 regcache_raw_read_unsigned (ir
.regcache
,
6663 ir
.regmap
[ir
.reg
| rex_r
],
6668 addr64
+= ((int16_t) addr
>> 4) << 4;
6671 addr64
+= ((int32_t) addr
>> 5) << 5;
6674 addr64
+= ((int64_t) addr
>> 6) << 6;
6677 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6679 if (i386_record_lea_modrm (&ir
))
6682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6685 case 0x0fbc: /* bsf */
6686 case 0x0fbd: /* bsr */
6687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6692 case 0x27: /* daa */
6693 case 0x2f: /* das */
6694 case 0x37: /* aaa */
6695 case 0x3f: /* aas */
6696 case 0xd4: /* aam */
6697 case 0xd5: /* aad */
6698 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6708 case 0x90: /* nop */
6709 if (prefixes
& PREFIX_LOCK
)
6716 case 0x9b: /* fwait */
6717 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6719 opcode
= (uint32_t) opcode8
;
6725 case 0xcc: /* int3 */
6726 printf_unfiltered (_("Process record does not support instruction "
6733 case 0xcd: /* int */
6737 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6740 if (interrupt
!= 0x80
6741 || tdep
->i386_intx80_record
== NULL
)
6743 printf_unfiltered (_("Process record does not support "
6744 "instruction int 0x%02x.\n"),
6749 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6756 case 0xce: /* into */
6757 printf_unfiltered (_("Process record does not support "
6758 "instruction into.\n"));
6763 case 0xfa: /* cli */
6764 case 0xfb: /* sti */
6767 case 0x62: /* bound */
6768 printf_unfiltered (_("Process record does not support "
6769 "instruction bound.\n"));
6774 case 0x0fc8: /* bswap reg */
6782 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6785 case 0xd6: /* salc */
6786 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6791 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6792 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6795 case 0xe0: /* loopnz */
6796 case 0xe1: /* loopz */
6797 case 0xe2: /* loop */
6798 case 0xe3: /* jecxz */
6799 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6800 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6803 case 0x0f30: /* wrmsr */
6804 printf_unfiltered (_("Process record does not support "
6805 "instruction wrmsr.\n"));
6810 case 0x0f32: /* rdmsr */
6811 printf_unfiltered (_("Process record does not support "
6812 "instruction rdmsr.\n"));
6817 case 0x0f31: /* rdtsc */
6818 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6822 case 0x0f34: /* sysenter */
6825 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6830 if (tdep
->i386_sysenter_record
== NULL
)
6832 printf_unfiltered (_("Process record does not support "
6833 "instruction sysenter.\n"));
6837 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6843 case 0x0f35: /* sysexit */
6844 printf_unfiltered (_("Process record does not support "
6845 "instruction sysexit.\n"));
6850 case 0x0f05: /* syscall */
6853 if (tdep
->i386_syscall_record
== NULL
)
6855 printf_unfiltered (_("Process record does not support "
6856 "instruction syscall.\n"));
6860 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6866 case 0x0f07: /* sysret */
6867 printf_unfiltered (_("Process record does not support "
6868 "instruction sysret.\n"));
6873 case 0x0fa2: /* cpuid */
6874 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6876 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6877 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6880 case 0xf4: /* hlt */
6881 printf_unfiltered (_("Process record does not support "
6882 "instruction hlt.\n"));
6888 if (i386_record_modrm (&ir
))
6895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6899 if (i386_record_lea_modrm (&ir
))
6908 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6912 opcode
= opcode
<< 8 | ir
.modrm
;
6919 if (i386_record_modrm (&ir
))
6930 opcode
= opcode
<< 8 | ir
.modrm
;
6933 if (ir
.override
>= 0)
6935 if (record_full_memory_query
)
6939 target_terminal_ours ();
6941 Process record ignores the memory change of instruction at address %s\n\
6942 because it can't get the value of the segment register.\n\
6943 Do you want to stop the program?"),
6944 paddress (gdbarch
, ir
.orig_addr
));
6945 target_terminal_inferior ();
6952 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6954 if (record_full_arch_list_add_mem (addr64
, 2))
6957 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6959 if (record_full_arch_list_add_mem (addr64
, 8))
6964 if (record_full_arch_list_add_mem (addr64
, 4))
6975 case 0: /* monitor */
6978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6982 opcode
= opcode
<< 8 | ir
.modrm
;
6990 if (ir
.override
>= 0)
6992 if (record_full_memory_query
)
6996 target_terminal_ours ();
6998 Process record ignores the memory change of instruction at address %s\n\
6999 because it can't get the value of the segment register.\n\
7000 Do you want to stop the program?"),
7001 paddress (gdbarch
, ir
.orig_addr
));
7002 target_terminal_inferior ();
7011 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7013 if (record_full_arch_list_add_mem (addr64
, 2))
7016 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7018 if (record_full_arch_list_add_mem (addr64
, 8))
7023 if (record_full_arch_list_add_mem (addr64
, 4))
7035 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7036 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7040 else if (ir
.rm
== 1)
7047 opcode
= opcode
<< 8 | ir
.modrm
;
7054 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7060 if (i386_record_lea_modrm (&ir
))
7063 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7066 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7068 case 7: /* invlpg */
7071 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7072 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7076 opcode
= opcode
<< 8 | ir
.modrm
;
7081 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7085 opcode
= opcode
<< 8 | ir
.modrm
;
7091 case 0x0f08: /* invd */
7092 case 0x0f09: /* wbinvd */
7095 case 0x63: /* arpl */
7096 if (i386_record_modrm (&ir
))
7098 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7100 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7101 ? (ir
.reg
| rex_r
) : ir
.rm
);
7105 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7106 if (i386_record_lea_modrm (&ir
))
7109 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7110 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7113 case 0x0f02: /* lar */
7114 case 0x0f03: /* lsl */
7115 if (i386_record_modrm (&ir
))
7117 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7118 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7122 if (i386_record_modrm (&ir
))
7124 if (ir
.mod
== 3 && ir
.reg
== 3)
7127 opcode
= opcode
<< 8 | ir
.modrm
;
7139 /* nop (multi byte) */
7142 case 0x0f20: /* mov reg, crN */
7143 case 0x0f22: /* mov crN, reg */
7144 if (i386_record_modrm (&ir
))
7146 if ((ir
.modrm
& 0xc0) != 0xc0)
7149 opcode
= opcode
<< 8 | ir
.modrm
;
7160 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7166 opcode
= opcode
<< 8 | ir
.modrm
;
7172 case 0x0f21: /* mov reg, drN */
7173 case 0x0f23: /* mov drN, reg */
7174 if (i386_record_modrm (&ir
))
7176 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7177 || ir
.reg
== 5 || ir
.reg
>= 8)
7180 opcode
= opcode
<< 8 | ir
.modrm
;
7184 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7189 case 0x0f06: /* clts */
7190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7193 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7195 case 0x0f0d: /* 3DNow! prefetch */
7198 case 0x0f0e: /* 3DNow! femms */
7199 case 0x0f77: /* emms */
7200 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7202 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7205 case 0x0f0f: /* 3DNow! data */
7206 if (i386_record_modrm (&ir
))
7208 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7213 case 0x0c: /* 3DNow! pi2fw */
7214 case 0x0d: /* 3DNow! pi2fd */
7215 case 0x1c: /* 3DNow! pf2iw */
7216 case 0x1d: /* 3DNow! pf2id */
7217 case 0x8a: /* 3DNow! pfnacc */
7218 case 0x8e: /* 3DNow! pfpnacc */
7219 case 0x90: /* 3DNow! pfcmpge */
7220 case 0x94: /* 3DNow! pfmin */
7221 case 0x96: /* 3DNow! pfrcp */
7222 case 0x97: /* 3DNow! pfrsqrt */
7223 case 0x9a: /* 3DNow! pfsub */
7224 case 0x9e: /* 3DNow! pfadd */
7225 case 0xa0: /* 3DNow! pfcmpgt */
7226 case 0xa4: /* 3DNow! pfmax */
7227 case 0xa6: /* 3DNow! pfrcpit1 */
7228 case 0xa7: /* 3DNow! pfrsqit1 */
7229 case 0xaa: /* 3DNow! pfsubr */
7230 case 0xae: /* 3DNow! pfacc */
7231 case 0xb0: /* 3DNow! pfcmpeq */
7232 case 0xb4: /* 3DNow! pfmul */
7233 case 0xb6: /* 3DNow! pfrcpit2 */
7234 case 0xb7: /* 3DNow! pmulhrw */
7235 case 0xbb: /* 3DNow! pswapd */
7236 case 0xbf: /* 3DNow! pavgusb */
7237 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7238 goto no_support_3dnow_data
;
7239 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7243 no_support_3dnow_data
:
7244 opcode
= (opcode
<< 8) | opcode8
;
7250 case 0x0faa: /* rsm */
7251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7252 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7254 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7256 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7257 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7263 if (i386_record_modrm (&ir
))
7267 case 0: /* fxsave */
7271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7272 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7274 if (record_full_arch_list_add_mem (tmpu64
, 512))
7279 case 1: /* fxrstor */
7283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7285 for (i
= I387_MM0_REGNUM (tdep
);
7286 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7287 record_full_arch_list_add_reg (ir
.regcache
, i
);
7289 for (i
= I387_XMM0_REGNUM (tdep
);
7290 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7291 record_full_arch_list_add_reg (ir
.regcache
, i
);
7293 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7294 record_full_arch_list_add_reg (ir
.regcache
,
7295 I387_MXCSR_REGNUM(tdep
));
7297 for (i
= I387_ST0_REGNUM (tdep
);
7298 i386_fp_regnum_p (gdbarch
, i
); i
++)
7299 record_full_arch_list_add_reg (ir
.regcache
, i
);
7301 for (i
= I387_FCTRL_REGNUM (tdep
);
7302 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7303 record_full_arch_list_add_reg (ir
.regcache
, i
);
7307 case 2: /* ldmxcsr */
7308 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7310 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7313 case 3: /* stmxcsr */
7315 if (i386_record_lea_modrm (&ir
))
7319 case 5: /* lfence */
7320 case 6: /* mfence */
7321 case 7: /* sfence clflush */
7325 opcode
= (opcode
<< 8) | ir
.modrm
;
7331 case 0x0fc3: /* movnti */
7332 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7333 if (i386_record_modrm (&ir
))
7338 if (i386_record_lea_modrm (&ir
))
7342 /* Add prefix to opcode. */
7457 /* Mask out PREFIX_ADDR. */
7458 switch ((prefixes
& ~PREFIX_ADDR
))
7470 reswitch_prefix_add
:
7478 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7481 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7482 goto reswitch_prefix_add
;
7485 case 0x0f10: /* movups */
7486 case 0x660f10: /* movupd */
7487 case 0xf30f10: /* movss */
7488 case 0xf20f10: /* movsd */
7489 case 0x0f12: /* movlps */
7490 case 0x660f12: /* movlpd */
7491 case 0xf30f12: /* movsldup */
7492 case 0xf20f12: /* movddup */
7493 case 0x0f14: /* unpcklps */
7494 case 0x660f14: /* unpcklpd */
7495 case 0x0f15: /* unpckhps */
7496 case 0x660f15: /* unpckhpd */
7497 case 0x0f16: /* movhps */
7498 case 0x660f16: /* movhpd */
7499 case 0xf30f16: /* movshdup */
7500 case 0x0f28: /* movaps */
7501 case 0x660f28: /* movapd */
7502 case 0x0f2a: /* cvtpi2ps */
7503 case 0x660f2a: /* cvtpi2pd */
7504 case 0xf30f2a: /* cvtsi2ss */
7505 case 0xf20f2a: /* cvtsi2sd */
7506 case 0x0f2c: /* cvttps2pi */
7507 case 0x660f2c: /* cvttpd2pi */
7508 case 0x0f2d: /* cvtps2pi */
7509 case 0x660f2d: /* cvtpd2pi */
7510 case 0x660f3800: /* pshufb */
7511 case 0x660f3801: /* phaddw */
7512 case 0x660f3802: /* phaddd */
7513 case 0x660f3803: /* phaddsw */
7514 case 0x660f3804: /* pmaddubsw */
7515 case 0x660f3805: /* phsubw */
7516 case 0x660f3806: /* phsubd */
7517 case 0x660f3807: /* phsubsw */
7518 case 0x660f3808: /* psignb */
7519 case 0x660f3809: /* psignw */
7520 case 0x660f380a: /* psignd */
7521 case 0x660f380b: /* pmulhrsw */
7522 case 0x660f3810: /* pblendvb */
7523 case 0x660f3814: /* blendvps */
7524 case 0x660f3815: /* blendvpd */
7525 case 0x660f381c: /* pabsb */
7526 case 0x660f381d: /* pabsw */
7527 case 0x660f381e: /* pabsd */
7528 case 0x660f3820: /* pmovsxbw */
7529 case 0x660f3821: /* pmovsxbd */
7530 case 0x660f3822: /* pmovsxbq */
7531 case 0x660f3823: /* pmovsxwd */
7532 case 0x660f3824: /* pmovsxwq */
7533 case 0x660f3825: /* pmovsxdq */
7534 case 0x660f3828: /* pmuldq */
7535 case 0x660f3829: /* pcmpeqq */
7536 case 0x660f382a: /* movntdqa */
7537 case 0x660f3a08: /* roundps */
7538 case 0x660f3a09: /* roundpd */
7539 case 0x660f3a0a: /* roundss */
7540 case 0x660f3a0b: /* roundsd */
7541 case 0x660f3a0c: /* blendps */
7542 case 0x660f3a0d: /* blendpd */
7543 case 0x660f3a0e: /* pblendw */
7544 case 0x660f3a0f: /* palignr */
7545 case 0x660f3a20: /* pinsrb */
7546 case 0x660f3a21: /* insertps */
7547 case 0x660f3a22: /* pinsrd pinsrq */
7548 case 0x660f3a40: /* dpps */
7549 case 0x660f3a41: /* dppd */
7550 case 0x660f3a42: /* mpsadbw */
7551 case 0x660f3a60: /* pcmpestrm */
7552 case 0x660f3a61: /* pcmpestri */
7553 case 0x660f3a62: /* pcmpistrm */
7554 case 0x660f3a63: /* pcmpistri */
7555 case 0x0f51: /* sqrtps */
7556 case 0x660f51: /* sqrtpd */
7557 case 0xf20f51: /* sqrtsd */
7558 case 0xf30f51: /* sqrtss */
7559 case 0x0f52: /* rsqrtps */
7560 case 0xf30f52: /* rsqrtss */
7561 case 0x0f53: /* rcpps */
7562 case 0xf30f53: /* rcpss */
7563 case 0x0f54: /* andps */
7564 case 0x660f54: /* andpd */
7565 case 0x0f55: /* andnps */
7566 case 0x660f55: /* andnpd */
7567 case 0x0f56: /* orps */
7568 case 0x660f56: /* orpd */
7569 case 0x0f57: /* xorps */
7570 case 0x660f57: /* xorpd */
7571 case 0x0f58: /* addps */
7572 case 0x660f58: /* addpd */
7573 case 0xf20f58: /* addsd */
7574 case 0xf30f58: /* addss */
7575 case 0x0f59: /* mulps */
7576 case 0x660f59: /* mulpd */
7577 case 0xf20f59: /* mulsd */
7578 case 0xf30f59: /* mulss */
7579 case 0x0f5a: /* cvtps2pd */
7580 case 0x660f5a: /* cvtpd2ps */
7581 case 0xf20f5a: /* cvtsd2ss */
7582 case 0xf30f5a: /* cvtss2sd */
7583 case 0x0f5b: /* cvtdq2ps */
7584 case 0x660f5b: /* cvtps2dq */
7585 case 0xf30f5b: /* cvttps2dq */
7586 case 0x0f5c: /* subps */
7587 case 0x660f5c: /* subpd */
7588 case 0xf20f5c: /* subsd */
7589 case 0xf30f5c: /* subss */
7590 case 0x0f5d: /* minps */
7591 case 0x660f5d: /* minpd */
7592 case 0xf20f5d: /* minsd */
7593 case 0xf30f5d: /* minss */
7594 case 0x0f5e: /* divps */
7595 case 0x660f5e: /* divpd */
7596 case 0xf20f5e: /* divsd */
7597 case 0xf30f5e: /* divss */
7598 case 0x0f5f: /* maxps */
7599 case 0x660f5f: /* maxpd */
7600 case 0xf20f5f: /* maxsd */
7601 case 0xf30f5f: /* maxss */
7602 case 0x660f60: /* punpcklbw */
7603 case 0x660f61: /* punpcklwd */
7604 case 0x660f62: /* punpckldq */
7605 case 0x660f63: /* packsswb */
7606 case 0x660f64: /* pcmpgtb */
7607 case 0x660f65: /* pcmpgtw */
7608 case 0x660f66: /* pcmpgtd */
7609 case 0x660f67: /* packuswb */
7610 case 0x660f68: /* punpckhbw */
7611 case 0x660f69: /* punpckhwd */
7612 case 0x660f6a: /* punpckhdq */
7613 case 0x660f6b: /* packssdw */
7614 case 0x660f6c: /* punpcklqdq */
7615 case 0x660f6d: /* punpckhqdq */
7616 case 0x660f6e: /* movd */
7617 case 0x660f6f: /* movdqa */
7618 case 0xf30f6f: /* movdqu */
7619 case 0x660f70: /* pshufd */
7620 case 0xf20f70: /* pshuflw */
7621 case 0xf30f70: /* pshufhw */
7622 case 0x660f74: /* pcmpeqb */
7623 case 0x660f75: /* pcmpeqw */
7624 case 0x660f76: /* pcmpeqd */
7625 case 0x660f7c: /* haddpd */
7626 case 0xf20f7c: /* haddps */
7627 case 0x660f7d: /* hsubpd */
7628 case 0xf20f7d: /* hsubps */
7629 case 0xf30f7e: /* movq */
7630 case 0x0fc2: /* cmpps */
7631 case 0x660fc2: /* cmppd */
7632 case 0xf20fc2: /* cmpsd */
7633 case 0xf30fc2: /* cmpss */
7634 case 0x660fc4: /* pinsrw */
7635 case 0x0fc6: /* shufps */
7636 case 0x660fc6: /* shufpd */
7637 case 0x660fd0: /* addsubpd */
7638 case 0xf20fd0: /* addsubps */
7639 case 0x660fd1: /* psrlw */
7640 case 0x660fd2: /* psrld */
7641 case 0x660fd3: /* psrlq */
7642 case 0x660fd4: /* paddq */
7643 case 0x660fd5: /* pmullw */
7644 case 0xf30fd6: /* movq2dq */
7645 case 0x660fd8: /* psubusb */
7646 case 0x660fd9: /* psubusw */
7647 case 0x660fda: /* pminub */
7648 case 0x660fdb: /* pand */
7649 case 0x660fdc: /* paddusb */
7650 case 0x660fdd: /* paddusw */
7651 case 0x660fde: /* pmaxub */
7652 case 0x660fdf: /* pandn */
7653 case 0x660fe0: /* pavgb */
7654 case 0x660fe1: /* psraw */
7655 case 0x660fe2: /* psrad */
7656 case 0x660fe3: /* pavgw */
7657 case 0x660fe4: /* pmulhuw */
7658 case 0x660fe5: /* pmulhw */
7659 case 0x660fe6: /* cvttpd2dq */
7660 case 0xf20fe6: /* cvtpd2dq */
7661 case 0xf30fe6: /* cvtdq2pd */
7662 case 0x660fe8: /* psubsb */
7663 case 0x660fe9: /* psubsw */
7664 case 0x660fea: /* pminsw */
7665 case 0x660feb: /* por */
7666 case 0x660fec: /* paddsb */
7667 case 0x660fed: /* paddsw */
7668 case 0x660fee: /* pmaxsw */
7669 case 0x660fef: /* pxor */
7670 case 0xf20ff0: /* lddqu */
7671 case 0x660ff1: /* psllw */
7672 case 0x660ff2: /* pslld */
7673 case 0x660ff3: /* psllq */
7674 case 0x660ff4: /* pmuludq */
7675 case 0x660ff5: /* pmaddwd */
7676 case 0x660ff6: /* psadbw */
7677 case 0x660ff8: /* psubb */
7678 case 0x660ff9: /* psubw */
7679 case 0x660ffa: /* psubd */
7680 case 0x660ffb: /* psubq */
7681 case 0x660ffc: /* paddb */
7682 case 0x660ffd: /* paddw */
7683 case 0x660ffe: /* paddd */
7684 if (i386_record_modrm (&ir
))
7687 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7689 record_full_arch_list_add_reg (ir
.regcache
,
7690 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7691 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7695 case 0x0f11: /* movups */
7696 case 0x660f11: /* movupd */
7697 case 0xf30f11: /* movss */
7698 case 0xf20f11: /* movsd */
7699 case 0x0f13: /* movlps */
7700 case 0x660f13: /* movlpd */
7701 case 0x0f17: /* movhps */
7702 case 0x660f17: /* movhpd */
7703 case 0x0f29: /* movaps */
7704 case 0x660f29: /* movapd */
7705 case 0x660f3a14: /* pextrb */
7706 case 0x660f3a15: /* pextrw */
7707 case 0x660f3a16: /* pextrd pextrq */
7708 case 0x660f3a17: /* extractps */
7709 case 0x660f7f: /* movdqa */
7710 case 0xf30f7f: /* movdqu */
7711 if (i386_record_modrm (&ir
))
7715 if (opcode
== 0x0f13 || opcode
== 0x660f13
7716 || opcode
== 0x0f17 || opcode
== 0x660f17)
7719 if (!i386_xmm_regnum_p (gdbarch
,
7720 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7722 record_full_arch_list_add_reg (ir
.regcache
,
7723 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7745 if (i386_record_lea_modrm (&ir
))
7750 case 0x0f2b: /* movntps */
7751 case 0x660f2b: /* movntpd */
7752 case 0x0fe7: /* movntq */
7753 case 0x660fe7: /* movntdq */
7756 if (opcode
== 0x0fe7)
7760 if (i386_record_lea_modrm (&ir
))
7764 case 0xf30f2c: /* cvttss2si */
7765 case 0xf20f2c: /* cvttsd2si */
7766 case 0xf30f2d: /* cvtss2si */
7767 case 0xf20f2d: /* cvtsd2si */
7768 case 0xf20f38f0: /* crc32 */
7769 case 0xf20f38f1: /* crc32 */
7770 case 0x0f50: /* movmskps */
7771 case 0x660f50: /* movmskpd */
7772 case 0x0fc5: /* pextrw */
7773 case 0x660fc5: /* pextrw */
7774 case 0x0fd7: /* pmovmskb */
7775 case 0x660fd7: /* pmovmskb */
7776 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7779 case 0x0f3800: /* pshufb */
7780 case 0x0f3801: /* phaddw */
7781 case 0x0f3802: /* phaddd */
7782 case 0x0f3803: /* phaddsw */
7783 case 0x0f3804: /* pmaddubsw */
7784 case 0x0f3805: /* phsubw */
7785 case 0x0f3806: /* phsubd */
7786 case 0x0f3807: /* phsubsw */
7787 case 0x0f3808: /* psignb */
7788 case 0x0f3809: /* psignw */
7789 case 0x0f380a: /* psignd */
7790 case 0x0f380b: /* pmulhrsw */
7791 case 0x0f381c: /* pabsb */
7792 case 0x0f381d: /* pabsw */
7793 case 0x0f381e: /* pabsd */
7794 case 0x0f382b: /* packusdw */
7795 case 0x0f3830: /* pmovzxbw */
7796 case 0x0f3831: /* pmovzxbd */
7797 case 0x0f3832: /* pmovzxbq */
7798 case 0x0f3833: /* pmovzxwd */
7799 case 0x0f3834: /* pmovzxwq */
7800 case 0x0f3835: /* pmovzxdq */
7801 case 0x0f3837: /* pcmpgtq */
7802 case 0x0f3838: /* pminsb */
7803 case 0x0f3839: /* pminsd */
7804 case 0x0f383a: /* pminuw */
7805 case 0x0f383b: /* pminud */
7806 case 0x0f383c: /* pmaxsb */
7807 case 0x0f383d: /* pmaxsd */
7808 case 0x0f383e: /* pmaxuw */
7809 case 0x0f383f: /* pmaxud */
7810 case 0x0f3840: /* pmulld */
7811 case 0x0f3841: /* phminposuw */
7812 case 0x0f3a0f: /* palignr */
7813 case 0x0f60: /* punpcklbw */
7814 case 0x0f61: /* punpcklwd */
7815 case 0x0f62: /* punpckldq */
7816 case 0x0f63: /* packsswb */
7817 case 0x0f64: /* pcmpgtb */
7818 case 0x0f65: /* pcmpgtw */
7819 case 0x0f66: /* pcmpgtd */
7820 case 0x0f67: /* packuswb */
7821 case 0x0f68: /* punpckhbw */
7822 case 0x0f69: /* punpckhwd */
7823 case 0x0f6a: /* punpckhdq */
7824 case 0x0f6b: /* packssdw */
7825 case 0x0f6e: /* movd */
7826 case 0x0f6f: /* movq */
7827 case 0x0f70: /* pshufw */
7828 case 0x0f74: /* pcmpeqb */
7829 case 0x0f75: /* pcmpeqw */
7830 case 0x0f76: /* pcmpeqd */
7831 case 0x0fc4: /* pinsrw */
7832 case 0x0fd1: /* psrlw */
7833 case 0x0fd2: /* psrld */
7834 case 0x0fd3: /* psrlq */
7835 case 0x0fd4: /* paddq */
7836 case 0x0fd5: /* pmullw */
7837 case 0xf20fd6: /* movdq2q */
7838 case 0x0fd8: /* psubusb */
7839 case 0x0fd9: /* psubusw */
7840 case 0x0fda: /* pminub */
7841 case 0x0fdb: /* pand */
7842 case 0x0fdc: /* paddusb */
7843 case 0x0fdd: /* paddusw */
7844 case 0x0fde: /* pmaxub */
7845 case 0x0fdf: /* pandn */
7846 case 0x0fe0: /* pavgb */
7847 case 0x0fe1: /* psraw */
7848 case 0x0fe2: /* psrad */
7849 case 0x0fe3: /* pavgw */
7850 case 0x0fe4: /* pmulhuw */
7851 case 0x0fe5: /* pmulhw */
7852 case 0x0fe8: /* psubsb */
7853 case 0x0fe9: /* psubsw */
7854 case 0x0fea: /* pminsw */
7855 case 0x0feb: /* por */
7856 case 0x0fec: /* paddsb */
7857 case 0x0fed: /* paddsw */
7858 case 0x0fee: /* pmaxsw */
7859 case 0x0fef: /* pxor */
7860 case 0x0ff1: /* psllw */
7861 case 0x0ff2: /* pslld */
7862 case 0x0ff3: /* psllq */
7863 case 0x0ff4: /* pmuludq */
7864 case 0x0ff5: /* pmaddwd */
7865 case 0x0ff6: /* psadbw */
7866 case 0x0ff8: /* psubb */
7867 case 0x0ff9: /* psubw */
7868 case 0x0ffa: /* psubd */
7869 case 0x0ffb: /* psubq */
7870 case 0x0ffc: /* paddb */
7871 case 0x0ffd: /* paddw */
7872 case 0x0ffe: /* paddd */
7873 if (i386_record_modrm (&ir
))
7875 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7877 record_full_arch_list_add_reg (ir
.regcache
,
7878 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7881 case 0x0f71: /* psllw */
7882 case 0x0f72: /* pslld */
7883 case 0x0f73: /* psllq */
7884 if (i386_record_modrm (&ir
))
7886 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7888 record_full_arch_list_add_reg (ir
.regcache
,
7889 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7892 case 0x660f71: /* psllw */
7893 case 0x660f72: /* pslld */
7894 case 0x660f73: /* psllq */
7895 if (i386_record_modrm (&ir
))
7898 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7900 record_full_arch_list_add_reg (ir
.regcache
,
7901 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7904 case 0x0f7e: /* movd */
7905 case 0x660f7e: /* movd */
7906 if (i386_record_modrm (&ir
))
7909 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7916 if (i386_record_lea_modrm (&ir
))
7921 case 0x0f7f: /* movq */
7922 if (i386_record_modrm (&ir
))
7926 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7928 record_full_arch_list_add_reg (ir
.regcache
,
7929 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7934 if (i386_record_lea_modrm (&ir
))
7939 case 0xf30fb8: /* popcnt */
7940 if (i386_record_modrm (&ir
))
7942 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7946 case 0x660fd6: /* movq */
7947 if (i386_record_modrm (&ir
))
7952 if (!i386_xmm_regnum_p (gdbarch
,
7953 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7955 record_full_arch_list_add_reg (ir
.regcache
,
7956 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7961 if (i386_record_lea_modrm (&ir
))
7966 case 0x660f3817: /* ptest */
7967 case 0x0f2e: /* ucomiss */
7968 case 0x660f2e: /* ucomisd */
7969 case 0x0f2f: /* comiss */
7970 case 0x660f2f: /* comisd */
7971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7974 case 0x0ff7: /* maskmovq */
7975 regcache_raw_read_unsigned (ir
.regcache
,
7976 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7978 if (record_full_arch_list_add_mem (addr
, 64))
7982 case 0x660ff7: /* maskmovdqu */
7983 regcache_raw_read_unsigned (ir
.regcache
,
7984 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7986 if (record_full_arch_list_add_mem (addr
, 128))
8001 /* In the future, maybe still need to deal with need_dasm. */
8002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8003 if (record_full_arch_list_add_end ())
8009 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8010 "at address %s.\n"),
8011 (unsigned int) (opcode
),
8012 paddress (gdbarch
, ir
.orig_addr
));
8016 static const int i386_record_regmap
[] =
8018 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8019 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8020 0, 0, 0, 0, 0, 0, 0, 0,
8021 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8022 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8025 /* Check that the given address appears suitable for a fast
8026 tracepoint, which on x86-64 means that we need an instruction of at
8027 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8028 jump and not have to worry about program jumps to an address in the
8029 middle of the tracepoint jump. On x86, it may be possible to use
8030 4-byte jumps with a 2-byte offset to a trampoline located in the
8031 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8032 of instruction to replace, and 0 if not, plus an explanatory
8036 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
8037 CORE_ADDR addr
, int *isize
, char **msg
)
8040 static struct ui_file
*gdb_null
= NULL
;
8042 /* Ask the target for the minimum instruction length supported. */
8043 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8047 /* If the target does not support the get_min_fast_tracepoint_insn_len
8048 operation, assume that fast tracepoints will always be implemented
8049 using 4-byte relative jumps on both x86 and x86-64. */
8052 else if (jumplen
== 0)
8054 /* If the target does support get_min_fast_tracepoint_insn_len but
8055 returns zero, then the IPA has not loaded yet. In this case,
8056 we optimistically assume that truncated 2-byte relative jumps
8057 will be available on x86, and compensate later if this assumption
8058 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8059 jumps will always be used. */
8060 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8063 /* Dummy file descriptor for the disassembler. */
8065 gdb_null
= ui_file_new ();
8067 /* Check for fit. */
8068 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
8074 /* Return a bit of target-specific detail to add to the caller's
8075 generic failure message. */
8077 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
8078 "need at least %d bytes for the jump"),
8091 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8092 struct tdesc_arch_data
*tdesc_data
)
8094 const struct target_desc
*tdesc
= tdep
->tdesc
;
8095 const struct tdesc_feature
*feature_core
;
8097 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8099 int i
, num_regs
, valid_p
;
8101 if (! tdesc_has_registers (tdesc
))
8104 /* Get core registers. */
8105 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8106 if (feature_core
== NULL
)
8109 /* Get SSE registers. */
8110 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8112 /* Try AVX registers. */
8113 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8115 /* Try MPX registers. */
8116 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8118 /* Try AVX512 registers. */
8119 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8123 /* The XCR0 bits. */
8126 /* AVX512 register description requires AVX register description. */
8130 tdep
->xcr0
= X86_XSTATE_MPX_AVX512_MASK
;
8132 /* It may have been set by OSABI initialization function. */
8133 if (tdep
->k0_regnum
< 0)
8135 tdep
->k_register_names
= i386_k_names
;
8136 tdep
->k0_regnum
= I386_K0_REGNUM
;
8139 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8140 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8141 tdep
->k0_regnum
+ i
,
8144 if (tdep
->num_zmm_regs
== 0)
8146 tdep
->zmmh_register_names
= i386_zmmh_names
;
8147 tdep
->num_zmm_regs
= 8;
8148 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8151 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8152 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8153 tdep
->zmm0h_regnum
+ i
,
8154 tdep
->zmmh_register_names
[i
]);
8156 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8157 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8158 tdep
->xmm16_regnum
+ i
,
8159 tdep
->xmm_avx512_register_names
[i
]);
8161 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8162 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8163 tdep
->ymm16h_regnum
+ i
,
8164 tdep
->ymm16h_register_names
[i
]);
8168 /* AVX register description requires SSE register description. */
8172 if (!feature_avx512
)
8173 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8175 /* It may have been set by OSABI initialization function. */
8176 if (tdep
->num_ymm_regs
== 0)
8178 tdep
->ymmh_register_names
= i386_ymmh_names
;
8179 tdep
->num_ymm_regs
= 8;
8180 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8183 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8184 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8185 tdep
->ymm0h_regnum
+ i
,
8186 tdep
->ymmh_register_names
[i
]);
8188 else if (feature_sse
)
8189 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8192 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8193 tdep
->num_xmm_regs
= 0;
8196 num_regs
= tdep
->num_core_regs
;
8197 for (i
= 0; i
< num_regs
; i
++)
8198 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8199 tdep
->register_names
[i
]);
8203 /* Need to include %mxcsr, so add one. */
8204 num_regs
+= tdep
->num_xmm_regs
+ 1;
8205 for (; i
< num_regs
; i
++)
8206 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8207 tdep
->register_names
[i
]);
8212 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8214 if (tdep
->bnd0r_regnum
< 0)
8216 tdep
->mpx_register_names
= i386_mpx_names
;
8217 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8218 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8221 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8222 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8223 I387_BND0R_REGNUM (tdep
) + i
,
8224 tdep
->mpx_register_names
[i
]);
8231 static struct gdbarch
*
8232 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8234 struct gdbarch_tdep
*tdep
;
8235 struct gdbarch
*gdbarch
;
8236 struct tdesc_arch_data
*tdesc_data
;
8237 const struct target_desc
*tdesc
;
8245 /* If there is already a candidate, use it. */
8246 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8248 return arches
->gdbarch
;
8250 /* Allocate space for the new architecture. */
8251 tdep
= XCNEW (struct gdbarch_tdep
);
8252 gdbarch
= gdbarch_alloc (&info
, tdep
);
8254 /* General-purpose registers. */
8255 tdep
->gregset_reg_offset
= NULL
;
8256 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8257 tdep
->sizeof_gregset
= 0;
8259 /* Floating-point registers. */
8260 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8261 tdep
->fpregset
= &i386_fpregset
;
8263 /* The default settings include the FPU registers, the MMX registers
8264 and the SSE registers. This can be overridden for a specific ABI
8265 by adjusting the members `st0_regnum', `mm0_regnum' and
8266 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8267 will show up in the output of "info all-registers". */
8269 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8271 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8272 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8274 tdep
->jb_pc_offset
= -1;
8275 tdep
->struct_return
= pcc_struct_return
;
8276 tdep
->sigtramp_start
= 0;
8277 tdep
->sigtramp_end
= 0;
8278 tdep
->sigtramp_p
= i386_sigtramp_p
;
8279 tdep
->sigcontext_addr
= NULL
;
8280 tdep
->sc_reg_offset
= NULL
;
8281 tdep
->sc_pc_offset
= -1;
8282 tdep
->sc_sp_offset
= -1;
8284 tdep
->xsave_xcr0_offset
= -1;
8286 tdep
->record_regmap
= i386_record_regmap
;
8288 set_gdbarch_long_long_align_bit (gdbarch
, 32);
8290 /* The format used for `long double' on almost all i386 targets is
8291 the i387 extended floating-point format. In fact, of all targets
8292 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8293 on having a `long double' that's not `long' at all. */
8294 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8296 /* Although the i387 extended floating-point has only 80 significant
8297 bits, a `long double' actually takes up 96, probably to enforce
8299 set_gdbarch_long_double_bit (gdbarch
, 96);
8301 /* Register numbers of various important registers. */
8302 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8303 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8304 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8305 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8307 /* NOTE: kettenis/20040418: GCC does have two possible register
8308 numbering schemes on the i386: dbx and SVR4. These schemes
8309 differ in how they number %ebp, %esp, %eflags, and the
8310 floating-point registers, and are implemented by the arrays
8311 dbx_register_map[] and svr4_dbx_register_map in
8312 gcc/config/i386.c. GCC also defines a third numbering scheme in
8313 gcc/config/i386.c, which it designates as the "default" register
8314 map used in 64bit mode. This last register numbering scheme is
8315 implemented in dbx64_register_map, and is used for AMD64; see
8318 Currently, each GCC i386 target always uses the same register
8319 numbering scheme across all its supported debugging formats
8320 i.e. SDB (COFF), stabs and DWARF 2. This is because
8321 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8322 DBX_REGISTER_NUMBER macro which is defined by each target's
8323 respective config header in a manner independent of the requested
8324 output debugging format.
8326 This does not match the arrangement below, which presumes that
8327 the SDB and stabs numbering schemes differ from the DWARF and
8328 DWARF 2 ones. The reason for this arrangement is that it is
8329 likely to get the numbering scheme for the target's
8330 default/native debug format right. For targets where GCC is the
8331 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8332 targets where the native toolchain uses a different numbering
8333 scheme for a particular debug format (stabs-in-ELF on Solaris)
8334 the defaults below will have to be overridden, like
8335 i386_elf_init_abi() does. */
8337 /* Use the dbx register numbering scheme for stabs and COFF. */
8338 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8339 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8341 /* Use the SVR4 register numbering scheme for DWARF 2. */
8342 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
8344 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8345 be in use on any of the supported i386 targets. */
8347 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8349 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8351 /* Call dummy code. */
8352 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8353 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8354 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8355 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8357 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8358 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8359 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8361 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8363 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8365 /* Stack grows downward. */
8366 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8368 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
8369 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8370 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8372 set_gdbarch_frame_args_skip (gdbarch
, 8);
8374 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8376 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8378 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8380 /* Add the i386 register groups. */
8381 i386_add_reggroups (gdbarch
);
8382 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8384 /* Helper for function argument information. */
8385 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8387 /* Hook the function epilogue frame unwinder. This unwinder is
8388 appended to the list first, so that it supercedes the DWARF
8389 unwinder in function epilogues (where the DWARF unwinder
8390 currently fails). */
8391 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8393 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8394 to the list before the prologue-based unwinders, so that DWARF
8395 CFI info will be used if it is available. */
8396 dwarf2_append_unwinders (gdbarch
);
8398 frame_base_set_default (gdbarch
, &i386_frame_base
);
8400 /* Pseudo registers may be changed by amd64_init_abi. */
8401 set_gdbarch_pseudo_register_read_value (gdbarch
,
8402 i386_pseudo_register_read_value
);
8403 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8405 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8406 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8408 /* Override the normal target description method to make the AVX
8409 upper halves anonymous. */
8410 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8412 /* Even though the default ABI only includes general-purpose registers,
8413 floating-point registers and the SSE registers, we have to leave a
8414 gap for the upper AVX, MPX and AVX512 registers. */
8415 set_gdbarch_num_regs (gdbarch
, I386_AVX512_NUM_REGS
);
8417 /* Get the x86 target description from INFO. */
8418 tdesc
= info
.target_desc
;
8419 if (! tdesc_has_registers (tdesc
))
8421 tdep
->tdesc
= tdesc
;
8423 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8424 tdep
->register_names
= i386_register_names
;
8426 /* No upper YMM registers. */
8427 tdep
->ymmh_register_names
= NULL
;
8428 tdep
->ymm0h_regnum
= -1;
8430 /* No upper ZMM registers. */
8431 tdep
->zmmh_register_names
= NULL
;
8432 tdep
->zmm0h_regnum
= -1;
8434 /* No high XMM registers. */
8435 tdep
->xmm_avx512_register_names
= NULL
;
8436 tdep
->xmm16_regnum
= -1;
8438 /* No upper YMM16-31 registers. */
8439 tdep
->ymm16h_register_names
= NULL
;
8440 tdep
->ymm16h_regnum
= -1;
8442 tdep
->num_byte_regs
= 8;
8443 tdep
->num_word_regs
= 8;
8444 tdep
->num_dword_regs
= 0;
8445 tdep
->num_mmx_regs
= 8;
8446 tdep
->num_ymm_regs
= 0;
8448 /* No MPX registers. */
8449 tdep
->bnd0r_regnum
= -1;
8450 tdep
->bndcfgu_regnum
= -1;
8452 /* No AVX512 registers. */
8453 tdep
->k0_regnum
= -1;
8454 tdep
->num_zmm_regs
= 0;
8455 tdep
->num_ymm_avx512_regs
= 0;
8456 tdep
->num_xmm_avx512_regs
= 0;
8458 tdesc_data
= tdesc_data_alloc ();
8460 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8462 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8464 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8465 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8466 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8468 /* Hook in ABI-specific overrides, if they have been registered. */
8469 info
.tdep_info
= (void *) tdesc_data
;
8470 gdbarch_init_osabi (info
, gdbarch
);
8472 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8474 tdesc_data_cleanup (tdesc_data
);
8476 gdbarch_free (gdbarch
);
8480 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8482 /* Wire in pseudo registers. Number of pseudo registers may be
8484 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8485 + tdep
->num_word_regs
8486 + tdep
->num_dword_regs
8487 + tdep
->num_mmx_regs
8488 + tdep
->num_ymm_regs
8490 + tdep
->num_ymm_avx512_regs
8491 + tdep
->num_zmm_regs
));
8493 /* Target description may be changed. */
8494 tdesc
= tdep
->tdesc
;
8496 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8498 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8499 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8501 /* Make %al the first pseudo-register. */
8502 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8503 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8505 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8506 if (tdep
->num_dword_regs
)
8508 /* Support dword pseudo-register if it hasn't been disabled. */
8509 tdep
->eax_regnum
= ymm0_regnum
;
8510 ymm0_regnum
+= tdep
->num_dword_regs
;
8513 tdep
->eax_regnum
= -1;
8515 mm0_regnum
= ymm0_regnum
;
8516 if (tdep
->num_ymm_regs
)
8518 /* Support YMM pseudo-register if it is available. */
8519 tdep
->ymm0_regnum
= ymm0_regnum
;
8520 mm0_regnum
+= tdep
->num_ymm_regs
;
8523 tdep
->ymm0_regnum
= -1;
8525 if (tdep
->num_ymm_avx512_regs
)
8527 /* Support YMM16-31 pseudo registers if available. */
8528 tdep
->ymm16_regnum
= mm0_regnum
;
8529 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8532 tdep
->ymm16_regnum
= -1;
8534 if (tdep
->num_zmm_regs
)
8536 /* Support ZMM pseudo-register if it is available. */
8537 tdep
->zmm0_regnum
= mm0_regnum
;
8538 mm0_regnum
+= tdep
->num_zmm_regs
;
8541 tdep
->zmm0_regnum
= -1;
8543 bnd0_regnum
= mm0_regnum
;
8544 if (tdep
->num_mmx_regs
!= 0)
8546 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8547 tdep
->mm0_regnum
= mm0_regnum
;
8548 bnd0_regnum
+= tdep
->num_mmx_regs
;
8551 tdep
->mm0_regnum
= -1;
8553 if (tdep
->bnd0r_regnum
> 0)
8554 tdep
->bnd0_regnum
= bnd0_regnum
;
8556 tdep
-> bnd0_regnum
= -1;
8558 /* Hook in the legacy prologue-based unwinders last (fallback). */
8559 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8560 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8561 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8563 /* If we have a register mapping, enable the generic core file
8564 support, unless it has already been enabled. */
8565 if (tdep
->gregset_reg_offset
8566 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8567 set_gdbarch_iterate_over_regset_sections
8568 (gdbarch
, i386_iterate_over_regset_sections
);
8570 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
8571 i386_skip_permanent_breakpoint
);
8573 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8574 i386_fast_tracepoint_valid_at
);
8579 static enum gdb_osabi
8580 i386_coff_osabi_sniffer (bfd
*abfd
)
8582 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8583 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8584 return GDB_OSABI_GO32
;
8586 return GDB_OSABI_UNKNOWN
;
8590 /* Provide a prototype to silence -Wmissing-prototypes. */
8591 void _initialize_i386_tdep (void);
8594 _initialize_i386_tdep (void)
8596 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8598 /* Add the variable that controls the disassembly flavor. */
8599 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8600 &disassembly_flavor
, _("\
8601 Set the disassembly flavor."), _("\
8602 Show the disassembly flavor."), _("\
8603 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8605 NULL
, /* FIXME: i18n: */
8606 &setlist
, &showlist
);
8608 /* Add the variable that controls the convention for returning
8610 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
8611 &struct_convention
, _("\
8612 Set the convention for returning small structs."), _("\
8613 Show the convention for returning small structs."), _("\
8614 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8617 NULL
, /* FIXME: i18n: */
8618 &setlist
, &showlist
);
8620 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
8621 i386_coff_osabi_sniffer
);
8623 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
8624 i386_svr4_init_abi
);
8625 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
8626 i386_go32_init_abi
);
8628 /* Initialize the i386-specific register groups. */
8629 i386_init_reggroups ();
8631 /* Initialize the standard target descriptions. */
8632 initialize_tdesc_i386 ();
8633 initialize_tdesc_i386_mmx ();
8634 initialize_tdesc_i386_avx ();
8635 initialize_tdesc_i386_mpx ();
8636 initialize_tdesc_i386_avx512 ();
8638 /* Tell remote stub that we support XML target description. */
8639 register_remote_support_xml ("i386");