1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
55 #include "features/i386/i386.c"
56 #include "features/i386/i386-avx.c"
57 #include "features/i386/i386-mpx.c"
58 #include "features/i386/i386-avx512.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_zmm_names
[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char *i386_zmmh_names
[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char *i386_k_names
[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char *i386_ymm_names
[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char *i386_ymmh_names
[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char *i386_mpx_names
[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 /* Register names for MPX pseudo-registers. */
125 static const char *i386_bnd_names
[] =
127 "bnd0", "bnd1", "bnd2", "bnd3"
130 /* Register names for MMX pseudo-registers. */
132 static const char *i386_mmx_names
[] =
134 "mm0", "mm1", "mm2", "mm3",
135 "mm4", "mm5", "mm6", "mm7"
138 /* Register names for byte pseudo-registers. */
140 static const char *i386_byte_names
[] =
142 "al", "cl", "dl", "bl",
143 "ah", "ch", "dh", "bh"
146 /* Register names for word pseudo-registers. */
148 static const char *i386_word_names
[] =
150 "ax", "cx", "dx", "bx",
154 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
155 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
156 we have 16 upper ZMM regs that have to be handled differently. */
158 const int num_lower_zmm_regs
= 16;
163 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
166 int mm0_regnum
= tdep
->mm0_regnum
;
171 regnum
-= mm0_regnum
;
172 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
178 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 regnum
-= tdep
->al_regnum
;
183 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
189 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
193 regnum
-= tdep
->ax_regnum
;
194 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
197 /* Dword register? */
200 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
203 int eax_regnum
= tdep
->eax_regnum
;
208 regnum
-= eax_regnum
;
209 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
212 /* AVX512 register? */
215 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
218 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
220 if (zmm0h_regnum
< 0)
223 regnum
-= zmm0h_regnum
;
224 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
228 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
231 int zmm0_regnum
= tdep
->zmm0_regnum
;
236 regnum
-= zmm0_regnum
;
237 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
241 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
244 int k0_regnum
= tdep
->k0_regnum
;
250 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
254 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
257 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
259 if (ymm0h_regnum
< 0)
262 regnum
-= ymm0h_regnum
;
263 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
269 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
272 int ymm0_regnum
= tdep
->ymm0_regnum
;
277 regnum
-= ymm0_regnum
;
278 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
282 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
285 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
287 if (ymm16h_regnum
< 0)
290 regnum
-= ymm16h_regnum
;
291 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
295 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
298 int ymm16_regnum
= tdep
->ymm16_regnum
;
300 if (ymm16_regnum
< 0)
303 regnum
-= ymm16_regnum
;
304 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
310 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
313 int bnd0_regnum
= tdep
->bnd0_regnum
;
318 regnum
-= bnd0_regnum
;
319 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
325 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
328 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
330 if (num_xmm_regs
== 0)
333 regnum
-= I387_XMM0_REGNUM (tdep
);
334 return regnum
>= 0 && regnum
< num_xmm_regs
;
337 /* XMM_512 register? */
340 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
343 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
345 if (num_xmm_avx512_regs
== 0)
348 regnum
-= I387_XMM16_REGNUM (tdep
);
349 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
353 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 if (I387_NUM_XMM_REGS (tdep
) == 0)
360 return (regnum
== I387_MXCSR_REGNUM (tdep
));
366 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
370 if (I387_ST0_REGNUM (tdep
) < 0)
373 return (I387_ST0_REGNUM (tdep
) <= regnum
374 && regnum
< I387_FCTRL_REGNUM (tdep
));
378 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
380 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
382 if (I387_ST0_REGNUM (tdep
) < 0)
385 return (I387_FCTRL_REGNUM (tdep
) <= regnum
386 && regnum
< I387_XMM0_REGNUM (tdep
));
389 /* BNDr (raw) register? */
392 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
394 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
396 if (I387_BND0R_REGNUM (tdep
) < 0)
399 regnum
-= tdep
->bnd0r_regnum
;
400 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
403 /* BND control register? */
406 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
410 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
413 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
414 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
417 /* Return the name of register REGNUM, or the empty string if it is
418 an anonymous register. */
421 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
423 /* Hide the upper YMM registers. */
424 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
427 /* Hide the upper YMM16-31 registers. */
428 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
431 /* Hide the upper ZMM registers. */
432 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
435 return tdesc_register_name (gdbarch
, regnum
);
438 /* Return the name of register REGNUM. */
441 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
444 if (i386_bnd_regnum_p (gdbarch
, regnum
))
445 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
446 if (i386_mmx_regnum_p (gdbarch
, regnum
))
447 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
448 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
449 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
450 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
451 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
452 else if (i386_byte_regnum_p (gdbarch
, regnum
))
453 return i386_byte_names
[regnum
- tdep
->al_regnum
];
454 else if (i386_word_regnum_p (gdbarch
, regnum
))
455 return i386_word_names
[regnum
- tdep
->ax_regnum
];
457 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
460 /* Convert a dbx register number REG to the appropriate register
461 number used by GDB. */
464 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
468 /* This implements what GCC calls the "default" register map
469 (dbx_register_map[]). */
471 if (reg
>= 0 && reg
<= 7)
473 /* General-purpose registers. The debug info calls %ebp
474 register 4, and %esp register 5. */
481 else if (reg
>= 12 && reg
<= 19)
483 /* Floating-point registers. */
484 return reg
- 12 + I387_ST0_REGNUM (tdep
);
486 else if (reg
>= 21 && reg
<= 28)
489 int ymm0_regnum
= tdep
->ymm0_regnum
;
492 && i386_xmm_regnum_p (gdbarch
, reg
))
493 return reg
- 21 + ymm0_regnum
;
495 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
497 else if (reg
>= 29 && reg
<= 36)
500 return reg
- 29 + I387_MM0_REGNUM (tdep
);
503 /* This will hopefully provoke a warning. */
504 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
507 /* Convert SVR4 register number REG to the appropriate register number
511 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
515 /* This implements the GCC register map that tries to be compatible
516 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
518 /* The SVR4 register numbering includes %eip and %eflags, and
519 numbers the floating point registers differently. */
520 if (reg
>= 0 && reg
<= 9)
522 /* General-purpose registers. */
525 else if (reg
>= 11 && reg
<= 18)
527 /* Floating-point registers. */
528 return reg
- 11 + I387_ST0_REGNUM (tdep
);
530 else if (reg
>= 21 && reg
<= 36)
532 /* The SSE and MMX registers have the same numbers as with dbx. */
533 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
538 case 37: return I387_FCTRL_REGNUM (tdep
);
539 case 38: return I387_FSTAT_REGNUM (tdep
);
540 case 39: return I387_MXCSR_REGNUM (tdep
);
541 case 40: return I386_ES_REGNUM
;
542 case 41: return I386_CS_REGNUM
;
543 case 42: return I386_SS_REGNUM
;
544 case 43: return I386_DS_REGNUM
;
545 case 44: return I386_FS_REGNUM
;
546 case 45: return I386_GS_REGNUM
;
549 /* This will hopefully provoke a warning. */
550 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
555 /* This is the variable that is set with "set disassembly-flavor", and
556 its legitimate values. */
557 static const char att_flavor
[] = "att";
558 static const char intel_flavor
[] = "intel";
559 static const char *const valid_flavors
[] =
565 static const char *disassembly_flavor
= att_flavor
;
568 /* Use the program counter to determine the contents and size of a
569 breakpoint instruction. Return a pointer to a string of bytes that
570 encode a breakpoint instruction, store the length of the string in
571 *LEN and optionally adjust *PC to point to the correct memory
572 location for inserting the breakpoint.
574 On the i386 we have a single breakpoint that fits in a single byte
575 and can be inserted anywhere.
577 This function is 64-bit safe. */
579 static const gdb_byte
*
580 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
582 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
584 *len
= sizeof (break_insn
);
588 /* Displaced instruction handling. */
590 /* Skip the legacy instruction prefixes in INSN.
591 Not all prefixes are valid for any particular insn
592 but we needn't care, the insn will fault if it's invalid.
593 The result is a pointer to the first opcode byte,
594 or NULL if we run off the end of the buffer. */
597 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
599 gdb_byte
*end
= insn
+ max_len
;
605 case DATA_PREFIX_OPCODE
:
606 case ADDR_PREFIX_OPCODE
:
607 case CS_PREFIX_OPCODE
:
608 case DS_PREFIX_OPCODE
:
609 case ES_PREFIX_OPCODE
:
610 case FS_PREFIX_OPCODE
:
611 case GS_PREFIX_OPCODE
:
612 case SS_PREFIX_OPCODE
:
613 case LOCK_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
615 case REPNE_PREFIX_OPCODE
:
627 i386_absolute_jmp_p (const gdb_byte
*insn
)
629 /* jmp far (absolute address in operand). */
635 /* jump near, absolute indirect (/4). */
636 if ((insn
[1] & 0x38) == 0x20)
639 /* jump far, absolute indirect (/5). */
640 if ((insn
[1] & 0x38) == 0x28)
647 /* Return non-zero if INSN is a jump, zero otherwise. */
650 i386_jmp_p (const gdb_byte
*insn
)
652 /* jump short, relative. */
656 /* jump near, relative. */
660 return i386_absolute_jmp_p (insn
);
664 i386_absolute_call_p (const gdb_byte
*insn
)
666 /* call far, absolute. */
672 /* Call near, absolute indirect (/2). */
673 if ((insn
[1] & 0x38) == 0x10)
676 /* Call far, absolute indirect (/3). */
677 if ((insn
[1] & 0x38) == 0x18)
685 i386_ret_p (const gdb_byte
*insn
)
689 case 0xc2: /* ret near, pop N bytes. */
690 case 0xc3: /* ret near */
691 case 0xca: /* ret far, pop N bytes. */
692 case 0xcb: /* ret far */
693 case 0xcf: /* iret */
702 i386_call_p (const gdb_byte
*insn
)
704 if (i386_absolute_call_p (insn
))
707 /* call near, relative. */
714 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
715 length in bytes. Otherwise, return zero. */
718 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
720 /* Is it 'int $0x80'? */
721 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
722 /* Or is it 'sysenter'? */
723 || (insn
[0] == 0x0f && insn
[1] == 0x34)
724 /* Or is it 'syscall'? */
725 || (insn
[0] == 0x0f && insn
[1] == 0x05))
734 /* The gdbarch insn_is_call method. */
737 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
739 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
741 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
742 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
744 return i386_call_p (insn
);
747 /* The gdbarch insn_is_ret method. */
750 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
752 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
754 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
755 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
757 return i386_ret_p (insn
);
760 /* The gdbarch insn_is_jump method. */
763 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
765 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
767 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
768 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
770 return i386_jmp_p (insn
);
773 /* Some kernels may run one past a syscall insn, so we have to cope.
774 Otherwise this is just simple_displaced_step_copy_insn. */
776 struct displaced_step_closure
*
777 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
778 CORE_ADDR from
, CORE_ADDR to
,
779 struct regcache
*regs
)
781 size_t len
= gdbarch_max_insn_length (gdbarch
);
782 gdb_byte
*buf
= xmalloc (len
);
784 read_memory (from
, buf
, len
);
786 /* GDB may get control back after the insn after the syscall.
787 Presumably this is a kernel bug.
788 If this is a syscall, make sure there's a nop afterwards. */
793 insn
= i386_skip_prefixes (buf
, len
);
794 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
795 insn
[syscall_length
] = NOP_OPCODE
;
798 write_memory (to
, buf
, len
);
802 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
803 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
804 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
807 return (struct displaced_step_closure
*) buf
;
810 /* Fix up the state of registers and memory after having single-stepped
811 a displaced instruction. */
814 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
815 struct displaced_step_closure
*closure
,
816 CORE_ADDR from
, CORE_ADDR to
,
817 struct regcache
*regs
)
819 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
821 /* The offset we applied to the instruction's address.
822 This could well be negative (when viewed as a signed 32-bit
823 value), but ULONGEST won't reflect that, so take care when
825 ULONGEST insn_offset
= to
- from
;
827 /* Since we use simple_displaced_step_copy_insn, our closure is a
828 copy of the instruction. */
829 gdb_byte
*insn
= (gdb_byte
*) closure
;
830 /* The start of the insn, needed in case we see some prefixes. */
831 gdb_byte
*insn_start
= insn
;
834 fprintf_unfiltered (gdb_stdlog
,
835 "displaced: fixup (%s, %s), "
836 "insn = 0x%02x 0x%02x ...\n",
837 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
840 /* The list of issues to contend with here is taken from
841 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
842 Yay for Free Software! */
844 /* Relocate the %eip, if necessary. */
846 /* The instruction recognizers we use assume any leading prefixes
847 have been skipped. */
849 /* This is the size of the buffer in closure. */
850 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
851 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
852 /* If there are too many prefixes, just ignore the insn.
853 It will fault when run. */
858 /* Except in the case of absolute or indirect jump or call
859 instructions, or a return instruction, the new eip is relative to
860 the displaced instruction; make it relative. Well, signal
861 handler returns don't need relocation either, but we use the
862 value of %eip to recognize those; see below. */
863 if (! i386_absolute_jmp_p (insn
)
864 && ! i386_absolute_call_p (insn
)
865 && ! i386_ret_p (insn
))
870 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
872 /* A signal trampoline system call changes the %eip, resuming
873 execution of the main program after the signal handler has
874 returned. That makes them like 'return' instructions; we
875 shouldn't relocate %eip.
877 But most system calls don't, and we do need to relocate %eip.
879 Our heuristic for distinguishing these cases: if stepping
880 over the system call instruction left control directly after
881 the instruction, the we relocate --- control almost certainly
882 doesn't belong in the displaced copy. Otherwise, we assume
883 the instruction has put control where it belongs, and leave
884 it unrelocated. Goodness help us if there are PC-relative
886 if (i386_syscall_p (insn
, &insn_len
)
887 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
888 /* GDB can get control back after the insn after the syscall.
889 Presumably this is a kernel bug.
890 i386_displaced_step_copy_insn ensures its a nop,
891 we add one to the length for it. */
892 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
895 fprintf_unfiltered (gdb_stdlog
,
896 "displaced: syscall changed %%eip; "
901 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
903 /* If we just stepped over a breakpoint insn, we don't backup
904 the pc on purpose; this is to match behaviour without
907 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
910 fprintf_unfiltered (gdb_stdlog
,
912 "relocated %%eip from %s to %s\n",
913 paddress (gdbarch
, orig_eip
),
914 paddress (gdbarch
, eip
));
918 /* If the instruction was PUSHFL, then the TF bit will be set in the
919 pushed value, and should be cleared. We'll leave this for later,
920 since GDB already messes up the TF flag when stepping over a
923 /* If the instruction was a call, the return address now atop the
924 stack is the address following the copied instruction. We need
925 to make it the address following the original instruction. */
926 if (i386_call_p (insn
))
930 const ULONGEST retaddr_len
= 4;
932 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
933 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
934 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
935 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
938 fprintf_unfiltered (gdb_stdlog
,
939 "displaced: relocated return addr at %s to %s\n",
940 paddress (gdbarch
, esp
),
941 paddress (gdbarch
, retaddr
));
946 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
948 target_write_memory (*to
, buf
, len
);
953 i386_relocate_instruction (struct gdbarch
*gdbarch
,
954 CORE_ADDR
*to
, CORE_ADDR oldloc
)
956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
957 gdb_byte buf
[I386_MAX_INSN_LEN
];
958 int offset
= 0, rel32
, newrel
;
960 gdb_byte
*insn
= buf
;
962 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
964 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
965 I386_MAX_INSN_LEN
, oldloc
);
967 /* Get past the prefixes. */
968 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
970 /* Adjust calls with 32-bit relative addresses as push/jump, with
971 the address pushed being the location where the original call in
972 the user program would return to. */
975 gdb_byte push_buf
[16];
976 unsigned int ret_addr
;
978 /* Where "ret" in the original code will return to. */
979 ret_addr
= oldloc
+ insn_length
;
980 push_buf
[0] = 0x68; /* pushq $... */
981 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
983 append_insns (to
, 5, push_buf
);
985 /* Convert the relative call to a relative jump. */
988 /* Adjust the destination offset. */
989 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
990 newrel
= (oldloc
- *to
) + rel32
;
991 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
994 fprintf_unfiltered (gdb_stdlog
,
995 "Adjusted insn rel32=%s at %s to"
997 hex_string (rel32
), paddress (gdbarch
, oldloc
),
998 hex_string (newrel
), paddress (gdbarch
, *to
));
1000 /* Write the adjusted jump into its displaced location. */
1001 append_insns (to
, 5, insn
);
1005 /* Adjust jumps with 32-bit relative addresses. Calls are already
1007 if (insn
[0] == 0xe9)
1009 /* Adjust conditional jumps. */
1010 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1015 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1016 newrel
= (oldloc
- *to
) + rel32
;
1017 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1018 if (debug_displaced
)
1019 fprintf_unfiltered (gdb_stdlog
,
1020 "Adjusted insn rel32=%s at %s to"
1021 " rel32=%s at %s\n",
1022 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1023 hex_string (newrel
), paddress (gdbarch
, *to
));
1026 /* Write the adjusted instructions into their displaced
1028 append_insns (to
, insn_length
, buf
);
1032 #ifdef I386_REGNO_TO_SYMMETRY
1033 #error "The Sequent Symmetry is no longer supported."
1036 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1037 and %esp "belong" to the calling function. Therefore these
1038 registers should be saved if they're going to be modified. */
1040 /* The maximum number of saved registers. This should include all
1041 registers mentioned above, and %eip. */
1042 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1044 struct i386_frame_cache
1052 /* Saved registers. */
1053 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1058 /* Stack space reserved for local variables. */
1062 /* Allocate and initialize a frame cache. */
1064 static struct i386_frame_cache
*
1065 i386_alloc_frame_cache (void)
1067 struct i386_frame_cache
*cache
;
1070 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1075 cache
->sp_offset
= -4;
1078 /* Saved registers. We initialize these to -1 since zero is a valid
1079 offset (that's where %ebp is supposed to be stored). */
1080 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1081 cache
->saved_regs
[i
] = -1;
1082 cache
->saved_sp
= 0;
1083 cache
->saved_sp_reg
= -1;
1084 cache
->pc_in_eax
= 0;
1086 /* Frameless until proven otherwise. */
1092 /* If the instruction at PC is a jump, return the address of its
1093 target. Otherwise, return PC. */
1096 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1098 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1103 if (target_read_code (pc
, &op
, 1))
1110 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1116 /* Relative jump: if data16 == 0, disp32, else disp16. */
1119 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1121 /* Include the size of the jmp instruction (including the
1127 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1129 /* Include the size of the jmp instruction. */
1134 /* Relative jump, disp8 (ignore data16). */
1135 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1137 delta
+= data16
+ 2;
1144 /* Check whether PC points at a prologue for a function returning a
1145 structure or union. If so, it updates CACHE and returns the
1146 address of the first instruction after the code sequence that
1147 removes the "hidden" argument from the stack or CURRENT_PC,
1148 whichever is smaller. Otherwise, return PC. */
1151 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1152 struct i386_frame_cache
*cache
)
1154 /* Functions that return a structure or union start with:
1157 xchgl %eax, (%esp) 0x87 0x04 0x24
1158 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1160 (the System V compiler puts out the second `xchg' instruction,
1161 and the assembler doesn't try to optimize it, so the 'sib' form
1162 gets generated). This sequence is used to get the address of the
1163 return buffer for a function that returns a structure. */
1164 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1165 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1169 if (current_pc
<= pc
)
1172 if (target_read_code (pc
, &op
, 1))
1175 if (op
!= 0x58) /* popl %eax */
1178 if (target_read_code (pc
+ 1, buf
, 4))
1181 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1184 if (current_pc
== pc
)
1186 cache
->sp_offset
+= 4;
1190 if (current_pc
== pc
+ 1)
1192 cache
->pc_in_eax
= 1;
1196 if (buf
[1] == proto1
[1])
1203 i386_skip_probe (CORE_ADDR pc
)
1205 /* A function may start with
1219 if (target_read_code (pc
, &op
, 1))
1222 if (op
== 0x68 || op
== 0x6a)
1226 /* Skip past the `pushl' instruction; it has either a one-byte or a
1227 four-byte operand, depending on the opcode. */
1233 /* Read the following 8 bytes, which should be `call _probe' (6
1234 bytes) followed by `addl $4,%esp' (2 bytes). */
1235 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1236 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1237 pc
+= delta
+ sizeof (buf
);
1243 /* GCC 4.1 and later, can put code in the prologue to realign the
1244 stack pointer. Check whether PC points to such code, and update
1245 CACHE accordingly. Return the first instruction after the code
1246 sequence or CURRENT_PC, whichever is smaller. If we don't
1247 recognize the code, return PC. */
1250 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1251 struct i386_frame_cache
*cache
)
1253 /* There are 2 code sequences to re-align stack before the frame
1256 1. Use a caller-saved saved register:
1262 2. Use a callee-saved saved register:
1269 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1271 0x83 0xe4 0xf0 andl $-16, %esp
1272 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1277 int offset
, offset_and
;
1278 static int regnums
[8] = {
1279 I386_EAX_REGNUM
, /* %eax */
1280 I386_ECX_REGNUM
, /* %ecx */
1281 I386_EDX_REGNUM
, /* %edx */
1282 I386_EBX_REGNUM
, /* %ebx */
1283 I386_ESP_REGNUM
, /* %esp */
1284 I386_EBP_REGNUM
, /* %ebp */
1285 I386_ESI_REGNUM
, /* %esi */
1286 I386_EDI_REGNUM
/* %edi */
1289 if (target_read_code (pc
, buf
, sizeof buf
))
1292 /* Check caller-saved saved register. The first instruction has
1293 to be "leal 4(%esp), %reg". */
1294 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1296 /* MOD must be binary 10 and R/M must be binary 100. */
1297 if ((buf
[1] & 0xc7) != 0x44)
1300 /* REG has register number. */
1301 reg
= (buf
[1] >> 3) & 7;
1306 /* Check callee-saved saved register. The first instruction
1307 has to be "pushl %reg". */
1308 if ((buf
[0] & 0xf8) != 0x50)
1314 /* The next instruction has to be "leal 8(%esp), %reg". */
1315 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1318 /* MOD must be binary 10 and R/M must be binary 100. */
1319 if ((buf
[2] & 0xc7) != 0x44)
1322 /* REG has register number. Registers in pushl and leal have to
1324 if (reg
!= ((buf
[2] >> 3) & 7))
1330 /* Rigister can't be %esp nor %ebp. */
1331 if (reg
== 4 || reg
== 5)
1334 /* The next instruction has to be "andl $-XXX, %esp". */
1335 if (buf
[offset
+ 1] != 0xe4
1336 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1339 offset_and
= offset
;
1340 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1342 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1343 0xfc. REG must be binary 110 and MOD must be binary 01. */
1344 if (buf
[offset
] != 0xff
1345 || buf
[offset
+ 2] != 0xfc
1346 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1349 /* R/M has register. Registers in leal and pushl have to be the
1351 if (reg
!= (buf
[offset
+ 1] & 7))
1354 if (current_pc
> pc
+ offset_and
)
1355 cache
->saved_sp_reg
= regnums
[reg
];
1357 return min (pc
+ offset
+ 3, current_pc
);
1360 /* Maximum instruction length we need to handle. */
1361 #define I386_MAX_MATCHED_INSN_LEN 6
1363 /* Instruction description. */
1367 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1368 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1371 /* Return whether instruction at PC matches PATTERN. */
1374 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1378 if (target_read_code (pc
, &op
, 1))
1381 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1383 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1384 int insn_matched
= 1;
1387 gdb_assert (pattern
.len
> 1);
1388 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1390 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1393 for (i
= 1; i
< pattern
.len
; i
++)
1395 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1398 return insn_matched
;
1403 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1404 the first instruction description that matches. Otherwise, return
1407 static struct i386_insn
*
1408 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1410 struct i386_insn
*pattern
;
1412 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1414 if (i386_match_pattern (pc
, *pattern
))
1421 /* Return whether PC points inside a sequence of instructions that
1422 matches INSN_PATTERNS. */
1425 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1427 CORE_ADDR current_pc
;
1429 struct i386_insn
*insn
;
1431 insn
= i386_match_insn (pc
, insn_patterns
);
1436 ix
= insn
- insn_patterns
;
1437 for (i
= ix
- 1; i
>= 0; i
--)
1439 current_pc
-= insn_patterns
[i
].len
;
1441 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1445 current_pc
= pc
+ insn
->len
;
1446 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1448 if (!i386_match_pattern (current_pc
, *insn
))
1451 current_pc
+= insn
->len
;
1457 /* Some special instructions that might be migrated by GCC into the
1458 part of the prologue that sets up the new stack frame. Because the
1459 stack frame hasn't been setup yet, no registers have been saved
1460 yet, and only the scratch registers %eax, %ecx and %edx can be
1463 struct i386_insn i386_frame_setup_skip_insns
[] =
1465 /* Check for `movb imm8, r' and `movl imm32, r'.
1467 ??? Should we handle 16-bit operand-sizes here? */
1469 /* `movb imm8, %al' and `movb imm8, %ah' */
1470 /* `movb imm8, %cl' and `movb imm8, %ch' */
1471 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1472 /* `movb imm8, %dl' and `movb imm8, %dh' */
1473 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1474 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1475 { 5, { 0xb8 }, { 0xfe } },
1476 /* `movl imm32, %edx' */
1477 { 5, { 0xba }, { 0xff } },
1479 /* Check for `mov imm32, r32'. Note that there is an alternative
1480 encoding for `mov m32, %eax'.
1482 ??? Should we handle SIB adressing here?
1483 ??? Should we handle 16-bit operand-sizes here? */
1485 /* `movl m32, %eax' */
1486 { 5, { 0xa1 }, { 0xff } },
1487 /* `movl m32, %eax' and `mov; m32, %ecx' */
1488 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1489 /* `movl m32, %edx' */
1490 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1492 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1493 Because of the symmetry, there are actually two ways to encode
1494 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1495 opcode bytes 0x31 and 0x33 for `xorl'. */
1497 /* `subl %eax, %eax' */
1498 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1499 /* `subl %ecx, %ecx' */
1500 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1501 /* `subl %edx, %edx' */
1502 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1503 /* `xorl %eax, %eax' */
1504 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1505 /* `xorl %ecx, %ecx' */
1506 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1507 /* `xorl %edx, %edx' */
1508 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1513 /* Check whether PC points to a no-op instruction. */
1515 i386_skip_noop (CORE_ADDR pc
)
1520 if (target_read_code (pc
, &op
, 1))
1526 /* Ignore `nop' instruction. */
1530 if (target_read_code (pc
, &op
, 1))
1534 /* Ignore no-op instruction `mov %edi, %edi'.
1535 Microsoft system dlls often start with
1536 a `mov %edi,%edi' instruction.
1537 The 5 bytes before the function start are
1538 filled with `nop' instructions.
1539 This pattern can be used for hot-patching:
1540 The `mov %edi, %edi' instruction can be replaced by a
1541 near jump to the location of the 5 `nop' instructions
1542 which can be replaced by a 32-bit jump to anywhere
1543 in the 32-bit address space. */
1545 else if (op
== 0x8b)
1547 if (target_read_code (pc
+ 1, &op
, 1))
1553 if (target_read_code (pc
, &op
, 1))
1563 /* Check whether PC points at a code that sets up a new stack frame.
1564 If so, it updates CACHE and returns the address of the first
1565 instruction after the sequence that sets up the frame or LIMIT,
1566 whichever is smaller. If we don't recognize the code, return PC. */
1569 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1570 CORE_ADDR pc
, CORE_ADDR limit
,
1571 struct i386_frame_cache
*cache
)
1573 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1574 struct i386_insn
*insn
;
1581 if (target_read_code (pc
, &op
, 1))
1584 if (op
== 0x55) /* pushl %ebp */
1586 /* Take into account that we've executed the `pushl %ebp' that
1587 starts this instruction sequence. */
1588 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1589 cache
->sp_offset
+= 4;
1592 /* If that's all, return now. */
1596 /* Check for some special instructions that might be migrated by
1597 GCC into the prologue and skip them. At this point in the
1598 prologue, code should only touch the scratch registers %eax,
1599 %ecx and %edx, so while the number of posibilities is sheer,
1602 Make sure we only skip these instructions if we later see the
1603 `movl %esp, %ebp' that actually sets up the frame. */
1604 while (pc
+ skip
< limit
)
1606 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1613 /* If that's all, return now. */
1614 if (limit
<= pc
+ skip
)
1617 if (target_read_code (pc
+ skip
, &op
, 1))
1620 /* The i386 prologue looks like
1626 and a different prologue can be generated for atom.
1630 lea -0x10(%esp),%esp
1632 We handle both of them here. */
1636 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1638 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1644 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1649 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1650 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1659 /* OK, we actually have a frame. We just don't know how large
1660 it is yet. Set its size to zero. We'll adjust it if
1661 necessary. We also now commit to skipping the special
1662 instructions mentioned before. */
1665 /* If that's all, return now. */
1669 /* Check for stack adjustment
1675 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1676 reg, so we don't have to worry about a data16 prefix. */
1677 if (target_read_code (pc
, &op
, 1))
1681 /* `subl' with 8-bit immediate. */
1682 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1683 /* Some instruction starting with 0x83 other than `subl'. */
1686 /* `subl' with signed 8-bit immediate (though it wouldn't
1687 make sense to be negative). */
1688 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1691 else if (op
== 0x81)
1693 /* Maybe it is `subl' with a 32-bit immediate. */
1694 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1695 /* Some instruction starting with 0x81 other than `subl'. */
1698 /* It is `subl' with a 32-bit immediate. */
1699 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1702 else if (op
== 0x8d)
1704 /* The ModR/M byte is 0x64. */
1705 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1707 /* 'lea' with 8-bit displacement. */
1708 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1713 /* Some instruction other than `subl' nor 'lea'. */
1717 else if (op
== 0xc8) /* enter */
1719 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1726 /* Check whether PC points at code that saves registers on the stack.
1727 If so, it updates CACHE and returns the address of the first
1728 instruction after the register saves or CURRENT_PC, whichever is
1729 smaller. Otherwise, return PC. */
1732 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1733 struct i386_frame_cache
*cache
)
1735 CORE_ADDR offset
= 0;
1739 if (cache
->locals
> 0)
1740 offset
-= cache
->locals
;
1741 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1743 if (target_read_code (pc
, &op
, 1))
1745 if (op
< 0x50 || op
> 0x57)
1749 cache
->saved_regs
[op
- 0x50] = offset
;
1750 cache
->sp_offset
+= 4;
1757 /* Do a full analysis of the prologue at PC and update CACHE
1758 accordingly. Bail out early if CURRENT_PC is reached. Return the
1759 address where the analysis stopped.
1761 We handle these cases:
1763 The startup sequence can be at the start of the function, or the
1764 function can start with a branch to startup code at the end.
1766 %ebp can be set up with either the 'enter' instruction, or "pushl
1767 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1768 once used in the System V compiler).
1770 Local space is allocated just below the saved %ebp by either the
1771 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1772 16-bit unsigned argument for space to allocate, and the 'addl'
1773 instruction could have either a signed byte, or 32-bit immediate.
1775 Next, the registers used by this function are pushed. With the
1776 System V compiler they will always be in the order: %edi, %esi,
1777 %ebx (and sometimes a harmless bug causes it to also save but not
1778 restore %eax); however, the code below is willing to see the pushes
1779 in any order, and will handle up to 8 of them.
1781 If the setup sequence is at the end of the function, then the next
1782 instruction will be a branch back to the start. */
1785 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1786 CORE_ADDR pc
, CORE_ADDR current_pc
,
1787 struct i386_frame_cache
*cache
)
1789 pc
= i386_skip_noop (pc
);
1790 pc
= i386_follow_jump (gdbarch
, pc
);
1791 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1792 pc
= i386_skip_probe (pc
);
1793 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1794 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1795 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1798 /* Return PC of first real instruction. */
1801 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1803 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1805 static gdb_byte pic_pat
[6] =
1807 0xe8, 0, 0, 0, 0, /* call 0x0 */
1808 0x5b, /* popl %ebx */
1810 struct i386_frame_cache cache
;
1814 CORE_ADDR func_addr
;
1816 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1818 CORE_ADDR post_prologue_pc
1819 = skip_prologue_using_sal (gdbarch
, func_addr
);
1820 struct symtab
*s
= find_pc_symtab (func_addr
);
1822 /* Clang always emits a line note before the prologue and another
1823 one after. We trust clang to emit usable line notes. */
1824 if (post_prologue_pc
1826 && s
->producer
!= NULL
1827 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1828 return max (start_pc
, post_prologue_pc
);
1832 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1833 if (cache
.locals
< 0)
1836 /* Found valid frame setup. */
1838 /* The native cc on SVR4 in -K PIC mode inserts the following code
1839 to get the address of the global offset table (GOT) into register
1844 movl %ebx,x(%ebp) (optional)
1847 This code is with the rest of the prologue (at the end of the
1848 function), so we have to skip it to get to the first real
1849 instruction at the start of the function. */
1851 for (i
= 0; i
< 6; i
++)
1853 if (target_read_code (pc
+ i
, &op
, 1))
1856 if (pic_pat
[i
] != op
)
1863 if (target_read_code (pc
+ delta
, &op
, 1))
1866 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1868 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1870 if (op
== 0x5d) /* One byte offset from %ebp. */
1872 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1874 else /* Unexpected instruction. */
1877 if (target_read_code (pc
+ delta
, &op
, 1))
1882 if (delta
> 0 && op
== 0x81
1883 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1890 /* If the function starts with a branch (to startup code at the end)
1891 the last instruction should bring us back to the first
1892 instruction of the real code. */
1893 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1894 pc
= i386_follow_jump (gdbarch
, pc
);
1899 /* Check that the code pointed to by PC corresponds to a call to
1900 __main, skip it if so. Return PC otherwise. */
1903 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1905 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1908 if (target_read_code (pc
, &op
, 1))
1914 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1916 /* Make sure address is computed correctly as a 32bit
1917 integer even if CORE_ADDR is 64 bit wide. */
1918 struct bound_minimal_symbol s
;
1919 CORE_ADDR call_dest
;
1921 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1922 call_dest
= call_dest
& 0xffffffffU
;
1923 s
= lookup_minimal_symbol_by_pc (call_dest
);
1924 if (s
.minsym
!= NULL
1925 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1926 && strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1934 /* This function is 64-bit safe. */
1937 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1941 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1942 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1946 /* Normal frames. */
1949 i386_frame_cache_1 (struct frame_info
*this_frame
,
1950 struct i386_frame_cache
*cache
)
1952 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1953 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1957 cache
->pc
= get_frame_func (this_frame
);
1959 /* In principle, for normal frames, %ebp holds the frame pointer,
1960 which holds the base address for the current stack frame.
1961 However, for functions that don't need it, the frame pointer is
1962 optional. For these "frameless" functions the frame pointer is
1963 actually the frame pointer of the calling frame. Signal
1964 trampolines are just a special case of a "frameless" function.
1965 They (usually) share their frame pointer with the frame that was
1966 in progress when the signal occurred. */
1968 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1969 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1970 if (cache
->base
== 0)
1976 /* For normal frames, %eip is stored at 4(%ebp). */
1977 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1980 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1983 if (cache
->locals
< 0)
1985 /* We didn't find a valid frame, which means that CACHE->base
1986 currently holds the frame pointer for our calling frame. If
1987 we're at the start of a function, or somewhere half-way its
1988 prologue, the function's frame probably hasn't been fully
1989 setup yet. Try to reconstruct the base address for the stack
1990 frame by looking at the stack pointer. For truly "frameless"
1991 functions this might work too. */
1993 if (cache
->saved_sp_reg
!= -1)
1995 /* Saved stack pointer has been saved. */
1996 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1997 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1999 /* We're halfway aligning the stack. */
2000 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2001 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2003 /* This will be added back below. */
2004 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2006 else if (cache
->pc
!= 0
2007 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2009 /* We're in a known function, but did not find a frame
2010 setup. Assume that the function does not use %ebp.
2011 Alternatively, we may have jumped to an invalid
2012 address; in that case there is definitely no new
2014 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2015 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2019 /* We're in an unknown function. We could not find the start
2020 of the function to analyze the prologue; our best option is
2021 to assume a typical frame layout with the caller's %ebp
2023 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2026 if (cache
->saved_sp_reg
!= -1)
2028 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2029 register may be unavailable). */
2030 if (cache
->saved_sp
== 0
2031 && deprecated_frame_register_read (this_frame
,
2032 cache
->saved_sp_reg
, buf
))
2033 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2035 /* Now that we have the base address for the stack frame we can
2036 calculate the value of %esp in the calling frame. */
2037 else if (cache
->saved_sp
== 0)
2038 cache
->saved_sp
= cache
->base
+ 8;
2040 /* Adjust all the saved registers such that they contain addresses
2041 instead of offsets. */
2042 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2043 if (cache
->saved_regs
[i
] != -1)
2044 cache
->saved_regs
[i
] += cache
->base
;
2049 static struct i386_frame_cache
*
2050 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2052 volatile struct gdb_exception ex
;
2053 struct i386_frame_cache
*cache
;
2058 cache
= i386_alloc_frame_cache ();
2059 *this_cache
= cache
;
2061 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2063 i386_frame_cache_1 (this_frame
, cache
);
2065 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2066 throw_exception (ex
);
2072 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2073 struct frame_id
*this_id
)
2075 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2078 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2079 else if (cache
->base
== 0)
2081 /* This marks the outermost frame. */
2085 /* See the end of i386_push_dummy_call. */
2086 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2090 static enum unwind_stop_reason
2091 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2094 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2097 return UNWIND_UNAVAILABLE
;
2099 /* This marks the outermost frame. */
2100 if (cache
->base
== 0)
2101 return UNWIND_OUTERMOST
;
2103 return UNWIND_NO_REASON
;
2106 static struct value
*
2107 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2110 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2112 gdb_assert (regnum
>= 0);
2114 /* The System V ABI says that:
2116 "The flags register contains the system flags, such as the
2117 direction flag and the carry flag. The direction flag must be
2118 set to the forward (that is, zero) direction before entry and
2119 upon exit from a function. Other user flags have no specified
2120 role in the standard calling sequence and are not preserved."
2122 To guarantee the "upon exit" part of that statement we fake a
2123 saved flags register that has its direction flag cleared.
2125 Note that GCC doesn't seem to rely on the fact that the direction
2126 flag is cleared after a function return; it always explicitly
2127 clears the flag before operations where it matters.
2129 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2130 right thing to do. The way we fake the flags register here makes
2131 it impossible to change it. */
2133 if (regnum
== I386_EFLAGS_REGNUM
)
2137 val
= get_frame_register_unsigned (this_frame
, regnum
);
2139 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2142 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2143 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2145 if (regnum
== I386_ESP_REGNUM
2146 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2148 /* If the SP has been saved, but we don't know where, then this
2149 means that SAVED_SP_REG register was found unavailable back
2150 when we built the cache. */
2151 if (cache
->saved_sp
== 0)
2152 return frame_unwind_got_register (this_frame
, regnum
,
2153 cache
->saved_sp_reg
);
2155 return frame_unwind_got_constant (this_frame
, regnum
,
2159 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2160 return frame_unwind_got_memory (this_frame
, regnum
,
2161 cache
->saved_regs
[regnum
]);
2163 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2166 static const struct frame_unwind i386_frame_unwind
=
2169 i386_frame_unwind_stop_reason
,
2171 i386_frame_prev_register
,
2173 default_frame_sniffer
2176 /* Normal frames, but in a function epilogue. */
2178 /* The epilogue is defined here as the 'ret' instruction, which will
2179 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2180 the function's stack frame. */
2183 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2186 struct symtab
*symtab
;
2188 symtab
= find_pc_symtab (pc
);
2189 if (symtab
&& symtab
->epilogue_unwind_valid
)
2192 if (target_read_memory (pc
, &insn
, 1))
2193 return 0; /* Can't read memory at pc. */
2195 if (insn
!= 0xc3) /* 'ret' instruction. */
2202 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2203 struct frame_info
*this_frame
,
2204 void **this_prologue_cache
)
2206 if (frame_relative_level (this_frame
) == 0)
2207 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
2208 get_frame_pc (this_frame
));
2213 static struct i386_frame_cache
*
2214 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2216 volatile struct gdb_exception ex
;
2217 struct i386_frame_cache
*cache
;
2223 cache
= i386_alloc_frame_cache ();
2224 *this_cache
= cache
;
2226 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2228 cache
->pc
= get_frame_func (this_frame
);
2230 /* At this point the stack looks as if we just entered the
2231 function, with the return address at the top of the
2233 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2234 cache
->base
= sp
+ cache
->sp_offset
;
2235 cache
->saved_sp
= cache
->base
+ 8;
2236 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2240 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2241 throw_exception (ex
);
2246 static enum unwind_stop_reason
2247 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2250 struct i386_frame_cache
*cache
=
2251 i386_epilogue_frame_cache (this_frame
, this_cache
);
2254 return UNWIND_UNAVAILABLE
;
2256 return UNWIND_NO_REASON
;
2260 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2262 struct frame_id
*this_id
)
2264 struct i386_frame_cache
*cache
=
2265 i386_epilogue_frame_cache (this_frame
, this_cache
);
2268 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2270 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2273 static struct value
*
2274 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2275 void **this_cache
, int regnum
)
2277 /* Make sure we've initialized the cache. */
2278 i386_epilogue_frame_cache (this_frame
, this_cache
);
2280 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2283 static const struct frame_unwind i386_epilogue_frame_unwind
=
2286 i386_epilogue_frame_unwind_stop_reason
,
2287 i386_epilogue_frame_this_id
,
2288 i386_epilogue_frame_prev_register
,
2290 i386_epilogue_frame_sniffer
2294 /* Stack-based trampolines. */
2296 /* These trampolines are used on cross x86 targets, when taking the
2297 address of a nested function. When executing these trampolines,
2298 no stack frame is set up, so we are in a similar situation as in
2299 epilogues and i386_epilogue_frame_this_id can be re-used. */
2301 /* Static chain passed in register. */
2303 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2305 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2306 { 5, { 0xb8 }, { 0xfe } },
2309 { 5, { 0xe9 }, { 0xff } },
2314 /* Static chain passed on stack (when regparm=3). */
2316 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2319 { 5, { 0x68 }, { 0xff } },
2322 { 5, { 0xe9 }, { 0xff } },
2327 /* Return whether PC points inside a stack trampoline. */
2330 i386_in_stack_tramp_p (CORE_ADDR pc
)
2335 /* A stack trampoline is detected if no name is associated
2336 to the current pc and if it points inside a trampoline
2339 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2343 if (target_read_memory (pc
, &insn
, 1))
2346 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2347 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2354 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2355 struct frame_info
*this_frame
,
2358 if (frame_relative_level (this_frame
) == 0)
2359 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2364 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2367 i386_epilogue_frame_unwind_stop_reason
,
2368 i386_epilogue_frame_this_id
,
2369 i386_epilogue_frame_prev_register
,
2371 i386_stack_tramp_frame_sniffer
2374 /* Generate a bytecode expression to get the value of the saved PC. */
2377 i386_gen_return_address (struct gdbarch
*gdbarch
,
2378 struct agent_expr
*ax
, struct axs_value
*value
,
2381 /* The following sequence assumes the traditional use of the base
2383 ax_reg (ax
, I386_EBP_REGNUM
);
2385 ax_simple (ax
, aop_add
);
2386 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2387 value
->kind
= axs_lvalue_memory
;
2391 /* Signal trampolines. */
2393 static struct i386_frame_cache
*
2394 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2396 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2398 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2399 volatile struct gdb_exception ex
;
2400 struct i386_frame_cache
*cache
;
2407 cache
= i386_alloc_frame_cache ();
2409 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2411 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2412 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2414 addr
= tdep
->sigcontext_addr (this_frame
);
2415 if (tdep
->sc_reg_offset
)
2419 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2421 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2422 if (tdep
->sc_reg_offset
[i
] != -1)
2423 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2427 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2428 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2433 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2434 throw_exception (ex
);
2436 *this_cache
= cache
;
2440 static enum unwind_stop_reason
2441 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2444 struct i386_frame_cache
*cache
=
2445 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2448 return UNWIND_UNAVAILABLE
;
2450 return UNWIND_NO_REASON
;
2454 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2455 struct frame_id
*this_id
)
2457 struct i386_frame_cache
*cache
=
2458 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2461 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2464 /* See the end of i386_push_dummy_call. */
2465 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2469 static struct value
*
2470 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2471 void **this_cache
, int regnum
)
2473 /* Make sure we've initialized the cache. */
2474 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2476 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2480 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2481 struct frame_info
*this_frame
,
2482 void **this_prologue_cache
)
2484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2486 /* We shouldn't even bother if we don't have a sigcontext_addr
2488 if (tdep
->sigcontext_addr
== NULL
)
2491 if (tdep
->sigtramp_p
!= NULL
)
2493 if (tdep
->sigtramp_p (this_frame
))
2497 if (tdep
->sigtramp_start
!= 0)
2499 CORE_ADDR pc
= get_frame_pc (this_frame
);
2501 gdb_assert (tdep
->sigtramp_end
!= 0);
2502 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2509 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2512 i386_sigtramp_frame_unwind_stop_reason
,
2513 i386_sigtramp_frame_this_id
,
2514 i386_sigtramp_frame_prev_register
,
2516 i386_sigtramp_frame_sniffer
2521 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2523 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2528 static const struct frame_base i386_frame_base
=
2531 i386_frame_base_address
,
2532 i386_frame_base_address
,
2533 i386_frame_base_address
2536 static struct frame_id
2537 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2541 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2543 /* See the end of i386_push_dummy_call. */
2544 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2547 /* _Decimal128 function return values need 16-byte alignment on the
2551 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2553 return sp
& -(CORE_ADDR
)16;
2557 /* Figure out where the longjmp will land. Slurp the args out of the
2558 stack. We expect the first arg to be a pointer to the jmp_buf
2559 structure from which we extract the address that we will land at.
2560 This address is copied into PC. This routine returns non-zero on
2564 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2567 CORE_ADDR sp
, jb_addr
;
2568 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2569 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2570 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2572 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2573 longjmp will land. */
2574 if (jb_pc_offset
== -1)
2577 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2578 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2579 if (target_read_memory (sp
+ 4, buf
, 4))
2582 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2583 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2586 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2591 /* Check whether TYPE must be 16-byte-aligned when passed as a
2592 function argument. 16-byte vectors, _Decimal128 and structures or
2593 unions containing such types must be 16-byte-aligned; other
2594 arguments are 4-byte-aligned. */
2597 i386_16_byte_align_p (struct type
*type
)
2599 type
= check_typedef (type
);
2600 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2601 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2602 && TYPE_LENGTH (type
) == 16)
2604 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2605 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2606 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2607 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2610 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2612 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2619 /* Implementation for set_gdbarch_push_dummy_code. */
2622 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2623 struct value
**args
, int nargs
, struct type
*value_type
,
2624 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2625 struct regcache
*regcache
)
2627 /* Use 0xcc breakpoint - 1 byte. */
2631 /* Keep the stack aligned. */
2636 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2637 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2638 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2639 CORE_ADDR struct_addr
)
2641 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2647 /* Determine the total space required for arguments and struct
2648 return address in a first pass (allowing for 16-byte-aligned
2649 arguments), then push arguments in a second pass. */
2651 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2653 int args_space_used
= 0;
2659 /* Push value address. */
2660 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2661 write_memory (sp
, buf
, 4);
2662 args_space_used
+= 4;
2668 for (i
= 0; i
< nargs
; i
++)
2670 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2674 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2675 args_space_used
= align_up (args_space_used
, 16);
2677 write_memory (sp
+ args_space_used
,
2678 value_contents_all (args
[i
]), len
);
2679 /* The System V ABI says that:
2681 "An argument's size is increased, if necessary, to make it a
2682 multiple of [32-bit] words. This may require tail padding,
2683 depending on the size of the argument."
2685 This makes sure the stack stays word-aligned. */
2686 args_space_used
+= align_up (len
, 4);
2690 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2691 args_space
= align_up (args_space
, 16);
2692 args_space
+= align_up (len
, 4);
2700 /* The original System V ABI only requires word alignment,
2701 but modern incarnations need 16-byte alignment in order
2702 to support SSE. Since wasting a few bytes here isn't
2703 harmful we unconditionally enforce 16-byte alignment. */
2708 /* Store return address. */
2710 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2711 write_memory (sp
, buf
, 4);
2713 /* Finally, update the stack pointer... */
2714 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2715 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2717 /* ...and fake a frame pointer. */
2718 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2720 /* MarkK wrote: This "+ 8" is all over the place:
2721 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2722 i386_dummy_id). It's there, since all frame unwinders for
2723 a given target have to agree (within a certain margin) on the
2724 definition of the stack address of a frame. Otherwise frame id
2725 comparison might not work correctly. Since DWARF2/GCC uses the
2726 stack address *before* the function call as a frame's CFA. On
2727 the i386, when %ebp is used as a frame pointer, the offset
2728 between the contents %ebp and the CFA as defined by GCC. */
2732 /* These registers are used for returning integers (and on some
2733 targets also for returning `struct' and `union' values when their
2734 size and alignment match an integer type). */
2735 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2736 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2738 /* Read, for architecture GDBARCH, a function return value of TYPE
2739 from REGCACHE, and copy that into VALBUF. */
2742 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2743 struct regcache
*regcache
, gdb_byte
*valbuf
)
2745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2746 int len
= TYPE_LENGTH (type
);
2747 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2749 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2751 if (tdep
->st0_regnum
< 0)
2753 warning (_("Cannot find floating-point return value."));
2754 memset (valbuf
, 0, len
);
2758 /* Floating-point return values can be found in %st(0). Convert
2759 its contents to the desired type. This is probably not
2760 exactly how it would happen on the target itself, but it is
2761 the best we can do. */
2762 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2763 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2767 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2768 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2770 if (len
<= low_size
)
2772 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2773 memcpy (valbuf
, buf
, len
);
2775 else if (len
<= (low_size
+ high_size
))
2777 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2778 memcpy (valbuf
, buf
, low_size
);
2779 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2780 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2783 internal_error (__FILE__
, __LINE__
,
2784 _("Cannot extract return value of %d bytes long."),
2789 /* Write, for architecture GDBARCH, a function return value of TYPE
2790 from VALBUF into REGCACHE. */
2793 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2794 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2797 int len
= TYPE_LENGTH (type
);
2799 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2802 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2804 if (tdep
->st0_regnum
< 0)
2806 warning (_("Cannot set floating-point return value."));
2810 /* Returning floating-point values is a bit tricky. Apart from
2811 storing the return value in %st(0), we have to simulate the
2812 state of the FPU at function return point. */
2814 /* Convert the value found in VALBUF to the extended
2815 floating-point format used by the FPU. This is probably
2816 not exactly how it would happen on the target itself, but
2817 it is the best we can do. */
2818 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2819 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2821 /* Set the top of the floating-point register stack to 7. The
2822 actual value doesn't really matter, but 7 is what a normal
2823 function return would end up with if the program started out
2824 with a freshly initialized FPU. */
2825 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2827 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2829 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2830 the floating-point register stack to 7, the appropriate value
2831 for the tag word is 0x3fff. */
2832 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2836 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2837 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2839 if (len
<= low_size
)
2840 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2841 else if (len
<= (low_size
+ high_size
))
2843 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2844 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2845 len
- low_size
, valbuf
+ low_size
);
2848 internal_error (__FILE__
, __LINE__
,
2849 _("Cannot store return value of %d bytes long."), len
);
2854 /* This is the variable that is set with "set struct-convention", and
2855 its legitimate values. */
2856 static const char default_struct_convention
[] = "default";
2857 static const char pcc_struct_convention
[] = "pcc";
2858 static const char reg_struct_convention
[] = "reg";
2859 static const char *const valid_conventions
[] =
2861 default_struct_convention
,
2862 pcc_struct_convention
,
2863 reg_struct_convention
,
2866 static const char *struct_convention
= default_struct_convention
;
2868 /* Return non-zero if TYPE, which is assumed to be a structure,
2869 a union type, or an array type, should be returned in registers
2870 for architecture GDBARCH. */
2873 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2876 enum type_code code
= TYPE_CODE (type
);
2877 int len
= TYPE_LENGTH (type
);
2879 gdb_assert (code
== TYPE_CODE_STRUCT
2880 || code
== TYPE_CODE_UNION
2881 || code
== TYPE_CODE_ARRAY
);
2883 if (struct_convention
== pcc_struct_convention
2884 || (struct_convention
== default_struct_convention
2885 && tdep
->struct_return
== pcc_struct_return
))
2888 /* Structures consisting of a single `float', `double' or 'long
2889 double' member are returned in %st(0). */
2890 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2892 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2893 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2894 return (len
== 4 || len
== 8 || len
== 12);
2897 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2900 /* Determine, for architecture GDBARCH, how a return value of TYPE
2901 should be returned. If it is supposed to be returned in registers,
2902 and READBUF is non-zero, read the appropriate value from REGCACHE,
2903 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2904 from WRITEBUF into REGCACHE. */
2906 static enum return_value_convention
2907 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2908 struct type
*type
, struct regcache
*regcache
,
2909 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2911 enum type_code code
= TYPE_CODE (type
);
2913 if (((code
== TYPE_CODE_STRUCT
2914 || code
== TYPE_CODE_UNION
2915 || code
== TYPE_CODE_ARRAY
)
2916 && !i386_reg_struct_return_p (gdbarch
, type
))
2917 /* Complex double and long double uses the struct return covention. */
2918 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2919 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2920 /* 128-bit decimal float uses the struct return convention. */
2921 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2923 /* The System V ABI says that:
2925 "A function that returns a structure or union also sets %eax
2926 to the value of the original address of the caller's area
2927 before it returns. Thus when the caller receives control
2928 again, the address of the returned object resides in register
2929 %eax and can be used to access the object."
2931 So the ABI guarantees that we can always find the return
2932 value just after the function has returned. */
2934 /* Note that the ABI doesn't mention functions returning arrays,
2935 which is something possible in certain languages such as Ada.
2936 In this case, the value is returned as if it was wrapped in
2937 a record, so the convention applied to records also applies
2944 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2945 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2948 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2951 /* This special case is for structures consisting of a single
2952 `float', `double' or 'long double' member. These structures are
2953 returned in %st(0). For these structures, we call ourselves
2954 recursively, changing TYPE into the type of the first member of
2955 the structure. Since that should work for all structures that
2956 have only one member, we don't bother to check the member's type
2958 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2960 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2961 return i386_return_value (gdbarch
, function
, type
, regcache
,
2966 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2968 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2970 return RETURN_VALUE_REGISTER_CONVENTION
;
2975 i387_ext_type (struct gdbarch
*gdbarch
)
2977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2979 if (!tdep
->i387_ext_type
)
2981 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2982 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2985 return tdep
->i387_ext_type
;
2988 /* Construct type for pseudo BND registers. We can't use
2989 tdesc_find_type since a complement of one value has to be used
2990 to describe the upper bound. */
2992 static struct type
*
2993 i386_bnd_type (struct gdbarch
*gdbarch
)
2995 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2998 if (!tdep
->i386_bnd_type
)
3000 struct type
*t
, *bound_t
;
3001 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3003 /* The type we're building is described bellow: */
3008 void *ubound
; /* One complement of raw ubound field. */
3012 t
= arch_composite_type (gdbarch
,
3013 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3015 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3016 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3018 TYPE_NAME (t
) = "builtin_type_bound128";
3019 tdep
->i386_bnd_type
= t
;
3022 return tdep
->i386_bnd_type
;
3025 /* Construct vector type for pseudo ZMM registers. We can't use
3026 tdesc_find_type since ZMM isn't described in target description. */
3028 static struct type
*
3029 i386_zmm_type (struct gdbarch
*gdbarch
)
3031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3033 if (!tdep
->i386_zmm_type
)
3035 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3037 /* The type we're building is this: */
3039 union __gdb_builtin_type_vec512i
3041 int128_t uint128
[4];
3042 int64_t v4_int64
[8];
3043 int32_t v8_int32
[16];
3044 int16_t v16_int16
[32];
3045 int8_t v32_int8
[64];
3046 double v4_double
[8];
3053 t
= arch_composite_type (gdbarch
,
3054 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3055 append_composite_type_field (t
, "v16_float",
3056 init_vector_type (bt
->builtin_float
, 16));
3057 append_composite_type_field (t
, "v8_double",
3058 init_vector_type (bt
->builtin_double
, 8));
3059 append_composite_type_field (t
, "v64_int8",
3060 init_vector_type (bt
->builtin_int8
, 64));
3061 append_composite_type_field (t
, "v32_int16",
3062 init_vector_type (bt
->builtin_int16
, 32));
3063 append_composite_type_field (t
, "v16_int32",
3064 init_vector_type (bt
->builtin_int32
, 16));
3065 append_composite_type_field (t
, "v8_int64",
3066 init_vector_type (bt
->builtin_int64
, 8));
3067 append_composite_type_field (t
, "v4_int128",
3068 init_vector_type (bt
->builtin_int128
, 4));
3070 TYPE_VECTOR (t
) = 1;
3071 TYPE_NAME (t
) = "builtin_type_vec512i";
3072 tdep
->i386_zmm_type
= t
;
3075 return tdep
->i386_zmm_type
;
3078 /* Construct vector type for pseudo YMM registers. We can't use
3079 tdesc_find_type since YMM isn't described in target description. */
3081 static struct type
*
3082 i386_ymm_type (struct gdbarch
*gdbarch
)
3084 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3086 if (!tdep
->i386_ymm_type
)
3088 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3090 /* The type we're building is this: */
3092 union __gdb_builtin_type_vec256i
3094 int128_t uint128
[2];
3095 int64_t v2_int64
[4];
3096 int32_t v4_int32
[8];
3097 int16_t v8_int16
[16];
3098 int8_t v16_int8
[32];
3099 double v2_double
[4];
3106 t
= arch_composite_type (gdbarch
,
3107 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3108 append_composite_type_field (t
, "v8_float",
3109 init_vector_type (bt
->builtin_float
, 8));
3110 append_composite_type_field (t
, "v4_double",
3111 init_vector_type (bt
->builtin_double
, 4));
3112 append_composite_type_field (t
, "v32_int8",
3113 init_vector_type (bt
->builtin_int8
, 32));
3114 append_composite_type_field (t
, "v16_int16",
3115 init_vector_type (bt
->builtin_int16
, 16));
3116 append_composite_type_field (t
, "v8_int32",
3117 init_vector_type (bt
->builtin_int32
, 8));
3118 append_composite_type_field (t
, "v4_int64",
3119 init_vector_type (bt
->builtin_int64
, 4));
3120 append_composite_type_field (t
, "v2_int128",
3121 init_vector_type (bt
->builtin_int128
, 2));
3123 TYPE_VECTOR (t
) = 1;
3124 TYPE_NAME (t
) = "builtin_type_vec256i";
3125 tdep
->i386_ymm_type
= t
;
3128 return tdep
->i386_ymm_type
;
3131 /* Construct vector type for MMX registers. */
3132 static struct type
*
3133 i386_mmx_type (struct gdbarch
*gdbarch
)
3135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3137 if (!tdep
->i386_mmx_type
)
3139 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3141 /* The type we're building is this: */
3143 union __gdb_builtin_type_vec64i
3146 int32_t v2_int32
[2];
3147 int16_t v4_int16
[4];
3154 t
= arch_composite_type (gdbarch
,
3155 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3157 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3158 append_composite_type_field (t
, "v2_int32",
3159 init_vector_type (bt
->builtin_int32
, 2));
3160 append_composite_type_field (t
, "v4_int16",
3161 init_vector_type (bt
->builtin_int16
, 4));
3162 append_composite_type_field (t
, "v8_int8",
3163 init_vector_type (bt
->builtin_int8
, 8));
3165 TYPE_VECTOR (t
) = 1;
3166 TYPE_NAME (t
) = "builtin_type_vec64i";
3167 tdep
->i386_mmx_type
= t
;
3170 return tdep
->i386_mmx_type
;
3173 /* Return the GDB type object for the "standard" data type of data in
3177 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3179 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3180 return i386_bnd_type (gdbarch
);
3181 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3182 return i386_mmx_type (gdbarch
);
3183 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3184 return i386_ymm_type (gdbarch
);
3185 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3186 return i386_ymm_type (gdbarch
);
3187 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3188 return i386_zmm_type (gdbarch
);
3191 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3192 if (i386_byte_regnum_p (gdbarch
, regnum
))
3193 return bt
->builtin_int8
;
3194 else if (i386_word_regnum_p (gdbarch
, regnum
))
3195 return bt
->builtin_int16
;
3196 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3197 return bt
->builtin_int32
;
3198 else if (i386_k_regnum_p (gdbarch
, regnum
))
3199 return bt
->builtin_int64
;
3202 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3205 /* Map a cooked register onto a raw register or memory. For the i386,
3206 the MMX registers need to be mapped onto floating point registers. */
3209 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
3211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
3216 mmxreg
= regnum
- tdep
->mm0_regnum
;
3217 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
3218 tos
= (fstat
>> 11) & 0x7;
3219 fpreg
= (mmxreg
+ tos
) % 8;
3221 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3224 /* A helper function for us by i386_pseudo_register_read_value and
3225 amd64_pseudo_register_read_value. It does all the work but reads
3226 the data into an already-allocated value. */
3229 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3230 struct regcache
*regcache
,
3232 struct value
*result_value
)
3234 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3235 enum register_status status
;
3236 gdb_byte
*buf
= value_contents_raw (result_value
);
3238 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3240 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3242 /* Extract (always little endian). */
3243 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3244 if (status
!= REG_VALID
)
3245 mark_value_bytes_unavailable (result_value
, 0,
3246 TYPE_LENGTH (value_type (result_value
)));
3248 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3252 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3253 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3255 regnum
-= tdep
->bnd0_regnum
;
3257 /* Extract (always little endian). Read lower 128bits. */
3258 status
= regcache_raw_read (regcache
,
3259 I387_BND0R_REGNUM (tdep
) + regnum
,
3261 if (status
!= REG_VALID
)
3262 mark_value_bytes_unavailable (result_value
, 0, 16);
3265 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3266 LONGEST upper
, lower
;
3267 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3269 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3270 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3273 memcpy (buf
, &lower
, size
);
3274 memcpy (buf
+ size
, &upper
, size
);
3277 else if (i386_k_regnum_p (gdbarch
, regnum
))
3279 regnum
-= tdep
->k0_regnum
;
3281 /* Extract (always little endian). */
3282 status
= regcache_raw_read (regcache
,
3283 tdep
->k0_regnum
+ regnum
,
3285 if (status
!= REG_VALID
)
3286 mark_value_bytes_unavailable (result_value
, 0, 8);
3288 memcpy (buf
, raw_buf
, 8);
3290 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3292 regnum
-= tdep
->zmm0_regnum
;
3294 if (regnum
< num_lower_zmm_regs
)
3296 /* Extract (always little endian). Read lower 128bits. */
3297 status
= regcache_raw_read (regcache
,
3298 I387_XMM0_REGNUM (tdep
) + regnum
,
3300 if (status
!= REG_VALID
)
3301 mark_value_bytes_unavailable (result_value
, 0, 16);
3303 memcpy (buf
, raw_buf
, 16);
3305 /* Extract (always little endian). Read upper 128bits. */
3306 status
= regcache_raw_read (regcache
,
3307 tdep
->ymm0h_regnum
+ regnum
,
3309 if (status
!= REG_VALID
)
3310 mark_value_bytes_unavailable (result_value
, 16, 16);
3312 memcpy (buf
+ 16, raw_buf
, 16);
3316 /* Extract (always little endian). Read lower 128bits. */
3317 status
= regcache_raw_read (regcache
,
3318 I387_XMM16_REGNUM (tdep
) + regnum
3319 - num_lower_zmm_regs
,
3321 if (status
!= REG_VALID
)
3322 mark_value_bytes_unavailable (result_value
, 0, 16);
3324 memcpy (buf
, raw_buf
, 16);
3326 /* Extract (always little endian). Read upper 128bits. */
3327 status
= regcache_raw_read (regcache
,
3328 I387_YMM16H_REGNUM (tdep
) + regnum
3329 - num_lower_zmm_regs
,
3331 if (status
!= REG_VALID
)
3332 mark_value_bytes_unavailable (result_value
, 16, 16);
3334 memcpy (buf
+ 16, raw_buf
, 16);
3337 /* Read upper 256bits. */
3338 status
= regcache_raw_read (regcache
,
3339 tdep
->zmm0h_regnum
+ regnum
,
3341 if (status
!= REG_VALID
)
3342 mark_value_bytes_unavailable (result_value
, 32, 32);
3344 memcpy (buf
+ 32, raw_buf
, 32);
3346 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3348 regnum
-= tdep
->ymm0_regnum
;
3350 /* Extract (always little endian). Read lower 128bits. */
3351 status
= regcache_raw_read (regcache
,
3352 I387_XMM0_REGNUM (tdep
) + regnum
,
3354 if (status
!= REG_VALID
)
3355 mark_value_bytes_unavailable (result_value
, 0, 16);
3357 memcpy (buf
, raw_buf
, 16);
3358 /* Read upper 128bits. */
3359 status
= regcache_raw_read (regcache
,
3360 tdep
->ymm0h_regnum
+ regnum
,
3362 if (status
!= REG_VALID
)
3363 mark_value_bytes_unavailable (result_value
, 16, 32);
3365 memcpy (buf
+ 16, raw_buf
, 16);
3367 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3369 regnum
-= tdep
->ymm16_regnum
;
3370 /* Extract (always little endian). Read lower 128bits. */
3371 status
= regcache_raw_read (regcache
,
3372 I387_XMM16_REGNUM (tdep
) + regnum
,
3374 if (status
!= REG_VALID
)
3375 mark_value_bytes_unavailable (result_value
, 0, 16);
3377 memcpy (buf
, raw_buf
, 16);
3378 /* Read upper 128bits. */
3379 status
= regcache_raw_read (regcache
,
3380 tdep
->ymm16h_regnum
+ regnum
,
3382 if (status
!= REG_VALID
)
3383 mark_value_bytes_unavailable (result_value
, 16, 16);
3385 memcpy (buf
+ 16, raw_buf
, 16);
3387 else if (i386_word_regnum_p (gdbarch
, regnum
))
3389 int gpnum
= regnum
- tdep
->ax_regnum
;
3391 /* Extract (always little endian). */
3392 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3393 if (status
!= REG_VALID
)
3394 mark_value_bytes_unavailable (result_value
, 0,
3395 TYPE_LENGTH (value_type (result_value
)));
3397 memcpy (buf
, raw_buf
, 2);
3399 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3401 /* Check byte pseudo registers last since this function will
3402 be called from amd64_pseudo_register_read, which handles
3403 byte pseudo registers differently. */
3404 int gpnum
= regnum
- tdep
->al_regnum
;
3406 /* Extract (always little endian). We read both lower and
3408 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3409 if (status
!= REG_VALID
)
3410 mark_value_bytes_unavailable (result_value
, 0,
3411 TYPE_LENGTH (value_type (result_value
)));
3412 else if (gpnum
>= 4)
3413 memcpy (buf
, raw_buf
+ 1, 1);
3415 memcpy (buf
, raw_buf
, 1);
3418 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3422 static struct value
*
3423 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3424 struct regcache
*regcache
,
3427 struct value
*result
;
3429 result
= allocate_value (register_type (gdbarch
, regnum
));
3430 VALUE_LVAL (result
) = lval_register
;
3431 VALUE_REGNUM (result
) = regnum
;
3433 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3439 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3440 int regnum
, const gdb_byte
*buf
)
3442 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3444 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3446 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3449 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3450 /* ... Modify ... (always little endian). */
3451 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3453 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3457 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3459 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3461 ULONGEST upper
, lower
;
3462 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3463 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3465 /* New values from input value. */
3466 regnum
-= tdep
->bnd0_regnum
;
3467 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3468 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3470 /* Fetching register buffer. */
3471 regcache_raw_read (regcache
,
3472 I387_BND0R_REGNUM (tdep
) + regnum
,
3477 /* Set register bits. */
3478 memcpy (raw_buf
, &lower
, 8);
3479 memcpy (raw_buf
+ 8, &upper
, 8);
3482 regcache_raw_write (regcache
,
3483 I387_BND0R_REGNUM (tdep
) + regnum
,
3486 else if (i386_k_regnum_p (gdbarch
, regnum
))
3488 regnum
-= tdep
->k0_regnum
;
3490 regcache_raw_write (regcache
,
3491 tdep
->k0_regnum
+ regnum
,
3494 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3496 regnum
-= tdep
->zmm0_regnum
;
3498 if (regnum
< num_lower_zmm_regs
)
3500 /* Write lower 128bits. */
3501 regcache_raw_write (regcache
,
3502 I387_XMM0_REGNUM (tdep
) + regnum
,
3504 /* Write upper 128bits. */
3505 regcache_raw_write (regcache
,
3506 I387_YMM0_REGNUM (tdep
) + regnum
,
3511 /* Write lower 128bits. */
3512 regcache_raw_write (regcache
,
3513 I387_XMM16_REGNUM (tdep
) + regnum
3514 - num_lower_zmm_regs
,
3516 /* Write upper 128bits. */
3517 regcache_raw_write (regcache
,
3518 I387_YMM16H_REGNUM (tdep
) + regnum
3519 - num_lower_zmm_regs
,
3522 /* Write upper 256bits. */
3523 regcache_raw_write (regcache
,
3524 tdep
->zmm0h_regnum
+ regnum
,
3527 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3529 regnum
-= tdep
->ymm0_regnum
;
3531 /* ... Write lower 128bits. */
3532 regcache_raw_write (regcache
,
3533 I387_XMM0_REGNUM (tdep
) + regnum
,
3535 /* ... Write upper 128bits. */
3536 regcache_raw_write (regcache
,
3537 tdep
->ymm0h_regnum
+ regnum
,
3540 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3542 regnum
-= tdep
->ymm16_regnum
;
3544 /* ... Write lower 128bits. */
3545 regcache_raw_write (regcache
,
3546 I387_XMM16_REGNUM (tdep
) + regnum
,
3548 /* ... Write upper 128bits. */
3549 regcache_raw_write (regcache
,
3550 tdep
->ymm16h_regnum
+ regnum
,
3553 else if (i386_word_regnum_p (gdbarch
, regnum
))
3555 int gpnum
= regnum
- tdep
->ax_regnum
;
3558 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3559 /* ... Modify ... (always little endian). */
3560 memcpy (raw_buf
, buf
, 2);
3562 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3564 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3566 /* Check byte pseudo registers last since this function will
3567 be called from amd64_pseudo_register_read, which handles
3568 byte pseudo registers differently. */
3569 int gpnum
= regnum
- tdep
->al_regnum
;
3571 /* Read ... We read both lower and upper registers. */
3572 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3573 /* ... Modify ... (always little endian). */
3575 memcpy (raw_buf
+ 1, buf
, 1);
3577 memcpy (raw_buf
, buf
, 1);
3579 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3582 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3587 /* Return the register number of the register allocated by GCC after
3588 REGNUM, or -1 if there is no such register. */
3591 i386_next_regnum (int regnum
)
3593 /* GCC allocates the registers in the order:
3595 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3597 Since storing a variable in %esp doesn't make any sense we return
3598 -1 for %ebp and for %esp itself. */
3599 static int next_regnum
[] =
3601 I386_EDX_REGNUM
, /* Slot for %eax. */
3602 I386_EBX_REGNUM
, /* Slot for %ecx. */
3603 I386_ECX_REGNUM
, /* Slot for %edx. */
3604 I386_ESI_REGNUM
, /* Slot for %ebx. */
3605 -1, -1, /* Slots for %esp and %ebp. */
3606 I386_EDI_REGNUM
, /* Slot for %esi. */
3607 I386_EBP_REGNUM
/* Slot for %edi. */
3610 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3611 return next_regnum
[regnum
];
3616 /* Return nonzero if a value of type TYPE stored in register REGNUM
3617 needs any special handling. */
3620 i386_convert_register_p (struct gdbarch
*gdbarch
,
3621 int regnum
, struct type
*type
)
3623 int len
= TYPE_LENGTH (type
);
3625 /* Values may be spread across multiple registers. Most debugging
3626 formats aren't expressive enough to specify the locations, so
3627 some heuristics is involved. Right now we only handle types that
3628 have a length that is a multiple of the word size, since GCC
3629 doesn't seem to put any other types into registers. */
3630 if (len
> 4 && len
% 4 == 0)
3632 int last_regnum
= regnum
;
3636 last_regnum
= i386_next_regnum (last_regnum
);
3640 if (last_regnum
!= -1)
3644 return i387_convert_register_p (gdbarch
, regnum
, type
);
3647 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3648 return its contents in TO. */
3651 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3652 struct type
*type
, gdb_byte
*to
,
3653 int *optimizedp
, int *unavailablep
)
3655 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3656 int len
= TYPE_LENGTH (type
);
3658 if (i386_fp_regnum_p (gdbarch
, regnum
))
3659 return i387_register_to_value (frame
, regnum
, type
, to
,
3660 optimizedp
, unavailablep
);
3662 /* Read a value spread across multiple registers. */
3664 gdb_assert (len
> 4 && len
% 4 == 0);
3668 gdb_assert (regnum
!= -1);
3669 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3671 if (!get_frame_register_bytes (frame
, regnum
, 0,
3672 register_size (gdbarch
, regnum
),
3673 to
, optimizedp
, unavailablep
))
3676 regnum
= i386_next_regnum (regnum
);
3681 *optimizedp
= *unavailablep
= 0;
3685 /* Write the contents FROM of a value of type TYPE into register
3686 REGNUM in frame FRAME. */
3689 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3690 struct type
*type
, const gdb_byte
*from
)
3692 int len
= TYPE_LENGTH (type
);
3694 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3696 i387_value_to_register (frame
, regnum
, type
, from
);
3700 /* Write a value spread across multiple registers. */
3702 gdb_assert (len
> 4 && len
% 4 == 0);
3706 gdb_assert (regnum
!= -1);
3707 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3709 put_frame_register (frame
, regnum
, from
);
3710 regnum
= i386_next_regnum (regnum
);
3716 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3717 in the general-purpose register set REGSET to register cache
3718 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3721 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3722 int regnum
, const void *gregs
, size_t len
)
3724 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3725 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3726 const gdb_byte
*regs
= gregs
;
3729 gdb_assert (len
== tdep
->sizeof_gregset
);
3731 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3733 if ((regnum
== i
|| regnum
== -1)
3734 && tdep
->gregset_reg_offset
[i
] != -1)
3735 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3739 /* Collect register REGNUM from the register cache REGCACHE and store
3740 it in the buffer specified by GREGS and LEN as described by the
3741 general-purpose register set REGSET. If REGNUM is -1, do this for
3742 all registers in REGSET. */
3745 i386_collect_gregset (const struct regset
*regset
,
3746 const struct regcache
*regcache
,
3747 int regnum
, void *gregs
, size_t len
)
3749 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3750 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3751 gdb_byte
*regs
= gregs
;
3754 gdb_assert (len
== tdep
->sizeof_gregset
);
3756 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3758 if ((regnum
== i
|| regnum
== -1)
3759 && tdep
->gregset_reg_offset
[i
] != -1)
3760 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3764 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3765 in the floating-point register set REGSET to register cache
3766 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3769 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3770 int regnum
, const void *fpregs
, size_t len
)
3772 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3773 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3775 if (len
== I387_SIZEOF_FXSAVE
)
3777 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3781 gdb_assert (len
== tdep
->sizeof_fpregset
);
3782 i387_supply_fsave (regcache
, regnum
, fpregs
);
3785 /* Collect register REGNUM from the register cache REGCACHE and store
3786 it in the buffer specified by FPREGS and LEN as described by the
3787 floating-point register set REGSET. If REGNUM is -1, do this for
3788 all registers in REGSET. */
3791 i386_collect_fpregset (const struct regset
*regset
,
3792 const struct regcache
*regcache
,
3793 int regnum
, void *fpregs
, size_t len
)
3795 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3796 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3798 if (len
== I387_SIZEOF_FXSAVE
)
3800 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3804 gdb_assert (len
== tdep
->sizeof_fpregset
);
3805 i387_collect_fsave (regcache
, regnum
, fpregs
);
3808 /* Register set definitions. */
3810 const struct regset i386_gregset
=
3812 NULL
, i386_supply_gregset
, i386_collect_gregset
3815 const struct regset i386_fpregset
=
3817 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3820 /* Default iterator over core file register note sections. */
3823 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3824 iterate_over_regset_sections_cb
*cb
,
3826 const struct regcache
*regcache
)
3828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3830 cb (".reg", tdep
->sizeof_gregset
, &i386_gregset
, NULL
, cb_data
);
3831 if (tdep
->sizeof_fpregset
)
3832 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
3836 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3839 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3840 CORE_ADDR pc
, char *name
)
3842 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3843 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3846 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3848 unsigned long indirect
=
3849 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3850 struct minimal_symbol
*indsym
=
3851 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3852 const char *symname
= indsym
? MSYMBOL_LINKAGE_NAME (indsym
) : 0;
3856 if (strncmp (symname
, "__imp_", 6) == 0
3857 || strncmp (symname
, "_imp_", 5) == 0)
3859 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3862 return 0; /* Not a trampoline. */
3866 /* Return whether the THIS_FRAME corresponds to a sigtramp
3870 i386_sigtramp_p (struct frame_info
*this_frame
)
3872 CORE_ADDR pc
= get_frame_pc (this_frame
);
3875 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3876 return (name
&& strcmp ("_sigtramp", name
) == 0);
3880 /* We have two flavours of disassembly. The machinery on this page
3881 deals with switching between those. */
3884 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3886 gdb_assert (disassembly_flavor
== att_flavor
3887 || disassembly_flavor
== intel_flavor
);
3889 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3890 constified, cast to prevent a compiler warning. */
3891 info
->disassembler_options
= (char *) disassembly_flavor
;
3893 return print_insn_i386 (pc
, info
);
3897 /* There are a few i386 architecture variants that differ only
3898 slightly from the generic i386 target. For now, we don't give them
3899 their own source file, but include them here. As a consequence,
3900 they'll always be included. */
3902 /* System V Release 4 (SVR4). */
3904 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3908 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3910 CORE_ADDR pc
= get_frame_pc (this_frame
);
3913 /* The origin of these symbols is currently unknown. */
3914 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3915 return (name
&& (strcmp ("_sigreturn", name
) == 0
3916 || strcmp ("sigvechandler", name
) == 0));
3919 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3920 address of the associated sigcontext (ucontext) structure. */
3923 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3925 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3926 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3930 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3931 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3933 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3938 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3942 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3944 return (*s
== '$' /* Literal number. */
3945 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3946 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3947 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3950 /* Helper function for i386_stap_parse_special_token.
3952 This function parses operands of the form `-8+3+1(%rbp)', which
3953 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3955 Return 1 if the operand was parsed successfully, zero
3959 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
3960 struct stap_parse_info
*p
)
3962 const char *s
= p
->arg
;
3964 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3968 long displacements
[3];
3984 if (!isdigit ((unsigned char) *s
))
3987 displacements
[0] = strtol (s
, &endp
, 10);
3990 if (*s
!= '+' && *s
!= '-')
3992 /* We are not dealing with a triplet. */
4005 if (!isdigit ((unsigned char) *s
))
4008 displacements
[1] = strtol (s
, &endp
, 10);
4011 if (*s
!= '+' && *s
!= '-')
4013 /* We are not dealing with a triplet. */
4026 if (!isdigit ((unsigned char) *s
))
4029 displacements
[2] = strtol (s
, &endp
, 10);
4032 if (*s
!= '(' || s
[1] != '%')
4038 while (isalnum (*s
))
4044 len
= s
- start
- 1;
4045 regname
= alloca (len
+ 1);
4047 strncpy (regname
, start
, len
);
4048 regname
[len
] = '\0';
4050 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4051 error (_("Invalid register name `%s' on expression `%s'."),
4052 regname
, p
->saved_arg
);
4054 for (i
= 0; i
< 3; i
++)
4056 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4058 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4059 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4060 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4062 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4065 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4068 write_exp_string (&p
->pstate
, str
);
4069 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4071 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4072 write_exp_elt_type (&p
->pstate
,
4073 builtin_type (gdbarch
)->builtin_data_ptr
);
4074 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4076 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4077 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4078 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4080 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4081 write_exp_elt_type (&p
->pstate
,
4082 lookup_pointer_type (p
->arg_type
));
4083 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4085 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4095 /* Helper function for i386_stap_parse_special_token.
4097 This function parses operands of the form `register base +
4098 (register index * size) + offset', as represented in
4099 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4101 Return 1 if the operand was parsed successfully, zero
4105 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4106 struct stap_parse_info
*p
)
4108 const char *s
= p
->arg
;
4110 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4112 int offset_minus
= 0;
4121 struct stoken base_token
, index_token
;
4131 if (offset_minus
&& !isdigit (*s
))
4138 offset
= strtol (s
, &endp
, 10);
4142 if (*s
!= '(' || s
[1] != '%')
4148 while (isalnum (*s
))
4151 if (*s
!= ',' || s
[1] != '%')
4154 len_base
= s
- start
;
4155 base
= alloca (len_base
+ 1);
4156 strncpy (base
, start
, len_base
);
4157 base
[len_base
] = '\0';
4159 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4160 error (_("Invalid register name `%s' on expression `%s'."),
4161 base
, p
->saved_arg
);
4166 while (isalnum (*s
))
4169 len_index
= s
- start
;
4170 index
= alloca (len_index
+ 1);
4171 strncpy (index
, start
, len_index
);
4172 index
[len_index
] = '\0';
4174 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4175 error (_("Invalid register name `%s' on expression `%s'."),
4176 index
, p
->saved_arg
);
4178 if (*s
!= ',' && *s
!= ')')
4194 size
= strtol (s
, &endp
, 10);
4205 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4206 write_exp_elt_type (&p
->pstate
,
4207 builtin_type (gdbarch
)->builtin_long
);
4208 write_exp_elt_longcst (&p
->pstate
, offset
);
4209 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4211 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4214 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4215 base_token
.ptr
= base
;
4216 base_token
.length
= len_base
;
4217 write_exp_string (&p
->pstate
, base_token
);
4218 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4221 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4223 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4224 index_token
.ptr
= index
;
4225 index_token
.length
= len_index
;
4226 write_exp_string (&p
->pstate
, index_token
);
4227 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4231 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4232 write_exp_elt_type (&p
->pstate
,
4233 builtin_type (gdbarch
)->builtin_long
);
4234 write_exp_elt_longcst (&p
->pstate
, size
);
4235 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4237 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4238 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4241 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4243 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4244 write_exp_elt_type (&p
->pstate
,
4245 lookup_pointer_type (p
->arg_type
));
4246 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4248 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4258 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4262 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4263 struct stap_parse_info
*p
)
4265 /* In order to parse special tokens, we use a state-machine that go
4266 through every known token and try to get a match. */
4270 THREE_ARG_DISPLACEMENT
,
4274 current_state
= TRIPLET
;
4276 /* The special tokens to be parsed here are:
4278 - `register base + (register index * size) + offset', as represented
4279 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4281 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4282 `*(-8 + 3 - 1 + (void *) $eax)'. */
4284 while (current_state
!= DONE
)
4286 switch (current_state
)
4289 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4293 case THREE_ARG_DISPLACEMENT
:
4294 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4299 /* Advancing to the next state. */
4311 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4313 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4314 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4315 static const char *const stap_register_indirection_prefixes
[] = { "(",
4317 static const char *const stap_register_indirection_suffixes
[] = { ")",
4320 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4321 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4323 /* Registering SystemTap handlers. */
4324 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4325 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4326 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4327 stap_register_indirection_prefixes
);
4328 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4329 stap_register_indirection_suffixes
);
4330 set_gdbarch_stap_is_single_operand (gdbarch
,
4331 i386_stap_is_single_operand
);
4332 set_gdbarch_stap_parse_special_token (gdbarch
,
4333 i386_stap_parse_special_token
);
4336 /* System V Release 4 (SVR4). */
4339 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4343 /* System V Release 4 uses ELF. */
4344 i386_elf_init_abi (info
, gdbarch
);
4346 /* System V Release 4 has shared libraries. */
4347 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4349 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4350 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4351 tdep
->sc_pc_offset
= 36 + 14 * 4;
4352 tdep
->sc_sp_offset
= 36 + 17 * 4;
4354 tdep
->jb_pc_offset
= 20;
4360 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4362 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4364 /* DJGPP doesn't have any special frames for signal handlers. */
4365 tdep
->sigtramp_p
= NULL
;
4367 tdep
->jb_pc_offset
= 36;
4369 /* DJGPP does not support the SSE registers. */
4370 if (! tdesc_has_registers (info
.target_desc
))
4371 tdep
->tdesc
= tdesc_i386_mmx
;
4373 /* Native compiler is GCC, which uses the SVR4 register numbering
4374 even in COFF and STABS. See the comment in i386_gdbarch_init,
4375 before the calls to set_gdbarch_stab_reg_to_regnum and
4376 set_gdbarch_sdb_reg_to_regnum. */
4377 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4378 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4380 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
4384 /* i386 register groups. In addition to the normal groups, add "mmx"
4387 static struct reggroup
*i386_sse_reggroup
;
4388 static struct reggroup
*i386_mmx_reggroup
;
4391 i386_init_reggroups (void)
4393 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4394 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4398 i386_add_reggroups (struct gdbarch
*gdbarch
)
4400 reggroup_add (gdbarch
, i386_sse_reggroup
);
4401 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4402 reggroup_add (gdbarch
, general_reggroup
);
4403 reggroup_add (gdbarch
, float_reggroup
);
4404 reggroup_add (gdbarch
, all_reggroup
);
4405 reggroup_add (gdbarch
, save_reggroup
);
4406 reggroup_add (gdbarch
, restore_reggroup
);
4407 reggroup_add (gdbarch
, vector_reggroup
);
4408 reggroup_add (gdbarch
, system_reggroup
);
4412 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4413 struct reggroup
*group
)
4415 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4416 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4417 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4418 bndr_regnum_p
, bnd_regnum_p
, k_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4419 zmm_avx512_regnum_p
, mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4420 avx512_p
, avx_p
, sse_p
;
4422 /* Don't include pseudo registers, except for MMX, in any register
4424 if (i386_byte_regnum_p (gdbarch
, regnum
))
4427 if (i386_word_regnum_p (gdbarch
, regnum
))
4430 if (i386_dword_regnum_p (gdbarch
, regnum
))
4433 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4434 if (group
== i386_mmx_reggroup
)
4435 return mmx_regnum_p
;
4437 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4438 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4439 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4440 if (group
== i386_sse_reggroup
)
4441 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4443 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4444 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4445 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4447 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4448 == X86_XSTATE_AVX512_MASK
);
4449 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4450 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4451 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX512_MASK
)
4452 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4454 if (group
== vector_reggroup
)
4455 return (mmx_regnum_p
4456 || (zmm_regnum_p
&& avx512_p
)
4457 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4458 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4461 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4462 || i386_fpc_regnum_p (gdbarch
, regnum
));
4463 if (group
== float_reggroup
)
4466 /* For "info reg all", don't include upper YMM registers nor XMM
4467 registers when AVX is supported. */
4468 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4469 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4470 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4471 if (group
== all_reggroup
4472 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4473 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4475 || ymmh_avx512_regnum_p
4479 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4480 if (group
== all_reggroup
4481 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4482 return bnd_regnum_p
;
4484 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4485 if (group
== all_reggroup
4486 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4489 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4490 if (group
== all_reggroup
4491 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4492 return mpx_ctrl_regnum_p
;
4494 if (group
== general_reggroup
)
4495 return (!fp_regnum_p
4499 && !xmm_avx512_regnum_p
4502 && !ymm_avx512_regnum_p
4503 && !ymmh_avx512_regnum_p
4506 && !mpx_ctrl_regnum_p
4510 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4514 /* Get the ARGIth function argument for the current function. */
4517 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4520 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4521 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4522 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4523 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4526 #define PREFIX_REPZ 0x01
4527 #define PREFIX_REPNZ 0x02
4528 #define PREFIX_LOCK 0x04
4529 #define PREFIX_DATA 0x08
4530 #define PREFIX_ADDR 0x10
4542 /* i386 arith/logic operations */
4555 struct i386_record_s
4557 struct gdbarch
*gdbarch
;
4558 struct regcache
*regcache
;
4559 CORE_ADDR orig_addr
;
4565 uint8_t mod
, reg
, rm
;
4574 /* Parse the "modrm" part of the memory address irp->addr points at.
4575 Returns -1 if something goes wrong, 0 otherwise. */
4578 i386_record_modrm (struct i386_record_s
*irp
)
4580 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4582 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4586 irp
->mod
= (irp
->modrm
>> 6) & 3;
4587 irp
->reg
= (irp
->modrm
>> 3) & 7;
4588 irp
->rm
= irp
->modrm
& 7;
4593 /* Extract the memory address that the current instruction writes to,
4594 and return it in *ADDR. Return -1 if something goes wrong. */
4597 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4599 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4600 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4605 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4612 uint8_t base
= irp
->rm
;
4617 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4620 scale
= (byte
>> 6) & 3;
4621 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4629 if ((base
& 7) == 5)
4632 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4635 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4636 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4637 *addr
+= irp
->addr
+ irp
->rip_offset
;
4641 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4644 *addr
= (int8_t) buf
[0];
4647 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4649 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4657 if (base
== 4 && irp
->popl_esp_hack
)
4658 *addr
+= irp
->popl_esp_hack
;
4659 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4662 if (irp
->aflag
== 2)
4667 *addr
= (uint32_t) (offset64
+ *addr
);
4669 if (havesib
&& (index
!= 4 || scale
!= 0))
4671 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4673 if (irp
->aflag
== 2)
4674 *addr
+= offset64
<< scale
;
4676 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4681 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4682 address from 32-bit to 64-bit. */
4683 *addr
= (uint32_t) *addr
;
4694 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4697 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4703 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4706 *addr
= (int8_t) buf
[0];
4709 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4712 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4719 regcache_raw_read_unsigned (irp
->regcache
,
4720 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4722 *addr
= (uint32_t) (*addr
+ offset64
);
4723 regcache_raw_read_unsigned (irp
->regcache
,
4724 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4726 *addr
= (uint32_t) (*addr
+ offset64
);
4729 regcache_raw_read_unsigned (irp
->regcache
,
4730 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4732 *addr
= (uint32_t) (*addr
+ offset64
);
4733 regcache_raw_read_unsigned (irp
->regcache
,
4734 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4736 *addr
= (uint32_t) (*addr
+ offset64
);
4739 regcache_raw_read_unsigned (irp
->regcache
,
4740 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4742 *addr
= (uint32_t) (*addr
+ offset64
);
4743 regcache_raw_read_unsigned (irp
->regcache
,
4744 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4746 *addr
= (uint32_t) (*addr
+ offset64
);
4749 regcache_raw_read_unsigned (irp
->regcache
,
4750 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4752 *addr
= (uint32_t) (*addr
+ offset64
);
4753 regcache_raw_read_unsigned (irp
->regcache
,
4754 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4756 *addr
= (uint32_t) (*addr
+ offset64
);
4759 regcache_raw_read_unsigned (irp
->regcache
,
4760 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4762 *addr
= (uint32_t) (*addr
+ offset64
);
4765 regcache_raw_read_unsigned (irp
->regcache
,
4766 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4768 *addr
= (uint32_t) (*addr
+ offset64
);
4771 regcache_raw_read_unsigned (irp
->regcache
,
4772 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4774 *addr
= (uint32_t) (*addr
+ offset64
);
4777 regcache_raw_read_unsigned (irp
->regcache
,
4778 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4780 *addr
= (uint32_t) (*addr
+ offset64
);
4790 /* Record the address and contents of the memory that will be changed
4791 by the current instruction. Return -1 if something goes wrong, 0
4795 i386_record_lea_modrm (struct i386_record_s
*irp
)
4797 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4800 if (irp
->override
>= 0)
4802 if (record_full_memory_query
)
4806 target_terminal_ours ();
4808 Process record ignores the memory change of instruction at address %s\n\
4809 because it can't get the value of the segment register.\n\
4810 Do you want to stop the program?"),
4811 paddress (gdbarch
, irp
->orig_addr
));
4812 target_terminal_inferior ();
4820 if (i386_record_lea_modrm_addr (irp
, &addr
))
4823 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4829 /* Record the effects of a push operation. Return -1 if something
4830 goes wrong, 0 otherwise. */
4833 i386_record_push (struct i386_record_s
*irp
, int size
)
4837 if (record_full_arch_list_add_reg (irp
->regcache
,
4838 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4840 regcache_raw_read_unsigned (irp
->regcache
,
4841 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4843 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4850 /* Defines contents to record. */
4851 #define I386_SAVE_FPU_REGS 0xfffd
4852 #define I386_SAVE_FPU_ENV 0xfffe
4853 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4855 /* Record the values of the floating point registers which will be
4856 changed by the current instruction. Returns -1 if something is
4857 wrong, 0 otherwise. */
4859 static int i386_record_floats (struct gdbarch
*gdbarch
,
4860 struct i386_record_s
*ir
,
4863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4866 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4867 happen. Currently we store st0-st7 registers, but we need not store all
4868 registers all the time, in future we use ftag register and record only
4869 those who are not marked as an empty. */
4871 if (I386_SAVE_FPU_REGS
== iregnum
)
4873 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4875 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4879 else if (I386_SAVE_FPU_ENV
== iregnum
)
4881 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4883 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4887 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4889 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4891 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4895 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4896 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4898 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4903 /* Parameter error. */
4906 if(I386_SAVE_FPU_ENV
!= iregnum
)
4908 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4910 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4917 /* Parse the current instruction, and record the values of the
4918 registers and memory that will be changed by the current
4919 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4921 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4922 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4925 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4926 CORE_ADDR input_addr
)
4928 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4934 gdb_byte buf
[MAX_REGISTER_SIZE
];
4935 struct i386_record_s ir
;
4936 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4940 memset (&ir
, 0, sizeof (struct i386_record_s
));
4941 ir
.regcache
= regcache
;
4942 ir
.addr
= input_addr
;
4943 ir
.orig_addr
= input_addr
;
4947 ir
.popl_esp_hack
= 0;
4948 ir
.regmap
= tdep
->record_regmap
;
4949 ir
.gdbarch
= gdbarch
;
4951 if (record_debug
> 1)
4952 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4954 paddress (gdbarch
, ir
.addr
));
4959 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4962 switch (opcode8
) /* Instruction prefixes */
4964 case REPE_PREFIX_OPCODE
:
4965 prefixes
|= PREFIX_REPZ
;
4967 case REPNE_PREFIX_OPCODE
:
4968 prefixes
|= PREFIX_REPNZ
;
4970 case LOCK_PREFIX_OPCODE
:
4971 prefixes
|= PREFIX_LOCK
;
4973 case CS_PREFIX_OPCODE
:
4974 ir
.override
= X86_RECORD_CS_REGNUM
;
4976 case SS_PREFIX_OPCODE
:
4977 ir
.override
= X86_RECORD_SS_REGNUM
;
4979 case DS_PREFIX_OPCODE
:
4980 ir
.override
= X86_RECORD_DS_REGNUM
;
4982 case ES_PREFIX_OPCODE
:
4983 ir
.override
= X86_RECORD_ES_REGNUM
;
4985 case FS_PREFIX_OPCODE
:
4986 ir
.override
= X86_RECORD_FS_REGNUM
;
4988 case GS_PREFIX_OPCODE
:
4989 ir
.override
= X86_RECORD_GS_REGNUM
;
4991 case DATA_PREFIX_OPCODE
:
4992 prefixes
|= PREFIX_DATA
;
4994 case ADDR_PREFIX_OPCODE
:
4995 prefixes
|= PREFIX_ADDR
;
4997 case 0x40: /* i386 inc %eax */
4998 case 0x41: /* i386 inc %ecx */
4999 case 0x42: /* i386 inc %edx */
5000 case 0x43: /* i386 inc %ebx */
5001 case 0x44: /* i386 inc %esp */
5002 case 0x45: /* i386 inc %ebp */
5003 case 0x46: /* i386 inc %esi */
5004 case 0x47: /* i386 inc %edi */
5005 case 0x48: /* i386 dec %eax */
5006 case 0x49: /* i386 dec %ecx */
5007 case 0x4a: /* i386 dec %edx */
5008 case 0x4b: /* i386 dec %ebx */
5009 case 0x4c: /* i386 dec %esp */
5010 case 0x4d: /* i386 dec %ebp */
5011 case 0x4e: /* i386 dec %esi */
5012 case 0x4f: /* i386 dec %edi */
5013 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5016 rex_w
= (opcode8
>> 3) & 1;
5017 rex_r
= (opcode8
& 0x4) << 1;
5018 ir
.rex_x
= (opcode8
& 0x2) << 2;
5019 ir
.rex_b
= (opcode8
& 0x1) << 3;
5021 else /* 32 bit target */
5030 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5036 if (prefixes
& PREFIX_DATA
)
5039 if (prefixes
& PREFIX_ADDR
)
5041 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5044 /* Now check op code. */
5045 opcode
= (uint32_t) opcode8
;
5050 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5053 opcode
= (uint32_t) opcode8
| 0x0f00;
5057 case 0x00: /* arith & logic */
5105 if (((opcode
>> 3) & 7) != OP_CMPL
)
5107 if ((opcode
& 1) == 0)
5110 ir
.ot
= ir
.dflag
+ OT_WORD
;
5112 switch ((opcode
>> 1) & 3)
5114 case 0: /* OP Ev, Gv */
5115 if (i386_record_modrm (&ir
))
5119 if (i386_record_lea_modrm (&ir
))
5125 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5127 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5130 case 1: /* OP Gv, Ev */
5131 if (i386_record_modrm (&ir
))
5134 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5136 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5138 case 2: /* OP A, Iv */
5139 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5143 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5146 case 0x80: /* GRP1 */
5150 if (i386_record_modrm (&ir
))
5153 if (ir
.reg
!= OP_CMPL
)
5155 if ((opcode
& 1) == 0)
5158 ir
.ot
= ir
.dflag
+ OT_WORD
;
5165 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5166 if (i386_record_lea_modrm (&ir
))
5170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5172 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5175 case 0x40: /* inc */
5184 case 0x48: /* dec */
5193 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5194 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5197 case 0xf6: /* GRP3 */
5199 if ((opcode
& 1) == 0)
5202 ir
.ot
= ir
.dflag
+ OT_WORD
;
5203 if (i386_record_modrm (&ir
))
5206 if (ir
.mod
!= 3 && ir
.reg
== 0)
5207 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5212 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5218 if (i386_record_lea_modrm (&ir
))
5224 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5226 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5228 if (ir
.reg
== 3) /* neg */
5229 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5235 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5236 if (ir
.ot
!= OT_BYTE
)
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5242 opcode
= opcode
<< 8 | ir
.modrm
;
5248 case 0xfe: /* GRP4 */
5249 case 0xff: /* GRP5 */
5250 if (i386_record_modrm (&ir
))
5252 if (ir
.reg
>= 2 && opcode
== 0xfe)
5255 opcode
= opcode
<< 8 | ir
.modrm
;
5262 if ((opcode
& 1) == 0)
5265 ir
.ot
= ir
.dflag
+ OT_WORD
;
5268 if (i386_record_lea_modrm (&ir
))
5274 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5281 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5283 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5288 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5289 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5291 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5295 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5298 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5300 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5305 opcode
= opcode
<< 8 | ir
.modrm
;
5311 case 0x84: /* test */
5315 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5318 case 0x98: /* CWDE/CBW */
5319 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5322 case 0x99: /* CDQ/CWD */
5323 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5327 case 0x0faf: /* imul */
5330 ir
.ot
= ir
.dflag
+ OT_WORD
;
5331 if (i386_record_modrm (&ir
))
5334 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5335 else if (opcode
== 0x6b)
5338 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5344 case 0x0fc0: /* xadd */
5346 if ((opcode
& 1) == 0)
5349 ir
.ot
= ir
.dflag
+ OT_WORD
;
5350 if (i386_record_modrm (&ir
))
5355 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5358 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5364 if (i386_record_lea_modrm (&ir
))
5366 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5373 case 0x0fb0: /* cmpxchg */
5375 if ((opcode
& 1) == 0)
5378 ir
.ot
= ir
.dflag
+ OT_WORD
;
5379 if (i386_record_modrm (&ir
))
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5385 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5392 if (i386_record_lea_modrm (&ir
))
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5398 case 0x0fc7: /* cmpxchg8b */
5399 if (i386_record_modrm (&ir
))
5404 opcode
= opcode
<< 8 | ir
.modrm
;
5407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5409 if (i386_record_lea_modrm (&ir
))
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5414 case 0x50: /* push */
5424 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5426 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5430 case 0x06: /* push es */
5431 case 0x0e: /* push cs */
5432 case 0x16: /* push ss */
5433 case 0x1e: /* push ds */
5434 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5439 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5443 case 0x0fa0: /* push fs */
5444 case 0x0fa8: /* push gs */
5445 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5450 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5454 case 0x60: /* pusha */
5455 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5460 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5464 case 0x58: /* pop */
5472 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5473 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5476 case 0x61: /* popa */
5477 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5482 for (regnum
= X86_RECORD_REAX_REGNUM
;
5483 regnum
<= X86_RECORD_REDI_REGNUM
;
5485 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5488 case 0x8f: /* pop */
5489 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5490 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5492 ir
.ot
= ir
.dflag
+ OT_WORD
;
5493 if (i386_record_modrm (&ir
))
5496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5499 ir
.popl_esp_hack
= 1 << ir
.ot
;
5500 if (i386_record_lea_modrm (&ir
))
5503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5506 case 0xc8: /* enter */
5507 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5508 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5510 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5514 case 0xc9: /* leave */
5515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5519 case 0x07: /* pop es */
5520 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5530 case 0x17: /* pop ss */
5531 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5541 case 0x1f: /* pop ds */
5542 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5552 case 0x0fa1: /* pop fs */
5553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5558 case 0x0fa9: /* pop gs */
5559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5564 case 0x88: /* mov */
5568 if ((opcode
& 1) == 0)
5571 ir
.ot
= ir
.dflag
+ OT_WORD
;
5573 if (i386_record_modrm (&ir
))
5578 if (opcode
== 0xc6 || opcode
== 0xc7)
5579 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5580 if (i386_record_lea_modrm (&ir
))
5585 if (opcode
== 0xc6 || opcode
== 0xc7)
5587 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5589 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5593 case 0x8a: /* mov */
5595 if ((opcode
& 1) == 0)
5598 ir
.ot
= ir
.dflag
+ OT_WORD
;
5599 if (i386_record_modrm (&ir
))
5602 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5604 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5607 case 0x8c: /* mov seg */
5608 if (i386_record_modrm (&ir
))
5613 opcode
= opcode
<< 8 | ir
.modrm
;
5618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5622 if (i386_record_lea_modrm (&ir
))
5627 case 0x8e: /* mov seg */
5628 if (i386_record_modrm (&ir
))
5633 regnum
= X86_RECORD_ES_REGNUM
;
5636 regnum
= X86_RECORD_SS_REGNUM
;
5639 regnum
= X86_RECORD_DS_REGNUM
;
5642 regnum
= X86_RECORD_FS_REGNUM
;
5645 regnum
= X86_RECORD_GS_REGNUM
;
5649 opcode
= opcode
<< 8 | ir
.modrm
;
5653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5657 case 0x0fb6: /* movzbS */
5658 case 0x0fb7: /* movzwS */
5659 case 0x0fbe: /* movsbS */
5660 case 0x0fbf: /* movswS */
5661 if (i386_record_modrm (&ir
))
5663 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5666 case 0x8d: /* lea */
5667 if (i386_record_modrm (&ir
))
5672 opcode
= opcode
<< 8 | ir
.modrm
;
5677 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5682 case 0xa0: /* mov EAX */
5685 case 0xd7: /* xlat */
5686 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5689 case 0xa2: /* mov EAX */
5691 if (ir
.override
>= 0)
5693 if (record_full_memory_query
)
5697 target_terminal_ours ();
5699 Process record ignores the memory change of instruction at address %s\n\
5700 because it can't get the value of the segment register.\n\
5701 Do you want to stop the program?"),
5702 paddress (gdbarch
, ir
.orig_addr
));
5703 target_terminal_inferior ();
5710 if ((opcode
& 1) == 0)
5713 ir
.ot
= ir
.dflag
+ OT_WORD
;
5716 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5719 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5723 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5726 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5730 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5733 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5735 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5740 case 0xb0: /* mov R, Ib */
5748 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5749 ? ((opcode
& 0x7) | ir
.rex_b
)
5750 : ((opcode
& 0x7) & 0x3));
5753 case 0xb8: /* mov R, Iv */
5761 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5764 case 0x91: /* xchg R, EAX */
5771 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5775 case 0x86: /* xchg Ev, Gv */
5777 if ((opcode
& 1) == 0)
5780 ir
.ot
= ir
.dflag
+ OT_WORD
;
5781 if (i386_record_modrm (&ir
))
5786 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5792 if (i386_record_lea_modrm (&ir
))
5796 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5798 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5801 case 0xc4: /* les Gv */
5802 case 0xc5: /* lds Gv */
5803 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5809 case 0x0fb2: /* lss Gv */
5810 case 0x0fb4: /* lfs Gv */
5811 case 0x0fb5: /* lgs Gv */
5812 if (i386_record_modrm (&ir
))
5820 opcode
= opcode
<< 8 | ir
.modrm
;
5825 case 0xc4: /* les Gv */
5826 regnum
= X86_RECORD_ES_REGNUM
;
5828 case 0xc5: /* lds Gv */
5829 regnum
= X86_RECORD_DS_REGNUM
;
5831 case 0x0fb2: /* lss Gv */
5832 regnum
= X86_RECORD_SS_REGNUM
;
5834 case 0x0fb4: /* lfs Gv */
5835 regnum
= X86_RECORD_FS_REGNUM
;
5837 case 0x0fb5: /* lgs Gv */
5838 regnum
= X86_RECORD_GS_REGNUM
;
5841 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5842 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5843 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5846 case 0xc0: /* shifts */
5852 if ((opcode
& 1) == 0)
5855 ir
.ot
= ir
.dflag
+ OT_WORD
;
5856 if (i386_record_modrm (&ir
))
5858 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5860 if (i386_record_lea_modrm (&ir
))
5866 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5868 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5870 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5877 if (i386_record_modrm (&ir
))
5881 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5886 if (i386_record_lea_modrm (&ir
))
5891 case 0xd8: /* Floats. */
5899 if (i386_record_modrm (&ir
))
5901 ir
.reg
|= ((opcode
& 7) << 3);
5907 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5915 /* For fcom, ficom nothing to do. */
5921 /* For fcomp, ficomp pop FPU stack, store all. */
5922 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5949 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5950 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5951 of code, always affects st(0) register. */
5952 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5976 /* Handling fld, fild. */
5977 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5981 switch (ir
.reg
>> 4)
5984 if (record_full_arch_list_add_mem (addr64
, 4))
5988 if (record_full_arch_list_add_mem (addr64
, 8))
5994 if (record_full_arch_list_add_mem (addr64
, 2))
6000 switch (ir
.reg
>> 4)
6003 if (record_full_arch_list_add_mem (addr64
, 4))
6005 if (3 == (ir
.reg
& 7))
6007 /* For fstp m32fp. */
6008 if (i386_record_floats (gdbarch
, &ir
,
6009 I386_SAVE_FPU_REGS
))
6014 if (record_full_arch_list_add_mem (addr64
, 4))
6016 if ((3 == (ir
.reg
& 7))
6017 || (5 == (ir
.reg
& 7))
6018 || (7 == (ir
.reg
& 7)))
6020 /* For fstp insn. */
6021 if (i386_record_floats (gdbarch
, &ir
,
6022 I386_SAVE_FPU_REGS
))
6027 if (record_full_arch_list_add_mem (addr64
, 8))
6029 if (3 == (ir
.reg
& 7))
6031 /* For fstp m64fp. */
6032 if (i386_record_floats (gdbarch
, &ir
,
6033 I386_SAVE_FPU_REGS
))
6038 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6040 /* For fistp, fbld, fild, fbstp. */
6041 if (i386_record_floats (gdbarch
, &ir
,
6042 I386_SAVE_FPU_REGS
))
6047 if (record_full_arch_list_add_mem (addr64
, 2))
6056 if (i386_record_floats (gdbarch
, &ir
,
6057 I386_SAVE_FPU_ENV_REG_STACK
))
6062 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6067 if (i386_record_floats (gdbarch
, &ir
,
6068 I386_SAVE_FPU_ENV_REG_STACK
))
6074 if (record_full_arch_list_add_mem (addr64
, 28))
6079 if (record_full_arch_list_add_mem (addr64
, 14))
6085 if (record_full_arch_list_add_mem (addr64
, 2))
6087 /* Insn fstp, fbstp. */
6088 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6093 if (record_full_arch_list_add_mem (addr64
, 10))
6099 if (record_full_arch_list_add_mem (addr64
, 28))
6105 if (record_full_arch_list_add_mem (addr64
, 14))
6109 if (record_full_arch_list_add_mem (addr64
, 80))
6112 if (i386_record_floats (gdbarch
, &ir
,
6113 I386_SAVE_FPU_ENV_REG_STACK
))
6117 if (record_full_arch_list_add_mem (addr64
, 8))
6120 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6125 opcode
= opcode
<< 8 | ir
.modrm
;
6130 /* Opcode is an extension of modR/M byte. */
6136 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6140 if (0x0c == (ir
.modrm
>> 4))
6142 if ((ir
.modrm
& 0x0f) <= 7)
6144 if (i386_record_floats (gdbarch
, &ir
,
6145 I386_SAVE_FPU_REGS
))
6150 if (i386_record_floats (gdbarch
, &ir
,
6151 I387_ST0_REGNUM (tdep
)))
6153 /* If only st(0) is changing, then we have already
6155 if ((ir
.modrm
& 0x0f) - 0x08)
6157 if (i386_record_floats (gdbarch
, &ir
,
6158 I387_ST0_REGNUM (tdep
) +
6159 ((ir
.modrm
& 0x0f) - 0x08)))
6177 if (i386_record_floats (gdbarch
, &ir
,
6178 I387_ST0_REGNUM (tdep
)))
6196 if (i386_record_floats (gdbarch
, &ir
,
6197 I386_SAVE_FPU_REGS
))
6201 if (i386_record_floats (gdbarch
, &ir
,
6202 I387_ST0_REGNUM (tdep
)))
6204 if (i386_record_floats (gdbarch
, &ir
,
6205 I387_ST0_REGNUM (tdep
) + 1))
6212 if (0xe9 == ir
.modrm
)
6214 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6217 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6219 if (i386_record_floats (gdbarch
, &ir
,
6220 I387_ST0_REGNUM (tdep
)))
6222 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6224 if (i386_record_floats (gdbarch
, &ir
,
6225 I387_ST0_REGNUM (tdep
) +
6229 else if ((ir
.modrm
& 0x0f) - 0x08)
6231 if (i386_record_floats (gdbarch
, &ir
,
6232 I387_ST0_REGNUM (tdep
) +
6233 ((ir
.modrm
& 0x0f) - 0x08)))
6239 if (0xe3 == ir
.modrm
)
6241 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6244 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6246 if (i386_record_floats (gdbarch
, &ir
,
6247 I387_ST0_REGNUM (tdep
)))
6249 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6251 if (i386_record_floats (gdbarch
, &ir
,
6252 I387_ST0_REGNUM (tdep
) +
6256 else if ((ir
.modrm
& 0x0f) - 0x08)
6258 if (i386_record_floats (gdbarch
, &ir
,
6259 I387_ST0_REGNUM (tdep
) +
6260 ((ir
.modrm
& 0x0f) - 0x08)))
6266 if ((0x0c == ir
.modrm
>> 4)
6267 || (0x0d == ir
.modrm
>> 4)
6268 || (0x0f == ir
.modrm
>> 4))
6270 if ((ir
.modrm
& 0x0f) <= 7)
6272 if (i386_record_floats (gdbarch
, &ir
,
6273 I387_ST0_REGNUM (tdep
) +
6279 if (i386_record_floats (gdbarch
, &ir
,
6280 I387_ST0_REGNUM (tdep
) +
6281 ((ir
.modrm
& 0x0f) - 0x08)))
6287 if (0x0c == ir
.modrm
>> 4)
6289 if (i386_record_floats (gdbarch
, &ir
,
6290 I387_FTAG_REGNUM (tdep
)))
6293 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6295 if ((ir
.modrm
& 0x0f) <= 7)
6297 if (i386_record_floats (gdbarch
, &ir
,
6298 I387_ST0_REGNUM (tdep
) +
6304 if (i386_record_floats (gdbarch
, &ir
,
6305 I386_SAVE_FPU_REGS
))
6311 if ((0x0c == ir
.modrm
>> 4)
6312 || (0x0e == ir
.modrm
>> 4)
6313 || (0x0f == ir
.modrm
>> 4)
6314 || (0xd9 == ir
.modrm
))
6316 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6321 if (0xe0 == ir
.modrm
)
6323 if (record_full_arch_list_add_reg (ir
.regcache
,
6327 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6329 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6337 case 0xa4: /* movsS */
6339 case 0xaa: /* stosS */
6341 case 0x6c: /* insS */
6343 regcache_raw_read_unsigned (ir
.regcache
,
6344 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6350 if ((opcode
& 1) == 0)
6353 ir
.ot
= ir
.dflag
+ OT_WORD
;
6354 regcache_raw_read_unsigned (ir
.regcache
,
6355 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6358 regcache_raw_read_unsigned (ir
.regcache
,
6359 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6361 regcache_raw_read_unsigned (ir
.regcache
,
6362 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6364 if (ir
.aflag
&& (es
!= ds
))
6366 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6367 if (record_full_memory_query
)
6371 target_terminal_ours ();
6373 Process record ignores the memory change of instruction at address %s\n\
6374 because it can't get the value of the segment register.\n\
6375 Do you want to stop the program?"),
6376 paddress (gdbarch
, ir
.orig_addr
));
6377 target_terminal_inferior ();
6384 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6388 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6390 if (opcode
== 0xa4 || opcode
== 0xa5)
6391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6392 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6397 case 0xa6: /* cmpsS */
6399 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6401 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6402 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6403 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6406 case 0xac: /* lodsS */
6408 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6410 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6415 case 0xae: /* scasS */
6417 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6418 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6423 case 0x6e: /* outsS */
6425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6426 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6431 case 0xe4: /* port I/O */
6435 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6446 case 0xc2: /* ret im */
6447 case 0xc3: /* ret */
6448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6452 case 0xca: /* lret im */
6453 case 0xcb: /* lret */
6454 case 0xcf: /* iret */
6455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6460 case 0xe8: /* call im */
6461 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6463 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6467 case 0x9a: /* lcall im */
6468 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6474 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6478 case 0xe9: /* jmp im */
6479 case 0xea: /* ljmp im */
6480 case 0xeb: /* jmp Jb */
6481 case 0x70: /* jcc Jb */
6497 case 0x0f80: /* jcc Jv */
6515 case 0x0f90: /* setcc Gv */
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6533 if (i386_record_modrm (&ir
))
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6540 if (i386_record_lea_modrm (&ir
))
6545 case 0x0f40: /* cmov Gv, Ev */
6561 if (i386_record_modrm (&ir
))
6564 if (ir
.dflag
== OT_BYTE
)
6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6570 case 0x9c: /* pushf */
6571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6572 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6574 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6578 case 0x9d: /* popf */
6579 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6583 case 0x9e: /* sahf */
6584 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6590 case 0xf5: /* cmc */
6591 case 0xf8: /* clc */
6592 case 0xf9: /* stc */
6593 case 0xfc: /* cld */
6594 case 0xfd: /* std */
6595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6598 case 0x9f: /* lahf */
6599 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6604 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6608 /* bit operations */
6609 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6610 ir
.ot
= ir
.dflag
+ OT_WORD
;
6611 if (i386_record_modrm (&ir
))
6616 opcode
= opcode
<< 8 | ir
.modrm
;
6622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6625 if (i386_record_lea_modrm (&ir
))
6629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6632 case 0x0fa3: /* bt Gv, Ev */
6633 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6636 case 0x0fab: /* bts */
6637 case 0x0fb3: /* btr */
6638 case 0x0fbb: /* btc */
6639 ir
.ot
= ir
.dflag
+ OT_WORD
;
6640 if (i386_record_modrm (&ir
))
6643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6647 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6649 regcache_raw_read_unsigned (ir
.regcache
,
6650 ir
.regmap
[ir
.reg
| rex_r
],
6655 addr64
+= ((int16_t) addr
>> 4) << 4;
6658 addr64
+= ((int32_t) addr
>> 5) << 5;
6661 addr64
+= ((int64_t) addr
>> 6) << 6;
6664 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6666 if (i386_record_lea_modrm (&ir
))
6669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6672 case 0x0fbc: /* bsf */
6673 case 0x0fbd: /* bsr */
6674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6679 case 0x27: /* daa */
6680 case 0x2f: /* das */
6681 case 0x37: /* aaa */
6682 case 0x3f: /* aas */
6683 case 0xd4: /* aam */
6684 case 0xd5: /* aad */
6685 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6695 case 0x90: /* nop */
6696 if (prefixes
& PREFIX_LOCK
)
6703 case 0x9b: /* fwait */
6704 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6706 opcode
= (uint32_t) opcode8
;
6712 case 0xcc: /* int3 */
6713 printf_unfiltered (_("Process record does not support instruction "
6720 case 0xcd: /* int */
6724 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6727 if (interrupt
!= 0x80
6728 || tdep
->i386_intx80_record
== NULL
)
6730 printf_unfiltered (_("Process record does not support "
6731 "instruction int 0x%02x.\n"),
6736 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6743 case 0xce: /* into */
6744 printf_unfiltered (_("Process record does not support "
6745 "instruction into.\n"));
6750 case 0xfa: /* cli */
6751 case 0xfb: /* sti */
6754 case 0x62: /* bound */
6755 printf_unfiltered (_("Process record does not support "
6756 "instruction bound.\n"));
6761 case 0x0fc8: /* bswap reg */
6769 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6772 case 0xd6: /* salc */
6773 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6782 case 0xe0: /* loopnz */
6783 case 0xe1: /* loopz */
6784 case 0xe2: /* loop */
6785 case 0xe3: /* jecxz */
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6790 case 0x0f30: /* wrmsr */
6791 printf_unfiltered (_("Process record does not support "
6792 "instruction wrmsr.\n"));
6797 case 0x0f32: /* rdmsr */
6798 printf_unfiltered (_("Process record does not support "
6799 "instruction rdmsr.\n"));
6804 case 0x0f31: /* rdtsc */
6805 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6806 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6809 case 0x0f34: /* sysenter */
6812 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6817 if (tdep
->i386_sysenter_record
== NULL
)
6819 printf_unfiltered (_("Process record does not support "
6820 "instruction sysenter.\n"));
6824 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6830 case 0x0f35: /* sysexit */
6831 printf_unfiltered (_("Process record does not support "
6832 "instruction sysexit.\n"));
6837 case 0x0f05: /* syscall */
6840 if (tdep
->i386_syscall_record
== NULL
)
6842 printf_unfiltered (_("Process record does not support "
6843 "instruction syscall.\n"));
6847 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6853 case 0x0f07: /* sysret */
6854 printf_unfiltered (_("Process record does not support "
6855 "instruction sysret.\n"));
6860 case 0x0fa2: /* cpuid */
6861 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6862 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6863 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6864 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6867 case 0xf4: /* hlt */
6868 printf_unfiltered (_("Process record does not support "
6869 "instruction hlt.\n"));
6875 if (i386_record_modrm (&ir
))
6882 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6886 if (i386_record_lea_modrm (&ir
))
6895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6899 opcode
= opcode
<< 8 | ir
.modrm
;
6906 if (i386_record_modrm (&ir
))
6917 opcode
= opcode
<< 8 | ir
.modrm
;
6920 if (ir
.override
>= 0)
6922 if (record_full_memory_query
)
6926 target_terminal_ours ();
6928 Process record ignores the memory change of instruction at address %s\n\
6929 because it can't get the value of the segment register.\n\
6930 Do you want to stop the program?"),
6931 paddress (gdbarch
, ir
.orig_addr
));
6932 target_terminal_inferior ();
6939 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6941 if (record_full_arch_list_add_mem (addr64
, 2))
6944 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6946 if (record_full_arch_list_add_mem (addr64
, 8))
6951 if (record_full_arch_list_add_mem (addr64
, 4))
6962 case 0: /* monitor */
6965 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6969 opcode
= opcode
<< 8 | ir
.modrm
;
6977 if (ir
.override
>= 0)
6979 if (record_full_memory_query
)
6983 target_terminal_ours ();
6985 Process record ignores the memory change of instruction at address %s\n\
6986 because it can't get the value of the segment register.\n\
6987 Do you want to stop the program?"),
6988 paddress (gdbarch
, ir
.orig_addr
));
6989 target_terminal_inferior ();
6998 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7000 if (record_full_arch_list_add_mem (addr64
, 2))
7003 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7005 if (record_full_arch_list_add_mem (addr64
, 8))
7010 if (record_full_arch_list_add_mem (addr64
, 4))
7022 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7023 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7027 else if (ir
.rm
== 1)
7034 opcode
= opcode
<< 8 | ir
.modrm
;
7041 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7047 if (i386_record_lea_modrm (&ir
))
7050 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7053 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7055 case 7: /* invlpg */
7058 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7059 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7063 opcode
= opcode
<< 8 | ir
.modrm
;
7068 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7072 opcode
= opcode
<< 8 | ir
.modrm
;
7078 case 0x0f08: /* invd */
7079 case 0x0f09: /* wbinvd */
7082 case 0x63: /* arpl */
7083 if (i386_record_modrm (&ir
))
7085 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7087 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7088 ? (ir
.reg
| rex_r
) : ir
.rm
);
7092 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7093 if (i386_record_lea_modrm (&ir
))
7096 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7100 case 0x0f02: /* lar */
7101 case 0x0f03: /* lsl */
7102 if (i386_record_modrm (&ir
))
7104 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7105 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7109 if (i386_record_modrm (&ir
))
7111 if (ir
.mod
== 3 && ir
.reg
== 3)
7114 opcode
= opcode
<< 8 | ir
.modrm
;
7126 /* nop (multi byte) */
7129 case 0x0f20: /* mov reg, crN */
7130 case 0x0f22: /* mov crN, reg */
7131 if (i386_record_modrm (&ir
))
7133 if ((ir
.modrm
& 0xc0) != 0xc0)
7136 opcode
= opcode
<< 8 | ir
.modrm
;
7147 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7149 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7153 opcode
= opcode
<< 8 | ir
.modrm
;
7159 case 0x0f21: /* mov reg, drN */
7160 case 0x0f23: /* mov drN, reg */
7161 if (i386_record_modrm (&ir
))
7163 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7164 || ir
.reg
== 5 || ir
.reg
>= 8)
7167 opcode
= opcode
<< 8 | ir
.modrm
;
7171 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7173 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7176 case 0x0f06: /* clts */
7177 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7180 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7182 case 0x0f0d: /* 3DNow! prefetch */
7185 case 0x0f0e: /* 3DNow! femms */
7186 case 0x0f77: /* emms */
7187 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7189 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7192 case 0x0f0f: /* 3DNow! data */
7193 if (i386_record_modrm (&ir
))
7195 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7200 case 0x0c: /* 3DNow! pi2fw */
7201 case 0x0d: /* 3DNow! pi2fd */
7202 case 0x1c: /* 3DNow! pf2iw */
7203 case 0x1d: /* 3DNow! pf2id */
7204 case 0x8a: /* 3DNow! pfnacc */
7205 case 0x8e: /* 3DNow! pfpnacc */
7206 case 0x90: /* 3DNow! pfcmpge */
7207 case 0x94: /* 3DNow! pfmin */
7208 case 0x96: /* 3DNow! pfrcp */
7209 case 0x97: /* 3DNow! pfrsqrt */
7210 case 0x9a: /* 3DNow! pfsub */
7211 case 0x9e: /* 3DNow! pfadd */
7212 case 0xa0: /* 3DNow! pfcmpgt */
7213 case 0xa4: /* 3DNow! pfmax */
7214 case 0xa6: /* 3DNow! pfrcpit1 */
7215 case 0xa7: /* 3DNow! pfrsqit1 */
7216 case 0xaa: /* 3DNow! pfsubr */
7217 case 0xae: /* 3DNow! pfacc */
7218 case 0xb0: /* 3DNow! pfcmpeq */
7219 case 0xb4: /* 3DNow! pfmul */
7220 case 0xb6: /* 3DNow! pfrcpit2 */
7221 case 0xb7: /* 3DNow! pmulhrw */
7222 case 0xbb: /* 3DNow! pswapd */
7223 case 0xbf: /* 3DNow! pavgusb */
7224 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7225 goto no_support_3dnow_data
;
7226 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7230 no_support_3dnow_data
:
7231 opcode
= (opcode
<< 8) | opcode8
;
7237 case 0x0faa: /* rsm */
7238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7240 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7244 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7250 if (i386_record_modrm (&ir
))
7254 case 0: /* fxsave */
7258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7259 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7261 if (record_full_arch_list_add_mem (tmpu64
, 512))
7266 case 1: /* fxrstor */
7270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7272 for (i
= I387_MM0_REGNUM (tdep
);
7273 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7274 record_full_arch_list_add_reg (ir
.regcache
, i
);
7276 for (i
= I387_XMM0_REGNUM (tdep
);
7277 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7278 record_full_arch_list_add_reg (ir
.regcache
, i
);
7280 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7281 record_full_arch_list_add_reg (ir
.regcache
,
7282 I387_MXCSR_REGNUM(tdep
));
7284 for (i
= I387_ST0_REGNUM (tdep
);
7285 i386_fp_regnum_p (gdbarch
, i
); i
++)
7286 record_full_arch_list_add_reg (ir
.regcache
, i
);
7288 for (i
= I387_FCTRL_REGNUM (tdep
);
7289 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7290 record_full_arch_list_add_reg (ir
.regcache
, i
);
7294 case 2: /* ldmxcsr */
7295 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7297 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7300 case 3: /* stmxcsr */
7302 if (i386_record_lea_modrm (&ir
))
7306 case 5: /* lfence */
7307 case 6: /* mfence */
7308 case 7: /* sfence clflush */
7312 opcode
= (opcode
<< 8) | ir
.modrm
;
7318 case 0x0fc3: /* movnti */
7319 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7320 if (i386_record_modrm (&ir
))
7325 if (i386_record_lea_modrm (&ir
))
7329 /* Add prefix to opcode. */
7444 /* Mask out PREFIX_ADDR. */
7445 switch ((prefixes
& ~PREFIX_ADDR
))
7457 reswitch_prefix_add
:
7465 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7468 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7469 goto reswitch_prefix_add
;
7472 case 0x0f10: /* movups */
7473 case 0x660f10: /* movupd */
7474 case 0xf30f10: /* movss */
7475 case 0xf20f10: /* movsd */
7476 case 0x0f12: /* movlps */
7477 case 0x660f12: /* movlpd */
7478 case 0xf30f12: /* movsldup */
7479 case 0xf20f12: /* movddup */
7480 case 0x0f14: /* unpcklps */
7481 case 0x660f14: /* unpcklpd */
7482 case 0x0f15: /* unpckhps */
7483 case 0x660f15: /* unpckhpd */
7484 case 0x0f16: /* movhps */
7485 case 0x660f16: /* movhpd */
7486 case 0xf30f16: /* movshdup */
7487 case 0x0f28: /* movaps */
7488 case 0x660f28: /* movapd */
7489 case 0x0f2a: /* cvtpi2ps */
7490 case 0x660f2a: /* cvtpi2pd */
7491 case 0xf30f2a: /* cvtsi2ss */
7492 case 0xf20f2a: /* cvtsi2sd */
7493 case 0x0f2c: /* cvttps2pi */
7494 case 0x660f2c: /* cvttpd2pi */
7495 case 0x0f2d: /* cvtps2pi */
7496 case 0x660f2d: /* cvtpd2pi */
7497 case 0x660f3800: /* pshufb */
7498 case 0x660f3801: /* phaddw */
7499 case 0x660f3802: /* phaddd */
7500 case 0x660f3803: /* phaddsw */
7501 case 0x660f3804: /* pmaddubsw */
7502 case 0x660f3805: /* phsubw */
7503 case 0x660f3806: /* phsubd */
7504 case 0x660f3807: /* phsubsw */
7505 case 0x660f3808: /* psignb */
7506 case 0x660f3809: /* psignw */
7507 case 0x660f380a: /* psignd */
7508 case 0x660f380b: /* pmulhrsw */
7509 case 0x660f3810: /* pblendvb */
7510 case 0x660f3814: /* blendvps */
7511 case 0x660f3815: /* blendvpd */
7512 case 0x660f381c: /* pabsb */
7513 case 0x660f381d: /* pabsw */
7514 case 0x660f381e: /* pabsd */
7515 case 0x660f3820: /* pmovsxbw */
7516 case 0x660f3821: /* pmovsxbd */
7517 case 0x660f3822: /* pmovsxbq */
7518 case 0x660f3823: /* pmovsxwd */
7519 case 0x660f3824: /* pmovsxwq */
7520 case 0x660f3825: /* pmovsxdq */
7521 case 0x660f3828: /* pmuldq */
7522 case 0x660f3829: /* pcmpeqq */
7523 case 0x660f382a: /* movntdqa */
7524 case 0x660f3a08: /* roundps */
7525 case 0x660f3a09: /* roundpd */
7526 case 0x660f3a0a: /* roundss */
7527 case 0x660f3a0b: /* roundsd */
7528 case 0x660f3a0c: /* blendps */
7529 case 0x660f3a0d: /* blendpd */
7530 case 0x660f3a0e: /* pblendw */
7531 case 0x660f3a0f: /* palignr */
7532 case 0x660f3a20: /* pinsrb */
7533 case 0x660f3a21: /* insertps */
7534 case 0x660f3a22: /* pinsrd pinsrq */
7535 case 0x660f3a40: /* dpps */
7536 case 0x660f3a41: /* dppd */
7537 case 0x660f3a42: /* mpsadbw */
7538 case 0x660f3a60: /* pcmpestrm */
7539 case 0x660f3a61: /* pcmpestri */
7540 case 0x660f3a62: /* pcmpistrm */
7541 case 0x660f3a63: /* pcmpistri */
7542 case 0x0f51: /* sqrtps */
7543 case 0x660f51: /* sqrtpd */
7544 case 0xf20f51: /* sqrtsd */
7545 case 0xf30f51: /* sqrtss */
7546 case 0x0f52: /* rsqrtps */
7547 case 0xf30f52: /* rsqrtss */
7548 case 0x0f53: /* rcpps */
7549 case 0xf30f53: /* rcpss */
7550 case 0x0f54: /* andps */
7551 case 0x660f54: /* andpd */
7552 case 0x0f55: /* andnps */
7553 case 0x660f55: /* andnpd */
7554 case 0x0f56: /* orps */
7555 case 0x660f56: /* orpd */
7556 case 0x0f57: /* xorps */
7557 case 0x660f57: /* xorpd */
7558 case 0x0f58: /* addps */
7559 case 0x660f58: /* addpd */
7560 case 0xf20f58: /* addsd */
7561 case 0xf30f58: /* addss */
7562 case 0x0f59: /* mulps */
7563 case 0x660f59: /* mulpd */
7564 case 0xf20f59: /* mulsd */
7565 case 0xf30f59: /* mulss */
7566 case 0x0f5a: /* cvtps2pd */
7567 case 0x660f5a: /* cvtpd2ps */
7568 case 0xf20f5a: /* cvtsd2ss */
7569 case 0xf30f5a: /* cvtss2sd */
7570 case 0x0f5b: /* cvtdq2ps */
7571 case 0x660f5b: /* cvtps2dq */
7572 case 0xf30f5b: /* cvttps2dq */
7573 case 0x0f5c: /* subps */
7574 case 0x660f5c: /* subpd */
7575 case 0xf20f5c: /* subsd */
7576 case 0xf30f5c: /* subss */
7577 case 0x0f5d: /* minps */
7578 case 0x660f5d: /* minpd */
7579 case 0xf20f5d: /* minsd */
7580 case 0xf30f5d: /* minss */
7581 case 0x0f5e: /* divps */
7582 case 0x660f5e: /* divpd */
7583 case 0xf20f5e: /* divsd */
7584 case 0xf30f5e: /* divss */
7585 case 0x0f5f: /* maxps */
7586 case 0x660f5f: /* maxpd */
7587 case 0xf20f5f: /* maxsd */
7588 case 0xf30f5f: /* maxss */
7589 case 0x660f60: /* punpcklbw */
7590 case 0x660f61: /* punpcklwd */
7591 case 0x660f62: /* punpckldq */
7592 case 0x660f63: /* packsswb */
7593 case 0x660f64: /* pcmpgtb */
7594 case 0x660f65: /* pcmpgtw */
7595 case 0x660f66: /* pcmpgtd */
7596 case 0x660f67: /* packuswb */
7597 case 0x660f68: /* punpckhbw */
7598 case 0x660f69: /* punpckhwd */
7599 case 0x660f6a: /* punpckhdq */
7600 case 0x660f6b: /* packssdw */
7601 case 0x660f6c: /* punpcklqdq */
7602 case 0x660f6d: /* punpckhqdq */
7603 case 0x660f6e: /* movd */
7604 case 0x660f6f: /* movdqa */
7605 case 0xf30f6f: /* movdqu */
7606 case 0x660f70: /* pshufd */
7607 case 0xf20f70: /* pshuflw */
7608 case 0xf30f70: /* pshufhw */
7609 case 0x660f74: /* pcmpeqb */
7610 case 0x660f75: /* pcmpeqw */
7611 case 0x660f76: /* pcmpeqd */
7612 case 0x660f7c: /* haddpd */
7613 case 0xf20f7c: /* haddps */
7614 case 0x660f7d: /* hsubpd */
7615 case 0xf20f7d: /* hsubps */
7616 case 0xf30f7e: /* movq */
7617 case 0x0fc2: /* cmpps */
7618 case 0x660fc2: /* cmppd */
7619 case 0xf20fc2: /* cmpsd */
7620 case 0xf30fc2: /* cmpss */
7621 case 0x660fc4: /* pinsrw */
7622 case 0x0fc6: /* shufps */
7623 case 0x660fc6: /* shufpd */
7624 case 0x660fd0: /* addsubpd */
7625 case 0xf20fd0: /* addsubps */
7626 case 0x660fd1: /* psrlw */
7627 case 0x660fd2: /* psrld */
7628 case 0x660fd3: /* psrlq */
7629 case 0x660fd4: /* paddq */
7630 case 0x660fd5: /* pmullw */
7631 case 0xf30fd6: /* movq2dq */
7632 case 0x660fd8: /* psubusb */
7633 case 0x660fd9: /* psubusw */
7634 case 0x660fda: /* pminub */
7635 case 0x660fdb: /* pand */
7636 case 0x660fdc: /* paddusb */
7637 case 0x660fdd: /* paddusw */
7638 case 0x660fde: /* pmaxub */
7639 case 0x660fdf: /* pandn */
7640 case 0x660fe0: /* pavgb */
7641 case 0x660fe1: /* psraw */
7642 case 0x660fe2: /* psrad */
7643 case 0x660fe3: /* pavgw */
7644 case 0x660fe4: /* pmulhuw */
7645 case 0x660fe5: /* pmulhw */
7646 case 0x660fe6: /* cvttpd2dq */
7647 case 0xf20fe6: /* cvtpd2dq */
7648 case 0xf30fe6: /* cvtdq2pd */
7649 case 0x660fe8: /* psubsb */
7650 case 0x660fe9: /* psubsw */
7651 case 0x660fea: /* pminsw */
7652 case 0x660feb: /* por */
7653 case 0x660fec: /* paddsb */
7654 case 0x660fed: /* paddsw */
7655 case 0x660fee: /* pmaxsw */
7656 case 0x660fef: /* pxor */
7657 case 0xf20ff0: /* lddqu */
7658 case 0x660ff1: /* psllw */
7659 case 0x660ff2: /* pslld */
7660 case 0x660ff3: /* psllq */
7661 case 0x660ff4: /* pmuludq */
7662 case 0x660ff5: /* pmaddwd */
7663 case 0x660ff6: /* psadbw */
7664 case 0x660ff8: /* psubb */
7665 case 0x660ff9: /* psubw */
7666 case 0x660ffa: /* psubd */
7667 case 0x660ffb: /* psubq */
7668 case 0x660ffc: /* paddb */
7669 case 0x660ffd: /* paddw */
7670 case 0x660ffe: /* paddd */
7671 if (i386_record_modrm (&ir
))
7674 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7676 record_full_arch_list_add_reg (ir
.regcache
,
7677 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7678 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7682 case 0x0f11: /* movups */
7683 case 0x660f11: /* movupd */
7684 case 0xf30f11: /* movss */
7685 case 0xf20f11: /* movsd */
7686 case 0x0f13: /* movlps */
7687 case 0x660f13: /* movlpd */
7688 case 0x0f17: /* movhps */
7689 case 0x660f17: /* movhpd */
7690 case 0x0f29: /* movaps */
7691 case 0x660f29: /* movapd */
7692 case 0x660f3a14: /* pextrb */
7693 case 0x660f3a15: /* pextrw */
7694 case 0x660f3a16: /* pextrd pextrq */
7695 case 0x660f3a17: /* extractps */
7696 case 0x660f7f: /* movdqa */
7697 case 0xf30f7f: /* movdqu */
7698 if (i386_record_modrm (&ir
))
7702 if (opcode
== 0x0f13 || opcode
== 0x660f13
7703 || opcode
== 0x0f17 || opcode
== 0x660f17)
7706 if (!i386_xmm_regnum_p (gdbarch
,
7707 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7709 record_full_arch_list_add_reg (ir
.regcache
,
7710 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7732 if (i386_record_lea_modrm (&ir
))
7737 case 0x0f2b: /* movntps */
7738 case 0x660f2b: /* movntpd */
7739 case 0x0fe7: /* movntq */
7740 case 0x660fe7: /* movntdq */
7743 if (opcode
== 0x0fe7)
7747 if (i386_record_lea_modrm (&ir
))
7751 case 0xf30f2c: /* cvttss2si */
7752 case 0xf20f2c: /* cvttsd2si */
7753 case 0xf30f2d: /* cvtss2si */
7754 case 0xf20f2d: /* cvtsd2si */
7755 case 0xf20f38f0: /* crc32 */
7756 case 0xf20f38f1: /* crc32 */
7757 case 0x0f50: /* movmskps */
7758 case 0x660f50: /* movmskpd */
7759 case 0x0fc5: /* pextrw */
7760 case 0x660fc5: /* pextrw */
7761 case 0x0fd7: /* pmovmskb */
7762 case 0x660fd7: /* pmovmskb */
7763 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7766 case 0x0f3800: /* pshufb */
7767 case 0x0f3801: /* phaddw */
7768 case 0x0f3802: /* phaddd */
7769 case 0x0f3803: /* phaddsw */
7770 case 0x0f3804: /* pmaddubsw */
7771 case 0x0f3805: /* phsubw */
7772 case 0x0f3806: /* phsubd */
7773 case 0x0f3807: /* phsubsw */
7774 case 0x0f3808: /* psignb */
7775 case 0x0f3809: /* psignw */
7776 case 0x0f380a: /* psignd */
7777 case 0x0f380b: /* pmulhrsw */
7778 case 0x0f381c: /* pabsb */
7779 case 0x0f381d: /* pabsw */
7780 case 0x0f381e: /* pabsd */
7781 case 0x0f382b: /* packusdw */
7782 case 0x0f3830: /* pmovzxbw */
7783 case 0x0f3831: /* pmovzxbd */
7784 case 0x0f3832: /* pmovzxbq */
7785 case 0x0f3833: /* pmovzxwd */
7786 case 0x0f3834: /* pmovzxwq */
7787 case 0x0f3835: /* pmovzxdq */
7788 case 0x0f3837: /* pcmpgtq */
7789 case 0x0f3838: /* pminsb */
7790 case 0x0f3839: /* pminsd */
7791 case 0x0f383a: /* pminuw */
7792 case 0x0f383b: /* pminud */
7793 case 0x0f383c: /* pmaxsb */
7794 case 0x0f383d: /* pmaxsd */
7795 case 0x0f383e: /* pmaxuw */
7796 case 0x0f383f: /* pmaxud */
7797 case 0x0f3840: /* pmulld */
7798 case 0x0f3841: /* phminposuw */
7799 case 0x0f3a0f: /* palignr */
7800 case 0x0f60: /* punpcklbw */
7801 case 0x0f61: /* punpcklwd */
7802 case 0x0f62: /* punpckldq */
7803 case 0x0f63: /* packsswb */
7804 case 0x0f64: /* pcmpgtb */
7805 case 0x0f65: /* pcmpgtw */
7806 case 0x0f66: /* pcmpgtd */
7807 case 0x0f67: /* packuswb */
7808 case 0x0f68: /* punpckhbw */
7809 case 0x0f69: /* punpckhwd */
7810 case 0x0f6a: /* punpckhdq */
7811 case 0x0f6b: /* packssdw */
7812 case 0x0f6e: /* movd */
7813 case 0x0f6f: /* movq */
7814 case 0x0f70: /* pshufw */
7815 case 0x0f74: /* pcmpeqb */
7816 case 0x0f75: /* pcmpeqw */
7817 case 0x0f76: /* pcmpeqd */
7818 case 0x0fc4: /* pinsrw */
7819 case 0x0fd1: /* psrlw */
7820 case 0x0fd2: /* psrld */
7821 case 0x0fd3: /* psrlq */
7822 case 0x0fd4: /* paddq */
7823 case 0x0fd5: /* pmullw */
7824 case 0xf20fd6: /* movdq2q */
7825 case 0x0fd8: /* psubusb */
7826 case 0x0fd9: /* psubusw */
7827 case 0x0fda: /* pminub */
7828 case 0x0fdb: /* pand */
7829 case 0x0fdc: /* paddusb */
7830 case 0x0fdd: /* paddusw */
7831 case 0x0fde: /* pmaxub */
7832 case 0x0fdf: /* pandn */
7833 case 0x0fe0: /* pavgb */
7834 case 0x0fe1: /* psraw */
7835 case 0x0fe2: /* psrad */
7836 case 0x0fe3: /* pavgw */
7837 case 0x0fe4: /* pmulhuw */
7838 case 0x0fe5: /* pmulhw */
7839 case 0x0fe8: /* psubsb */
7840 case 0x0fe9: /* psubsw */
7841 case 0x0fea: /* pminsw */
7842 case 0x0feb: /* por */
7843 case 0x0fec: /* paddsb */
7844 case 0x0fed: /* paddsw */
7845 case 0x0fee: /* pmaxsw */
7846 case 0x0fef: /* pxor */
7847 case 0x0ff1: /* psllw */
7848 case 0x0ff2: /* pslld */
7849 case 0x0ff3: /* psllq */
7850 case 0x0ff4: /* pmuludq */
7851 case 0x0ff5: /* pmaddwd */
7852 case 0x0ff6: /* psadbw */
7853 case 0x0ff8: /* psubb */
7854 case 0x0ff9: /* psubw */
7855 case 0x0ffa: /* psubd */
7856 case 0x0ffb: /* psubq */
7857 case 0x0ffc: /* paddb */
7858 case 0x0ffd: /* paddw */
7859 case 0x0ffe: /* paddd */
7860 if (i386_record_modrm (&ir
))
7862 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7864 record_full_arch_list_add_reg (ir
.regcache
,
7865 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7868 case 0x0f71: /* psllw */
7869 case 0x0f72: /* pslld */
7870 case 0x0f73: /* psllq */
7871 if (i386_record_modrm (&ir
))
7873 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7875 record_full_arch_list_add_reg (ir
.regcache
,
7876 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7879 case 0x660f71: /* psllw */
7880 case 0x660f72: /* pslld */
7881 case 0x660f73: /* psllq */
7882 if (i386_record_modrm (&ir
))
7885 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7887 record_full_arch_list_add_reg (ir
.regcache
,
7888 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7891 case 0x0f7e: /* movd */
7892 case 0x660f7e: /* movd */
7893 if (i386_record_modrm (&ir
))
7896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7903 if (i386_record_lea_modrm (&ir
))
7908 case 0x0f7f: /* movq */
7909 if (i386_record_modrm (&ir
))
7913 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7915 record_full_arch_list_add_reg (ir
.regcache
,
7916 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7921 if (i386_record_lea_modrm (&ir
))
7926 case 0xf30fb8: /* popcnt */
7927 if (i386_record_modrm (&ir
))
7929 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7930 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7933 case 0x660fd6: /* movq */
7934 if (i386_record_modrm (&ir
))
7939 if (!i386_xmm_regnum_p (gdbarch
,
7940 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7942 record_full_arch_list_add_reg (ir
.regcache
,
7943 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7948 if (i386_record_lea_modrm (&ir
))
7953 case 0x660f3817: /* ptest */
7954 case 0x0f2e: /* ucomiss */
7955 case 0x660f2e: /* ucomisd */
7956 case 0x0f2f: /* comiss */
7957 case 0x660f2f: /* comisd */
7958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7961 case 0x0ff7: /* maskmovq */
7962 regcache_raw_read_unsigned (ir
.regcache
,
7963 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7965 if (record_full_arch_list_add_mem (addr
, 64))
7969 case 0x660ff7: /* maskmovdqu */
7970 regcache_raw_read_unsigned (ir
.regcache
,
7971 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7973 if (record_full_arch_list_add_mem (addr
, 128))
7988 /* In the future, maybe still need to deal with need_dasm. */
7989 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7990 if (record_full_arch_list_add_end ())
7996 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7997 "at address %s.\n"),
7998 (unsigned int) (opcode
),
7999 paddress (gdbarch
, ir
.orig_addr
));
8003 static const int i386_record_regmap
[] =
8005 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8006 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8007 0, 0, 0, 0, 0, 0, 0, 0,
8008 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8009 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8012 /* Check that the given address appears suitable for a fast
8013 tracepoint, which on x86-64 means that we need an instruction of at
8014 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8015 jump and not have to worry about program jumps to an address in the
8016 middle of the tracepoint jump. On x86, it may be possible to use
8017 4-byte jumps with a 2-byte offset to a trampoline located in the
8018 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8019 of instruction to replace, and 0 if not, plus an explanatory
8023 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
8024 CORE_ADDR addr
, int *isize
, char **msg
)
8027 static struct ui_file
*gdb_null
= NULL
;
8029 /* Ask the target for the minimum instruction length supported. */
8030 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8034 /* If the target does not support the get_min_fast_tracepoint_insn_len
8035 operation, assume that fast tracepoints will always be implemented
8036 using 4-byte relative jumps on both x86 and x86-64. */
8039 else if (jumplen
== 0)
8041 /* If the target does support get_min_fast_tracepoint_insn_len but
8042 returns zero, then the IPA has not loaded yet. In this case,
8043 we optimistically assume that truncated 2-byte relative jumps
8044 will be available on x86, and compensate later if this assumption
8045 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8046 jumps will always be used. */
8047 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8050 /* Dummy file descriptor for the disassembler. */
8052 gdb_null
= ui_file_new ();
8054 /* Check for fit. */
8055 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
8061 /* Return a bit of target-specific detail to add to the caller's
8062 generic failure message. */
8064 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
8065 "need at least %d bytes for the jump"),
8078 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8079 struct tdesc_arch_data
*tdesc_data
)
8081 const struct target_desc
*tdesc
= tdep
->tdesc
;
8082 const struct tdesc_feature
*feature_core
;
8084 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8086 int i
, num_regs
, valid_p
;
8088 if (! tdesc_has_registers (tdesc
))
8091 /* Get core registers. */
8092 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8093 if (feature_core
== NULL
)
8096 /* Get SSE registers. */
8097 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8099 /* Try AVX registers. */
8100 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8102 /* Try MPX registers. */
8103 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8105 /* Try AVX512 registers. */
8106 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8110 /* The XCR0 bits. */
8113 /* AVX512 register description requires AVX register description. */
8117 tdep
->xcr0
= X86_XSTATE_MPX_AVX512_MASK
;
8119 /* It may have been set by OSABI initialization function. */
8120 if (tdep
->k0_regnum
< 0)
8122 tdep
->k_register_names
= i386_k_names
;
8123 tdep
->k0_regnum
= I386_K0_REGNUM
;
8126 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8127 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8128 tdep
->k0_regnum
+ i
,
8131 if (tdep
->num_zmm_regs
== 0)
8133 tdep
->zmmh_register_names
= i386_zmmh_names
;
8134 tdep
->num_zmm_regs
= 8;
8135 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8138 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8139 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8140 tdep
->zmm0h_regnum
+ i
,
8141 tdep
->zmmh_register_names
[i
]);
8143 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8144 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8145 tdep
->xmm16_regnum
+ i
,
8146 tdep
->xmm_avx512_register_names
[i
]);
8148 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8149 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8150 tdep
->ymm16h_regnum
+ i
,
8151 tdep
->ymm16h_register_names
[i
]);
8155 /* AVX register description requires SSE register description. */
8159 if (!feature_avx512
)
8160 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8162 /* It may have been set by OSABI initialization function. */
8163 if (tdep
->num_ymm_regs
== 0)
8165 tdep
->ymmh_register_names
= i386_ymmh_names
;
8166 tdep
->num_ymm_regs
= 8;
8167 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8170 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8171 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8172 tdep
->ymm0h_regnum
+ i
,
8173 tdep
->ymmh_register_names
[i
]);
8175 else if (feature_sse
)
8176 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8179 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8180 tdep
->num_xmm_regs
= 0;
8183 num_regs
= tdep
->num_core_regs
;
8184 for (i
= 0; i
< num_regs
; i
++)
8185 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8186 tdep
->register_names
[i
]);
8190 /* Need to include %mxcsr, so add one. */
8191 num_regs
+= tdep
->num_xmm_regs
+ 1;
8192 for (; i
< num_regs
; i
++)
8193 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8194 tdep
->register_names
[i
]);
8199 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8201 if (tdep
->bnd0r_regnum
< 0)
8203 tdep
->mpx_register_names
= i386_mpx_names
;
8204 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8205 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8208 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8209 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8210 I387_BND0R_REGNUM (tdep
) + i
,
8211 tdep
->mpx_register_names
[i
]);
8218 static struct gdbarch
*
8219 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8221 struct gdbarch_tdep
*tdep
;
8222 struct gdbarch
*gdbarch
;
8223 struct tdesc_arch_data
*tdesc_data
;
8224 const struct target_desc
*tdesc
;
8232 /* If there is already a candidate, use it. */
8233 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8235 return arches
->gdbarch
;
8237 /* Allocate space for the new architecture. */
8238 tdep
= XCNEW (struct gdbarch_tdep
);
8239 gdbarch
= gdbarch_alloc (&info
, tdep
);
8241 /* General-purpose registers. */
8242 tdep
->gregset_reg_offset
= NULL
;
8243 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8244 tdep
->sizeof_gregset
= 0;
8246 /* Floating-point registers. */
8247 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8248 tdep
->fpregset
= &i386_fpregset
;
8250 /* The default settings include the FPU registers, the MMX registers
8251 and the SSE registers. This can be overridden for a specific ABI
8252 by adjusting the members `st0_regnum', `mm0_regnum' and
8253 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8254 will show up in the output of "info all-registers". */
8256 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8258 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8259 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8261 tdep
->jb_pc_offset
= -1;
8262 tdep
->struct_return
= pcc_struct_return
;
8263 tdep
->sigtramp_start
= 0;
8264 tdep
->sigtramp_end
= 0;
8265 tdep
->sigtramp_p
= i386_sigtramp_p
;
8266 tdep
->sigcontext_addr
= NULL
;
8267 tdep
->sc_reg_offset
= NULL
;
8268 tdep
->sc_pc_offset
= -1;
8269 tdep
->sc_sp_offset
= -1;
8271 tdep
->xsave_xcr0_offset
= -1;
8273 tdep
->record_regmap
= i386_record_regmap
;
8275 set_gdbarch_long_long_align_bit (gdbarch
, 32);
8277 /* The format used for `long double' on almost all i386 targets is
8278 the i387 extended floating-point format. In fact, of all targets
8279 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8280 on having a `long double' that's not `long' at all. */
8281 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8283 /* Although the i387 extended floating-point has only 80 significant
8284 bits, a `long double' actually takes up 96, probably to enforce
8286 set_gdbarch_long_double_bit (gdbarch
, 96);
8288 /* Register numbers of various important registers. */
8289 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8290 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8291 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8292 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8294 /* NOTE: kettenis/20040418: GCC does have two possible register
8295 numbering schemes on the i386: dbx and SVR4. These schemes
8296 differ in how they number %ebp, %esp, %eflags, and the
8297 floating-point registers, and are implemented by the arrays
8298 dbx_register_map[] and svr4_dbx_register_map in
8299 gcc/config/i386.c. GCC also defines a third numbering scheme in
8300 gcc/config/i386.c, which it designates as the "default" register
8301 map used in 64bit mode. This last register numbering scheme is
8302 implemented in dbx64_register_map, and is used for AMD64; see
8305 Currently, each GCC i386 target always uses the same register
8306 numbering scheme across all its supported debugging formats
8307 i.e. SDB (COFF), stabs and DWARF 2. This is because
8308 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8309 DBX_REGISTER_NUMBER macro which is defined by each target's
8310 respective config header in a manner independent of the requested
8311 output debugging format.
8313 This does not match the arrangement below, which presumes that
8314 the SDB and stabs numbering schemes differ from the DWARF and
8315 DWARF 2 ones. The reason for this arrangement is that it is
8316 likely to get the numbering scheme for the target's
8317 default/native debug format right. For targets where GCC is the
8318 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8319 targets where the native toolchain uses a different numbering
8320 scheme for a particular debug format (stabs-in-ELF on Solaris)
8321 the defaults below will have to be overridden, like
8322 i386_elf_init_abi() does. */
8324 /* Use the dbx register numbering scheme for stabs and COFF. */
8325 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8326 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8328 /* Use the SVR4 register numbering scheme for DWARF 2. */
8329 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
8331 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8332 be in use on any of the supported i386 targets. */
8334 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8336 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8338 /* Call dummy code. */
8339 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8340 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8341 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8342 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8344 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8345 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8346 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8348 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8350 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8352 /* Stack grows downward. */
8353 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8355 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
8356 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8357 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8359 set_gdbarch_frame_args_skip (gdbarch
, 8);
8361 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8363 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8365 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8367 /* Add the i386 register groups. */
8368 i386_add_reggroups (gdbarch
);
8369 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8371 /* Helper for function argument information. */
8372 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8374 /* Hook the function epilogue frame unwinder. This unwinder is
8375 appended to the list first, so that it supercedes the DWARF
8376 unwinder in function epilogues (where the DWARF unwinder
8377 currently fails). */
8378 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8380 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8381 to the list before the prologue-based unwinders, so that DWARF
8382 CFI info will be used if it is available. */
8383 dwarf2_append_unwinders (gdbarch
);
8385 frame_base_set_default (gdbarch
, &i386_frame_base
);
8387 /* Pseudo registers may be changed by amd64_init_abi. */
8388 set_gdbarch_pseudo_register_read_value (gdbarch
,
8389 i386_pseudo_register_read_value
);
8390 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8392 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8393 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8395 /* Override the normal target description method to make the AVX
8396 upper halves anonymous. */
8397 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8399 /* Even though the default ABI only includes general-purpose registers,
8400 floating-point registers and the SSE registers, we have to leave a
8401 gap for the upper AVX, MPX and AVX512 registers. */
8402 set_gdbarch_num_regs (gdbarch
, I386_AVX512_NUM_REGS
);
8404 /* Get the x86 target description from INFO. */
8405 tdesc
= info
.target_desc
;
8406 if (! tdesc_has_registers (tdesc
))
8408 tdep
->tdesc
= tdesc
;
8410 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8411 tdep
->register_names
= i386_register_names
;
8413 /* No upper YMM registers. */
8414 tdep
->ymmh_register_names
= NULL
;
8415 tdep
->ymm0h_regnum
= -1;
8417 /* No upper ZMM registers. */
8418 tdep
->zmmh_register_names
= NULL
;
8419 tdep
->zmm0h_regnum
= -1;
8421 /* No high XMM registers. */
8422 tdep
->xmm_avx512_register_names
= NULL
;
8423 tdep
->xmm16_regnum
= -1;
8425 /* No upper YMM16-31 registers. */
8426 tdep
->ymm16h_register_names
= NULL
;
8427 tdep
->ymm16h_regnum
= -1;
8429 tdep
->num_byte_regs
= 8;
8430 tdep
->num_word_regs
= 8;
8431 tdep
->num_dword_regs
= 0;
8432 tdep
->num_mmx_regs
= 8;
8433 tdep
->num_ymm_regs
= 0;
8435 /* No MPX registers. */
8436 tdep
->bnd0r_regnum
= -1;
8437 tdep
->bndcfgu_regnum
= -1;
8439 /* No AVX512 registers. */
8440 tdep
->k0_regnum
= -1;
8441 tdep
->num_zmm_regs
= 0;
8442 tdep
->num_ymm_avx512_regs
= 0;
8443 tdep
->num_xmm_avx512_regs
= 0;
8445 tdesc_data
= tdesc_data_alloc ();
8447 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8449 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8451 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8452 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8453 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8455 /* Hook in ABI-specific overrides, if they have been registered. */
8456 info
.tdep_info
= (void *) tdesc_data
;
8457 gdbarch_init_osabi (info
, gdbarch
);
8459 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8461 tdesc_data_cleanup (tdesc_data
);
8463 gdbarch_free (gdbarch
);
8467 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8469 /* Wire in pseudo registers. Number of pseudo registers may be
8471 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8472 + tdep
->num_word_regs
8473 + tdep
->num_dword_regs
8474 + tdep
->num_mmx_regs
8475 + tdep
->num_ymm_regs
8477 + tdep
->num_ymm_avx512_regs
8478 + tdep
->num_zmm_regs
));
8480 /* Target description may be changed. */
8481 tdesc
= tdep
->tdesc
;
8483 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8485 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8486 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8488 /* Make %al the first pseudo-register. */
8489 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8490 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8492 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8493 if (tdep
->num_dword_regs
)
8495 /* Support dword pseudo-register if it hasn't been disabled. */
8496 tdep
->eax_regnum
= ymm0_regnum
;
8497 ymm0_regnum
+= tdep
->num_dword_regs
;
8500 tdep
->eax_regnum
= -1;
8502 mm0_regnum
= ymm0_regnum
;
8503 if (tdep
->num_ymm_regs
)
8505 /* Support YMM pseudo-register if it is available. */
8506 tdep
->ymm0_regnum
= ymm0_regnum
;
8507 mm0_regnum
+= tdep
->num_ymm_regs
;
8510 tdep
->ymm0_regnum
= -1;
8512 if (tdep
->num_ymm_avx512_regs
)
8514 /* Support YMM16-31 pseudo registers if available. */
8515 tdep
->ymm16_regnum
= mm0_regnum
;
8516 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8519 tdep
->ymm16_regnum
= -1;
8521 if (tdep
->num_zmm_regs
)
8523 /* Support ZMM pseudo-register if it is available. */
8524 tdep
->zmm0_regnum
= mm0_regnum
;
8525 mm0_regnum
+= tdep
->num_zmm_regs
;
8528 tdep
->zmm0_regnum
= -1;
8530 bnd0_regnum
= mm0_regnum
;
8531 if (tdep
->num_mmx_regs
!= 0)
8533 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8534 tdep
->mm0_regnum
= mm0_regnum
;
8535 bnd0_regnum
+= tdep
->num_mmx_regs
;
8538 tdep
->mm0_regnum
= -1;
8540 if (tdep
->bnd0r_regnum
> 0)
8541 tdep
->bnd0_regnum
= bnd0_regnum
;
8543 tdep
-> bnd0_regnum
= -1;
8545 /* Hook in the legacy prologue-based unwinders last (fallback). */
8546 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8547 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8548 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8550 /* If we have a register mapping, enable the generic core file
8551 support, unless it has already been enabled. */
8552 if (tdep
->gregset_reg_offset
8553 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8554 set_gdbarch_iterate_over_regset_sections
8555 (gdbarch
, i386_iterate_over_regset_sections
);
8557 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8558 i386_fast_tracepoint_valid_at
);
8563 static enum gdb_osabi
8564 i386_coff_osabi_sniffer (bfd
*abfd
)
8566 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8567 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8568 return GDB_OSABI_GO32
;
8570 return GDB_OSABI_UNKNOWN
;
8574 /* Provide a prototype to silence -Wmissing-prototypes. */
8575 void _initialize_i386_tdep (void);
8578 _initialize_i386_tdep (void)
8580 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8582 /* Add the variable that controls the disassembly flavor. */
8583 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8584 &disassembly_flavor
, _("\
8585 Set the disassembly flavor."), _("\
8586 Show the disassembly flavor."), _("\
8587 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8589 NULL
, /* FIXME: i18n: */
8590 &setlist
, &showlist
);
8592 /* Add the variable that controls the convention for returning
8594 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
8595 &struct_convention
, _("\
8596 Set the convention for returning small structs."), _("\
8597 Show the convention for returning small structs."), _("\
8598 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8601 NULL
, /* FIXME: i18n: */
8602 &setlist
, &showlist
);
8604 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
8605 i386_coff_osabi_sniffer
);
8607 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
8608 i386_svr4_init_abi
);
8609 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
8610 i386_go32_init_abi
);
8612 /* Initialize the i386-specific register groups. */
8613 i386_init_reggroups ();
8615 /* Initialize the standard target descriptions. */
8616 initialize_tdesc_i386 ();
8617 initialize_tdesc_i386_mmx ();
8618 initialize_tdesc_i386_avx ();
8619 initialize_tdesc_i386_mpx ();
8620 initialize_tdesc_i386_avx512 ();
8622 /* Tell remote stub that we support XML target description. */
8623 register_remote_support_xml ("i386");