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[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "doublest.h"
22 #include "frame.h"
23 #include "gdbcore.h"
24 #include "inferior.h"
25 #include "language.h"
26 #include "regcache.h"
27 #include "value.h"
28
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "x86-xstate.h"
32
33 /* Print the floating point number specified by RAW. */
34
35 static void
36 print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38 {
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct floatformat *fmt
44 = floatformat_from_type (i387_ext_type (gdbarch));
45 std::string str = floatformat_to_string (fmt, raw, " %-+27.19g");
46 fprintf_filtered (file, "%s", str.c_str ());
47 }
48
49 /* Print the classification for the register contents RAW. */
50
51 static void
52 print_i387_ext (struct gdbarch *gdbarch,
53 const gdb_byte *raw, struct ui_file *file)
54 {
55 int sign;
56 int integer;
57 unsigned int exponent;
58 unsigned long fraction[2];
59
60 sign = raw[9] & 0x80;
61 integer = raw[7] & 0x80;
62 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
63 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
64 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
65 | (raw[5] << 8) | raw[4]);
66
67 if (exponent == 0x7fff && integer)
68 {
69 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
70 /* Infinity. */
71 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
72 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
73 /* Real Indefinite (QNaN). */
74 fputs_unfiltered (" Real Indefinite (QNaN)", file);
75 else if (fraction[1] & 0x40000000)
76 /* QNaN. */
77 fputs_filtered (" QNaN", file);
78 else
79 /* SNaN. */
80 fputs_filtered (" SNaN", file);
81 }
82 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
83 /* Normal. */
84 print_i387_value (gdbarch, raw, file);
85 else if (exponent == 0x0000)
86 {
87 /* Denormal or zero. */
88 print_i387_value (gdbarch, raw, file);
89
90 if (integer)
91 /* Pseudo-denormal. */
92 fputs_filtered (" Pseudo-denormal", file);
93 else if (fraction[0] || fraction[1])
94 /* Denormal. */
95 fputs_filtered (" Denormal", file);
96 }
97 else
98 /* Unsupported. */
99 fputs_filtered (" Unsupported", file);
100 }
101
102 /* Print the status word STATUS. If STATUS_P is false, then STATUS
103 was unavailable. */
104
105 static void
106 print_i387_status_word (int status_p,
107 unsigned int status, struct ui_file *file)
108 {
109 fprintf_filtered (file, "Status Word: ");
110 if (!status_p)
111 {
112 fprintf_filtered (file, "%s\n", _("<unavailable>"));
113 return;
114 }
115
116 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
117 fputs_filtered (" ", file);
118 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
119 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
120 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
121 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
122 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
123 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
124 fputs_filtered (" ", file);
125 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
126 fputs_filtered (" ", file);
127 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
128 fputs_filtered (" ", file);
129 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
130 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
131 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
132 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
133
134 fputs_filtered ("\n", file);
135
136 fprintf_filtered (file,
137 " TOP: %d\n", ((status >> 11) & 7));
138 }
139
140 /* Print the control word CONTROL. If CONTROL_P is false, then
141 CONTROL was unavailable. */
142
143 static void
144 print_i387_control_word (int control_p,
145 unsigned int control, struct ui_file *file)
146 {
147 fprintf_filtered (file, "Control Word: ");
148 if (!control_p)
149 {
150 fprintf_filtered (file, "%s\n", _("<unavailable>"));
151 return;
152 }
153
154 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
155 fputs_filtered (" ", file);
156 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
157 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
158 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
159 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
160 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
161 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
162
163 fputs_filtered ("\n", file);
164
165 fputs_filtered (" PC: ", file);
166 switch ((control >> 8) & 3)
167 {
168 case 0:
169 fputs_filtered ("Single Precision (24-bits)\n", file);
170 break;
171 case 1:
172 fputs_filtered ("Reserved\n", file);
173 break;
174 case 2:
175 fputs_filtered ("Double Precision (53-bits)\n", file);
176 break;
177 case 3:
178 fputs_filtered ("Extended Precision (64-bits)\n", file);
179 break;
180 }
181
182 fputs_filtered (" RC: ", file);
183 switch ((control >> 10) & 3)
184 {
185 case 0:
186 fputs_filtered ("Round to nearest\n", file);
187 break;
188 case 1:
189 fputs_filtered ("Round down\n", file);
190 break;
191 case 2:
192 fputs_filtered ("Round up\n", file);
193 break;
194 case 3:
195 fputs_filtered ("Round toward zero\n", file);
196 break;
197 }
198 }
199
200 /* Print out the i387 floating point state. Note that we ignore FRAME
201 in the code below. That's OK since floating-point registers are
202 never saved on the stack. */
203
204 void
205 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
206 struct frame_info *frame, const char *args)
207 {
208 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
209 ULONGEST fctrl;
210 int fctrl_p;
211 ULONGEST fstat;
212 int fstat_p;
213 ULONGEST ftag;
214 int ftag_p;
215 ULONGEST fiseg;
216 int fiseg_p;
217 ULONGEST fioff;
218 int fioff_p;
219 ULONGEST foseg;
220 int foseg_p;
221 ULONGEST fooff;
222 int fooff_p;
223 ULONGEST fop;
224 int fop_p;
225 int fpreg;
226 int top;
227
228 gdb_assert (gdbarch == get_frame_arch (frame));
229
230 fctrl_p = read_frame_register_unsigned (frame,
231 I387_FCTRL_REGNUM (tdep), &fctrl);
232 fstat_p = read_frame_register_unsigned (frame,
233 I387_FSTAT_REGNUM (tdep), &fstat);
234 ftag_p = read_frame_register_unsigned (frame,
235 I387_FTAG_REGNUM (tdep), &ftag);
236 fiseg_p = read_frame_register_unsigned (frame,
237 I387_FISEG_REGNUM (tdep), &fiseg);
238 fioff_p = read_frame_register_unsigned (frame,
239 I387_FIOFF_REGNUM (tdep), &fioff);
240 foseg_p = read_frame_register_unsigned (frame,
241 I387_FOSEG_REGNUM (tdep), &foseg);
242 fooff_p = read_frame_register_unsigned (frame,
243 I387_FOOFF_REGNUM (tdep), &fooff);
244 fop_p = read_frame_register_unsigned (frame,
245 I387_FOP_REGNUM (tdep), &fop);
246
247 if (fstat_p)
248 {
249 top = ((fstat >> 11) & 7);
250
251 for (fpreg = 7; fpreg >= 0; fpreg--)
252 {
253 struct value *regval;
254 int regnum;
255 int i;
256 int tag = -1;
257
258 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
259
260 if (ftag_p)
261 {
262 tag = (ftag >> (fpreg * 2)) & 3;
263
264 switch (tag)
265 {
266 case 0:
267 fputs_filtered ("Valid ", file);
268 break;
269 case 1:
270 fputs_filtered ("Zero ", file);
271 break;
272 case 2:
273 fputs_filtered ("Special ", file);
274 break;
275 case 3:
276 fputs_filtered ("Empty ", file);
277 break;
278 }
279 }
280 else
281 fputs_filtered ("Unknown ", file);
282
283 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
284 regval = get_frame_register_value (frame, regnum);
285
286 if (value_entirely_available (regval))
287 {
288 const gdb_byte *raw = value_contents (regval);
289
290 fputs_filtered ("0x", file);
291 for (i = 9; i >= 0; i--)
292 fprintf_filtered (file, "%02x", raw[i]);
293
294 if (tag != -1 && tag != 3)
295 print_i387_ext (gdbarch, raw, file);
296 }
297 else
298 fprintf_filtered (file, "%s", _("<unavailable>"));
299
300 fputs_filtered ("\n", file);
301 }
302 }
303
304 fputs_filtered ("\n", file);
305 print_i387_status_word (fstat_p, fstat, file);
306 print_i387_control_word (fctrl_p, fctrl, file);
307 fprintf_filtered (file, "Tag Word: %s\n",
308 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
309 fprintf_filtered (file, "Instruction Pointer: %s:",
310 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
311 fprintf_filtered (file, "%s\n",
312 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
313 fprintf_filtered (file, "Operand Pointer: %s:",
314 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
315 fprintf_filtered (file, "%s\n",
316 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
317 fprintf_filtered (file, "Opcode: %s\n",
318 fop_p
319 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
320 : _("<unavailable>"));
321 }
322 \f
323
324 /* Return nonzero if a value of type TYPE stored in register REGNUM
325 needs any special handling. */
326
327 int
328 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
329 struct type *type)
330 {
331 if (i386_fp_regnum_p (gdbarch, regnum))
332 {
333 /* Floating point registers must be converted unless we are
334 accessing them in their hardware type or TYPE is not float. */
335 if (type == i387_ext_type (gdbarch)
336 || TYPE_CODE (type) != TYPE_CODE_FLT)
337 return 0;
338 else
339 return 1;
340 }
341
342 return 0;
343 }
344
345 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
346 return its contents in TO. */
347
348 int
349 i387_register_to_value (struct frame_info *frame, int regnum,
350 struct type *type, gdb_byte *to,
351 int *optimizedp, int *unavailablep)
352 {
353 struct gdbarch *gdbarch = get_frame_arch (frame);
354 gdb_byte from[I386_MAX_REGISTER_SIZE];
355
356 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
357
358 /* We only support floating-point values. */
359 if (TYPE_CODE (type) != TYPE_CODE_FLT)
360 {
361 warning (_("Cannot convert floating-point register value "
362 "to non-floating-point type."));
363 *optimizedp = *unavailablep = 0;
364 return 0;
365 }
366
367 /* Convert to TYPE. */
368 if (!get_frame_register_bytes (frame, regnum, 0,
369 register_size (gdbarch, regnum),
370 from, optimizedp, unavailablep))
371 return 0;
372
373 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
374 *optimizedp = *unavailablep = 0;
375 return 1;
376 }
377
378 /* Write the contents FROM of a value of type TYPE into register
379 REGNUM in frame FRAME. */
380
381 void
382 i387_value_to_register (struct frame_info *frame, int regnum,
383 struct type *type, const gdb_byte *from)
384 {
385 struct gdbarch *gdbarch = get_frame_arch (frame);
386 gdb_byte to[I386_MAX_REGISTER_SIZE];
387
388 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
389
390 /* We only support floating-point values. */
391 if (TYPE_CODE (type) != TYPE_CODE_FLT)
392 {
393 warning (_("Cannot convert non-floating-point type "
394 "to floating-point register value."));
395 return;
396 }
397
398 /* Convert from TYPE. */
399 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
400 put_frame_register (frame, regnum, to);
401 }
402 \f
403
404 /* Handle FSAVE and FXSAVE formats. */
405
406 /* At fsave_offset[REGNUM] you'll find the offset to the location in
407 the data structure used by the "fsave" instruction where GDB
408 register REGNUM is stored. */
409
410 static int fsave_offset[] =
411 {
412 28 + 0 * 10, /* %st(0) ... */
413 28 + 1 * 10,
414 28 + 2 * 10,
415 28 + 3 * 10,
416 28 + 4 * 10,
417 28 + 5 * 10,
418 28 + 6 * 10,
419 28 + 7 * 10, /* ... %st(7). */
420 0, /* `fctrl' (16 bits). */
421 4, /* `fstat' (16 bits). */
422 8, /* `ftag' (16 bits). */
423 16, /* `fiseg' (16 bits). */
424 12, /* `fioff'. */
425 24, /* `foseg' (16 bits). */
426 20, /* `fooff'. */
427 18 /* `fop' (bottom 11 bits). */
428 };
429
430 #define FSAVE_ADDR(tdep, fsave, regnum) \
431 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
432 \f
433
434 /* Fill register REGNUM in REGCACHE with the appropriate value from
435 *FSAVE. This function masks off any of the reserved bits in
436 *FSAVE. */
437
438 void
439 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
440 {
441 struct gdbarch *gdbarch = regcache->arch ();
442 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
443 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
444 const gdb_byte *regs = (const gdb_byte *) fsave;
445 int i;
446
447 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
448
449 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
450 if (regnum == -1 || regnum == i)
451 {
452 if (fsave == NULL)
453 {
454 regcache_raw_supply (regcache, i, NULL);
455 continue;
456 }
457
458 /* Most of the FPU control registers occupy only 16 bits in the
459 fsave area. Give those a special treatment. */
460 if (i >= I387_FCTRL_REGNUM (tdep)
461 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
462 {
463 gdb_byte val[4];
464
465 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
466 val[2] = val[3] = 0;
467 if (i == I387_FOP_REGNUM (tdep))
468 val[1] &= ((1 << 3) - 1);
469 regcache_raw_supply (regcache, i, val);
470 }
471 else
472 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
473 }
474
475 /* Provide dummy values for the SSE registers. */
476 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
477 if (regnum == -1 || regnum == i)
478 regcache_raw_supply (regcache, i, NULL);
479 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
480 {
481 gdb_byte buf[4];
482
483 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
484 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
485 }
486 }
487
488 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
489 with the value from REGCACHE. If REGNUM is -1, do this for all
490 registers. This function doesn't touch any of the reserved bits in
491 *FSAVE. */
492
493 void
494 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
495 {
496 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
497 gdb_byte *regs = (gdb_byte *) fsave;
498 int i;
499
500 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
501
502 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
503 if (regnum == -1 || regnum == i)
504 {
505 /* Most of the FPU control registers occupy only 16 bits in
506 the fsave area. Give those a special treatment. */
507 if (i >= I387_FCTRL_REGNUM (tdep)
508 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
509 {
510 gdb_byte buf[4];
511
512 regcache_raw_collect (regcache, i, buf);
513
514 if (i == I387_FOP_REGNUM (tdep))
515 {
516 /* The opcode occupies only 11 bits. Make sure we
517 don't touch the other bits. */
518 buf[1] &= ((1 << 3) - 1);
519 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
520 }
521 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
522 }
523 else
524 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
525 }
526 }
527 \f
528
529 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
530 the data structure used by the "fxsave" instruction where GDB
531 register REGNUM is stored. */
532
533 static int fxsave_offset[] =
534 {
535 32, /* %st(0) through ... */
536 48,
537 64,
538 80,
539 96,
540 112,
541 128,
542 144, /* ... %st(7) (80 bits each). */
543 0, /* `fctrl' (16 bits). */
544 2, /* `fstat' (16 bits). */
545 4, /* `ftag' (16 bits). */
546 12, /* `fiseg' (16 bits). */
547 8, /* `fioff'. */
548 20, /* `foseg' (16 bits). */
549 16, /* `fooff'. */
550 6, /* `fop' (bottom 11 bits). */
551 160 + 0 * 16, /* %xmm0 through ... */
552 160 + 1 * 16,
553 160 + 2 * 16,
554 160 + 3 * 16,
555 160 + 4 * 16,
556 160 + 5 * 16,
557 160 + 6 * 16,
558 160 + 7 * 16,
559 160 + 8 * 16,
560 160 + 9 * 16,
561 160 + 10 * 16,
562 160 + 11 * 16,
563 160 + 12 * 16,
564 160 + 13 * 16,
565 160 + 14 * 16,
566 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
567 };
568
569 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
570 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
571
572 /* We made an unfortunate choice in putting %mxcsr after the SSE
573 registers %xmm0-%xmm7 instead of before, since it makes supporting
574 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
575 don't include the offset for %mxcsr here above. */
576
577 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
578
579 static int i387_tag (const gdb_byte *raw);
580 \f
581
582 /* Fill register REGNUM in REGCACHE with the appropriate
583 floating-point or SSE register value from *FXSAVE. This function
584 masks off any of the reserved bits in *FXSAVE. */
585
586 void
587 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
588 {
589 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
590 const gdb_byte *regs = (const gdb_byte *) fxsave;
591 int i;
592
593 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
594 gdb_assert (tdep->num_xmm_regs > 0);
595
596 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
597 if (regnum == -1 || regnum == i)
598 {
599 if (regs == NULL)
600 {
601 regcache_raw_supply (regcache, i, NULL);
602 continue;
603 }
604
605 /* Most of the FPU control registers occupy only 16 bits in
606 the fxsave area. Give those a special treatment. */
607 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
608 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
609 {
610 gdb_byte val[4];
611
612 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
613 val[2] = val[3] = 0;
614 if (i == I387_FOP_REGNUM (tdep))
615 val[1] &= ((1 << 3) - 1);
616 else if (i== I387_FTAG_REGNUM (tdep))
617 {
618 /* The fxsave area contains a simplified version of
619 the tag word. We have to look at the actual 80-bit
620 FP data to recreate the traditional i387 tag word. */
621
622 unsigned long ftag = 0;
623 int fpreg;
624 int top;
625
626 top = ((FXSAVE_ADDR (tdep, regs,
627 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
628 top &= 0x7;
629
630 for (fpreg = 7; fpreg >= 0; fpreg--)
631 {
632 int tag;
633
634 if (val[0] & (1 << fpreg))
635 {
636 int thisreg = (fpreg + 8 - top) % 8
637 + I387_ST0_REGNUM (tdep);
638 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
639 }
640 else
641 tag = 3; /* Empty */
642
643 ftag |= tag << (2 * fpreg);
644 }
645 val[0] = ftag & 0xff;
646 val[1] = (ftag >> 8) & 0xff;
647 }
648 regcache_raw_supply (regcache, i, val);
649 }
650 else
651 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
652 }
653
654 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
655 {
656 if (regs == NULL)
657 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
658 else
659 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
660 FXSAVE_MXCSR_ADDR (regs));
661 }
662 }
663
664 /* Fill register REGNUM (if it is a floating-point or SSE register) in
665 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
666 all registers. This function doesn't touch any of the reserved
667 bits in *FXSAVE. */
668
669 void
670 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
671 {
672 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
673 gdb_byte *regs = (gdb_byte *) fxsave;
674 int i;
675
676 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
677 gdb_assert (tdep->num_xmm_regs > 0);
678
679 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
680 if (regnum == -1 || regnum == i)
681 {
682 /* Most of the FPU control registers occupy only 16 bits in
683 the fxsave area. Give those a special treatment. */
684 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
685 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
686 {
687 gdb_byte buf[4];
688
689 regcache_raw_collect (regcache, i, buf);
690
691 if (i == I387_FOP_REGNUM (tdep))
692 {
693 /* The opcode occupies only 11 bits. Make sure we
694 don't touch the other bits. */
695 buf[1] &= ((1 << 3) - 1);
696 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
697 }
698 else if (i == I387_FTAG_REGNUM (tdep))
699 {
700 /* Converting back is much easier. */
701
702 unsigned short ftag;
703 int fpreg;
704
705 ftag = (buf[1] << 8) | buf[0];
706 buf[0] = 0;
707 buf[1] = 0;
708
709 for (fpreg = 7; fpreg >= 0; fpreg--)
710 {
711 int tag = (ftag >> (fpreg * 2)) & 3;
712
713 if (tag != 3)
714 buf[0] |= (1 << fpreg);
715 }
716 }
717 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
718 }
719 else
720 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
721 }
722
723 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
724 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
725 FXSAVE_MXCSR_ADDR (regs));
726 }
727
728 /* `xstate_bv' is at byte offset 512. */
729 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
730
731 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
732 the upper 128bit of AVX register data structure used by the "xsave"
733 instruction where GDB register REGNUM is stored. */
734
735 static int xsave_avxh_offset[] =
736 {
737 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
738 576 + 1 * 16,
739 576 + 2 * 16,
740 576 + 3 * 16,
741 576 + 4 * 16,
742 576 + 5 * 16,
743 576 + 6 * 16,
744 576 + 7 * 16,
745 576 + 8 * 16,
746 576 + 9 * 16,
747 576 + 10 * 16,
748 576 + 11 * 16,
749 576 + 12 * 16,
750 576 + 13 * 16,
751 576 + 14 * 16,
752 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
753 };
754
755 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
756 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
757
758 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
759 the upper 128bit of ZMM register data structure used by the "xsave"
760 instruction where GDB register REGNUM is stored. */
761
762 static int xsave_ymm_avx512_offset[] =
763 {
764 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
765 1664 + 16 + 0 * 64, /* %ymm16 through... */
766 1664 + 16 + 1 * 64,
767 1664 + 16 + 2 * 64,
768 1664 + 16 + 3 * 64,
769 1664 + 16 + 4 * 64,
770 1664 + 16 + 5 * 64,
771 1664 + 16 + 6 * 64,
772 1664 + 16 + 7 * 64,
773 1664 + 16 + 8 * 64,
774 1664 + 16 + 9 * 64,
775 1664 + 16 + 10 * 64,
776 1664 + 16 + 11 * 64,
777 1664 + 16 + 12 * 64,
778 1664 + 16 + 13 * 64,
779 1664 + 16 + 14 * 64,
780 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
781 };
782
783 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
784 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
785
786 static int xsave_xmm_avx512_offset[] =
787 {
788 1664 + 0 * 64, /* %ymm16 through... */
789 1664 + 1 * 64,
790 1664 + 2 * 64,
791 1664 + 3 * 64,
792 1664 + 4 * 64,
793 1664 + 5 * 64,
794 1664 + 6 * 64,
795 1664 + 7 * 64,
796 1664 + 8 * 64,
797 1664 + 9 * 64,
798 1664 + 10 * 64,
799 1664 + 11 * 64,
800 1664 + 12 * 64,
801 1664 + 13 * 64,
802 1664 + 14 * 64,
803 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
804 };
805
806 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
807 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
808
809 static int xsave_mpx_offset[] = {
810 960 + 0 * 16, /* bnd0r...bnd3r registers. */
811 960 + 1 * 16,
812 960 + 2 * 16,
813 960 + 3 * 16,
814 1024 + 0 * 8, /* bndcfg ... bndstatus. */
815 1024 + 1 * 8,
816 };
817
818 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
819 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
820
821 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
822 of the AVX512 opmask register data structure used by the "xsave"
823 instruction where GDB register REGNUM is stored. */
824
825 static int xsave_avx512_k_offset[] =
826 {
827 1088 + 0 * 8, /* %k0 through... */
828 1088 + 1 * 8,
829 1088 + 2 * 8,
830 1088 + 3 * 8,
831 1088 + 4 * 8,
832 1088 + 5 * 8,
833 1088 + 6 * 8,
834 1088 + 7 * 8 /* %k7 (64 bits each). */
835 };
836
837 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
838 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
839
840 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
841 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
842 instruction where GDB register REGNUM is stored. */
843
844 static int xsave_avx512_zmm_h_offset[] =
845 {
846 1152 + 0 * 32,
847 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
848 1152 + 2 * 32,
849 1152 + 3 * 32,
850 1152 + 4 * 32,
851 1152 + 5 * 32,
852 1152 + 6 * 32,
853 1152 + 7 * 32,
854 1152 + 8 * 32,
855 1152 + 9 * 32,
856 1152 + 10 * 32,
857 1152 + 11 * 32,
858 1152 + 12 * 32,
859 1152 + 13 * 32,
860 1152 + 14 * 32,
861 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
862 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
863 1664 + 32 + 1 * 64,
864 1664 + 32 + 2 * 64,
865 1664 + 32 + 3 * 64,
866 1664 + 32 + 4 * 64,
867 1664 + 32 + 5 * 64,
868 1664 + 32 + 6 * 64,
869 1664 + 32 + 7 * 64,
870 1664 + 32 + 8 * 64,
871 1664 + 32 + 9 * 64,
872 1664 + 32 + 10 * 64,
873 1664 + 32 + 11 * 64,
874 1664 + 32 + 12 * 64,
875 1664 + 32 + 13 * 64,
876 1664 + 32 + 14 * 64,
877 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
878 };
879
880 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
881 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
882
883 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location
884 of the PKRU register data structure used by the "xsave"
885 instruction where GDB register REGNUM is stored. */
886
887 static int xsave_pkeys_offset[] =
888 {
889 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
890 instructions and applications). */
891 };
892
893 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
894 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
895
896 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
897
898 void
899 i387_supply_xsave (struct regcache *regcache, int regnum,
900 const void *xsave)
901 {
902 struct gdbarch *gdbarch = regcache->arch ();
903 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
904 const gdb_byte *regs = (const gdb_byte *) xsave;
905 int i;
906 ULONGEST clear_bv;
907 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
908 enum
909 {
910 none = 0x0,
911 x87 = 0x1,
912 sse = 0x2,
913 avxh = 0x4,
914 mpx = 0x8,
915 avx512_k = 0x10,
916 avx512_zmm_h = 0x20,
917 avx512_ymmh_avx512 = 0x40,
918 avx512_xmm_avx512 = 0x80,
919 pkeys = 0x100,
920 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
921 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
922 } regclass;
923
924 gdb_assert (regs != NULL);
925 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
926 gdb_assert (tdep->num_xmm_regs > 0);
927
928 if (regnum == -1)
929 regclass = all;
930 else if (regnum >= I387_PKRU_REGNUM (tdep)
931 && regnum < I387_PKEYSEND_REGNUM (tdep))
932 regclass = pkeys;
933 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
934 && regnum < I387_ZMMENDH_REGNUM (tdep))
935 regclass = avx512_zmm_h;
936 else if (regnum >= I387_K0_REGNUM (tdep)
937 && regnum < I387_KEND_REGNUM (tdep))
938 regclass = avx512_k;
939 else if (regnum >= I387_YMM16H_REGNUM (tdep)
940 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
941 regclass = avx512_ymmh_avx512;
942 else if (regnum >= I387_XMM16_REGNUM (tdep)
943 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
944 regclass = avx512_xmm_avx512;
945 else if (regnum >= I387_YMM0H_REGNUM (tdep)
946 && regnum < I387_YMMENDH_REGNUM (tdep))
947 regclass = avxh;
948 else if (regnum >= I387_BND0R_REGNUM (tdep)
949 && regnum < I387_MPXEND_REGNUM (tdep))
950 regclass = mpx;
951 else if (regnum >= I387_XMM0_REGNUM (tdep)
952 && regnum < I387_MXCSR_REGNUM (tdep))
953 regclass = sse;
954 else if (regnum >= I387_ST0_REGNUM (tdep)
955 && regnum < I387_FCTRL_REGNUM (tdep))
956 regclass = x87;
957 else
958 regclass = none;
959
960 if (regclass != none)
961 {
962 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
963 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
964 ULONGEST xstate_bv = 0;
965
966 xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
967 8, byte_order);
968
969 /* Clear part in vector registers if its bit in xstat_bv is zero. */
970 clear_bv = (~(xstate_bv)) & tdep->xcr0;
971 }
972 else
973 clear_bv = X86_XSTATE_ALL_MASK;
974
975 /* With the delayed xsave mechanism, in between the program
976 starting, and the program accessing the vector registers for the
977 first time, the register's values are invalid. The kernel
978 initializes register states to zero when they are set the first
979 time in a program. This means that from the user-space programs'
980 perspective, it's the same as if the registers have always been
981 zero from the start of the program. Therefore, the debugger
982 should provide the same illusion to the user. */
983
984 switch (regclass)
985 {
986 case none:
987 break;
988
989 case pkeys:
990 if ((clear_bv & X86_XSTATE_PKRU))
991 regcache_raw_supply (regcache, regnum, zero);
992 else
993 regcache_raw_supply (regcache, regnum,
994 XSAVE_PKEYS_ADDR (tdep, regs, regnum));
995 return;
996
997 case avx512_zmm_h:
998 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
999 regcache_raw_supply (regcache, regnum, zero);
1000 else
1001 regcache_raw_supply (regcache, regnum,
1002 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
1003 return;
1004
1005 case avx512_k:
1006 if ((clear_bv & X86_XSTATE_K))
1007 regcache_raw_supply (regcache, regnum, zero);
1008 else
1009 regcache_raw_supply (regcache, regnum,
1010 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1011 return;
1012
1013 case avx512_ymmh_avx512:
1014 if ((clear_bv & X86_XSTATE_ZMM))
1015 regcache_raw_supply (regcache, regnum, zero);
1016 else
1017 regcache_raw_supply (regcache, regnum,
1018 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1019 return;
1020
1021 case avx512_xmm_avx512:
1022 if ((clear_bv & X86_XSTATE_ZMM))
1023 regcache_raw_supply (regcache, regnum, zero);
1024 else
1025 regcache_raw_supply (regcache, regnum,
1026 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1027 return;
1028
1029 case avxh:
1030 if ((clear_bv & X86_XSTATE_AVX))
1031 regcache_raw_supply (regcache, regnum, zero);
1032 else
1033 regcache_raw_supply (regcache, regnum,
1034 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1035 return;
1036
1037 case mpx:
1038 if ((clear_bv & X86_XSTATE_BNDREGS))
1039 regcache_raw_supply (regcache, regnum, zero);
1040 else
1041 regcache_raw_supply (regcache, regnum,
1042 XSAVE_MPX_ADDR (tdep, regs, regnum));
1043 return;
1044
1045 case sse:
1046 if ((clear_bv & X86_XSTATE_SSE))
1047 regcache_raw_supply (regcache, regnum, zero);
1048 else
1049 regcache_raw_supply (regcache, regnum,
1050 FXSAVE_ADDR (tdep, regs, regnum));
1051 return;
1052
1053 case x87:
1054 if ((clear_bv & X86_XSTATE_X87))
1055 regcache_raw_supply (regcache, regnum, zero);
1056 else
1057 regcache_raw_supply (regcache, regnum,
1058 FXSAVE_ADDR (tdep, regs, regnum));
1059 return;
1060
1061 case all:
1062 /* Handle PKEYS registers. */
1063 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1064 {
1065 if ((clear_bv & X86_XSTATE_PKRU))
1066 {
1067 for (i = I387_PKRU_REGNUM (tdep);
1068 i < I387_PKEYSEND_REGNUM (tdep);
1069 i++)
1070 regcache_raw_supply (regcache, i, zero);
1071 }
1072 else
1073 {
1074 for (i = I387_PKRU_REGNUM (tdep);
1075 i < I387_PKEYSEND_REGNUM (tdep);
1076 i++)
1077 regcache_raw_supply (regcache, i,
1078 XSAVE_PKEYS_ADDR (tdep, regs, i));
1079 }
1080 }
1081
1082 /* Handle the upper ZMM registers. */
1083 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1084 {
1085 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1086 {
1087 for (i = I387_ZMM0H_REGNUM (tdep);
1088 i < I387_ZMMENDH_REGNUM (tdep);
1089 i++)
1090 regcache_raw_supply (regcache, i, zero);
1091 }
1092 else
1093 {
1094 for (i = I387_ZMM0H_REGNUM (tdep);
1095 i < I387_ZMMENDH_REGNUM (tdep);
1096 i++)
1097 regcache_raw_supply (regcache, i,
1098 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1099 }
1100 }
1101
1102 /* Handle AVX512 OpMask registers. */
1103 if ((tdep->xcr0 & X86_XSTATE_K))
1104 {
1105 if ((clear_bv & X86_XSTATE_K))
1106 {
1107 for (i = I387_K0_REGNUM (tdep);
1108 i < I387_KEND_REGNUM (tdep);
1109 i++)
1110 regcache_raw_supply (regcache, i, zero);
1111 }
1112 else
1113 {
1114 for (i = I387_K0_REGNUM (tdep);
1115 i < I387_KEND_REGNUM (tdep);
1116 i++)
1117 regcache_raw_supply (regcache, i,
1118 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1119 }
1120 }
1121
1122 /* Handle the YMM_AVX512 registers. */
1123 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1124 {
1125 if ((clear_bv & X86_XSTATE_ZMM))
1126 {
1127 for (i = I387_YMM16H_REGNUM (tdep);
1128 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1129 i++)
1130 regcache_raw_supply (regcache, i, zero);
1131 for (i = I387_XMM16_REGNUM (tdep);
1132 i < I387_XMM_AVX512_END_REGNUM (tdep);
1133 i++)
1134 regcache_raw_supply (regcache, i, zero);
1135 }
1136 else
1137 {
1138 for (i = I387_YMM16H_REGNUM (tdep);
1139 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1140 i++)
1141 regcache_raw_supply (regcache, i,
1142 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1143 for (i = I387_XMM16_REGNUM (tdep);
1144 i < I387_XMM_AVX512_END_REGNUM (tdep);
1145 i++)
1146 regcache_raw_supply (regcache, i,
1147 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1148 }
1149 }
1150 /* Handle the upper YMM registers. */
1151 if ((tdep->xcr0 & X86_XSTATE_AVX))
1152 {
1153 if ((clear_bv & X86_XSTATE_AVX))
1154 {
1155 for (i = I387_YMM0H_REGNUM (tdep);
1156 i < I387_YMMENDH_REGNUM (tdep);
1157 i++)
1158 regcache_raw_supply (regcache, i, zero);
1159 }
1160 else
1161 {
1162 for (i = I387_YMM0H_REGNUM (tdep);
1163 i < I387_YMMENDH_REGNUM (tdep);
1164 i++)
1165 regcache_raw_supply (regcache, i,
1166 XSAVE_AVXH_ADDR (tdep, regs, i));
1167 }
1168 }
1169
1170 /* Handle the MPX registers. */
1171 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1172 {
1173 if (clear_bv & X86_XSTATE_BNDREGS)
1174 {
1175 for (i = I387_BND0R_REGNUM (tdep);
1176 i < I387_BNDCFGU_REGNUM (tdep); i++)
1177 regcache_raw_supply (regcache, i, zero);
1178 }
1179 else
1180 {
1181 for (i = I387_BND0R_REGNUM (tdep);
1182 i < I387_BNDCFGU_REGNUM (tdep); i++)
1183 regcache_raw_supply (regcache, i,
1184 XSAVE_MPX_ADDR (tdep, regs, i));
1185 }
1186 }
1187
1188 /* Handle the MPX registers. */
1189 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1190 {
1191 if (clear_bv & X86_XSTATE_BNDCFG)
1192 {
1193 for (i = I387_BNDCFGU_REGNUM (tdep);
1194 i < I387_MPXEND_REGNUM (tdep); i++)
1195 regcache_raw_supply (regcache, i, zero);
1196 }
1197 else
1198 {
1199 for (i = I387_BNDCFGU_REGNUM (tdep);
1200 i < I387_MPXEND_REGNUM (tdep); i++)
1201 regcache_raw_supply (regcache, i,
1202 XSAVE_MPX_ADDR (tdep, regs, i));
1203 }
1204 }
1205
1206 /* Handle the XMM registers. */
1207 if ((tdep->xcr0 & X86_XSTATE_SSE))
1208 {
1209 if ((clear_bv & X86_XSTATE_SSE))
1210 {
1211 for (i = I387_XMM0_REGNUM (tdep);
1212 i < I387_MXCSR_REGNUM (tdep);
1213 i++)
1214 regcache_raw_supply (regcache, i, zero);
1215 }
1216 else
1217 {
1218 for (i = I387_XMM0_REGNUM (tdep);
1219 i < I387_MXCSR_REGNUM (tdep); i++)
1220 regcache_raw_supply (regcache, i,
1221 FXSAVE_ADDR (tdep, regs, i));
1222 }
1223 }
1224
1225 /* Handle the x87 registers. */
1226 if ((tdep->xcr0 & X86_XSTATE_X87))
1227 {
1228 if ((clear_bv & X86_XSTATE_X87))
1229 {
1230 for (i = I387_ST0_REGNUM (tdep);
1231 i < I387_FCTRL_REGNUM (tdep);
1232 i++)
1233 regcache_raw_supply (regcache, i, zero);
1234 }
1235 else
1236 {
1237 for (i = I387_ST0_REGNUM (tdep);
1238 i < I387_FCTRL_REGNUM (tdep);
1239 i++)
1240 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1241 }
1242 }
1243 break;
1244 }
1245
1246 /* Only handle x87 control registers. */
1247 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1248 if (regnum == -1 || regnum == i)
1249 {
1250 /* Most of the FPU control registers occupy only 16 bits in
1251 the xsave extended state. Give those a special treatment. */
1252 if (i != I387_FIOFF_REGNUM (tdep)
1253 && i != I387_FOOFF_REGNUM (tdep))
1254 {
1255 gdb_byte val[4];
1256
1257 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1258 val[2] = val[3] = 0;
1259 if (i == I387_FOP_REGNUM (tdep))
1260 val[1] &= ((1 << 3) - 1);
1261 else if (i== I387_FTAG_REGNUM (tdep))
1262 {
1263 /* The fxsave area contains a simplified version of
1264 the tag word. We have to look at the actual 80-bit
1265 FP data to recreate the traditional i387 tag word. */
1266
1267 unsigned long ftag = 0;
1268 int fpreg;
1269 int top;
1270
1271 top = ((FXSAVE_ADDR (tdep, regs,
1272 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1273 top &= 0x7;
1274
1275 for (fpreg = 7; fpreg >= 0; fpreg--)
1276 {
1277 int tag;
1278
1279 if (val[0] & (1 << fpreg))
1280 {
1281 int thisreg = (fpreg + 8 - top) % 8
1282 + I387_ST0_REGNUM (tdep);
1283 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1284 }
1285 else
1286 tag = 3; /* Empty */
1287
1288 ftag |= tag << (2 * fpreg);
1289 }
1290 val[0] = ftag & 0xff;
1291 val[1] = (ftag >> 8) & 0xff;
1292 }
1293 regcache_raw_supply (regcache, i, val);
1294 }
1295 else
1296 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1297 }
1298
1299 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1300 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1301 FXSAVE_MXCSR_ADDR (regs));
1302 }
1303
1304 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1305
1306 void
1307 i387_collect_xsave (const struct regcache *regcache, int regnum,
1308 void *xsave, int gcore)
1309 {
1310 struct gdbarch *gdbarch = regcache->arch ();
1311 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1312 gdb_byte *regs = (gdb_byte *) xsave;
1313 int i;
1314 enum
1315 {
1316 none = 0x0,
1317 check = 0x1,
1318 x87 = 0x2 | check,
1319 sse = 0x4 | check,
1320 avxh = 0x8 | check,
1321 mpx = 0x10 | check,
1322 avx512_k = 0x20 | check,
1323 avx512_zmm_h = 0x40 | check,
1324 avx512_ymmh_avx512 = 0x80 | check,
1325 avx512_xmm_avx512 = 0x100 | check,
1326 pkeys = 0x200 | check,
1327 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1328 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1329 } regclass;
1330
1331 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1332 gdb_assert (tdep->num_xmm_regs > 0);
1333
1334 if (regnum == -1)
1335 regclass = all;
1336 else if (regnum >= I387_PKRU_REGNUM (tdep)
1337 && regnum < I387_PKEYSEND_REGNUM (tdep))
1338 regclass = pkeys;
1339 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1340 && regnum < I387_ZMMENDH_REGNUM (tdep))
1341 regclass = avx512_zmm_h;
1342 else if (regnum >= I387_K0_REGNUM (tdep)
1343 && regnum < I387_KEND_REGNUM (tdep))
1344 regclass = avx512_k;
1345 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1346 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1347 regclass = avx512_ymmh_avx512;
1348 else if (regnum >= I387_XMM16_REGNUM (tdep)
1349 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1350 regclass = avx512_xmm_avx512;
1351 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1352 && regnum < I387_YMMENDH_REGNUM (tdep))
1353 regclass = avxh;
1354 else if (regnum >= I387_BND0R_REGNUM (tdep)
1355 && regnum < I387_MPXEND_REGNUM (tdep))
1356 regclass = mpx;
1357 else if (regnum >= I387_XMM0_REGNUM (tdep)
1358 && regnum < I387_MXCSR_REGNUM (tdep))
1359 regclass = sse;
1360 else if (regnum >= I387_ST0_REGNUM (tdep)
1361 && regnum < I387_FCTRL_REGNUM (tdep))
1362 regclass = x87;
1363 else
1364 regclass = none;
1365
1366 if (gcore)
1367 {
1368 /* Clear XSAVE extended state. */
1369 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
1370
1371 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1372 if (tdep->xsave_xcr0_offset != -1)
1373 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1374 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1375 }
1376
1377 if ((regclass & check))
1378 {
1379 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1380 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1381 gdb_byte *p;
1382 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1383
1384 /* The supported bits in `xstat_bv' are 8 bytes. */
1385 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1386 8, byte_order);
1387 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1388
1389 /* Clear register set if its bit in xstat_bv is zero. */
1390 if (clear_bv)
1391 {
1392 if ((clear_bv & X86_XSTATE_PKRU))
1393 for (i = I387_PKRU_REGNUM (tdep);
1394 i < I387_PKEYSEND_REGNUM (tdep); i++)
1395 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1396
1397 if ((clear_bv & X86_XSTATE_BNDREGS))
1398 for (i = I387_BND0R_REGNUM (tdep);
1399 i < I387_BNDCFGU_REGNUM (tdep); i++)
1400 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1401
1402 if ((clear_bv & X86_XSTATE_BNDCFG))
1403 for (i = I387_BNDCFGU_REGNUM (tdep);
1404 i < I387_MPXEND_REGNUM (tdep); i++)
1405 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1406
1407 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1408 for (i = I387_ZMM0H_REGNUM (tdep);
1409 i < I387_ZMMENDH_REGNUM (tdep); i++)
1410 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1411
1412 if ((clear_bv & X86_XSTATE_K))
1413 for (i = I387_K0_REGNUM (tdep);
1414 i < I387_KEND_REGNUM (tdep); i++)
1415 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1416
1417 if ((clear_bv & X86_XSTATE_ZMM))
1418 {
1419 for (i = I387_YMM16H_REGNUM (tdep);
1420 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1421 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1422 for (i = I387_XMM16_REGNUM (tdep);
1423 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1424 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1425 }
1426
1427 if ((clear_bv & X86_XSTATE_AVX))
1428 for (i = I387_YMM0H_REGNUM (tdep);
1429 i < I387_YMMENDH_REGNUM (tdep); i++)
1430 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1431
1432 if ((clear_bv & X86_XSTATE_SSE))
1433 for (i = I387_XMM0_REGNUM (tdep);
1434 i < I387_MXCSR_REGNUM (tdep); i++)
1435 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1436
1437 if ((clear_bv & X86_XSTATE_X87))
1438 for (i = I387_ST0_REGNUM (tdep);
1439 i < I387_FCTRL_REGNUM (tdep); i++)
1440 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1441 }
1442
1443 if (regclass == all)
1444 {
1445 /* Check if any PKEYS registers are changed. */
1446 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1447 for (i = I387_PKRU_REGNUM (tdep);
1448 i < I387_PKEYSEND_REGNUM (tdep); i++)
1449 {
1450 regcache_raw_collect (regcache, i, raw);
1451 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1452 if (memcmp (raw, p, 4) != 0)
1453 {
1454 xstate_bv |= X86_XSTATE_PKRU;
1455 memcpy (p, raw, 4);
1456 }
1457 }
1458
1459 /* Check if any ZMMH registers are changed. */
1460 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1461 for (i = I387_ZMM0H_REGNUM (tdep);
1462 i < I387_ZMMENDH_REGNUM (tdep); i++)
1463 {
1464 regcache_raw_collect (regcache, i, raw);
1465 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1466 if (memcmp (raw, p, 32) != 0)
1467 {
1468 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1469 memcpy (p, raw, 32);
1470 }
1471 }
1472
1473 /* Check if any K registers are changed. */
1474 if ((tdep->xcr0 & X86_XSTATE_K))
1475 for (i = I387_K0_REGNUM (tdep);
1476 i < I387_KEND_REGNUM (tdep); i++)
1477 {
1478 regcache_raw_collect (regcache, i, raw);
1479 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1480 if (memcmp (raw, p, 8) != 0)
1481 {
1482 xstate_bv |= X86_XSTATE_K;
1483 memcpy (p, raw, 8);
1484 }
1485 }
1486
1487 /* Check if any XMM or upper YMM registers are changed. */
1488 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1489 {
1490 for (i = I387_YMM16H_REGNUM (tdep);
1491 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1492 {
1493 regcache_raw_collect (regcache, i, raw);
1494 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1495 if (memcmp (raw, p, 16) != 0)
1496 {
1497 xstate_bv |= X86_XSTATE_ZMM;
1498 memcpy (p, raw, 16);
1499 }
1500 }
1501 for (i = I387_XMM16_REGNUM (tdep);
1502 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1503 {
1504 regcache_raw_collect (regcache, i, raw);
1505 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1506 if (memcmp (raw, p, 16) != 0)
1507 {
1508 xstate_bv |= X86_XSTATE_ZMM;
1509 memcpy (p, raw, 16);
1510 }
1511 }
1512 }
1513
1514 /* Check if any upper YMM registers are changed. */
1515 if ((tdep->xcr0 & X86_XSTATE_AVX))
1516 for (i = I387_YMM0H_REGNUM (tdep);
1517 i < I387_YMMENDH_REGNUM (tdep); i++)
1518 {
1519 regcache_raw_collect (regcache, i, raw);
1520 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1521 if (memcmp (raw, p, 16))
1522 {
1523 xstate_bv |= X86_XSTATE_AVX;
1524 memcpy (p, raw, 16);
1525 }
1526 }
1527 /* Check if any upper MPX registers are changed. */
1528 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1529 for (i = I387_BND0R_REGNUM (tdep);
1530 i < I387_BNDCFGU_REGNUM (tdep); i++)
1531 {
1532 regcache_raw_collect (regcache, i, raw);
1533 p = XSAVE_MPX_ADDR (tdep, regs, i);
1534 if (memcmp (raw, p, 16))
1535 {
1536 xstate_bv |= X86_XSTATE_BNDREGS;
1537 memcpy (p, raw, 16);
1538 }
1539 }
1540
1541 /* Check if any upper MPX registers are changed. */
1542 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1543 for (i = I387_BNDCFGU_REGNUM (tdep);
1544 i < I387_MPXEND_REGNUM (tdep); i++)
1545 {
1546 regcache_raw_collect (regcache, i, raw);
1547 p = XSAVE_MPX_ADDR (tdep, regs, i);
1548 if (memcmp (raw, p, 8))
1549 {
1550 xstate_bv |= X86_XSTATE_BNDCFG;
1551 memcpy (p, raw, 8);
1552 }
1553 }
1554
1555 /* Check if any SSE registers are changed. */
1556 if ((tdep->xcr0 & X86_XSTATE_SSE))
1557 for (i = I387_XMM0_REGNUM (tdep);
1558 i < I387_MXCSR_REGNUM (tdep); i++)
1559 {
1560 regcache_raw_collect (regcache, i, raw);
1561 p = FXSAVE_ADDR (tdep, regs, i);
1562 if (memcmp (raw, p, 16))
1563 {
1564 xstate_bv |= X86_XSTATE_SSE;
1565 memcpy (p, raw, 16);
1566 }
1567 }
1568
1569 /* Check if any X87 registers are changed. */
1570 if ((tdep->xcr0 & X86_XSTATE_X87))
1571 for (i = I387_ST0_REGNUM (tdep);
1572 i < I387_FCTRL_REGNUM (tdep); i++)
1573 {
1574 regcache_raw_collect (regcache, i, raw);
1575 p = FXSAVE_ADDR (tdep, regs, i);
1576 if (memcmp (raw, p, 10))
1577 {
1578 xstate_bv |= X86_XSTATE_X87;
1579 memcpy (p, raw, 10);
1580 }
1581 }
1582 }
1583 else
1584 {
1585 /* Check if REGNUM is changed. */
1586 regcache_raw_collect (regcache, regnum, raw);
1587
1588 switch (regclass)
1589 {
1590 default:
1591 internal_error (__FILE__, __LINE__,
1592 _("invalid i387 regclass"));
1593
1594 case pkeys:
1595 /* This is a PKEYS register. */
1596 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1597 if (memcmp (raw, p, 4) != 0)
1598 {
1599 xstate_bv |= X86_XSTATE_PKRU;
1600 memcpy (p, raw, 4);
1601 }
1602 break;
1603
1604 case avx512_zmm_h:
1605 /* This is a ZMM register. */
1606 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1607 if (memcmp (raw, p, 32) != 0)
1608 {
1609 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1610 memcpy (p, raw, 32);
1611 }
1612 break;
1613 case avx512_k:
1614 /* This is a AVX512 mask register. */
1615 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1616 if (memcmp (raw, p, 8) != 0)
1617 {
1618 xstate_bv |= X86_XSTATE_K;
1619 memcpy (p, raw, 8);
1620 }
1621 break;
1622
1623 case avx512_ymmh_avx512:
1624 /* This is an upper YMM16-31 register. */
1625 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1626 if (memcmp (raw, p, 16) != 0)
1627 {
1628 xstate_bv |= X86_XSTATE_ZMM;
1629 memcpy (p, raw, 16);
1630 }
1631 break;
1632
1633 case avx512_xmm_avx512:
1634 /* This is an upper XMM16-31 register. */
1635 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1636 if (memcmp (raw, p, 16) != 0)
1637 {
1638 xstate_bv |= X86_XSTATE_ZMM;
1639 memcpy (p, raw, 16);
1640 }
1641 break;
1642
1643 case avxh:
1644 /* This is an upper YMM register. */
1645 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1646 if (memcmp (raw, p, 16))
1647 {
1648 xstate_bv |= X86_XSTATE_AVX;
1649 memcpy (p, raw, 16);
1650 }
1651 break;
1652
1653 case mpx:
1654 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1655 {
1656 regcache_raw_collect (regcache, regnum, raw);
1657 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1658 if (memcmp (raw, p, 16))
1659 {
1660 xstate_bv |= X86_XSTATE_BNDREGS;
1661 memcpy (p, raw, 16);
1662 }
1663 }
1664 else
1665 {
1666 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1667 xstate_bv |= X86_XSTATE_BNDCFG;
1668 memcpy (p, raw, 8);
1669 }
1670 break;
1671
1672 case sse:
1673 /* This is an SSE register. */
1674 p = FXSAVE_ADDR (tdep, regs, regnum);
1675 if (memcmp (raw, p, 16))
1676 {
1677 xstate_bv |= X86_XSTATE_SSE;
1678 memcpy (p, raw, 16);
1679 }
1680 break;
1681
1682 case x87:
1683 /* This is an x87 register. */
1684 p = FXSAVE_ADDR (tdep, regs, regnum);
1685 if (memcmp (raw, p, 10))
1686 {
1687 xstate_bv |= X86_XSTATE_X87;
1688 memcpy (p, raw, 10);
1689 }
1690 break;
1691 }
1692 }
1693
1694 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1695 registers are changed. */
1696 if (xstate_bv)
1697 {
1698 /* The supported bits in `xstat_bv' are 8 bytes. */
1699 initial_xstate_bv |= xstate_bv;
1700 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1701 8, byte_order,
1702 initial_xstate_bv);
1703
1704 switch (regclass)
1705 {
1706 default:
1707 internal_error (__FILE__, __LINE__,
1708 _("invalid i387 regclass"));
1709
1710 case all:
1711 break;
1712
1713 case x87:
1714 case sse:
1715 case avxh:
1716 case mpx:
1717 case avx512_k:
1718 case avx512_zmm_h:
1719 case avx512_ymmh_avx512:
1720 case avx512_xmm_avx512:
1721 case pkeys:
1722 /* Register REGNUM has been updated. Return. */
1723 return;
1724 }
1725 }
1726 else
1727 {
1728 /* Return if REGNUM isn't changed. */
1729 if (regclass != all)
1730 return;
1731 }
1732 }
1733
1734 /* Only handle x87 control registers. */
1735 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1736 if (regnum == -1 || regnum == i)
1737 {
1738 /* Most of the FPU control registers occupy only 16 bits in
1739 the xsave extended state. Give those a special treatment. */
1740 if (i != I387_FIOFF_REGNUM (tdep)
1741 && i != I387_FOOFF_REGNUM (tdep))
1742 {
1743 gdb_byte buf[4];
1744
1745 regcache_raw_collect (regcache, i, buf);
1746
1747 if (i == I387_FOP_REGNUM (tdep))
1748 {
1749 /* The opcode occupies only 11 bits. Make sure we
1750 don't touch the other bits. */
1751 buf[1] &= ((1 << 3) - 1);
1752 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1753 }
1754 else if (i == I387_FTAG_REGNUM (tdep))
1755 {
1756 /* Converting back is much easier. */
1757
1758 unsigned short ftag;
1759 int fpreg;
1760
1761 ftag = (buf[1] << 8) | buf[0];
1762 buf[0] = 0;
1763 buf[1] = 0;
1764
1765 for (fpreg = 7; fpreg >= 0; fpreg--)
1766 {
1767 int tag = (ftag >> (fpreg * 2)) & 3;
1768
1769 if (tag != 3)
1770 buf[0] |= (1 << fpreg);
1771 }
1772 }
1773 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1774 }
1775 else
1776 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1777 }
1778
1779 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1780 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1781 FXSAVE_MXCSR_ADDR (regs));
1782 }
1783
1784 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1785 *RAW. */
1786
1787 static int
1788 i387_tag (const gdb_byte *raw)
1789 {
1790 int integer;
1791 unsigned int exponent;
1792 unsigned long fraction[2];
1793
1794 integer = raw[7] & 0x80;
1795 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1796 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1797 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1798 | (raw[5] << 8) | raw[4]);
1799
1800 if (exponent == 0x7fff)
1801 {
1802 /* Special. */
1803 return (2);
1804 }
1805 else if (exponent == 0x0000)
1806 {
1807 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1808 {
1809 /* Zero. */
1810 return (1);
1811 }
1812 else
1813 {
1814 /* Special. */
1815 return (2);
1816 }
1817 }
1818 else
1819 {
1820 if (integer)
1821 {
1822 /* Valid. */
1823 return (0);
1824 }
1825 else
1826 {
1827 /* Special. */
1828 return (2);
1829 }
1830 }
1831 }
1832
1833 /* Prepare the FPU stack in REGCACHE for a function return. */
1834
1835 void
1836 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1837 {
1838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1839 ULONGEST fstat;
1840
1841 /* Set the top of the floating-point register stack to 7. The
1842 actual value doesn't really matter, but 7 is what a normal
1843 function return would end up with if the program started out with
1844 a freshly initialized FPU. */
1845 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1846 fstat |= (7 << 11);
1847 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1848
1849 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1850 floating-point register stack to 7, the appropriate value for the
1851 tag word is 0x3fff. */
1852 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1853
1854 }
1855
1856 /* See i387-tdep.h. */
1857
1858 void
1859 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
1860 {
1861 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1862
1863 if (I387_BND0R_REGNUM (tdep) > 0)
1864 {
1865 gdb_byte bnd_buf[16];
1866
1867 memset (bnd_buf, 0, 16);
1868 for (int i = 0; i < I387_NUM_BND_REGS; i++)
1869 regcache_raw_write (regcache, I387_BND0R_REGNUM (tdep) + i, bnd_buf);
1870 }
1871 }
GDB Binutils - Deliverables
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