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gdb/x86: Fix write out of mxcsr register for xsave targets
[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "frame.h"
22 #include "gdbcore.h"
23 #include "inferior.h"
24 #include "language.h"
25 #include "regcache.h"
26 #include "target-float.h"
27 #include "value.h"
28
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "x86-xstate.h"
32
33 /* Print the floating point number specified by RAW. */
34
35 static void
36 print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38 {
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type *type = i387_ext_type (gdbarch);
44 std::string str = target_float_to_string (raw, type, " %-+27.19g");
45 fprintf_filtered (file, "%s", str.c_str ());
46 }
47
48 /* Print the classification for the register contents RAW. */
49
50 static void
51 print_i387_ext (struct gdbarch *gdbarch,
52 const gdb_byte *raw, struct ui_file *file)
53 {
54 int sign;
55 int integer;
56 unsigned int exponent;
57 unsigned long fraction[2];
58
59 sign = raw[9] & 0x80;
60 integer = raw[7] & 0x80;
61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
64 | (raw[5] << 8) | raw[4]);
65
66 if (exponent == 0x7fff && integer)
67 {
68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
69 /* Infinity. */
70 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 fputs_unfiltered (" Real Indefinite (QNaN)", file);
74 else if (fraction[1] & 0x40000000)
75 /* QNaN. */
76 fputs_filtered (" QNaN", file);
77 else
78 /* SNaN. */
79 fputs_filtered (" SNaN", file);
80 }
81 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
82 /* Normal. */
83 print_i387_value (gdbarch, raw, file);
84 else if (exponent == 0x0000)
85 {
86 /* Denormal or zero. */
87 print_i387_value (gdbarch, raw, file);
88
89 if (integer)
90 /* Pseudo-denormal. */
91 fputs_filtered (" Pseudo-denormal", file);
92 else if (fraction[0] || fraction[1])
93 /* Denormal. */
94 fputs_filtered (" Denormal", file);
95 }
96 else
97 /* Unsupported. */
98 fputs_filtered (" Unsupported", file);
99 }
100
101 /* Print the status word STATUS. If STATUS_P is false, then STATUS
102 was unavailable. */
103
104 static void
105 print_i387_status_word (int status_p,
106 unsigned int status, struct ui_file *file)
107 {
108 fprintf_filtered (file, "Status Word: ");
109 if (!status_p)
110 {
111 fprintf_filtered (file, "%s\n", _("<unavailable>"));
112 return;
113 }
114
115 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
116 fputs_filtered (" ", file);
117 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
118 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
119 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
120 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
121 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
122 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
123 fputs_filtered (" ", file);
124 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
125 fputs_filtered (" ", file);
126 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
127 fputs_filtered (" ", file);
128 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
129 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
130 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
131 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
132
133 fputs_filtered ("\n", file);
134
135 fprintf_filtered (file,
136 " TOP: %d\n", ((status >> 11) & 7));
137 }
138
139 /* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
141
142 static void
143 print_i387_control_word (int control_p,
144 unsigned int control, struct ui_file *file)
145 {
146 fprintf_filtered (file, "Control Word: ");
147 if (!control_p)
148 {
149 fprintf_filtered (file, "%s\n", _("<unavailable>"));
150 return;
151 }
152
153 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
154 fputs_filtered (" ", file);
155 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
156 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
157 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
158 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
159 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
160 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
161
162 fputs_filtered ("\n", file);
163
164 fputs_filtered (" PC: ", file);
165 switch ((control >> 8) & 3)
166 {
167 case 0:
168 fputs_filtered ("Single Precision (24-bits)\n", file);
169 break;
170 case 1:
171 fputs_filtered ("Reserved\n", file);
172 break;
173 case 2:
174 fputs_filtered ("Double Precision (53-bits)\n", file);
175 break;
176 case 3:
177 fputs_filtered ("Extended Precision (64-bits)\n", file);
178 break;
179 }
180
181 fputs_filtered (" RC: ", file);
182 switch ((control >> 10) & 3)
183 {
184 case 0:
185 fputs_filtered ("Round to nearest\n", file);
186 break;
187 case 1:
188 fputs_filtered ("Round down\n", file);
189 break;
190 case 2:
191 fputs_filtered ("Round up\n", file);
192 break;
193 case 3:
194 fputs_filtered ("Round toward zero\n", file);
195 break;
196 }
197 }
198
199 /* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
202
203 void
204 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
205 struct frame_info *frame, const char *args)
206 {
207 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
208 ULONGEST fctrl;
209 int fctrl_p;
210 ULONGEST fstat;
211 int fstat_p;
212 ULONGEST ftag;
213 int ftag_p;
214 ULONGEST fiseg;
215 int fiseg_p;
216 ULONGEST fioff;
217 int fioff_p;
218 ULONGEST foseg;
219 int foseg_p;
220 ULONGEST fooff;
221 int fooff_p;
222 ULONGEST fop;
223 int fop_p;
224 int fpreg;
225 int top;
226
227 gdb_assert (gdbarch == get_frame_arch (frame));
228
229 fctrl_p = read_frame_register_unsigned (frame,
230 I387_FCTRL_REGNUM (tdep), &fctrl);
231 fstat_p = read_frame_register_unsigned (frame,
232 I387_FSTAT_REGNUM (tdep), &fstat);
233 ftag_p = read_frame_register_unsigned (frame,
234 I387_FTAG_REGNUM (tdep), &ftag);
235 fiseg_p = read_frame_register_unsigned (frame,
236 I387_FISEG_REGNUM (tdep), &fiseg);
237 fioff_p = read_frame_register_unsigned (frame,
238 I387_FIOFF_REGNUM (tdep), &fioff);
239 foseg_p = read_frame_register_unsigned (frame,
240 I387_FOSEG_REGNUM (tdep), &foseg);
241 fooff_p = read_frame_register_unsigned (frame,
242 I387_FOOFF_REGNUM (tdep), &fooff);
243 fop_p = read_frame_register_unsigned (frame,
244 I387_FOP_REGNUM (tdep), &fop);
245
246 if (fstat_p)
247 {
248 top = ((fstat >> 11) & 7);
249
250 for (fpreg = 7; fpreg >= 0; fpreg--)
251 {
252 struct value *regval;
253 int regnum;
254 int i;
255 int tag = -1;
256
257 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
258
259 if (ftag_p)
260 {
261 tag = (ftag >> (fpreg * 2)) & 3;
262
263 switch (tag)
264 {
265 case 0:
266 fputs_filtered ("Valid ", file);
267 break;
268 case 1:
269 fputs_filtered ("Zero ", file);
270 break;
271 case 2:
272 fputs_filtered ("Special ", file);
273 break;
274 case 3:
275 fputs_filtered ("Empty ", file);
276 break;
277 }
278 }
279 else
280 fputs_filtered ("Unknown ", file);
281
282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
283 regval = get_frame_register_value (frame, regnum);
284
285 if (value_entirely_available (regval))
286 {
287 const gdb_byte *raw = value_contents (regval);
288
289 fputs_filtered ("0x", file);
290 for (i = 9; i >= 0; i--)
291 fprintf_filtered (file, "%02x", raw[i]);
292
293 if (tag != -1 && tag != 3)
294 print_i387_ext (gdbarch, raw, file);
295 }
296 else
297 fprintf_filtered (file, "%s", _("<unavailable>"));
298
299 fputs_filtered ("\n", file);
300 }
301 }
302
303 fputs_filtered ("\n", file);
304 print_i387_status_word (fstat_p, fstat, file);
305 print_i387_control_word (fctrl_p, fctrl, file);
306 fprintf_filtered (file, "Tag Word: %s\n",
307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
308 fprintf_filtered (file, "Instruction Pointer: %s:",
309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
310 fprintf_filtered (file, "%s\n",
311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
312 fprintf_filtered (file, "Operand Pointer: %s:",
313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
314 fprintf_filtered (file, "%s\n",
315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
316 fprintf_filtered (file, "Opcode: %s\n",
317 fop_p
318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
319 : _("<unavailable>"));
320 }
321 \f
322
323 /* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
325
326 int
327 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
328 struct type *type)
329 {
330 if (i386_fp_regnum_p (gdbarch, regnum))
331 {
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type == i387_ext_type (gdbarch)
335 || TYPE_CODE (type) != TYPE_CODE_FLT)
336 return 0;
337 else
338 return 1;
339 }
340
341 return 0;
342 }
343
344 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
346
347 int
348 i387_register_to_value (struct frame_info *frame, int regnum,
349 struct type *type, gdb_byte *to,
350 int *optimizedp, int *unavailablep)
351 {
352 struct gdbarch *gdbarch = get_frame_arch (frame);
353 gdb_byte from[I386_MAX_REGISTER_SIZE];
354
355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
356
357 /* We only support floating-point values. */
358 if (TYPE_CODE (type) != TYPE_CODE_FLT)
359 {
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp = *unavailablep = 0;
363 return 0;
364 }
365
366 /* Convert to TYPE. */
367 if (!get_frame_register_bytes (frame, regnum, 0,
368 register_size (gdbarch, regnum),
369 from, optimizedp, unavailablep))
370 return 0;
371
372 target_float_convert (from, i387_ext_type (gdbarch), to, type);
373 *optimizedp = *unavailablep = 0;
374 return 1;
375 }
376
377 /* Write the contents FROM of a value of type TYPE into register
378 REGNUM in frame FRAME. */
379
380 void
381 i387_value_to_register (struct frame_info *frame, int regnum,
382 struct type *type, const gdb_byte *from)
383 {
384 struct gdbarch *gdbarch = get_frame_arch (frame);
385 gdb_byte to[I386_MAX_REGISTER_SIZE];
386
387 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
388
389 /* We only support floating-point values. */
390 if (TYPE_CODE (type) != TYPE_CODE_FLT)
391 {
392 warning (_("Cannot convert non-floating-point type "
393 "to floating-point register value."));
394 return;
395 }
396
397 /* Convert from TYPE. */
398 target_float_convert (from, type, to, i387_ext_type (gdbarch));
399 put_frame_register (frame, regnum, to);
400 }
401 \f
402
403 /* Handle FSAVE and FXSAVE formats. */
404
405 /* At fsave_offset[REGNUM] you'll find the offset to the location in
406 the data structure used by the "fsave" instruction where GDB
407 register REGNUM is stored. */
408
409 static int fsave_offset[] =
410 {
411 28 + 0 * 10, /* %st(0) ... */
412 28 + 1 * 10,
413 28 + 2 * 10,
414 28 + 3 * 10,
415 28 + 4 * 10,
416 28 + 5 * 10,
417 28 + 6 * 10,
418 28 + 7 * 10, /* ... %st(7). */
419 0, /* `fctrl' (16 bits). */
420 4, /* `fstat' (16 bits). */
421 8, /* `ftag' (16 bits). */
422 16, /* `fiseg' (16 bits). */
423 12, /* `fioff'. */
424 24, /* `foseg' (16 bits). */
425 20, /* `fooff'. */
426 18 /* `fop' (bottom 11 bits). */
427 };
428
429 #define FSAVE_ADDR(tdep, fsave, regnum) \
430 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
431 \f
432
433 /* Fill register REGNUM in REGCACHE with the appropriate value from
434 *FSAVE. This function masks off any of the reserved bits in
435 *FSAVE. */
436
437 void
438 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
439 {
440 struct gdbarch *gdbarch = regcache->arch ();
441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
442 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
443 const gdb_byte *regs = (const gdb_byte *) fsave;
444 int i;
445
446 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
447
448 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
449 if (regnum == -1 || regnum == i)
450 {
451 if (fsave == NULL)
452 {
453 regcache_raw_supply (regcache, i, NULL);
454 continue;
455 }
456
457 /* Most of the FPU control registers occupy only 16 bits in the
458 fsave area. Give those a special treatment. */
459 if (i >= I387_FCTRL_REGNUM (tdep)
460 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
461 {
462 gdb_byte val[4];
463
464 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
465 val[2] = val[3] = 0;
466 if (i == I387_FOP_REGNUM (tdep))
467 val[1] &= ((1 << 3) - 1);
468 regcache_raw_supply (regcache, i, val);
469 }
470 else
471 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
472 }
473
474 /* Provide dummy values for the SSE registers. */
475 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
476 if (regnum == -1 || regnum == i)
477 regcache_raw_supply (regcache, i, NULL);
478 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
479 {
480 gdb_byte buf[4];
481
482 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
483 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
484 }
485 }
486
487 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
488 with the value from REGCACHE. If REGNUM is -1, do this for all
489 registers. This function doesn't touch any of the reserved bits in
490 *FSAVE. */
491
492 void
493 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
494 {
495 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
496 gdb_byte *regs = (gdb_byte *) fsave;
497 int i;
498
499 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
500
501 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
502 if (regnum == -1 || regnum == i)
503 {
504 /* Most of the FPU control registers occupy only 16 bits in
505 the fsave area. Give those a special treatment. */
506 if (i >= I387_FCTRL_REGNUM (tdep)
507 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
508 {
509 gdb_byte buf[4];
510
511 regcache_raw_collect (regcache, i, buf);
512
513 if (i == I387_FOP_REGNUM (tdep))
514 {
515 /* The opcode occupies only 11 bits. Make sure we
516 don't touch the other bits. */
517 buf[1] &= ((1 << 3) - 1);
518 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
519 }
520 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
521 }
522 else
523 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
524 }
525 }
526 \f
527
528 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
529 the data structure used by the "fxsave" instruction where GDB
530 register REGNUM is stored. */
531
532 static int fxsave_offset[] =
533 {
534 32, /* %st(0) through ... */
535 48,
536 64,
537 80,
538 96,
539 112,
540 128,
541 144, /* ... %st(7) (80 bits each). */
542 0, /* `fctrl' (16 bits). */
543 2, /* `fstat' (16 bits). */
544 4, /* `ftag' (16 bits). */
545 12, /* `fiseg' (16 bits). */
546 8, /* `fioff'. */
547 20, /* `foseg' (16 bits). */
548 16, /* `fooff'. */
549 6, /* `fop' (bottom 11 bits). */
550 160 + 0 * 16, /* %xmm0 through ... */
551 160 + 1 * 16,
552 160 + 2 * 16,
553 160 + 3 * 16,
554 160 + 4 * 16,
555 160 + 5 * 16,
556 160 + 6 * 16,
557 160 + 7 * 16,
558 160 + 8 * 16,
559 160 + 9 * 16,
560 160 + 10 * 16,
561 160 + 11 * 16,
562 160 + 12 * 16,
563 160 + 13 * 16,
564 160 + 14 * 16,
565 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
566 };
567
568 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
569 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
570
571 /* We made an unfortunate choice in putting %mxcsr after the SSE
572 registers %xmm0-%xmm7 instead of before, since it makes supporting
573 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
574 don't include the offset for %mxcsr here above. */
575
576 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
577
578 static int i387_tag (const gdb_byte *raw);
579 \f
580
581 /* Fill register REGNUM in REGCACHE with the appropriate
582 floating-point or SSE register value from *FXSAVE. This function
583 masks off any of the reserved bits in *FXSAVE. */
584
585 void
586 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
587 {
588 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
589 const gdb_byte *regs = (const gdb_byte *) fxsave;
590 int i;
591
592 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
593 gdb_assert (tdep->num_xmm_regs > 0);
594
595 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
596 if (regnum == -1 || regnum == i)
597 {
598 if (regs == NULL)
599 {
600 regcache_raw_supply (regcache, i, NULL);
601 continue;
602 }
603
604 /* Most of the FPU control registers occupy only 16 bits in
605 the fxsave area. Give those a special treatment. */
606 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
607 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
608 {
609 gdb_byte val[4];
610
611 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
612 val[2] = val[3] = 0;
613 if (i == I387_FOP_REGNUM (tdep))
614 val[1] &= ((1 << 3) - 1);
615 else if (i== I387_FTAG_REGNUM (tdep))
616 {
617 /* The fxsave area contains a simplified version of
618 the tag word. We have to look at the actual 80-bit
619 FP data to recreate the traditional i387 tag word. */
620
621 unsigned long ftag = 0;
622 int fpreg;
623 int top;
624
625 top = ((FXSAVE_ADDR (tdep, regs,
626 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
627 top &= 0x7;
628
629 for (fpreg = 7; fpreg >= 0; fpreg--)
630 {
631 int tag;
632
633 if (val[0] & (1 << fpreg))
634 {
635 int thisreg = (fpreg + 8 - top) % 8
636 + I387_ST0_REGNUM (tdep);
637 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
638 }
639 else
640 tag = 3; /* Empty */
641
642 ftag |= tag << (2 * fpreg);
643 }
644 val[0] = ftag & 0xff;
645 val[1] = (ftag >> 8) & 0xff;
646 }
647 regcache_raw_supply (regcache, i, val);
648 }
649 else
650 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
651 }
652
653 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
654 {
655 if (regs == NULL)
656 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
657 else
658 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
659 FXSAVE_MXCSR_ADDR (regs));
660 }
661 }
662
663 /* Fill register REGNUM (if it is a floating-point or SSE register) in
664 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
665 all registers. This function doesn't touch any of the reserved
666 bits in *FXSAVE. */
667
668 void
669 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
670 {
671 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
672 gdb_byte *regs = (gdb_byte *) fxsave;
673 int i;
674
675 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
676 gdb_assert (tdep->num_xmm_regs > 0);
677
678 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
679 if (regnum == -1 || regnum == i)
680 {
681 /* Most of the FPU control registers occupy only 16 bits in
682 the fxsave area. Give those a special treatment. */
683 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
684 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
685 {
686 gdb_byte buf[4];
687
688 regcache_raw_collect (regcache, i, buf);
689
690 if (i == I387_FOP_REGNUM (tdep))
691 {
692 /* The opcode occupies only 11 bits. Make sure we
693 don't touch the other bits. */
694 buf[1] &= ((1 << 3) - 1);
695 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
696 }
697 else if (i == I387_FTAG_REGNUM (tdep))
698 {
699 /* Converting back is much easier. */
700
701 unsigned short ftag;
702 int fpreg;
703
704 ftag = (buf[1] << 8) | buf[0];
705 buf[0] = 0;
706 buf[1] = 0;
707
708 for (fpreg = 7; fpreg >= 0; fpreg--)
709 {
710 int tag = (ftag >> (fpreg * 2)) & 3;
711
712 if (tag != 3)
713 buf[0] |= (1 << fpreg);
714 }
715 }
716 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
717 }
718 else
719 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
720 }
721
722 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
723 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
724 FXSAVE_MXCSR_ADDR (regs));
725 }
726
727 /* `xstate_bv' is at byte offset 512. */
728 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
729
730 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
731 the upper 128bit of AVX register data structure used by the "xsave"
732 instruction where GDB register REGNUM is stored. */
733
734 static int xsave_avxh_offset[] =
735 {
736 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
737 576 + 1 * 16,
738 576 + 2 * 16,
739 576 + 3 * 16,
740 576 + 4 * 16,
741 576 + 5 * 16,
742 576 + 6 * 16,
743 576 + 7 * 16,
744 576 + 8 * 16,
745 576 + 9 * 16,
746 576 + 10 * 16,
747 576 + 11 * 16,
748 576 + 12 * 16,
749 576 + 13 * 16,
750 576 + 14 * 16,
751 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
752 };
753
754 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
755 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
756
757 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
758 the upper 128bit of ZMM register data structure used by the "xsave"
759 instruction where GDB register REGNUM is stored. */
760
761 static int xsave_ymm_avx512_offset[] =
762 {
763 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
764 1664 + 16 + 0 * 64, /* %ymm16 through... */
765 1664 + 16 + 1 * 64,
766 1664 + 16 + 2 * 64,
767 1664 + 16 + 3 * 64,
768 1664 + 16 + 4 * 64,
769 1664 + 16 + 5 * 64,
770 1664 + 16 + 6 * 64,
771 1664 + 16 + 7 * 64,
772 1664 + 16 + 8 * 64,
773 1664 + 16 + 9 * 64,
774 1664 + 16 + 10 * 64,
775 1664 + 16 + 11 * 64,
776 1664 + 16 + 12 * 64,
777 1664 + 16 + 13 * 64,
778 1664 + 16 + 14 * 64,
779 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
780 };
781
782 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
783 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
784
785 static int xsave_xmm_avx512_offset[] =
786 {
787 1664 + 0 * 64, /* %ymm16 through... */
788 1664 + 1 * 64,
789 1664 + 2 * 64,
790 1664 + 3 * 64,
791 1664 + 4 * 64,
792 1664 + 5 * 64,
793 1664 + 6 * 64,
794 1664 + 7 * 64,
795 1664 + 8 * 64,
796 1664 + 9 * 64,
797 1664 + 10 * 64,
798 1664 + 11 * 64,
799 1664 + 12 * 64,
800 1664 + 13 * 64,
801 1664 + 14 * 64,
802 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
803 };
804
805 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
806 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
807
808 static int xsave_mpx_offset[] = {
809 960 + 0 * 16, /* bnd0r...bnd3r registers. */
810 960 + 1 * 16,
811 960 + 2 * 16,
812 960 + 3 * 16,
813 1024 + 0 * 8, /* bndcfg ... bndstatus. */
814 1024 + 1 * 8,
815 };
816
817 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
818 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
819
820 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
821 of the AVX512 opmask register data structure used by the "xsave"
822 instruction where GDB register REGNUM is stored. */
823
824 static int xsave_avx512_k_offset[] =
825 {
826 1088 + 0 * 8, /* %k0 through... */
827 1088 + 1 * 8,
828 1088 + 2 * 8,
829 1088 + 3 * 8,
830 1088 + 4 * 8,
831 1088 + 5 * 8,
832 1088 + 6 * 8,
833 1088 + 7 * 8 /* %k7 (64 bits each). */
834 };
835
836 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
837 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
838
839 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
840 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
841 instruction where GDB register REGNUM is stored. */
842
843 static int xsave_avx512_zmm_h_offset[] =
844 {
845 1152 + 0 * 32,
846 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
847 1152 + 2 * 32,
848 1152 + 3 * 32,
849 1152 + 4 * 32,
850 1152 + 5 * 32,
851 1152 + 6 * 32,
852 1152 + 7 * 32,
853 1152 + 8 * 32,
854 1152 + 9 * 32,
855 1152 + 10 * 32,
856 1152 + 11 * 32,
857 1152 + 12 * 32,
858 1152 + 13 * 32,
859 1152 + 14 * 32,
860 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
861 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
862 1664 + 32 + 1 * 64,
863 1664 + 32 + 2 * 64,
864 1664 + 32 + 3 * 64,
865 1664 + 32 + 4 * 64,
866 1664 + 32 + 5 * 64,
867 1664 + 32 + 6 * 64,
868 1664 + 32 + 7 * 64,
869 1664 + 32 + 8 * 64,
870 1664 + 32 + 9 * 64,
871 1664 + 32 + 10 * 64,
872 1664 + 32 + 11 * 64,
873 1664 + 32 + 12 * 64,
874 1664 + 32 + 13 * 64,
875 1664 + 32 + 14 * 64,
876 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
877 };
878
879 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
880 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
881
882 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location
883 of the PKRU register data structure used by the "xsave"
884 instruction where GDB register REGNUM is stored. */
885
886 static int xsave_pkeys_offset[] =
887 {
888 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
889 instructions and applications). */
890 };
891
892 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
893 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
894
895
896 /* Extract from XSAVE a bitset of the features that are available on the
897 target, but which have not yet been enabled. */
898
899 ULONGEST
900 i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave)
901 {
902 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
903 const gdb_byte *regs = (const gdb_byte *) xsave;
904 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
905
906 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
907 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
908 8, byte_order);
909
910 /* Clear part in vector registers if its bit in xstat_bv is zero. */
911 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0;
912
913 return clear_bv;
914 }
915
916 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
917
918 void
919 i387_supply_xsave (struct regcache *regcache, int regnum,
920 const void *xsave)
921 {
922 struct gdbarch *gdbarch = regcache->arch ();
923 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
924 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
925 const gdb_byte *regs = (const gdb_byte *) xsave;
926 int i;
927 ULONGEST clear_bv;
928 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
929 enum
930 {
931 none = 0x0,
932 x87 = 0x1,
933 sse = 0x2,
934 avxh = 0x4,
935 mpx = 0x8,
936 avx512_k = 0x10,
937 avx512_zmm_h = 0x20,
938 avx512_ymmh_avx512 = 0x40,
939 avx512_xmm_avx512 = 0x80,
940 pkeys = 0x100,
941 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
942 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
943 } regclass;
944
945 gdb_assert (regs != NULL);
946 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
947 gdb_assert (tdep->num_xmm_regs > 0);
948
949 if (regnum == -1)
950 regclass = all;
951 else if (regnum >= I387_PKRU_REGNUM (tdep)
952 && regnum < I387_PKEYSEND_REGNUM (tdep))
953 regclass = pkeys;
954 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
955 && regnum < I387_ZMMENDH_REGNUM (tdep))
956 regclass = avx512_zmm_h;
957 else if (regnum >= I387_K0_REGNUM (tdep)
958 && regnum < I387_KEND_REGNUM (tdep))
959 regclass = avx512_k;
960 else if (regnum >= I387_YMM16H_REGNUM (tdep)
961 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
962 regclass = avx512_ymmh_avx512;
963 else if (regnum >= I387_XMM16_REGNUM (tdep)
964 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
965 regclass = avx512_xmm_avx512;
966 else if (regnum >= I387_YMM0H_REGNUM (tdep)
967 && regnum < I387_YMMENDH_REGNUM (tdep))
968 regclass = avxh;
969 else if (regnum >= I387_BND0R_REGNUM (tdep)
970 && regnum < I387_MPXEND_REGNUM (tdep))
971 regclass = mpx;
972 else if (regnum >= I387_XMM0_REGNUM (tdep)
973 && regnum < I387_MXCSR_REGNUM (tdep))
974 regclass = sse;
975 else if (regnum >= I387_ST0_REGNUM (tdep)
976 && regnum < I387_FCTRL_REGNUM (tdep))
977 regclass = x87;
978 else
979 regclass = none;
980
981 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
982
983 /* With the delayed xsave mechanism, in between the program
984 starting, and the program accessing the vector registers for the
985 first time, the register's values are invalid. The kernel
986 initializes register states to zero when they are set the first
987 time in a program. This means that from the user-space programs'
988 perspective, it's the same as if the registers have always been
989 zero from the start of the program. Therefore, the debugger
990 should provide the same illusion to the user. */
991
992 switch (regclass)
993 {
994 case none:
995 break;
996
997 case pkeys:
998 if ((clear_bv & X86_XSTATE_PKRU))
999 regcache_raw_supply (regcache, regnum, zero);
1000 else
1001 regcache_raw_supply (regcache, regnum,
1002 XSAVE_PKEYS_ADDR (tdep, regs, regnum));
1003 return;
1004
1005 case avx512_zmm_h:
1006 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1007 regcache_raw_supply (regcache, regnum, zero);
1008 else
1009 regcache_raw_supply (regcache, regnum,
1010 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
1011 return;
1012
1013 case avx512_k:
1014 if ((clear_bv & X86_XSTATE_K))
1015 regcache_raw_supply (regcache, regnum, zero);
1016 else
1017 regcache_raw_supply (regcache, regnum,
1018 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1019 return;
1020
1021 case avx512_ymmh_avx512:
1022 if ((clear_bv & X86_XSTATE_ZMM))
1023 regcache_raw_supply (regcache, regnum, zero);
1024 else
1025 regcache_raw_supply (regcache, regnum,
1026 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1027 return;
1028
1029 case avx512_xmm_avx512:
1030 if ((clear_bv & X86_XSTATE_ZMM))
1031 regcache_raw_supply (regcache, regnum, zero);
1032 else
1033 regcache_raw_supply (regcache, regnum,
1034 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1035 return;
1036
1037 case avxh:
1038 if ((clear_bv & X86_XSTATE_AVX))
1039 regcache_raw_supply (regcache, regnum, zero);
1040 else
1041 regcache_raw_supply (regcache, regnum,
1042 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1043 return;
1044
1045 case mpx:
1046 if ((clear_bv & X86_XSTATE_BNDREGS))
1047 regcache_raw_supply (regcache, regnum, zero);
1048 else
1049 regcache_raw_supply (regcache, regnum,
1050 XSAVE_MPX_ADDR (tdep, regs, regnum));
1051 return;
1052
1053 case sse:
1054 if ((clear_bv & X86_XSTATE_SSE))
1055 regcache_raw_supply (regcache, regnum, zero);
1056 else
1057 regcache_raw_supply (regcache, regnum,
1058 FXSAVE_ADDR (tdep, regs, regnum));
1059 return;
1060
1061 case x87:
1062 if ((clear_bv & X86_XSTATE_X87))
1063 regcache_raw_supply (regcache, regnum, zero);
1064 else
1065 regcache_raw_supply (regcache, regnum,
1066 FXSAVE_ADDR (tdep, regs, regnum));
1067 return;
1068
1069 case all:
1070 /* Handle PKEYS registers. */
1071 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1072 {
1073 if ((clear_bv & X86_XSTATE_PKRU))
1074 {
1075 for (i = I387_PKRU_REGNUM (tdep);
1076 i < I387_PKEYSEND_REGNUM (tdep);
1077 i++)
1078 regcache_raw_supply (regcache, i, zero);
1079 }
1080 else
1081 {
1082 for (i = I387_PKRU_REGNUM (tdep);
1083 i < I387_PKEYSEND_REGNUM (tdep);
1084 i++)
1085 regcache_raw_supply (regcache, i,
1086 XSAVE_PKEYS_ADDR (tdep, regs, i));
1087 }
1088 }
1089
1090 /* Handle the upper ZMM registers. */
1091 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1092 {
1093 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1094 {
1095 for (i = I387_ZMM0H_REGNUM (tdep);
1096 i < I387_ZMMENDH_REGNUM (tdep);
1097 i++)
1098 regcache_raw_supply (regcache, i, zero);
1099 }
1100 else
1101 {
1102 for (i = I387_ZMM0H_REGNUM (tdep);
1103 i < I387_ZMMENDH_REGNUM (tdep);
1104 i++)
1105 regcache_raw_supply (regcache, i,
1106 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1107 }
1108 }
1109
1110 /* Handle AVX512 OpMask registers. */
1111 if ((tdep->xcr0 & X86_XSTATE_K))
1112 {
1113 if ((clear_bv & X86_XSTATE_K))
1114 {
1115 for (i = I387_K0_REGNUM (tdep);
1116 i < I387_KEND_REGNUM (tdep);
1117 i++)
1118 regcache_raw_supply (regcache, i, zero);
1119 }
1120 else
1121 {
1122 for (i = I387_K0_REGNUM (tdep);
1123 i < I387_KEND_REGNUM (tdep);
1124 i++)
1125 regcache_raw_supply (regcache, i,
1126 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1127 }
1128 }
1129
1130 /* Handle the YMM_AVX512 registers. */
1131 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1132 {
1133 if ((clear_bv & X86_XSTATE_ZMM))
1134 {
1135 for (i = I387_YMM16H_REGNUM (tdep);
1136 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1137 i++)
1138 regcache_raw_supply (regcache, i, zero);
1139 for (i = I387_XMM16_REGNUM (tdep);
1140 i < I387_XMM_AVX512_END_REGNUM (tdep);
1141 i++)
1142 regcache_raw_supply (regcache, i, zero);
1143 }
1144 else
1145 {
1146 for (i = I387_YMM16H_REGNUM (tdep);
1147 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1148 i++)
1149 regcache_raw_supply (regcache, i,
1150 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1151 for (i = I387_XMM16_REGNUM (tdep);
1152 i < I387_XMM_AVX512_END_REGNUM (tdep);
1153 i++)
1154 regcache_raw_supply (regcache, i,
1155 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1156 }
1157 }
1158 /* Handle the upper YMM registers. */
1159 if ((tdep->xcr0 & X86_XSTATE_AVX))
1160 {
1161 if ((clear_bv & X86_XSTATE_AVX))
1162 {
1163 for (i = I387_YMM0H_REGNUM (tdep);
1164 i < I387_YMMENDH_REGNUM (tdep);
1165 i++)
1166 regcache_raw_supply (regcache, i, zero);
1167 }
1168 else
1169 {
1170 for (i = I387_YMM0H_REGNUM (tdep);
1171 i < I387_YMMENDH_REGNUM (tdep);
1172 i++)
1173 regcache_raw_supply (regcache, i,
1174 XSAVE_AVXH_ADDR (tdep, regs, i));
1175 }
1176 }
1177
1178 /* Handle the MPX registers. */
1179 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1180 {
1181 if (clear_bv & X86_XSTATE_BNDREGS)
1182 {
1183 for (i = I387_BND0R_REGNUM (tdep);
1184 i < I387_BNDCFGU_REGNUM (tdep); i++)
1185 regcache_raw_supply (regcache, i, zero);
1186 }
1187 else
1188 {
1189 for (i = I387_BND0R_REGNUM (tdep);
1190 i < I387_BNDCFGU_REGNUM (tdep); i++)
1191 regcache_raw_supply (regcache, i,
1192 XSAVE_MPX_ADDR (tdep, regs, i));
1193 }
1194 }
1195
1196 /* Handle the MPX registers. */
1197 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1198 {
1199 if (clear_bv & X86_XSTATE_BNDCFG)
1200 {
1201 for (i = I387_BNDCFGU_REGNUM (tdep);
1202 i < I387_MPXEND_REGNUM (tdep); i++)
1203 regcache_raw_supply (regcache, i, zero);
1204 }
1205 else
1206 {
1207 for (i = I387_BNDCFGU_REGNUM (tdep);
1208 i < I387_MPXEND_REGNUM (tdep); i++)
1209 regcache_raw_supply (regcache, i,
1210 XSAVE_MPX_ADDR (tdep, regs, i));
1211 }
1212 }
1213
1214 /* Handle the XMM registers. */
1215 if ((tdep->xcr0 & X86_XSTATE_SSE))
1216 {
1217 if ((clear_bv & X86_XSTATE_SSE))
1218 {
1219 for (i = I387_XMM0_REGNUM (tdep);
1220 i < I387_MXCSR_REGNUM (tdep);
1221 i++)
1222 regcache_raw_supply (regcache, i, zero);
1223 }
1224 else
1225 {
1226 for (i = I387_XMM0_REGNUM (tdep);
1227 i < I387_MXCSR_REGNUM (tdep); i++)
1228 regcache_raw_supply (regcache, i,
1229 FXSAVE_ADDR (tdep, regs, i));
1230 }
1231 }
1232
1233 /* Handle the x87 registers. */
1234 if ((tdep->xcr0 & X86_XSTATE_X87))
1235 {
1236 if ((clear_bv & X86_XSTATE_X87))
1237 {
1238 for (i = I387_ST0_REGNUM (tdep);
1239 i < I387_FCTRL_REGNUM (tdep);
1240 i++)
1241 regcache_raw_supply (regcache, i, zero);
1242 }
1243 else
1244 {
1245 for (i = I387_ST0_REGNUM (tdep);
1246 i < I387_FCTRL_REGNUM (tdep);
1247 i++)
1248 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1249 }
1250 }
1251 break;
1252 }
1253
1254 /* Only handle x87 control registers. */
1255 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1256 if (regnum == -1 || regnum == i)
1257 {
1258 if (clear_bv & X86_XSTATE_X87)
1259 {
1260 if (i == I387_FCTRL_REGNUM (tdep))
1261 {
1262 gdb_byte buf[4];
1263
1264 store_unsigned_integer (buf, 4, byte_order,
1265 I387_FCTRL_INIT_VAL);
1266 regcache_raw_supply (regcache, i, buf);
1267 }
1268 else if (i == I387_FTAG_REGNUM (tdep))
1269 {
1270 gdb_byte buf[4];
1271
1272 store_unsigned_integer (buf, 4, byte_order, 0xffff);
1273 regcache_raw_supply (regcache, i, buf);
1274 }
1275 else
1276 regcache_raw_supply (regcache, i, zero);
1277 }
1278 /* Most of the FPU control registers occupy only 16 bits in
1279 the xsave extended state. Give those a special treatment. */
1280 else if (i != I387_FIOFF_REGNUM (tdep)
1281 && i != I387_FOOFF_REGNUM (tdep))
1282 {
1283 gdb_byte val[4];
1284
1285 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1286 val[2] = val[3] = 0;
1287 if (i == I387_FOP_REGNUM (tdep))
1288 val[1] &= ((1 << 3) - 1);
1289 else if (i == I387_FTAG_REGNUM (tdep))
1290 {
1291 /* The fxsave area contains a simplified version of
1292 the tag word. We have to look at the actual 80-bit
1293 FP data to recreate the traditional i387 tag word. */
1294
1295 unsigned long ftag = 0;
1296 int fpreg;
1297 int top;
1298
1299 top = ((FXSAVE_ADDR (tdep, regs,
1300 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1301 top &= 0x7;
1302
1303 for (fpreg = 7; fpreg >= 0; fpreg--)
1304 {
1305 int tag;
1306
1307 if (val[0] & (1 << fpreg))
1308 {
1309 int thisreg = (fpreg + 8 - top) % 8
1310 + I387_ST0_REGNUM (tdep);
1311 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1312 }
1313 else
1314 tag = 3; /* Empty */
1315
1316 ftag |= tag << (2 * fpreg);
1317 }
1318 val[0] = ftag & 0xff;
1319 val[1] = (ftag >> 8) & 0xff;
1320 }
1321 regcache_raw_supply (regcache, i, val);
1322 }
1323 else
1324 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1325 }
1326
1327 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1328 {
1329 /* The MXCSR register is placed into the xsave buffer if either the
1330 AVX or SSE features are enabled. */
1331 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1332 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1333 {
1334 gdb_byte buf[4];
1335
1336 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
1337 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
1338 }
1339 else
1340 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1341 FXSAVE_MXCSR_ADDR (regs));
1342 }
1343 }
1344
1345 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1346
1347 void
1348 i387_collect_xsave (const struct regcache *regcache, int regnum,
1349 void *xsave, int gcore)
1350 {
1351 struct gdbarch *gdbarch = regcache->arch ();
1352 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1353 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1354 gdb_byte *p, *regs = (gdb_byte *) xsave;
1355 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1356 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1357 int i;
1358 enum
1359 {
1360 x87_ctrl_or_mxcsr = 0x1,
1361 x87 = 0x2,
1362 sse = 0x4,
1363 avxh = 0x8,
1364 mpx = 0x10,
1365 avx512_k = 0x20,
1366 avx512_zmm_h = 0x40,
1367 avx512_ymmh_avx512 = 0x80,
1368 avx512_xmm_avx512 = 0x100,
1369 pkeys = 0x200,
1370 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1371 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1372 } regclass;
1373
1374 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1375 gdb_assert (tdep->num_xmm_regs > 0);
1376
1377 if (regnum == -1)
1378 regclass = all;
1379 else if (regnum >= I387_PKRU_REGNUM (tdep)
1380 && regnum < I387_PKEYSEND_REGNUM (tdep))
1381 regclass = pkeys;
1382 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1383 && regnum < I387_ZMMENDH_REGNUM (tdep))
1384 regclass = avx512_zmm_h;
1385 else if (regnum >= I387_K0_REGNUM (tdep)
1386 && regnum < I387_KEND_REGNUM (tdep))
1387 regclass = avx512_k;
1388 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1389 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1390 regclass = avx512_ymmh_avx512;
1391 else if (regnum >= I387_XMM16_REGNUM (tdep)
1392 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1393 regclass = avx512_xmm_avx512;
1394 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1395 && regnum < I387_YMMENDH_REGNUM (tdep))
1396 regclass = avxh;
1397 else if (regnum >= I387_BND0R_REGNUM (tdep)
1398 && regnum < I387_MPXEND_REGNUM (tdep))
1399 regclass = mpx;
1400 else if (regnum >= I387_XMM0_REGNUM (tdep)
1401 && regnum < I387_MXCSR_REGNUM (tdep))
1402 regclass = sse;
1403 else if (regnum >= I387_ST0_REGNUM (tdep)
1404 && regnum < I387_FCTRL_REGNUM (tdep))
1405 regclass = x87;
1406 else if ((regnum >= I387_FCTRL_REGNUM (tdep)
1407 && regnum < I387_XMM0_REGNUM (tdep))
1408 || regnum == I387_MXCSR_REGNUM (tdep))
1409 regclass = x87_ctrl_or_mxcsr;
1410 else
1411 internal_error (__FILE__, __LINE__, _("invalid i387 regnum %d"), regnum);
1412
1413 if (gcore)
1414 {
1415 /* Clear XSAVE extended state. */
1416 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
1417
1418 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1419 if (tdep->xsave_xcr0_offset != -1)
1420 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1421 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1422 }
1423
1424 /* The supported bits in `xstat_bv' are 8 bytes. */
1425 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1426 8, byte_order);
1427 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1428
1429 /* The XSAVE buffer was filled lazily by the kernel. Only those
1430 features that are enabled were written into the buffer, disabled
1431 features left the buffer uninitialised. In order to identify if any
1432 registers have changed we will be comparing the register cache
1433 version to the version in the XSAVE buffer, it is important then that
1434 at this point we initialise to the default values any features in
1435 XSAVE that are not yet initialised.
1436
1437 This could be made more efficient, we know which features (from
1438 REGNUM) we will be potentially updating, and could limit ourselves to
1439 only clearing that feature. However, the extra complexity does not
1440 seem justified at this point. */
1441 if (clear_bv)
1442 {
1443 if ((clear_bv & X86_XSTATE_PKRU))
1444 for (i = I387_PKRU_REGNUM (tdep);
1445 i < I387_PKEYSEND_REGNUM (tdep); i++)
1446 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1447
1448 if ((clear_bv & X86_XSTATE_BNDREGS))
1449 for (i = I387_BND0R_REGNUM (tdep);
1450 i < I387_BNDCFGU_REGNUM (tdep); i++)
1451 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1452
1453 if ((clear_bv & X86_XSTATE_BNDCFG))
1454 for (i = I387_BNDCFGU_REGNUM (tdep);
1455 i < I387_MPXEND_REGNUM (tdep); i++)
1456 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1457
1458 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1459 for (i = I387_ZMM0H_REGNUM (tdep);
1460 i < I387_ZMMENDH_REGNUM (tdep); i++)
1461 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1462
1463 if ((clear_bv & X86_XSTATE_K))
1464 for (i = I387_K0_REGNUM (tdep);
1465 i < I387_KEND_REGNUM (tdep); i++)
1466 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1467
1468 if ((clear_bv & X86_XSTATE_ZMM))
1469 {
1470 for (i = I387_YMM16H_REGNUM (tdep);
1471 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1472 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1473 for (i = I387_XMM16_REGNUM (tdep);
1474 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1475 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1476 }
1477
1478 if ((clear_bv & X86_XSTATE_AVX))
1479 for (i = I387_YMM0H_REGNUM (tdep);
1480 i < I387_YMMENDH_REGNUM (tdep); i++)
1481 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1482
1483 if ((clear_bv & X86_XSTATE_SSE))
1484 for (i = I387_XMM0_REGNUM (tdep);
1485 i < I387_MXCSR_REGNUM (tdep); i++)
1486 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1487
1488 /* The mxcsr register is written into the xsave buffer if either AVX
1489 or SSE is enabled, so only clear it if both of those features
1490 require clearing. */
1491 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1492 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1493 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order,
1494 I387_MXCSR_INIT_VAL);
1495
1496 if ((clear_bv & X86_XSTATE_X87))
1497 {
1498 for (i = I387_ST0_REGNUM (tdep);
1499 i < I387_FCTRL_REGNUM (tdep); i++)
1500 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1501
1502 for (i = I387_FCTRL_REGNUM (tdep);
1503 i < I387_XMM0_REGNUM (tdep); i++)
1504 {
1505 if (i == I387_FCTRL_REGNUM (tdep))
1506 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2,
1507 byte_order, I387_FCTRL_INIT_VAL);
1508 else
1509 memset (FXSAVE_ADDR (tdep, regs, i), 0,
1510 regcache_register_size (regcache, i));
1511 }
1512 }
1513 }
1514
1515 if (regclass == all)
1516 {
1517 /* Check if any PKEYS registers are changed. */
1518 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1519 for (i = I387_PKRU_REGNUM (tdep);
1520 i < I387_PKEYSEND_REGNUM (tdep); i++)
1521 {
1522 regcache_raw_collect (regcache, i, raw);
1523 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1524 if (memcmp (raw, p, 4) != 0)
1525 {
1526 xstate_bv |= X86_XSTATE_PKRU;
1527 memcpy (p, raw, 4);
1528 }
1529 }
1530
1531 /* Check if any ZMMH registers are changed. */
1532 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1533 for (i = I387_ZMM0H_REGNUM (tdep);
1534 i < I387_ZMMENDH_REGNUM (tdep); i++)
1535 {
1536 regcache_raw_collect (regcache, i, raw);
1537 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1538 if (memcmp (raw, p, 32) != 0)
1539 {
1540 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1541 memcpy (p, raw, 32);
1542 }
1543 }
1544
1545 /* Check if any K registers are changed. */
1546 if ((tdep->xcr0 & X86_XSTATE_K))
1547 for (i = I387_K0_REGNUM (tdep);
1548 i < I387_KEND_REGNUM (tdep); i++)
1549 {
1550 regcache_raw_collect (regcache, i, raw);
1551 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1552 if (memcmp (raw, p, 8) != 0)
1553 {
1554 xstate_bv |= X86_XSTATE_K;
1555 memcpy (p, raw, 8);
1556 }
1557 }
1558
1559 /* Check if any XMM or upper YMM registers are changed. */
1560 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1561 {
1562 for (i = I387_YMM16H_REGNUM (tdep);
1563 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1564 {
1565 regcache_raw_collect (regcache, i, raw);
1566 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1567 if (memcmp (raw, p, 16) != 0)
1568 {
1569 xstate_bv |= X86_XSTATE_ZMM;
1570 memcpy (p, raw, 16);
1571 }
1572 }
1573 for (i = I387_XMM16_REGNUM (tdep);
1574 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1575 {
1576 regcache_raw_collect (regcache, i, raw);
1577 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1578 if (memcmp (raw, p, 16) != 0)
1579 {
1580 xstate_bv |= X86_XSTATE_ZMM;
1581 memcpy (p, raw, 16);
1582 }
1583 }
1584 }
1585
1586 /* Check if any upper MPX registers are changed. */
1587 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1588 for (i = I387_BND0R_REGNUM (tdep);
1589 i < I387_BNDCFGU_REGNUM (tdep); i++)
1590 {
1591 regcache_raw_collect (regcache, i, raw);
1592 p = XSAVE_MPX_ADDR (tdep, regs, i);
1593 if (memcmp (raw, p, 16))
1594 {
1595 xstate_bv |= X86_XSTATE_BNDREGS;
1596 memcpy (p, raw, 16);
1597 }
1598 }
1599
1600 /* Check if any upper MPX registers are changed. */
1601 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1602 for (i = I387_BNDCFGU_REGNUM (tdep);
1603 i < I387_MPXEND_REGNUM (tdep); i++)
1604 {
1605 regcache_raw_collect (regcache, i, raw);
1606 p = XSAVE_MPX_ADDR (tdep, regs, i);
1607 if (memcmp (raw, p, 8))
1608 {
1609 xstate_bv |= X86_XSTATE_BNDCFG;
1610 memcpy (p, raw, 8);
1611 }
1612 }
1613
1614 /* Check if any upper YMM registers are changed. */
1615 if ((tdep->xcr0 & X86_XSTATE_AVX))
1616 for (i = I387_YMM0H_REGNUM (tdep);
1617 i < I387_YMMENDH_REGNUM (tdep); i++)
1618 {
1619 regcache_raw_collect (regcache, i, raw);
1620 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1621 if (memcmp (raw, p, 16))
1622 {
1623 xstate_bv |= X86_XSTATE_AVX;
1624 memcpy (p, raw, 16);
1625 }
1626 }
1627
1628 /* Check if any SSE registers are changed. */
1629 if ((tdep->xcr0 & X86_XSTATE_SSE))
1630 for (i = I387_XMM0_REGNUM (tdep);
1631 i < I387_MXCSR_REGNUM (tdep); i++)
1632 {
1633 regcache_raw_collect (regcache, i, raw);
1634 p = FXSAVE_ADDR (tdep, regs, i);
1635 if (memcmp (raw, p, 16))
1636 {
1637 xstate_bv |= X86_XSTATE_SSE;
1638 memcpy (p, raw, 16);
1639 }
1640 }
1641
1642 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE))
1643 {
1644 i = I387_MXCSR_REGNUM (tdep);
1645 regcache_raw_collect (regcache, i, raw);
1646 p = FXSAVE_MXCSR_ADDR (regs);
1647 if (memcmp (raw, p, 4))
1648 {
1649 /* Now, we need to mark one of either SSE of AVX as enabled.
1650 We could pick either. What we do is check to see if one
1651 of the features is already enabled, if it is then we leave
1652 it at that, otherwise we pick SSE. */
1653 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0)
1654 xstate_bv |= X86_XSTATE_SSE;
1655 memcpy (p, raw, 4);
1656 }
1657 }
1658
1659 /* Check if any X87 registers are changed. Only the non-control
1660 registers are handled here, the control registers are all handled
1661 later on in this function. */
1662 if ((tdep->xcr0 & X86_XSTATE_X87))
1663 for (i = I387_ST0_REGNUM (tdep);
1664 i < I387_FCTRL_REGNUM (tdep); i++)
1665 {
1666 regcache_raw_collect (regcache, i, raw);
1667 p = FXSAVE_ADDR (tdep, regs, i);
1668 if (memcmp (raw, p, 10))
1669 {
1670 xstate_bv |= X86_XSTATE_X87;
1671 memcpy (p, raw, 10);
1672 }
1673 }
1674 }
1675 else
1676 {
1677 /* Check if REGNUM is changed. */
1678 regcache_raw_collect (regcache, regnum, raw);
1679
1680 switch (regclass)
1681 {
1682 default:
1683 internal_error (__FILE__, __LINE__,
1684 _("invalid i387 regclass"));
1685
1686 case pkeys:
1687 /* This is a PKEYS register. */
1688 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1689 if (memcmp (raw, p, 4) != 0)
1690 {
1691 xstate_bv |= X86_XSTATE_PKRU;
1692 memcpy (p, raw, 4);
1693 }
1694 break;
1695
1696 case avx512_zmm_h:
1697 /* This is a ZMM register. */
1698 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1699 if (memcmp (raw, p, 32) != 0)
1700 {
1701 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1702 memcpy (p, raw, 32);
1703 }
1704 break;
1705 case avx512_k:
1706 /* This is a AVX512 mask register. */
1707 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1708 if (memcmp (raw, p, 8) != 0)
1709 {
1710 xstate_bv |= X86_XSTATE_K;
1711 memcpy (p, raw, 8);
1712 }
1713 break;
1714
1715 case avx512_ymmh_avx512:
1716 /* This is an upper YMM16-31 register. */
1717 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1718 if (memcmp (raw, p, 16) != 0)
1719 {
1720 xstate_bv |= X86_XSTATE_ZMM;
1721 memcpy (p, raw, 16);
1722 }
1723 break;
1724
1725 case avx512_xmm_avx512:
1726 /* This is an upper XMM16-31 register. */
1727 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1728 if (memcmp (raw, p, 16) != 0)
1729 {
1730 xstate_bv |= X86_XSTATE_ZMM;
1731 memcpy (p, raw, 16);
1732 }
1733 break;
1734
1735 case avxh:
1736 /* This is an upper YMM register. */
1737 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1738 if (memcmp (raw, p, 16))
1739 {
1740 xstate_bv |= X86_XSTATE_AVX;
1741 memcpy (p, raw, 16);
1742 }
1743 break;
1744
1745 case mpx:
1746 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1747 {
1748 regcache_raw_collect (regcache, regnum, raw);
1749 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1750 if (memcmp (raw, p, 16))
1751 {
1752 xstate_bv |= X86_XSTATE_BNDREGS;
1753 memcpy (p, raw, 16);
1754 }
1755 }
1756 else
1757 {
1758 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1759 xstate_bv |= X86_XSTATE_BNDCFG;
1760 memcpy (p, raw, 8);
1761 }
1762 break;
1763
1764 case sse:
1765 /* This is an SSE register. */
1766 p = FXSAVE_ADDR (tdep, regs, regnum);
1767 if (memcmp (raw, p, 16))
1768 {
1769 xstate_bv |= X86_XSTATE_SSE;
1770 memcpy (p, raw, 16);
1771 }
1772 break;
1773
1774 case x87:
1775 /* This is an x87 register. */
1776 p = FXSAVE_ADDR (tdep, regs, regnum);
1777 if (memcmp (raw, p, 10))
1778 {
1779 xstate_bv |= X86_XSTATE_X87;
1780 memcpy (p, raw, 10);
1781 }
1782 break;
1783
1784 case x87_ctrl_or_mxcsr:
1785 /* We only handle MXCSR here. All other x87 control registers
1786 are handled separately below. */
1787 if (regnum == I387_MXCSR_REGNUM (tdep))
1788 {
1789 p = FXSAVE_MXCSR_ADDR (regs);
1790 if (memcmp (raw, p, 2))
1791 {
1792 /* We're only setting MXCSR, so check the initial state
1793 to see if either of AVX or SSE are already enabled.
1794 If they are then we'll attribute this changed MXCSR to
1795 that feature. If neither feature is enabled, then
1796 we'll attribute this change to the SSE feature. */
1797 xstate_bv |= (initial_xstate_bv
1798 & (X86_XSTATE_AVX | X86_XSTATE_SSE));
1799 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0)
1800 xstate_bv |= X86_XSTATE_SSE;
1801 memcpy (p, raw, 2);
1802 }
1803 }
1804 }
1805 }
1806
1807 /* Only handle x87 control registers. */
1808 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1809 if (regnum == -1 || regnum == i)
1810 {
1811 /* Most of the FPU control registers occupy only 16 bits in
1812 the xsave extended state. Give those a special treatment. */
1813 if (i != I387_FIOFF_REGNUM (tdep)
1814 && i != I387_FOOFF_REGNUM (tdep))
1815 {
1816 gdb_byte buf[4];
1817
1818 regcache_raw_collect (regcache, i, buf);
1819
1820 if (i == I387_FOP_REGNUM (tdep))
1821 {
1822 /* The opcode occupies only 11 bits. Make sure we
1823 don't touch the other bits. */
1824 buf[1] &= ((1 << 3) - 1);
1825 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1826 }
1827 else if (i == I387_FTAG_REGNUM (tdep))
1828 {
1829 /* Converting back is much easier. */
1830
1831 unsigned short ftag;
1832 int fpreg;
1833
1834 ftag = (buf[1] << 8) | buf[0];
1835 buf[0] = 0;
1836 buf[1] = 0;
1837
1838 for (fpreg = 7; fpreg >= 0; fpreg--)
1839 {
1840 int tag = (ftag >> (fpreg * 2)) & 3;
1841
1842 if (tag != 3)
1843 buf[0] |= (1 << fpreg);
1844 }
1845 }
1846 p = FXSAVE_ADDR (tdep, regs, i);
1847 if (memcmp (p, buf, 2))
1848 {
1849 xstate_bv |= X86_XSTATE_X87;
1850 memcpy (p, buf, 2);
1851 }
1852 }
1853 else
1854 {
1855 int regsize;
1856
1857 regcache_raw_collect (regcache, i, raw);
1858 regsize = regcache_register_size (regcache, i);
1859 p = FXSAVE_ADDR (tdep, regs, i);
1860 if (memcmp (raw, p, regsize))
1861 {
1862 xstate_bv |= X86_XSTATE_X87;
1863 memcpy (p, raw, regsize);
1864 }
1865 }
1866 }
1867
1868 /* Update the corresponding bits in `xstate_bv' if any
1869 registers are changed. */
1870 if (xstate_bv)
1871 {
1872 /* The supported bits in `xstat_bv' are 8 bytes. */
1873 initial_xstate_bv |= xstate_bv;
1874 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1875 8, byte_order,
1876 initial_xstate_bv);
1877 }
1878 }
1879
1880 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1881 *RAW. */
1882
1883 static int
1884 i387_tag (const gdb_byte *raw)
1885 {
1886 int integer;
1887 unsigned int exponent;
1888 unsigned long fraction[2];
1889
1890 integer = raw[7] & 0x80;
1891 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1892 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1893 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1894 | (raw[5] << 8) | raw[4]);
1895
1896 if (exponent == 0x7fff)
1897 {
1898 /* Special. */
1899 return (2);
1900 }
1901 else if (exponent == 0x0000)
1902 {
1903 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1904 {
1905 /* Zero. */
1906 return (1);
1907 }
1908 else
1909 {
1910 /* Special. */
1911 return (2);
1912 }
1913 }
1914 else
1915 {
1916 if (integer)
1917 {
1918 /* Valid. */
1919 return (0);
1920 }
1921 else
1922 {
1923 /* Special. */
1924 return (2);
1925 }
1926 }
1927 }
1928
1929 /* Prepare the FPU stack in REGCACHE for a function return. */
1930
1931 void
1932 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1933 {
1934 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1935 ULONGEST fstat;
1936
1937 /* Set the top of the floating-point register stack to 7. The
1938 actual value doesn't really matter, but 7 is what a normal
1939 function return would end up with if the program started out with
1940 a freshly initialized FPU. */
1941 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1942 fstat |= (7 << 11);
1943 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1944
1945 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1946 floating-point register stack to 7, the appropriate value for the
1947 tag word is 0x3fff. */
1948 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1949
1950 }
1951
1952 /* See i387-tdep.h. */
1953
1954 void
1955 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
1956 {
1957 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1958
1959 if (I387_BND0R_REGNUM (tdep) > 0)
1960 {
1961 gdb_byte bnd_buf[16];
1962
1963 memset (bnd_buf, 0, 16);
1964 for (int i = 0; i < I387_NUM_BND_REGS; i++)
1965 regcache_raw_write (regcache, I387_BND0R_REGNUM (tdep) + i, bnd_buf);
1966 }
1967 }
GDB Binutils - Deliverables
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