gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999-2018 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "target.h"
  24 #include "gdbcore.h"
  25 #include "regcache.h"
  26 #include "ia64-tdep.h"
  27 #include "linux-nat.h"
  28
  29 #include <signal.h>
  30 #include "nat/gdb_ptrace.h"
  31 #include "gdb_wait.h"
  32 #ifdef HAVE_SYS_REG_H
  33 #include <sys/reg.h>
  34 #endif
  35 #include <sys/syscall.h>
  36 #include <sys/user.h>
  37
  38 #include <asm/ptrace_offsets.h>
  39 #include <sys/procfs.h>
  40
  41 /* Prototypes for supply_gregset etc.  */
  42 #include "gregset.h"
  43
  44 #include "inf-ptrace.h"
  45
  46 class ia64_linux_nat_target final : public linux_nat_target
  47 {
  48 public:
  49   /* Add our register access methods.  */
  50   void fetch_registers (struct regcache *, int) override;
  51   void store_registers (struct regcache *, int) override;
  52
  53   enum target_xfer_status xfer_partial (enum target_object object,
  54                                         const char *annex,
  55                                         gdb_byte *readbuf,
  56                                         const gdb_byte *writebuf,
  57                                         ULONGEST offset, ULONGEST len,
  58                                         ULONGEST *xfered_len) override;
  59
  60   const struct target_desc *read_description () override;
  61
  62   /* Override watchpoint routines.  */
  63
  64   /* The IA-64 architecture can step over a watch point (without
  65      triggering it again) if the "dd" (data debug fault disable) bit
  66      in the processor status word is set.
  67
  68      This PSR bit is set in
  69      ia64_linux_nat_target::stopped_by_watchpoint when the code there
  70      has determined that a hardware watchpoint has indeed been hit.
  71      The CPU will then be able to execute one instruction without
  72      triggering a watchpoint.  */
  73   bool have_steppable_watchpoint () { return 1; }
  74
  75   int can_use_hw_breakpoint (enum bptype, int, int) override;
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78   int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  79                          struct expression *) override;
  80   int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  81                          struct expression *) override;
  82   /* Override linux_nat_target low methods.  */
  83   void low_new_thread (struct lwp_info *lp) override;
  84   bool low_status_is_event (int status) override;
  85 };
  86
  87 static ia64_linux_nat_target the_ia64_linux_nat_target;
  88
  89 /* These must match the order of the register names.
  90
  91    Some sort of lookup table is needed because the offsets associated
  92    with the registers are all over the board.  */
  93
  94 static int u_offsets[] =
  95   {
  96     /* general registers */
  97     -1,         /* gr0 not available; i.e, it's always zero.  */
  98     PT_R1,
  99     PT_R2,
 100     PT_R3,
 101     PT_R4,
 102     PT_R5,
 103     PT_R6,
 104     PT_R7,
 105     PT_R8,
 106     PT_R9,
 107     PT_R10,
 108     PT_R11,
 109     PT_R12,
 110     PT_R13,
 111     PT_R14,
 112     PT_R15,
 113     PT_R16,
 114     PT_R17,
 115     PT_R18,
 116     PT_R19,
 117     PT_R20,
 118     PT_R21,
 119     PT_R22,
 120     PT_R23,
 121     PT_R24,
 122     PT_R25,
 123     PT_R26,
 124     PT_R27,
 125     PT_R28,
 126     PT_R29,
 127     PT_R30,
 128     PT_R31,
 129     /* gr32 through gr127 not directly available via the ptrace interface.  */
 130     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 131     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 132     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 133     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 134     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 135     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 136     /* Floating point registers */
 137     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0).  */
 138     PT_F2,
 139     PT_F3,
 140     PT_F4,
 141     PT_F5,
 142     PT_F6,
 143     PT_F7,
 144     PT_F8,
 145     PT_F9,
 146     PT_F10,
 147     PT_F11,
 148     PT_F12,
 149     PT_F13,
 150     PT_F14,
 151     PT_F15,
 152     PT_F16,
 153     PT_F17,
 154     PT_F18,
 155     PT_F19,
 156     PT_F20,
 157     PT_F21,
 158     PT_F22,
 159     PT_F23,
 160     PT_F24,
 161     PT_F25,
 162     PT_F26,
 163     PT_F27,
 164     PT_F28,
 165     PT_F29,
 166     PT_F30,
 167     PT_F31,
 168     PT_F32,
 169     PT_F33,
 170     PT_F34,
 171     PT_F35,
 172     PT_F36,
 173     PT_F37,
 174     PT_F38,
 175     PT_F39,
 176     PT_F40,
 177     PT_F41,
 178     PT_F42,
 179     PT_F43,
 180     PT_F44,
 181     PT_F45,
 182     PT_F46,
 183     PT_F47,
 184     PT_F48,
 185     PT_F49,
 186     PT_F50,
 187     PT_F51,
 188     PT_F52,
 189     PT_F53,
 190     PT_F54,
 191     PT_F55,
 192     PT_F56,
 193     PT_F57,
 194     PT_F58,
 195     PT_F59,
 196     PT_F60,
 197     PT_F61,
 198     PT_F62,
 199     PT_F63,
 200     PT_F64,
 201     PT_F65,
 202     PT_F66,
 203     PT_F67,
 204     PT_F68,
 205     PT_F69,
 206     PT_F70,
 207     PT_F71,
 208     PT_F72,
 209     PT_F73,
 210     PT_F74,
 211     PT_F75,
 212     PT_F76,
 213     PT_F77,
 214     PT_F78,
 215     PT_F79,
 216     PT_F80,
 217     PT_F81,
 218     PT_F82,
 219     PT_F83,
 220     PT_F84,
 221     PT_F85,
 222     PT_F86,
 223     PT_F87,
 224     PT_F88,
 225     PT_F89,
 226     PT_F90,
 227     PT_F91,
 228     PT_F92,
 229     PT_F93,
 230     PT_F94,
 231     PT_F95,
 232     PT_F96,
 233     PT_F97,
 234     PT_F98,
 235     PT_F99,
 236     PT_F100,
 237     PT_F101,
 238     PT_F102,
 239     PT_F103,
 240     PT_F104,
 241     PT_F105,
 242     PT_F106,
 243     PT_F107,
 244     PT_F108,
 245     PT_F109,
 246     PT_F110,
 247     PT_F111,
 248     PT_F112,
 249     PT_F113,
 250     PT_F114,
 251     PT_F115,
 252     PT_F116,
 253     PT_F117,
 254     PT_F118,
 255     PT_F119,
 256     PT_F120,
 257     PT_F121,
 258     PT_F122,
 259     PT_F123,
 260     PT_F124,
 261     PT_F125,
 262     PT_F126,
 263     PT_F127,
 264     /* Predicate registers - we don't fetch these individually.  */
 265     -1, -1, -1, -1, -1, -1, -1, -1,
 266     -1, -1, -1, -1, -1, -1, -1, -1,
 267     -1, -1, -1, -1, -1, -1, -1, -1,
 268     -1, -1, -1, -1, -1, -1, -1, -1,
 269     -1, -1, -1, -1, -1, -1, -1, -1,
 270     -1, -1, -1, -1, -1, -1, -1, -1,
 271     -1, -1, -1, -1, -1, -1, -1, -1,
 272     -1, -1, -1, -1, -1, -1, -1, -1,
 273     /* branch registers */
 274     PT_B0,
 275     PT_B1,
 276     PT_B2,
 277     PT_B3,
 278     PT_B4,
 279     PT_B5,
 280     PT_B6,
 281     PT_B7,
 282     /* Virtual frame pointer and virtual return address pointer.  */
 283     -1, -1,
 284     /* other registers */
 285     PT_PR,
 286     PT_CR_IIP,  /* ip */
 287     PT_CR_IPSR, /* psr */
 288     PT_CFM,     /* cfm */
 289     /* kernel registers not visible via ptrace interface (?)  */
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     /* hole */
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     PT_AR_RSC,
 294     PT_AR_BSP,
 295     PT_AR_BSPSTORE,
 296     PT_AR_RNAT,
 297     -1,
 298     -1,         /* Not available: FCR, IA32 floating control register.  */
 299     -1, -1,
 300     -1,         /* Not available: EFLAG */
 301     -1,         /* Not available: CSD */
 302     -1,         /* Not available: SSD */
 303     -1,         /* Not available: CFLG */
 304     -1,         /* Not available: FSR */
 305     -1,         /* Not available: FIR */
 306     -1,         /* Not available: FDR */
 307     -1,
 308     PT_AR_CCV,
 309     -1, -1, -1,
 310     PT_AR_UNAT,
 311     -1, -1, -1,
 312     PT_AR_FPSR,
 313     -1, -1, -1,
 314     -1,         /* Not available: ITC */
 315     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 316     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 317     PT_AR_PFS,
 318     PT_AR_LC,
 319     PT_AR_EC,
 320     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 321     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 322     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 323     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 324     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 325     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 326     -1,
 327     /* nat bits - not fetched directly; instead we obtain these bits from
 328        either rnat or unat or from memory.  */
 329     -1, -1, -1, -1, -1, -1, -1, -1,
 330     -1, -1, -1, -1, -1, -1, -1, -1,
 331     -1, -1, -1, -1, -1, -1, -1, -1,
 332     -1, -1, -1, -1, -1, -1, -1, -1,
 333     -1, -1, -1, -1, -1, -1, -1, -1,
 334     -1, -1, -1, -1, -1, -1, -1, -1,
 335     -1, -1, -1, -1, -1, -1, -1, -1,
 336     -1, -1, -1, -1, -1, -1, -1, -1,
 337     -1, -1, -1, -1, -1, -1, -1, -1,
 338     -1, -1, -1, -1, -1, -1, -1, -1,
 339     -1, -1, -1, -1, -1, -1, -1, -1,
 340     -1, -1, -1, -1, -1, -1, -1, -1,
 341     -1, -1, -1, -1, -1, -1, -1, -1,
 342     -1, -1, -1, -1, -1, -1, -1, -1,
 343     -1, -1, -1, -1, -1, -1, -1, -1,
 344     -1, -1, -1, -1, -1, -1, -1, -1,
 345   };
 346
 347 static CORE_ADDR
 348 ia64_register_addr (struct gdbarch *gdbarch, int regno)
 349 {
 350   CORE_ADDR addr;
 351
 352   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 353     error (_("Invalid register number %d."), regno);
 354
 355   if (u_offsets[regno] == -1)
 356     addr = 0;
 357   else
 358     addr = (CORE_ADDR) u_offsets[regno];
 359
 360   return addr;
 361 }
 362
 363 static int
 364 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
 365 {
 366   return regno < 0
 367          || regno >= gdbarch_num_regs (gdbarch)
 368          || u_offsets[regno] == -1;
 369 }
 370
 371 static int
 372 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
 373 {
 374   /* Rationale behind not permitting stores to bspstore...
 375
 376      The IA-64 architecture provides bspstore and bsp which refer
 377      memory locations in the RSE's backing store.  bspstore is the
 378      next location which will be written when the RSE needs to write
 379      to memory.  bsp is the address at which r32 in the current frame
 380      would be found if it were written to the backing store.
 381
 382      The IA-64 architecture provides read-only access to bsp and
 383      read/write access to bspstore (but only when the RSE is in
 384      the enforced lazy mode).  It should be noted that stores
 385      to bspstore also affect the value of bsp.  Changing bspstore
 386      does not affect the number of dirty entries between bspstore
 387      and bsp, so changing bspstore by N words will also cause bsp
 388      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 389      depending upon where the NaT collection bits fall.)
 390
 391      OTOH, the Linux kernel provides read/write access to bsp (and
 392      currently read/write access to bspstore as well).  But it
 393      is definitely the case that if you change one, the other
 394      will change at the same time.  It is more useful to gdb to
 395      be able to change bsp.  So in order to prevent strange and
 396      undesirable things from happening when a dummy stack frame
 397      is popped (after calling an inferior function), we allow
 398      bspstore to be read, but not written.  (Note that popping
 399      a (generic) dummy stack frame causes all registers that
 400      were previously read from the inferior process to be written
 401      back.)  */
 402
 403   return regno < 0
 404          || regno >= gdbarch_num_regs (gdbarch)
 405          || u_offsets[regno] == -1
 406          || regno == IA64_BSPSTORE_REGNUM;
 407 }
 408
 409 void
 410 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
 411 {
 412   int regi;
 413   const greg_t *regp = (const greg_t *) gregsetp;
 414
 415   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 416     {
 417       regcache->raw_supply (regi, regp + (regi - IA64_GR0_REGNUM));
 418     }
 419
 420   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 421      somehow...  */
 422
 423   regcache->raw_supply (IA64_PR_REGNUM, regp + 33);
 424
 425   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 426     {
 427       regcache->raw_supply (regi, regp + 34 + (regi - IA64_BR0_REGNUM));
 428     }
 429
 430   regcache->raw_supply (IA64_IP_REGNUM, regp + 42);
 431   regcache->raw_supply (IA64_CFM_REGNUM, regp + 43);
 432   regcache->raw_supply (IA64_PSR_REGNUM, regp + 44);
 433   regcache->raw_supply (IA64_RSC_REGNUM, regp + 45);
 434   regcache->raw_supply (IA64_BSP_REGNUM, regp + 46);
 435   regcache->raw_supply (IA64_BSPSTORE_REGNUM, regp + 47);
 436   regcache->raw_supply (IA64_RNAT_REGNUM, regp + 48);
 437   regcache->raw_supply (IA64_CCV_REGNUM, regp + 49);
 438   regcache->raw_supply (IA64_UNAT_REGNUM, regp + 50);
 439   regcache->raw_supply (IA64_FPSR_REGNUM, regp + 51);
 440   regcache->raw_supply (IA64_PFS_REGNUM, regp + 52);
 441   regcache->raw_supply (IA64_LC_REGNUM, regp + 53);
 442   regcache->raw_supply (IA64_EC_REGNUM, regp + 54);
 443 }
 444
 445 void
 446 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
 447 {
 448   int regi;
 449   greg_t *regp = (greg_t *) gregsetp;
 450
 451 #define COPY_REG(_idx_,_regi_) \
 452   if ((regno == -1) || regno == _regi_) \
 453     regcache_raw_collect (regcache, _regi_, regp + _idx_)
 454
 455   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 456     {
 457       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 458     }
 459
 460   /* FIXME: NAT collection bits at index 32?  */
 461
 462   COPY_REG (33, IA64_PR_REGNUM);
 463
 464   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 465     {
 466       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 467     }
 468
 469   COPY_REG (42, IA64_IP_REGNUM);
 470   COPY_REG (43, IA64_CFM_REGNUM);
 471   COPY_REG (44, IA64_PSR_REGNUM);
 472   COPY_REG (45, IA64_RSC_REGNUM);
 473   COPY_REG (46, IA64_BSP_REGNUM);
 474   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 475   COPY_REG (48, IA64_RNAT_REGNUM);
 476   COPY_REG (49, IA64_CCV_REGNUM);
 477   COPY_REG (50, IA64_UNAT_REGNUM);
 478   COPY_REG (51, IA64_FPSR_REGNUM);
 479   COPY_REG (52, IA64_PFS_REGNUM);
 480   COPY_REG (53, IA64_LC_REGNUM);
 481   COPY_REG (54, IA64_EC_REGNUM);
 482 }
 483
 484 /*  Given a pointer to a floating point register set in /proc format
 485    (fpregset_t *), unpack the register contents and supply them as gdb's
 486    idea of the current floating point register values.  */
 487
 488 void
 489 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
 490 {
 491   int regi;
 492   const char *from;
 493   const gdb_byte f_zero[16] = { 0 };
 494   const gdb_byte f_one[16] =
 495     { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 496
 497   /* Kernel generated cores have fr1==0 instead of 1.0.  Older GDBs
 498      did the same.  So ignore whatever might be recorded in fpregset_t
 499      for fr0/fr1 and always supply their expected values.  */
 500
 501   /* fr0 is always read as zero.  */
 502   regcache->raw_supply (IA64_FR0_REGNUM, f_zero);
 503   /* fr1 is always read as one (1.0).  */
 504   regcache->raw_supply (IA64_FR1_REGNUM, f_one);
 505
 506   for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 507     {
 508       from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 509       regcache->raw_supply (regi, from);
 510     }
 511 }
 512
 513 /*  Given a pointer to a floating point register set in /proc format
 514    (fpregset_t *), update the register specified by REGNO from gdb's idea
 515    of the current floating point register set.  If REGNO is -1, update
 516    them all.  */
 517
 518 void
 519 fill_fpregset (const struct regcache *regcache,
 520                fpregset_t *fpregsetp, int regno)
 521 {
 522   int regi;
 523
 524   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 525     {
 526       if ((regno == -1) || (regno == regi))
 527         regcache_raw_collect (regcache, regi,
 528                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 529     }
 530 }
 531
 532 #define IA64_PSR_DB (1UL << 24)
 533 #define IA64_PSR_DD (1UL << 39)
 534
 535 static void
 536 enable_watchpoints_in_psr (ptid_t ptid)
 537 {
 538   struct regcache *regcache = get_thread_regcache (ptid);
 539   ULONGEST psr;
 540
 541   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 542   if (!(psr & IA64_PSR_DB))
 543     {
 544       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 545                                    watchpoints and breakpoints.  */
 546       regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 547     }
 548 }
 549
 550 static long debug_registers[8];
 551
 552 static void
 553 store_debug_register (ptid_t ptid, int idx, long val)
 554 {
 555   int tid;
 556
 557   tid = ptid_get_lwp (ptid);
 558   if (tid == 0)
 559     tid = ptid_get_pid (ptid);
 560
 561   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 562 }
 563
 564 static void
 565 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
 566                            long *dbr_mask)
 567 {
 568   if (dbr_addr)
 569     store_debug_register (ptid, 2 * idx, *dbr_addr);
 570   if (dbr_mask)
 571     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 572 }
 573
 574 static int
 575 is_power_of_2 (int val)
 576 {
 577   int i, onecount;
 578
 579   onecount = 0;
 580   for (i = 0; i < 8 * sizeof (val); i++)
 581     if (val & (1 << i))
 582       onecount++;
 583
 584   return onecount <= 1;
 585 }
 586
 587 int
 588 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
 589                                           enum target_hw_bp_type type,
 590                                           struct expression *cond)
 591 {
 592   struct lwp_info *lp;
 593   int idx;
 594   long dbr_addr, dbr_mask;
 595   int max_watchpoints = 4;
 596
 597   if (len <= 0 || !is_power_of_2 (len))
 598     return -1;
 599
 600   for (idx = 0; idx < max_watchpoints; idx++)
 601     {
 602       dbr_mask = debug_registers[idx * 2 + 1];
 603       if ((dbr_mask & (0x3UL << 62)) == 0)
 604         {
 605           /* Exit loop if both r and w bits clear.  */
 606           break;
 607         }
 608     }
 609
 610   if (idx == max_watchpoints)
 611     return -1;
 612
 613   dbr_addr = (long) addr;
 614   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 615   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 616   switch (type)
 617     {
 618     case hw_write:
 619       dbr_mask |= (1L << 62);                   /* Set w bit */
 620       break;
 621     case hw_read:
 622       dbr_mask |= (1L << 63);                   /* Set r bit */
 623       break;
 624     case hw_access:
 625       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 626       break;
 627     default:
 628       return -1;
 629     }
 630
 631   debug_registers[2 * idx] = dbr_addr;
 632   debug_registers[2 * idx + 1] = dbr_mask;
 633   ALL_LWPS (lp)
 634     {
 635       store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 636       enable_watchpoints_in_psr (lp->ptid);
 637     }
 638
 639   return 0;
 640 }
 641
 642 int
 643 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
 644                                           enum target_hw_bp_type type,
 645                                           struct expression *cond)
 646 {
 647   int idx;
 648   long dbr_addr, dbr_mask;
 649   int max_watchpoints = 4;
 650
 651   if (len <= 0 || !is_power_of_2 (len))
 652     return -1;
 653
 654   for (idx = 0; idx < max_watchpoints; idx++)
 655     {
 656       dbr_addr = debug_registers[2 * idx];
 657       dbr_mask = debug_registers[2 * idx + 1];
 658       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 659         {
 660           struct lwp_info *lp;
 661
 662           debug_registers[2 * idx] = 0;
 663           debug_registers[2 * idx + 1] = 0;
 664           dbr_addr = 0;
 665           dbr_mask = 0;
 666
 667           ALL_LWPS (lp)
 668             store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 669
 670           return 0;
 671         }
 672     }
 673   return -1;
 674 }
 675
 676 static void
 677 ia64_linux_new_thread (struct lwp_info *lp)
 678 {
 679   int i, any;
 680
 681   any = 0;
 682   for (i = 0; i < 8; i++)
 683     {
 684       if (debug_registers[i] != 0)
 685         any = 1;
 686       store_debug_register (lp->ptid, i, debug_registers[i]);
 687     }
 688
 689   if (any)
 690     enable_watchpoints_in_psr (lp->ptid);
 691 }
 692
 693 bool
 694 ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 695 {
 696   CORE_ADDR psr;
 697   siginfo_t siginfo;
 698   struct regcache *regcache = get_current_regcache ();
 699
 700   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 701     return false;
 702
 703   if (siginfo.si_signo != SIGTRAP
 704       || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 705     return false;
 706
 707   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 708   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 709                            for the next instruction.  */
 710   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 711
 712   *addr_p = (CORE_ADDR) siginfo.si_addr;
 713   return true;
 714 }
 715
 716 bool
 717 ia64_linux_nat_target::stopped_by_watchpoint ()
 718 {
 719   CORE_ADDR addr;
 720   return stopped_data_address (&addr);
 721 }
 722
 723 static int
 724 ia64_linux_can_use_hw_breakpoint (struct target_ops *self,
 725                                   enum bptype type,
 726                                   int cnt, int othertype)
 727 {
 728   return 1;
 729 }
 730
 731
 732 /* Fetch register REGNUM from the inferior.  */
 733
 734 static void
 735 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
 736 {
 737   struct gdbarch *gdbarch = regcache->arch ();
 738   CORE_ADDR addr;
 739   size_t size;
 740   PTRACE_TYPE_RET *buf;
 741   pid_t pid;
 742   int i;
 743
 744   /* r0 cannot be fetched but is always zero.  */
 745   if (regnum == IA64_GR0_REGNUM)
 746     {
 747       const gdb_byte zero[8] = { 0 };
 748
 749       gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
 750       regcache->raw_supply (regnum, zero);
 751       return;
 752     }
 753
 754   /* fr0 cannot be fetched but is always zero.  */
 755   if (regnum == IA64_FR0_REGNUM)
 756     {
 757       const gdb_byte f_zero[16] = { 0 };
 758
 759       gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
 760       regcache->raw_supply (regnum, f_zero);
 761       return;
 762     }
 763
 764   /* fr1 cannot be fetched but is always one (1.0).  */
 765   if (regnum == IA64_FR1_REGNUM)
 766     {
 767       const gdb_byte f_one[16] =
 768         { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 769
 770       gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
 771       regcache->raw_supply (regnum, f_one);
 772       return;
 773     }
 774
 775   if (ia64_cannot_fetch_register (gdbarch, regnum))
 776     {
 777       regcache->raw_supply (regnum, NULL);
 778       return;
 779     }
 780
 781   pid = get_ptrace_pid (regcache->ptid ());
 782
 783   /* This isn't really an address, but ptrace thinks of it as one.  */
 784   addr = ia64_register_addr (gdbarch, regnum);
 785   size = register_size (gdbarch, regnum);
 786
 787   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 788   buf = (PTRACE_TYPE_RET *) alloca (size);
 789
 790   /* Read the register contents from the inferior a chunk at a time.  */
 791   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 792     {
 793       errno = 0;
 794       buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
 795       if (errno != 0)
 796         error (_("Couldn't read register %s (#%d): %s."),
 797                gdbarch_register_name (gdbarch, regnum),
 798                regnum, safe_strerror (errno));
 799
 800       addr += sizeof (PTRACE_TYPE_RET);
 801     }
 802   regcache->raw_supply (regnum, buf);
 803 }
 804
 805 /* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
 806    for all registers.  */
 807
 808 void
 809 ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 810 {
 811   if (regnum == -1)
 812     for (regnum = 0;
 813          regnum < gdbarch_num_regs (regcache->arch ());
 814          regnum++)
 815       ia64_linux_fetch_register (regcache, regnum);
 816   else
 817     ia64_linux_fetch_register (regcache, regnum);
 818 }
 819
 820 /* Store register REGNUM into the inferior.  */
 821
 822 static void
 823 ia64_linux_store_register (const struct regcache *regcache, int regnum)
 824 {
 825   struct gdbarch *gdbarch = regcache->arch ();
 826   CORE_ADDR addr;
 827   size_t size;
 828   PTRACE_TYPE_RET *buf;
 829   pid_t pid;
 830   int i;
 831
 832   if (ia64_cannot_store_register (gdbarch, regnum))
 833     return;
 834
 835   pid = get_ptrace_pid (regcache->ptid ());
 836
 837   /* This isn't really an address, but ptrace thinks of it as one.  */
 838   addr = ia64_register_addr (gdbarch, regnum);
 839   size = register_size (gdbarch, regnum);
 840
 841   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 842   buf = (PTRACE_TYPE_RET *) alloca (size);
 843
 844   /* Write the register contents into the inferior a chunk at a time.  */
 845   regcache_raw_collect (regcache, regnum, buf);
 846   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 847     {
 848       errno = 0;
 849       ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
 850       if (errno != 0)
 851         error (_("Couldn't write register %s (#%d): %s."),
 852                gdbarch_register_name (gdbarch, regnum),
 853                regnum, safe_strerror (errno));
 854
 855       addr += sizeof (PTRACE_TYPE_RET);
 856     }
 857 }
 858
 859 /* Store register REGNUM back into the inferior.  If REGNUM is -1, do
 860    this for all registers.  */
 861
 862 void
 863 ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 864 {
 865   if (regnum == -1)
 866     for (regnum = 0;
 867          regnum < gdbarch_num_regs (regcache->arch ());
 868          regnum++)
 869       ia64_linux_store_register (regcache, regnum);
 870   else
 871     ia64_linux_store_register (regcache, regnum);
 872 }
 873
 874 /* Implement the xfer_partial target_ops method.  */
 875
 876 enum target_xfer_status
 877 ia64_linux_nat_target::xfer_partial (enum target_object object,
 878                                      const char *annex,
 879                                      gdb_byte *readbuf, const gdb_byte *writebuf,
 880                                      ULONGEST offset, ULONGEST len,
 881                                      ULONGEST *xfered_len)
 882 {
 883   if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
 884     {
 885       static long gate_table_size;
 886       gdb_byte *tmp_buf;
 887       long res;
 888
 889       /* Probe for the table size once.  */
 890       if (gate_table_size == 0)
 891         gate_table_size = syscall (__NR_getunwind, NULL, 0);
 892       if (gate_table_size < 0)
 893         return TARGET_XFER_E_IO;
 894
 895       if (offset >= gate_table_size)
 896         return TARGET_XFER_EOF;
 897
 898       tmp_buf = (gdb_byte *) alloca (gate_table_size);
 899       res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
 900       if (res < 0)
 901         return TARGET_XFER_E_IO;
 902       gdb_assert (res == gate_table_size);
 903
 904       if (offset + len > gate_table_size)
 905         len = gate_table_size - offset;
 906
 907       memcpy (readbuf, tmp_buf + offset, len);
 908       *xfered_len = len;
 909       return TARGET_XFER_OK;
 910     }
 911
 912   return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
 913                                          offset, len, xfered_len);
 914 }
 915
 916 /* For break.b instruction ia64 CPU forgets the immediate value and generates
 917    SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
 918    ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
 919    difference for the signals here.  */
 920
 921 bool
 922 ia64_linux_nat_target::low_status_is_event (int status)
 923 {
 924   return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
 925                                  || WSTOPSIG (status) == SIGILL);
 926 }
 927
 928 void
 929 _initialize_ia64_linux_nat (void)
 930 {
 931   /* Register the target.  */
 932   linux_target = &the_ia64_linux_nat_target;
 933   add_inf_child_target (&the_ia64_linux_nat_target);
 934 }