gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999-2012 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "gdb_string.h"
  23 #include "inferior.h"
  24 #include "target.h"
  25 #include "gdbcore.h"
  26 #include "regcache.h"
  27 #include "ia64-tdep.h"
  28 #include "linux-nat.h"
  29
  30 #include <signal.h>
  31 #include <sys/ptrace.h>
  32 #include "gdb_wait.h"
  33 #ifdef HAVE_SYS_REG_H
  34 #include <sys/reg.h>
  35 #endif
  36 #include <sys/syscall.h>
  37 #include <sys/user.h>
  38
  39 #include <asm/ptrace_offsets.h>
  40 #include <sys/procfs.h>
  41
  42 /* Prototypes for supply_gregset etc.  */
  43 #include "gregset.h"
  44
  45 /* These must match the order of the register names.
  46
  47    Some sort of lookup table is needed because the offsets associated
  48    with the registers are all over the board.  */
  49
  50 static int u_offsets[] =
  51   {
  52     /* general registers */
  53     -1,         /* gr0 not available; i.e, it's always zero.  */
  54     PT_R1,
  55     PT_R2,
  56     PT_R3,
  57     PT_R4,
  58     PT_R5,
  59     PT_R6,
  60     PT_R7,
  61     PT_R8,
  62     PT_R9,
  63     PT_R10,
  64     PT_R11,
  65     PT_R12,
  66     PT_R13,
  67     PT_R14,
  68     PT_R15,
  69     PT_R16,
  70     PT_R17,
  71     PT_R18,
  72     PT_R19,
  73     PT_R20,
  74     PT_R21,
  75     PT_R22,
  76     PT_R23,
  77     PT_R24,
  78     PT_R25,
  79     PT_R26,
  80     PT_R27,
  81     PT_R28,
  82     PT_R29,
  83     PT_R30,
  84     PT_R31,
  85     /* gr32 through gr127 not directly available via the ptrace interface.  */
  86     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  87     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  88     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  89     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  90     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  91     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  92     /* Floating point registers */
  93     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0).  */
  94     PT_F2,
  95     PT_F3,
  96     PT_F4,
  97     PT_F5,
  98     PT_F6,
  99     PT_F7,
 100     PT_F8,
 101     PT_F9,
 102     PT_F10,
 103     PT_F11,
 104     PT_F12,
 105     PT_F13,
 106     PT_F14,
 107     PT_F15,
 108     PT_F16,
 109     PT_F17,
 110     PT_F18,
 111     PT_F19,
 112     PT_F20,
 113     PT_F21,
 114     PT_F22,
 115     PT_F23,
 116     PT_F24,
 117     PT_F25,
 118     PT_F26,
 119     PT_F27,
 120     PT_F28,
 121     PT_F29,
 122     PT_F30,
 123     PT_F31,
 124     PT_F32,
 125     PT_F33,
 126     PT_F34,
 127     PT_F35,
 128     PT_F36,
 129     PT_F37,
 130     PT_F38,
 131     PT_F39,
 132     PT_F40,
 133     PT_F41,
 134     PT_F42,
 135     PT_F43,
 136     PT_F44,
 137     PT_F45,
 138     PT_F46,
 139     PT_F47,
 140     PT_F48,
 141     PT_F49,
 142     PT_F50,
 143     PT_F51,
 144     PT_F52,
 145     PT_F53,
 146     PT_F54,
 147     PT_F55,
 148     PT_F56,
 149     PT_F57,
 150     PT_F58,
 151     PT_F59,
 152     PT_F60,
 153     PT_F61,
 154     PT_F62,
 155     PT_F63,
 156     PT_F64,
 157     PT_F65,
 158     PT_F66,
 159     PT_F67,
 160     PT_F68,
 161     PT_F69,
 162     PT_F70,
 163     PT_F71,
 164     PT_F72,
 165     PT_F73,
 166     PT_F74,
 167     PT_F75,
 168     PT_F76,
 169     PT_F77,
 170     PT_F78,
 171     PT_F79,
 172     PT_F80,
 173     PT_F81,
 174     PT_F82,
 175     PT_F83,
 176     PT_F84,
 177     PT_F85,
 178     PT_F86,
 179     PT_F87,
 180     PT_F88,
 181     PT_F89,
 182     PT_F90,
 183     PT_F91,
 184     PT_F92,
 185     PT_F93,
 186     PT_F94,
 187     PT_F95,
 188     PT_F96,
 189     PT_F97,
 190     PT_F98,
 191     PT_F99,
 192     PT_F100,
 193     PT_F101,
 194     PT_F102,
 195     PT_F103,
 196     PT_F104,
 197     PT_F105,
 198     PT_F106,
 199     PT_F107,
 200     PT_F108,
 201     PT_F109,
 202     PT_F110,
 203     PT_F111,
 204     PT_F112,
 205     PT_F113,
 206     PT_F114,
 207     PT_F115,
 208     PT_F116,
 209     PT_F117,
 210     PT_F118,
 211     PT_F119,
 212     PT_F120,
 213     PT_F121,
 214     PT_F122,
 215     PT_F123,
 216     PT_F124,
 217     PT_F125,
 218     PT_F126,
 219     PT_F127,
 220     /* Predicate registers - we don't fetch these individually.  */
 221     -1, -1, -1, -1, -1, -1, -1, -1,
 222     -1, -1, -1, -1, -1, -1, -1, -1,
 223     -1, -1, -1, -1, -1, -1, -1, -1,
 224     -1, -1, -1, -1, -1, -1, -1, -1,
 225     -1, -1, -1, -1, -1, -1, -1, -1,
 226     -1, -1, -1, -1, -1, -1, -1, -1,
 227     -1, -1, -1, -1, -1, -1, -1, -1,
 228     -1, -1, -1, -1, -1, -1, -1, -1,
 229     /* branch registers */
 230     PT_B0,
 231     PT_B1,
 232     PT_B2,
 233     PT_B3,
 234     PT_B4,
 235     PT_B5,
 236     PT_B6,
 237     PT_B7,
 238     /* Virtual frame pointer and virtual return address pointer.  */
 239     -1, -1,
 240     /* other registers */
 241     PT_PR,
 242     PT_CR_IIP,  /* ip */
 243     PT_CR_IPSR, /* psr */
 244     PT_CFM,     /* cfm */
 245     /* kernel registers not visible via ptrace interface (?)  */
 246     -1, -1, -1, -1, -1, -1, -1, -1,
 247     /* hole */
 248     -1, -1, -1, -1, -1, -1, -1, -1,
 249     PT_AR_RSC,
 250     PT_AR_BSP,
 251     PT_AR_BSPSTORE,
 252     PT_AR_RNAT,
 253     -1,
 254     -1,         /* Not available: FCR, IA32 floating control register.  */
 255     -1, -1,
 256     -1,         /* Not available: EFLAG */
 257     -1,         /* Not available: CSD */
 258     -1,         /* Not available: SSD */
 259     -1,         /* Not available: CFLG */
 260     -1,         /* Not available: FSR */
 261     -1,         /* Not available: FIR */
 262     -1,         /* Not available: FDR */
 263     -1,
 264     PT_AR_CCV,
 265     -1, -1, -1,
 266     PT_AR_UNAT,
 267     -1, -1, -1,
 268     PT_AR_FPSR,
 269     -1, -1, -1,
 270     -1,         /* Not available: ITC */
 271     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 272     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 273     PT_AR_PFS,
 274     PT_AR_LC,
 275     -1,         /* Not available: EC, the Epilog Count register.  */
 276     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 277     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 278     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 279     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 280     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 281     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 282     -1,
 283     /* nat bits - not fetched directly; instead we obtain these bits from
 284        either rnat or unat or from memory.  */
 285     -1, -1, -1, -1, -1, -1, -1, -1,
 286     -1, -1, -1, -1, -1, -1, -1, -1,
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296     -1, -1, -1, -1, -1, -1, -1, -1,
 297     -1, -1, -1, -1, -1, -1, -1, -1,
 298     -1, -1, -1, -1, -1, -1, -1, -1,
 299     -1, -1, -1, -1, -1, -1, -1, -1,
 300     -1, -1, -1, -1, -1, -1, -1, -1,
 301   };
 302
 303 static CORE_ADDR
 304 ia64_register_addr (struct gdbarch *gdbarch, int regno)
 305 {
 306   CORE_ADDR addr;
 307
 308   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 309     error (_("Invalid register number %d."), regno);
 310
 311   if (u_offsets[regno] == -1)
 312     addr = 0;
 313   else
 314     addr = (CORE_ADDR) u_offsets[regno];
 315
 316   return addr;
 317 }
 318
 319 static int
 320 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
 321 {
 322   return regno < 0
 323          || regno >= gdbarch_num_regs (gdbarch)
 324          || u_offsets[regno] == -1;
 325 }
 326
 327 static int
 328 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
 329 {
 330   /* Rationale behind not permitting stores to bspstore...
 331
 332      The IA-64 architecture provides bspstore and bsp which refer
 333      memory locations in the RSE's backing store.  bspstore is the
 334      next location which will be written when the RSE needs to write
 335      to memory.  bsp is the address at which r32 in the current frame
 336      would be found if it were written to the backing store.
 337
 338      The IA-64 architecture provides read-only access to bsp and
 339      read/write access to bspstore (but only when the RSE is in
 340      the enforced lazy mode).  It should be noted that stores
 341      to bspstore also affect the value of bsp.  Changing bspstore
 342      does not affect the number of dirty entries between bspstore
 343      and bsp, so changing bspstore by N words will also cause bsp
 344      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 345      depending upon where the NaT collection bits fall.)
 346
 347      OTOH, the Linux kernel provides read/write access to bsp (and
 348      currently read/write access to bspstore as well).  But it
 349      is definitely the case that if you change one, the other
 350      will change at the same time.  It is more useful to gdb to
 351      be able to change bsp.  So in order to prevent strange and
 352      undesirable things from happening when a dummy stack frame
 353      is popped (after calling an inferior function), we allow
 354      bspstore to be read, but not written.  (Note that popping
 355      a (generic) dummy stack frame causes all registers that
 356      were previously read from the inferior process to be written
 357      back.)  */
 358
 359   return regno < 0
 360          || regno >= gdbarch_num_regs (gdbarch)
 361          || u_offsets[regno] == -1
 362          || regno == IA64_BSPSTORE_REGNUM;
 363 }
 364
 365 void
 366 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
 367 {
 368   int regi;
 369   const greg_t *regp = (const greg_t *) gregsetp;
 370
 371   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 372     {
 373       regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
 374     }
 375
 376   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 377      somehow...  */
 378
 379   regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
 380
 381   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 382     {
 383       regcache_raw_supply (regcache, regi,
 384                            regp + 34 + (regi - IA64_BR0_REGNUM));
 385     }
 386
 387   regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
 388   regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
 389   regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
 390   regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
 391   regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
 392   regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
 393   regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
 394   regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
 395   regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
 396   regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
 397   regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
 398   regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
 399   regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
 400 }
 401
 402 void
 403 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
 404 {
 405   int regi;
 406   greg_t *regp = (greg_t *) gregsetp;
 407
 408 #define COPY_REG(_idx_,_regi_) \
 409   if ((regno == -1) || regno == _regi_) \
 410     regcache_raw_collect (regcache, _regi_, regp + _idx_)
 411
 412   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 413     {
 414       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 415     }
 416
 417   /* FIXME: NAT collection bits at index 32?  */
 418
 419   COPY_REG (33, IA64_PR_REGNUM);
 420
 421   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 422     {
 423       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 424     }
 425
 426   COPY_REG (42, IA64_IP_REGNUM);
 427   COPY_REG (43, IA64_CFM_REGNUM);
 428   COPY_REG (44, IA64_PSR_REGNUM);
 429   COPY_REG (45, IA64_RSC_REGNUM);
 430   COPY_REG (46, IA64_BSP_REGNUM);
 431   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 432   COPY_REG (48, IA64_RNAT_REGNUM);
 433   COPY_REG (49, IA64_CCV_REGNUM);
 434   COPY_REG (50, IA64_UNAT_REGNUM);
 435   COPY_REG (51, IA64_FPSR_REGNUM);
 436   COPY_REG (52, IA64_PFS_REGNUM);
 437   COPY_REG (53, IA64_LC_REGNUM);
 438   COPY_REG (54, IA64_EC_REGNUM);
 439 }
 440
 441 /*  Given a pointer to a floating point register set in /proc format
 442    (fpregset_t *), unpack the register contents and supply them as gdb's
 443    idea of the current floating point register values.  */
 444
 445 void
 446 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
 447 {
 448   int regi;
 449   const char *from;
 450
 451   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 452     {
 453       from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 454       regcache_raw_supply (regcache, regi, from);
 455     }
 456 }
 457
 458 /*  Given a pointer to a floating point register set in /proc format
 459    (fpregset_t *), update the register specified by REGNO from gdb's idea
 460    of the current floating point register set.  If REGNO is -1, update
 461    them all.  */
 462
 463 void
 464 fill_fpregset (const struct regcache *regcache,
 465                fpregset_t *fpregsetp, int regno)
 466 {
 467   int regi;
 468
 469   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 470     {
 471       if ((regno == -1) || (regno == regi))
 472         regcache_raw_collect (regcache, regi,
 473                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 474     }
 475 }
 476
 477 #define IA64_PSR_DB (1UL << 24)
 478 #define IA64_PSR_DD (1UL << 39)
 479
 480 static void
 481 enable_watchpoints_in_psr (ptid_t ptid)
 482 {
 483   struct regcache *regcache = get_thread_regcache (ptid);
 484   ULONGEST psr;
 485
 486   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 487   if (!(psr & IA64_PSR_DB))
 488     {
 489       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 490                                    watchpoints and breakpoints.  */
 491       regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 492     }
 493 }
 494
 495 static long debug_registers[8];
 496
 497 static void
 498 store_debug_register (ptid_t ptid, int idx, long val)
 499 {
 500   int tid;
 501
 502   tid = TIDGET (ptid);
 503   if (tid == 0)
 504     tid = PIDGET (ptid);
 505
 506   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 507 }
 508
 509 static void
 510 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
 511                            long *dbr_mask)
 512 {
 513   if (dbr_addr)
 514     store_debug_register (ptid, 2 * idx, *dbr_addr);
 515   if (dbr_mask)
 516     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 517 }
 518
 519 static int
 520 is_power_of_2 (int val)
 521 {
 522   int i, onecount;
 523
 524   onecount = 0;
 525   for (i = 0; i < 8 * sizeof (val); i++)
 526     if (val & (1 << i))
 527       onecount++;
 528
 529   return onecount <= 1;
 530 }
 531
 532 static int
 533 ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
 534                               struct expression *cond)
 535 {
 536   struct lwp_info *lp;
 537   int idx;
 538   long dbr_addr, dbr_mask;
 539   int max_watchpoints = 4;
 540
 541   if (len <= 0 || !is_power_of_2 (len))
 542     return -1;
 543
 544   for (idx = 0; idx < max_watchpoints; idx++)
 545     {
 546       dbr_mask = debug_registers[idx * 2 + 1];
 547       if ((dbr_mask & (0x3UL << 62)) == 0)
 548         {
 549           /* Exit loop if both r and w bits clear.  */
 550           break;
 551         }
 552     }
 553
 554   if (idx == max_watchpoints)
 555     return -1;
 556
 557   dbr_addr = (long) addr;
 558   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 559   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 560   switch (rw)
 561     {
 562     case hw_write:
 563       dbr_mask |= (1L << 62);                   /* Set w bit */
 564       break;
 565     case hw_read:
 566       dbr_mask |= (1L << 63);                   /* Set r bit */
 567       break;
 568     case hw_access:
 569       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 570       break;
 571     default:
 572       return -1;
 573     }
 574
 575   debug_registers[2 * idx] = dbr_addr;
 576   debug_registers[2 * idx + 1] = dbr_mask;
 577   ALL_LWPS (lp)
 578     {
 579       store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 580       enable_watchpoints_in_psr (lp->ptid);
 581     }
 582
 583   return 0;
 584 }
 585
 586 static int
 587 ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
 588                               struct expression *cond)
 589 {
 590   int idx;
 591   long dbr_addr, dbr_mask;
 592   int max_watchpoints = 4;
 593
 594   if (len <= 0 || !is_power_of_2 (len))
 595     return -1;
 596
 597   for (idx = 0; idx < max_watchpoints; idx++)
 598     {
 599       dbr_addr = debug_registers[2 * idx];
 600       dbr_mask = debug_registers[2 * idx + 1];
 601       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 602         {
 603           struct lwp_info *lp;
 604
 605           debug_registers[2 * idx] = 0;
 606           debug_registers[2 * idx + 1] = 0;
 607           dbr_addr = 0;
 608           dbr_mask = 0;
 609
 610           ALL_LWPS (lp)
 611             store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 612
 613           return 0;
 614         }
 615     }
 616   return -1;
 617 }
 618
 619 static void
 620 ia64_linux_new_thread (struct lwp_info *lp)
 621 {
 622   int i, any;
 623
 624   any = 0;
 625   for (i = 0; i < 8; i++)
 626     {
 627       if (debug_registers[i] != 0)
 628         any = 1;
 629       store_debug_register (lp->ptid, i, debug_registers[i]);
 630     }
 631
 632   if (any)
 633     enable_watchpoints_in_psr (lp->ptid);
 634 }
 635
 636 static int
 637 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
 638 {
 639   CORE_ADDR psr;
 640   struct siginfo *siginfo_p;
 641   struct regcache *regcache = get_current_regcache ();
 642
 643   siginfo_p = linux_nat_get_siginfo (inferior_ptid);
 644
 645   if (siginfo_p->si_signo != SIGTRAP
 646       || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 647     return 0;
 648
 649   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 650   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 651                            for the next instruction.  */
 652   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 653
 654   *addr_p = (CORE_ADDR)siginfo_p->si_addr;
 655   return 1;
 656 }
 657
 658 static int
 659 ia64_linux_stopped_by_watchpoint (void)
 660 {
 661   CORE_ADDR addr;
 662   return ia64_linux_stopped_data_address (&current_target, &addr);
 663 }
 664
 665 static int
 666 ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
 667 {
 668   return 1;
 669 }
 670
 671
 672 /* Fetch register REGNUM from the inferior.  */
 673
 674 static void
 675 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
 676 {
 677   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 678   CORE_ADDR addr;
 679   size_t size;
 680   PTRACE_TYPE_RET *buf;
 681   int pid, i;
 682
 683   if (ia64_cannot_fetch_register (gdbarch, regnum))
 684     {
 685       regcache_raw_supply (regcache, regnum, NULL);
 686       return;
 687     }
 688
 689   /* Cater for systems like GNU/Linux, that implement threads as
 690      separate processes.  */
 691   pid = ptid_get_lwp (inferior_ptid);
 692   if (pid == 0)
 693     pid = ptid_get_pid (inferior_ptid);
 694
 695   /* This isn't really an address, but ptrace thinks of it as one.  */
 696   addr = ia64_register_addr (gdbarch, regnum);
 697   size = register_size (gdbarch, regnum);
 698
 699   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 700   buf = alloca (size);
 701
 702   /* Read the register contents from the inferior a chunk at a time.  */
 703   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 704     {
 705       errno = 0;
 706       buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
 707       if (errno != 0)
 708         error (_("Couldn't read register %s (#%d): %s."),
 709                gdbarch_register_name (gdbarch, regnum),
 710                regnum, safe_strerror (errno));
 711
 712       addr += sizeof (PTRACE_TYPE_RET);
 713     }
 714   regcache_raw_supply (regcache, regnum, buf);
 715 }
 716
 717 /* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
 718    for all registers.  */
 719
 720 static void
 721 ia64_linux_fetch_registers (struct target_ops *ops,
 722                             struct regcache *regcache, int regnum)
 723 {
 724   if (regnum == -1)
 725     for (regnum = 0;
 726          regnum < gdbarch_num_regs (get_regcache_arch (regcache));
 727          regnum++)
 728       ia64_linux_fetch_register (regcache, regnum);
 729   else
 730     ia64_linux_fetch_register (regcache, regnum);
 731 }
 732
 733 /* Store register REGNUM into the inferior.  */
 734
 735 static void
 736 ia64_linux_store_register (const struct regcache *regcache, int regnum)
 737 {
 738   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 739   CORE_ADDR addr;
 740   size_t size;
 741   PTRACE_TYPE_RET *buf;
 742   int pid, i;
 743
 744   if (ia64_cannot_store_register (gdbarch, regnum))
 745     return;
 746
 747   /* Cater for systems like GNU/Linux, that implement threads as
 748      separate processes.  */
 749   pid = ptid_get_lwp (inferior_ptid);
 750   if (pid == 0)
 751     pid = ptid_get_pid (inferior_ptid);
 752
 753   /* This isn't really an address, but ptrace thinks of it as one.  */
 754   addr = ia64_register_addr (gdbarch, regnum);
 755   size = register_size (gdbarch, regnum);
 756
 757   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 758   buf = alloca (size);
 759
 760   /* Write the register contents into the inferior a chunk at a time.  */
 761   regcache_raw_collect (regcache, regnum, buf);
 762   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 763     {
 764       errno = 0;
 765       ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
 766       if (errno != 0)
 767         error (_("Couldn't write register %s (#%d): %s."),
 768                gdbarch_register_name (gdbarch, regnum),
 769                regnum, safe_strerror (errno));
 770
 771       addr += sizeof (PTRACE_TYPE_RET);
 772     }
 773 }
 774
 775 /* Store register REGNUM back into the inferior.  If REGNUM is -1, do
 776    this for all registers.  */
 777
 778 static void
 779 ia64_linux_store_registers (struct target_ops *ops,
 780                             struct regcache *regcache, int regnum)
 781 {
 782   if (regnum == -1)
 783     for (regnum = 0;
 784          regnum < gdbarch_num_regs (get_regcache_arch (regcache));
 785          regnum++)
 786       ia64_linux_store_register (regcache, regnum);
 787   else
 788     ia64_linux_store_register (regcache, regnum);
 789 }
 790
 791
 792 static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
 793                                       const char *, gdb_byte *,
 794                                       const gdb_byte *, ULONGEST, LONGEST);
 795
 796 static LONGEST
 797 ia64_linux_xfer_partial (struct target_ops *ops,
 798                          enum target_object object,
 799                          const char *annex,
 800                          gdb_byte *readbuf, const gdb_byte *writebuf,
 801                          ULONGEST offset, LONGEST len)
 802 {
 803   if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
 804     return syscall (__NR_getunwind, readbuf, len);
 805
 806   return super_xfer_partial (ops, object, annex, readbuf, writebuf,
 807                              offset, len);
 808 }
 809
 810 /* For break.b instruction ia64 CPU forgets the immediate value and generates
 811    SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
 812    ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
 813    difference for the signals here.  */
 814
 815 static int
 816 ia64_linux_status_is_event (int status)
 817 {
 818   return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
 819                                  || WSTOPSIG (status) == SIGILL);
 820 }
 821
 822 void _initialize_ia64_linux_nat (void);
 823
 824 void
 825 _initialize_ia64_linux_nat (void)
 826 {
 827   struct target_ops *t;
 828
 829   /* Fill in the generic GNU/Linux methods.  */
 830   t = linux_target ();
 831
 832   /* Override the default fetch/store register routines.  */
 833   t->to_fetch_registers = ia64_linux_fetch_registers;
 834   t->to_store_registers = ia64_linux_store_registers;
 835
 836   /* Override the default to_xfer_partial.  */
 837   super_xfer_partial = t->to_xfer_partial;
 838   t->to_xfer_partial = ia64_linux_xfer_partial;
 839
 840   /* Override watchpoint routines.  */
 841
 842   /* The IA-64 architecture can step over a watch point (without triggering
 843      it again) if the "dd" (data debug fault disable) bit in the processor
 844      status word is set.
 845
 846      This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
 847      code there has determined that a hardware watchpoint has indeed
 848      been hit.  The CPU will then be able to execute one instruction
 849      without triggering a watchpoint.  */
 850
 851   t->to_have_steppable_watchpoint = 1;
 852   t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
 853   t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
 854   t->to_stopped_data_address = ia64_linux_stopped_data_address;
 855   t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
 856   t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
 857
 858   /* Register the target.  */
 859   linux_nat_add_target (t);
 860   linux_nat_set_new_thread (t, ia64_linux_new_thread);
 861   linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
 862 }