gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999-2018 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "target.h"
  24 #include "gdbcore.h"
  25 #include "regcache.h"
  26 #include "ia64-tdep.h"
  27 #include "linux-nat.h"
  28
  29 #include <signal.h>
  30 #include "nat/gdb_ptrace.h"
  31 #include "gdb_wait.h"
  32 #ifdef HAVE_SYS_REG_H
  33 #include <sys/reg.h>
  34 #endif
  35 #include <sys/syscall.h>
  36 #include <sys/user.h>
  37
  38 #include <asm/ptrace_offsets.h>
  39 #include <sys/procfs.h>
  40
  41 /* Prototypes for supply_gregset etc.  */
  42 #include "gregset.h"
  43
  44 #include "inf-ptrace.h"
  45
  46 class ia64_linux_nat_target final : public linux_nat_target
  47 {
  48 public:
  49   /* Add our register access methods.  */
  50   void fetch_registers (struct regcache *, int) override;
  51   void store_registers (struct regcache *, int) override;
  52
  53   enum target_xfer_status xfer_partial (enum target_object object,
  54                                         const char *annex,
  55                                         gdb_byte *readbuf,
  56                                         const gdb_byte *writebuf,
  57                                         ULONGEST offset, ULONGEST len,
  58                                         ULONGEST *xfered_len) override;
  59
  60   const struct target_desc *read_description () override;
  61
  62   /* Override watchpoint routines.  */
  63
  64   /* The IA-64 architecture can step over a watch point (without
  65      triggering it again) if the "dd" (data debug fault disable) bit
  66      in the processor status word is set.
  67
  68      This PSR bit is set in
  69      ia64_linux_nat_target::stopped_by_watchpoint when the code there
  70      has determined that a hardware watchpoint has indeed been hit.
  71      The CPU will then be able to execute one instruction without
  72      triggering a watchpoint.  */
  73   bool have_steppable_watchpoint () { return 1; }
  74
  75   int can_use_hw_breakpoint (enum bptype, int, int) override;
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78   int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  79                          struct expression *) override;
  80   int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  81                          struct expression *) override;
  82   /* Override linux_nat_target low methods.  */
  83   void low_new_thread (struct lwp_info *lp) override;
  84   bool low_status_is_event (int status) override;
  85 };
  86
  87 static ia64_linux_nat_target the_ia64_linux_nat_target;
  88
  89 /* These must match the order of the register names.
  90
  91    Some sort of lookup table is needed because the offsets associated
  92    with the registers are all over the board.  */
  93
  94 static int u_offsets[] =
  95   {
  96     /* general registers */
  97     -1,         /* gr0 not available; i.e, it's always zero.  */
  98     PT_R1,
  99     PT_R2,
 100     PT_R3,
 101     PT_R4,
 102     PT_R5,
 103     PT_R6,
 104     PT_R7,
 105     PT_R8,
 106     PT_R9,
 107     PT_R10,
 108     PT_R11,
 109     PT_R12,
 110     PT_R13,
 111     PT_R14,
 112     PT_R15,
 113     PT_R16,
 114     PT_R17,
 115     PT_R18,
 116     PT_R19,
 117     PT_R20,
 118     PT_R21,
 119     PT_R22,
 120     PT_R23,
 121     PT_R24,
 122     PT_R25,
 123     PT_R26,
 124     PT_R27,
 125     PT_R28,
 126     PT_R29,
 127     PT_R30,
 128     PT_R31,
 129     /* gr32 through gr127 not directly available via the ptrace interface.  */
 130     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 131     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 132     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 133     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 134     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 135     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 136     /* Floating point registers */
 137     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0).  */
 138     PT_F2,
 139     PT_F3,
 140     PT_F4,
 141     PT_F5,
 142     PT_F6,
 143     PT_F7,
 144     PT_F8,
 145     PT_F9,
 146     PT_F10,
 147     PT_F11,
 148     PT_F12,
 149     PT_F13,
 150     PT_F14,
 151     PT_F15,
 152     PT_F16,
 153     PT_F17,
 154     PT_F18,
 155     PT_F19,
 156     PT_F20,
 157     PT_F21,
 158     PT_F22,
 159     PT_F23,
 160     PT_F24,
 161     PT_F25,
 162     PT_F26,
 163     PT_F27,
 164     PT_F28,
 165     PT_F29,
 166     PT_F30,
 167     PT_F31,
 168     PT_F32,
 169     PT_F33,
 170     PT_F34,
 171     PT_F35,
 172     PT_F36,
 173     PT_F37,
 174     PT_F38,
 175     PT_F39,
 176     PT_F40,
 177     PT_F41,
 178     PT_F42,
 179     PT_F43,
 180     PT_F44,
 181     PT_F45,
 182     PT_F46,
 183     PT_F47,
 184     PT_F48,
 185     PT_F49,
 186     PT_F50,
 187     PT_F51,
 188     PT_F52,
 189     PT_F53,
 190     PT_F54,
 191     PT_F55,
 192     PT_F56,
 193     PT_F57,
 194     PT_F58,
 195     PT_F59,
 196     PT_F60,
 197     PT_F61,
 198     PT_F62,
 199     PT_F63,
 200     PT_F64,
 201     PT_F65,
 202     PT_F66,
 203     PT_F67,
 204     PT_F68,
 205     PT_F69,
 206     PT_F70,
 207     PT_F71,
 208     PT_F72,
 209     PT_F73,
 210     PT_F74,
 211     PT_F75,
 212     PT_F76,
 213     PT_F77,
 214     PT_F78,
 215     PT_F79,
 216     PT_F80,
 217     PT_F81,
 218     PT_F82,
 219     PT_F83,
 220     PT_F84,
 221     PT_F85,
 222     PT_F86,
 223     PT_F87,
 224     PT_F88,
 225     PT_F89,
 226     PT_F90,
 227     PT_F91,
 228     PT_F92,
 229     PT_F93,
 230     PT_F94,
 231     PT_F95,
 232     PT_F96,
 233     PT_F97,
 234     PT_F98,
 235     PT_F99,
 236     PT_F100,
 237     PT_F101,
 238     PT_F102,
 239     PT_F103,
 240     PT_F104,
 241     PT_F105,
 242     PT_F106,
 243     PT_F107,
 244     PT_F108,
 245     PT_F109,
 246     PT_F110,
 247     PT_F111,
 248     PT_F112,
 249     PT_F113,
 250     PT_F114,
 251     PT_F115,
 252     PT_F116,
 253     PT_F117,
 254     PT_F118,
 255     PT_F119,
 256     PT_F120,
 257     PT_F121,
 258     PT_F122,
 259     PT_F123,
 260     PT_F124,
 261     PT_F125,
 262     PT_F126,
 263     PT_F127,
 264     /* Predicate registers - we don't fetch these individually.  */
 265     -1, -1, -1, -1, -1, -1, -1, -1,
 266     -1, -1, -1, -1, -1, -1, -1, -1,
 267     -1, -1, -1, -1, -1, -1, -1, -1,
 268     -1, -1, -1, -1, -1, -1, -1, -1,
 269     -1, -1, -1, -1, -1, -1, -1, -1,
 270     -1, -1, -1, -1, -1, -1, -1, -1,
 271     -1, -1, -1, -1, -1, -1, -1, -1,
 272     -1, -1, -1, -1, -1, -1, -1, -1,
 273     /* branch registers */
 274     PT_B0,
 275     PT_B1,
 276     PT_B2,
 277     PT_B3,
 278     PT_B4,
 279     PT_B5,
 280     PT_B6,
 281     PT_B7,
 282     /* Virtual frame pointer and virtual return address pointer.  */
 283     -1, -1,
 284     /* other registers */
 285     PT_PR,
 286     PT_CR_IIP,  /* ip */
 287     PT_CR_IPSR, /* psr */
 288     PT_CFM,     /* cfm */
 289     /* kernel registers not visible via ptrace interface (?)  */
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     /* hole */
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     PT_AR_RSC,
 294     PT_AR_BSP,
 295     PT_AR_BSPSTORE,
 296     PT_AR_RNAT,
 297     -1,
 298     -1,         /* Not available: FCR, IA32 floating control register.  */
 299     -1, -1,
 300     -1,         /* Not available: EFLAG */
 301     -1,         /* Not available: CSD */
 302     -1,         /* Not available: SSD */
 303     -1,         /* Not available: CFLG */
 304     -1,         /* Not available: FSR */
 305     -1,         /* Not available: FIR */
 306     -1,         /* Not available: FDR */
 307     -1,
 308     PT_AR_CCV,
 309     -1, -1, -1,
 310     PT_AR_UNAT,
 311     -1, -1, -1,
 312     PT_AR_FPSR,
 313     -1, -1, -1,
 314     -1,         /* Not available: ITC */
 315     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 316     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 317     PT_AR_PFS,
 318     PT_AR_LC,
 319     PT_AR_EC,
 320     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 321     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 322     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 323     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 324     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 325     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 326     -1,
 327     /* nat bits - not fetched directly; instead we obtain these bits from
 328        either rnat or unat or from memory.  */
 329     -1, -1, -1, -1, -1, -1, -1, -1,
 330     -1, -1, -1, -1, -1, -1, -1, -1,
 331     -1, -1, -1, -1, -1, -1, -1, -1,
 332     -1, -1, -1, -1, -1, -1, -1, -1,
 333     -1, -1, -1, -1, -1, -1, -1, -1,
 334     -1, -1, -1, -1, -1, -1, -1, -1,
 335     -1, -1, -1, -1, -1, -1, -1, -1,
 336     -1, -1, -1, -1, -1, -1, -1, -1,
 337     -1, -1, -1, -1, -1, -1, -1, -1,
 338     -1, -1, -1, -1, -1, -1, -1, -1,
 339     -1, -1, -1, -1, -1, -1, -1, -1,
 340     -1, -1, -1, -1, -1, -1, -1, -1,
 341     -1, -1, -1, -1, -1, -1, -1, -1,
 342     -1, -1, -1, -1, -1, -1, -1, -1,
 343     -1, -1, -1, -1, -1, -1, -1, -1,
 344     -1, -1, -1, -1, -1, -1, -1, -1,
 345   };
 346
 347 static CORE_ADDR
 348 ia64_register_addr (struct gdbarch *gdbarch, int regno)
 349 {
 350   CORE_ADDR addr;
 351
 352   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 353     error (_("Invalid register number %d."), regno);
 354
 355   if (u_offsets[regno] == -1)
 356     addr = 0;
 357   else
 358     addr = (CORE_ADDR) u_offsets[regno];
 359
 360   return addr;
 361 }
 362
 363 static int
 364 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
 365 {
 366   return regno < 0
 367          || regno >= gdbarch_num_regs (gdbarch)
 368          || u_offsets[regno] == -1;
 369 }
 370
 371 static int
 372 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
 373 {
 374   /* Rationale behind not permitting stores to bspstore...
 375
 376      The IA-64 architecture provides bspstore and bsp which refer
 377      memory locations in the RSE's backing store.  bspstore is the
 378      next location which will be written when the RSE needs to write
 379      to memory.  bsp is the address at which r32 in the current frame
 380      would be found if it were written to the backing store.
 381
 382      The IA-64 architecture provides read-only access to bsp and
 383      read/write access to bspstore (but only when the RSE is in
 384      the enforced lazy mode).  It should be noted that stores
 385      to bspstore also affect the value of bsp.  Changing bspstore
 386      does not affect the number of dirty entries between bspstore
 387      and bsp, so changing bspstore by N words will also cause bsp
 388      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 389      depending upon where the NaT collection bits fall.)
 390
 391      OTOH, the Linux kernel provides read/write access to bsp (and
 392      currently read/write access to bspstore as well).  But it
 393      is definitely the case that if you change one, the other
 394      will change at the same time.  It is more useful to gdb to
 395      be able to change bsp.  So in order to prevent strange and
 396      undesirable things from happening when a dummy stack frame
 397      is popped (after calling an inferior function), we allow
 398      bspstore to be read, but not written.  (Note that popping
 399      a (generic) dummy stack frame causes all registers that
 400      were previously read from the inferior process to be written
 401      back.)  */
 402
 403   return regno < 0
 404          || regno >= gdbarch_num_regs (gdbarch)
 405          || u_offsets[regno] == -1
 406          || regno == IA64_BSPSTORE_REGNUM;
 407 }
 408
 409 void
 410 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
 411 {
 412   int regi;
 413   const greg_t *regp = (const greg_t *) gregsetp;
 414
 415   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 416     {
 417       regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
 418     }
 419
 420   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 421      somehow...  */
 422
 423   regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
 424
 425   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 426     {
 427       regcache_raw_supply (regcache, regi,
 428                            regp + 34 + (regi - IA64_BR0_REGNUM));
 429     }
 430
 431   regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
 432   regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
 433   regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
 434   regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
 435   regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
 436   regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
 437   regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
 438   regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
 439   regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
 440   regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
 441   regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
 442   regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
 443   regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
 444 }
 445
 446 void
 447 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
 448 {
 449   int regi;
 450   greg_t *regp = (greg_t *) gregsetp;
 451
 452 #define COPY_REG(_idx_,_regi_) \
 453   if ((regno == -1) || regno == _regi_) \
 454     regcache_raw_collect (regcache, _regi_, regp + _idx_)
 455
 456   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 457     {
 458       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 459     }
 460
 461   /* FIXME: NAT collection bits at index 32?  */
 462
 463   COPY_REG (33, IA64_PR_REGNUM);
 464
 465   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 466     {
 467       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 468     }
 469
 470   COPY_REG (42, IA64_IP_REGNUM);
 471   COPY_REG (43, IA64_CFM_REGNUM);
 472   COPY_REG (44, IA64_PSR_REGNUM);
 473   COPY_REG (45, IA64_RSC_REGNUM);
 474   COPY_REG (46, IA64_BSP_REGNUM);
 475   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 476   COPY_REG (48, IA64_RNAT_REGNUM);
 477   COPY_REG (49, IA64_CCV_REGNUM);
 478   COPY_REG (50, IA64_UNAT_REGNUM);
 479   COPY_REG (51, IA64_FPSR_REGNUM);
 480   COPY_REG (52, IA64_PFS_REGNUM);
 481   COPY_REG (53, IA64_LC_REGNUM);
 482   COPY_REG (54, IA64_EC_REGNUM);
 483 }
 484
 485 /*  Given a pointer to a floating point register set in /proc format
 486    (fpregset_t *), unpack the register contents and supply them as gdb's
 487    idea of the current floating point register values.  */
 488
 489 void
 490 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
 491 {
 492   int regi;
 493   const char *from;
 494   const gdb_byte f_zero[16] = { 0 };
 495   const gdb_byte f_one[16] =
 496     { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 497
 498   /* Kernel generated cores have fr1==0 instead of 1.0.  Older GDBs
 499      did the same.  So ignore whatever might be recorded in fpregset_t
 500      for fr0/fr1 and always supply their expected values.  */
 501
 502   /* fr0 is always read as zero.  */
 503   regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero);
 504   /* fr1 is always read as one (1.0).  */
 505   regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one);
 506
 507   for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 508     {
 509       from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 510       regcache_raw_supply (regcache, regi, from);
 511     }
 512 }
 513
 514 /*  Given a pointer to a floating point register set in /proc format
 515    (fpregset_t *), update the register specified by REGNO from gdb's idea
 516    of the current floating point register set.  If REGNO is -1, update
 517    them all.  */
 518
 519 void
 520 fill_fpregset (const struct regcache *regcache,
 521                fpregset_t *fpregsetp, int regno)
 522 {
 523   int regi;
 524
 525   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 526     {
 527       if ((regno == -1) || (regno == regi))
 528         regcache_raw_collect (regcache, regi,
 529                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 530     }
 531 }
 532
 533 #define IA64_PSR_DB (1UL << 24)
 534 #define IA64_PSR_DD (1UL << 39)
 535
 536 static void
 537 enable_watchpoints_in_psr (ptid_t ptid)
 538 {
 539   struct regcache *regcache = get_thread_regcache (ptid);
 540   ULONGEST psr;
 541
 542   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 543   if (!(psr & IA64_PSR_DB))
 544     {
 545       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 546                                    watchpoints and breakpoints.  */
 547       regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 548     }
 549 }
 550
 551 static long debug_registers[8];
 552
 553 static void
 554 store_debug_register (ptid_t ptid, int idx, long val)
 555 {
 556   int tid;
 557
 558   tid = ptid_get_lwp (ptid);
 559   if (tid == 0)
 560     tid = ptid_get_pid (ptid);
 561
 562   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 563 }
 564
 565 static void
 566 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
 567                            long *dbr_mask)
 568 {
 569   if (dbr_addr)
 570     store_debug_register (ptid, 2 * idx, *dbr_addr);
 571   if (dbr_mask)
 572     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 573 }
 574
 575 static int
 576 is_power_of_2 (int val)
 577 {
 578   int i, onecount;
 579
 580   onecount = 0;
 581   for (i = 0; i < 8 * sizeof (val); i++)
 582     if (val & (1 << i))
 583       onecount++;
 584
 585   return onecount <= 1;
 586 }
 587
 588 int
 589 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
 590                                           enum target_hw_bp_type type,
 591                                           struct expression *cond)
 592 {
 593   struct lwp_info *lp;
 594   int idx;
 595   long dbr_addr, dbr_mask;
 596   int max_watchpoints = 4;
 597
 598   if (len <= 0 || !is_power_of_2 (len))
 599     return -1;
 600
 601   for (idx = 0; idx < max_watchpoints; idx++)
 602     {
 603       dbr_mask = debug_registers[idx * 2 + 1];
 604       if ((dbr_mask & (0x3UL << 62)) == 0)
 605         {
 606           /* Exit loop if both r and w bits clear.  */
 607           break;
 608         }
 609     }
 610
 611   if (idx == max_watchpoints)
 612     return -1;
 613
 614   dbr_addr = (long) addr;
 615   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 616   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 617   switch (type)
 618     {
 619     case hw_write:
 620       dbr_mask |= (1L << 62);                   /* Set w bit */
 621       break;
 622     case hw_read:
 623       dbr_mask |= (1L << 63);                   /* Set r bit */
 624       break;
 625     case hw_access:
 626       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 627       break;
 628     default:
 629       return -1;
 630     }
 631
 632   debug_registers[2 * idx] = dbr_addr;
 633   debug_registers[2 * idx + 1] = dbr_mask;
 634   ALL_LWPS (lp)
 635     {
 636       store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 637       enable_watchpoints_in_psr (lp->ptid);
 638     }
 639
 640   return 0;
 641 }
 642
 643 int
 644 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
 645                                           enum target_hw_bp_type type,
 646                                           struct expression *cond)
 647 {
 648   int idx;
 649   long dbr_addr, dbr_mask;
 650   int max_watchpoints = 4;
 651
 652   if (len <= 0 || !is_power_of_2 (len))
 653     return -1;
 654
 655   for (idx = 0; idx < max_watchpoints; idx++)
 656     {
 657       dbr_addr = debug_registers[2 * idx];
 658       dbr_mask = debug_registers[2 * idx + 1];
 659       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 660         {
 661           struct lwp_info *lp;
 662
 663           debug_registers[2 * idx] = 0;
 664           debug_registers[2 * idx + 1] = 0;
 665           dbr_addr = 0;
 666           dbr_mask = 0;
 667
 668           ALL_LWPS (lp)
 669             store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 670
 671           return 0;
 672         }
 673     }
 674   return -1;
 675 }
 676
 677 static void
 678 ia64_linux_new_thread (struct lwp_info *lp)
 679 {
 680   int i, any;
 681
 682   any = 0;
 683   for (i = 0; i < 8; i++)
 684     {
 685       if (debug_registers[i] != 0)
 686         any = 1;
 687       store_debug_register (lp->ptid, i, debug_registers[i]);
 688     }
 689
 690   if (any)
 691     enable_watchpoints_in_psr (lp->ptid);
 692 }
 693
 694 bool
 695 ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 696 {
 697   CORE_ADDR psr;
 698   siginfo_t siginfo;
 699   struct regcache *regcache = get_current_regcache ();
 700
 701   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 702     return false;
 703
 704   if (siginfo.si_signo != SIGTRAP
 705       || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 706     return false;
 707
 708   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 709   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 710                            for the next instruction.  */
 711   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 712
 713   *addr_p = (CORE_ADDR) siginfo.si_addr;
 714   return true;
 715 }
 716
 717 bool
 718 ia64_linux_nat_target::stopped_by_watchpoint ()
 719 {
 720   CORE_ADDR addr;
 721   return stopped_data_address (&addr);
 722 }
 723
 724 static int
 725 ia64_linux_can_use_hw_breakpoint (struct target_ops *self,
 726                                   enum bptype type,
 727                                   int cnt, int othertype)
 728 {
 729   return 1;
 730 }
 731
 732
 733 /* Fetch register REGNUM from the inferior.  */
 734
 735 static void
 736 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
 737 {
 738   struct gdbarch *gdbarch = regcache->arch ();
 739   CORE_ADDR addr;
 740   size_t size;
 741   PTRACE_TYPE_RET *buf;
 742   pid_t pid;
 743   int i;
 744
 745   /* r0 cannot be fetched but is always zero.  */
 746   if (regnum == IA64_GR0_REGNUM)
 747     {
 748       const gdb_byte zero[8] = { 0 };
 749
 750       gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
 751       regcache_raw_supply (regcache, regnum, zero);
 752       return;
 753     }
 754
 755   /* fr0 cannot be fetched but is always zero.  */
 756   if (regnum == IA64_FR0_REGNUM)
 757     {
 758       const gdb_byte f_zero[16] = { 0 };
 759
 760       gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
 761       regcache_raw_supply (regcache, regnum, f_zero);
 762       return;
 763     }
 764
 765   /* fr1 cannot be fetched but is always one (1.0).  */
 766   if (regnum == IA64_FR1_REGNUM)
 767     {
 768       const gdb_byte f_one[16] =
 769         { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 770
 771       gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
 772       regcache_raw_supply (regcache, regnum, f_one);
 773       return;
 774     }
 775
 776   if (ia64_cannot_fetch_register (gdbarch, regnum))
 777     {
 778       regcache_raw_supply (regcache, regnum, NULL);
 779       return;
 780     }
 781
 782   pid = get_ptrace_pid (regcache->ptid ());
 783
 784   /* This isn't really an address, but ptrace thinks of it as one.  */
 785   addr = ia64_register_addr (gdbarch, regnum);
 786   size = register_size (gdbarch, regnum);
 787
 788   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 789   buf = (PTRACE_TYPE_RET *) alloca (size);
 790
 791   /* Read the register contents from the inferior a chunk at a time.  */
 792   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 793     {
 794       errno = 0;
 795       buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
 796       if (errno != 0)
 797         error (_("Couldn't read register %s (#%d): %s."),
 798                gdbarch_register_name (gdbarch, regnum),
 799                regnum, safe_strerror (errno));
 800
 801       addr += sizeof (PTRACE_TYPE_RET);
 802     }
 803   regcache_raw_supply (regcache, regnum, buf);
 804 }
 805
 806 /* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
 807    for all registers.  */
 808
 809 void
 810 ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 811 {
 812   if (regnum == -1)
 813     for (regnum = 0;
 814          regnum < gdbarch_num_regs (regcache->arch ());
 815          regnum++)
 816       ia64_linux_fetch_register (regcache, regnum);
 817   else
 818     ia64_linux_fetch_register (regcache, regnum);
 819 }
 820
 821 /* Store register REGNUM into the inferior.  */
 822
 823 static void
 824 ia64_linux_store_register (const struct regcache *regcache, int regnum)
 825 {
 826   struct gdbarch *gdbarch = regcache->arch ();
 827   CORE_ADDR addr;
 828   size_t size;
 829   PTRACE_TYPE_RET *buf;
 830   pid_t pid;
 831   int i;
 832
 833   if (ia64_cannot_store_register (gdbarch, regnum))
 834     return;
 835
 836   pid = get_ptrace_pid (regcache->ptid ());
 837
 838   /* This isn't really an address, but ptrace thinks of it as one.  */
 839   addr = ia64_register_addr (gdbarch, regnum);
 840   size = register_size (gdbarch, regnum);
 841
 842   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 843   buf = (PTRACE_TYPE_RET *) alloca (size);
 844
 845   /* Write the register contents into the inferior a chunk at a time.  */
 846   regcache_raw_collect (regcache, regnum, buf);
 847   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 848     {
 849       errno = 0;
 850       ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
 851       if (errno != 0)
 852         error (_("Couldn't write register %s (#%d): %s."),
 853                gdbarch_register_name (gdbarch, regnum),
 854                regnum, safe_strerror (errno));
 855
 856       addr += sizeof (PTRACE_TYPE_RET);
 857     }
 858 }
 859
 860 /* Store register REGNUM back into the inferior.  If REGNUM is -1, do
 861    this for all registers.  */
 862
 863 void
 864 ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 865 {
 866   if (regnum == -1)
 867     for (regnum = 0;
 868          regnum < gdbarch_num_regs (regcache->arch ());
 869          regnum++)
 870       ia64_linux_store_register (regcache, regnum);
 871   else
 872     ia64_linux_store_register (regcache, regnum);
 873 }
 874
 875 /* Implement the xfer_partial target_ops method.  */
 876
 877 enum target_xfer_status
 878 ia64_linux_nat_target::xfer_partial (enum target_object object,
 879                                      const char *annex,
 880                                      gdb_byte *readbuf, const gdb_byte *writebuf,
 881                                      ULONGEST offset, ULONGEST len,
 882                                      ULONGEST *xfered_len)
 883 {
 884   if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
 885     {
 886       static long gate_table_size;
 887       gdb_byte *tmp_buf;
 888       long res;
 889
 890       /* Probe for the table size once.  */
 891       if (gate_table_size == 0)
 892         gate_table_size = syscall (__NR_getunwind, NULL, 0);
 893       if (gate_table_size < 0)
 894         return TARGET_XFER_E_IO;
 895
 896       if (offset >= gate_table_size)
 897         return TARGET_XFER_EOF;
 898
 899       tmp_buf = (gdb_byte *) alloca (gate_table_size);
 900       res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
 901       if (res < 0)
 902         return TARGET_XFER_E_IO;
 903       gdb_assert (res == gate_table_size);
 904
 905       if (offset + len > gate_table_size)
 906         len = gate_table_size - offset;
 907
 908       memcpy (readbuf, tmp_buf + offset, len);
 909       *xfered_len = len;
 910       return TARGET_XFER_OK;
 911     }
 912
 913   return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
 914                                          offset, len, xfered_len);
 915 }
 916
 917 /* For break.b instruction ia64 CPU forgets the immediate value and generates
 918    SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
 919    ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
 920    difference for the signals here.  */
 921
 922 bool
 923 ia64_linux_nat_target::low_status_is_event (int status)
 924 {
 925   return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
 926                                  || WSTOPSIG (status) == SIGILL);
 927 }
 928
 929 void
 930 _initialize_ia64_linux_nat (void)
 931 {
 932   /* Register the target.  */
 933   linux_target = &the_ia64_linux_nat_target;
 934   add_inf_child_target (&the_ia64_linux_nat_target);
 935 }