gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running Linux.
   2    Copyright 1999, 2000 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330,
  19    Boston, MA 02111-1307, USA.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "target.h"
  24 #include "gdbcore.h"
  25
  26 #include <signal.h>
  27 #include <sys/ptrace.h>
  28 #include <sys/wait.h>
  29 #ifdef HAVE_SYS_REG_H
  30 #include <sys/reg.h>
  31 #endif
  32 #include <sys/user.h>
  33
  34 #include <asm/ptrace_offsets.h>
  35 #include <sys/procfs.h>
  36
  37 /* Prototypes for supply_gregset etc. */
  38 #include "gregset.h"
  39
  40 /* These must match the order of the register names.
  41
  42    Some sort of lookup table is needed because the offsets associated
  43    with the registers are all over the board.  */
  44
  45 static int u_offsets[] =
  46   {
  47     /* general registers */
  48     -1,         /* gr0 not available; i.e, it's always zero */
  49     PT_R1,
  50     PT_R2,
  51     PT_R3,
  52     PT_R4,
  53     PT_R5,
  54     PT_R6,
  55     PT_R7,
  56     PT_R8,
  57     PT_R9,
  58     PT_R10,
  59     PT_R11,
  60     PT_R12,
  61     PT_R13,
  62     PT_R14,
  63     PT_R15,
  64     PT_R16,
  65     PT_R17,
  66     PT_R18,
  67     PT_R19,
  68     PT_R20,
  69     PT_R21,
  70     PT_R22,
  71     PT_R23,
  72     PT_R24,
  73     PT_R25,
  74     PT_R26,
  75     PT_R27,
  76     PT_R28,
  77     PT_R29,
  78     PT_R30,
  79     PT_R31,
  80     /* gr32 through gr127 not directly available via the ptrace interface */
  81     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  82     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  83     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  84     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  85     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  86     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  87     /* Floating point registers */
  88     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
  89     PT_F2,
  90     PT_F3,
  91     PT_F4,
  92     PT_F5,
  93     PT_F6,
  94     PT_F7,
  95     PT_F8,
  96     PT_F9,
  97     PT_F10,
  98     PT_F11,
  99     PT_F12,
 100     PT_F13,
 101     PT_F14,
 102     PT_F15,
 103     PT_F16,
 104     PT_F17,
 105     PT_F18,
 106     PT_F19,
 107     PT_F20,
 108     PT_F21,
 109     PT_F22,
 110     PT_F23,
 111     PT_F24,
 112     PT_F25,
 113     PT_F26,
 114     PT_F27,
 115     PT_F28,
 116     PT_F29,
 117     PT_F30,
 118     PT_F31,
 119     PT_F32,
 120     PT_F33,
 121     PT_F34,
 122     PT_F35,
 123     PT_F36,
 124     PT_F37,
 125     PT_F38,
 126     PT_F39,
 127     PT_F40,
 128     PT_F41,
 129     PT_F42,
 130     PT_F43,
 131     PT_F44,
 132     PT_F45,
 133     PT_F46,
 134     PT_F47,
 135     PT_F48,
 136     PT_F49,
 137     PT_F50,
 138     PT_F51,
 139     PT_F52,
 140     PT_F53,
 141     PT_F54,
 142     PT_F55,
 143     PT_F56,
 144     PT_F57,
 145     PT_F58,
 146     PT_F59,
 147     PT_F60,
 148     PT_F61,
 149     PT_F62,
 150     PT_F63,
 151     PT_F64,
 152     PT_F65,
 153     PT_F66,
 154     PT_F67,
 155     PT_F68,
 156     PT_F69,
 157     PT_F70,
 158     PT_F71,
 159     PT_F72,
 160     PT_F73,
 161     PT_F74,
 162     PT_F75,
 163     PT_F76,
 164     PT_F77,
 165     PT_F78,
 166     PT_F79,
 167     PT_F80,
 168     PT_F81,
 169     PT_F82,
 170     PT_F83,
 171     PT_F84,
 172     PT_F85,
 173     PT_F86,
 174     PT_F87,
 175     PT_F88,
 176     PT_F89,
 177     PT_F90,
 178     PT_F91,
 179     PT_F92,
 180     PT_F93,
 181     PT_F94,
 182     PT_F95,
 183     PT_F96,
 184     PT_F97,
 185     PT_F98,
 186     PT_F99,
 187     PT_F100,
 188     PT_F101,
 189     PT_F102,
 190     PT_F103,
 191     PT_F104,
 192     PT_F105,
 193     PT_F106,
 194     PT_F107,
 195     PT_F108,
 196     PT_F109,
 197     PT_F110,
 198     PT_F111,
 199     PT_F112,
 200     PT_F113,
 201     PT_F114,
 202     PT_F115,
 203     PT_F116,
 204     PT_F117,
 205     PT_F118,
 206     PT_F119,
 207     PT_F120,
 208     PT_F121,
 209     PT_F122,
 210     PT_F123,
 211     PT_F124,
 212     PT_F125,
 213     PT_F126,
 214     PT_F127,
 215     /* predicate registers - we don't fetch these individually */
 216     -1, -1, -1, -1, -1, -1, -1, -1,
 217     -1, -1, -1, -1, -1, -1, -1, -1,
 218     -1, -1, -1, -1, -1, -1, -1, -1,
 219     -1, -1, -1, -1, -1, -1, -1, -1,
 220     -1, -1, -1, -1, -1, -1, -1, -1,
 221     -1, -1, -1, -1, -1, -1, -1, -1,
 222     -1, -1, -1, -1, -1, -1, -1, -1,
 223     -1, -1, -1, -1, -1, -1, -1, -1,
 224     /* branch registers */
 225     PT_B0,
 226     PT_B1,
 227     PT_B2,
 228     PT_B3,
 229     PT_B4,
 230     PT_B5,
 231     PT_B6,
 232     PT_B7,
 233     /* virtual frame pointer and virtual return address pointer */
 234     -1, -1,
 235     /* other registers */
 236     PT_PR,
 237     PT_CR_IIP,  /* ip */
 238     PT_CR_IPSR, /* psr */
 239     PT_CFM,     /* cfm */
 240     /* kernel registers not visible via ptrace interface (?) */
 241     -1, -1, -1, -1, -1, -1, -1, -1,
 242     /* hole */
 243     -1, -1, -1, -1, -1, -1, -1, -1,
 244     PT_AR_RSC,
 245     PT_AR_BSP,
 246     PT_AR_BSPSTORE,
 247     PT_AR_RNAT,
 248     -1,
 249     -1,         /* Not available: FCR, IA32 floating control register */
 250     -1, -1,
 251     -1,         /* Not available: EFLAG */
 252     -1,         /* Not available: CSD */
 253     -1,         /* Not available: SSD */
 254     -1,         /* Not available: CFLG */
 255     -1,         /* Not available: FSR */
 256     -1,         /* Not available: FIR */
 257     -1,         /* Not available: FDR */
 258     -1,
 259     PT_AR_CCV,
 260     -1, -1, -1,
 261     PT_AR_UNAT,
 262     -1, -1, -1,
 263     PT_AR_FPSR,
 264     -1, -1, -1,
 265     -1,         /* Not available: ITC */
 266     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 267     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 268     PT_AR_PFS,
 269     PT_AR_LC,
 270     -1,         /* Not available: EC, the Epilog Count register */
 271     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 272     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 273     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 274     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 275     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 276     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 277     -1,
 278     /* nat bits - not fetched directly; instead we obtain these bits from
 279        either rnat or unat or from memory. */
 280     -1, -1, -1, -1, -1, -1, -1, -1,
 281     -1, -1, -1, -1, -1, -1, -1, -1,
 282     -1, -1, -1, -1, -1, -1, -1, -1,
 283     -1, -1, -1, -1, -1, -1, -1, -1,
 284     -1, -1, -1, -1, -1, -1, -1, -1,
 285     -1, -1, -1, -1, -1, -1, -1, -1,
 286     -1, -1, -1, -1, -1, -1, -1, -1,
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296   };
 297
 298 CORE_ADDR
 299 register_addr (regno, blockend)
 300      int regno;
 301      CORE_ADDR blockend;
 302 {
 303   CORE_ADDR addr;
 304
 305   if (regno < 0 || regno >= NUM_REGS)
 306     error ("Invalid register number %d.", regno);
 307
 308   if (u_offsets[regno] == -1)
 309     addr = 0;
 310   else
 311     addr = (CORE_ADDR) u_offsets[regno];
 312
 313   return addr;
 314 }
 315
 316 int ia64_cannot_fetch_register (regno)
 317      int regno;
 318 {
 319   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
 320 }
 321
 322 int ia64_cannot_store_register (regno)
 323      int regno;
 324 {
 325   /* Rationale behind not permitting stores to bspstore...
 326
 327      The IA-64 architecture provides bspstore and bsp which refer
 328      memory locations in the RSE's backing store.  bspstore is the
 329      next location which will be written when the RSE needs to write
 330      to memory.  bsp is the address at which r32 in the current frame
 331      would be found if it were written to the backing store.
 332
 333      The IA-64 architecture provides read-only access to bsp and
 334      read/write access to bspstore (but only when the RSE is in
 335      the enforced lazy mode).  It should be noted that stores
 336      to bspstore also affect the value of bsp.  Changing bspstore
 337      does not affect the number of dirty entries between bspstore
 338      and bsp, so changing bspstore by N words will also cause bsp
 339      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 340      depending upon where the NaT collection bits fall.)
 341
 342      OTOH, the linux kernel provides read/write access to bsp (and
 343      currently read/write access to bspstore as well).  But it
 344      is definitely the case that if you change one, the other
 345      will change at the same time.  It is more useful to gdb to
 346      be able to change bsp.  So in order to prevent strange and
 347      undesirable things from happening when a dummy stack frame
 348      is popped (after calling an inferior function), we allow
 349      bspstore to be read, but not written.  (Note that popping
 350      a (generic) dummy stack frame causes all registers that
 351      were previously read from the inferior process to be written
 352      back.)  */
 353
 354   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
 355          || regno == IA64_BSPSTORE_REGNUM;
 356 }
 357
 358 void
 359 supply_gregset (gregsetp)
 360      gregset_t *gregsetp;
 361 {
 362   int regi;
 363   greg_t *regp = (greg_t *) gregsetp;
 364
 365   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 366     {
 367       supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
 368     }
 369
 370   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 371      somehow... */
 372
 373   supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
 374
 375   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 376     {
 377       supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
 378     }
 379
 380   supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
 381   supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
 382   supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
 383   supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
 384   supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
 385   supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
 386   supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
 387   supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
 388   supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
 389   supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
 390   supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
 391   supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
 392   supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
 393 }
 394
 395 void
 396 fill_gregset (gregsetp, regno)
 397      gregset_t *gregsetp;
 398      int regno;
 399 {
 400   int regi;
 401   greg_t *regp = (greg_t *) gregsetp;
 402
 403 #define COPY_REG(_idx_,_regi_) \
 404   if ((regno == -1) || regno == _regi_) \
 405     memcpy (regp + _idx_, &registers[REGISTER_BYTE (_regi_)], \
 406             REGISTER_RAW_SIZE (_regi_))
 407
 408   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 409     {
 410       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 411     }
 412
 413   /* FIXME: NAT collection bits at index 32? */
 414
 415   COPY_REG (33, IA64_PR_REGNUM);
 416
 417   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 418     {
 419       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 420     }
 421
 422   COPY_REG (42, IA64_IP_REGNUM);
 423   COPY_REG (43, IA64_CFM_REGNUM);
 424   COPY_REG (44, IA64_PSR_REGNUM);
 425   COPY_REG (45, IA64_RSC_REGNUM);
 426   COPY_REG (46, IA64_BSP_REGNUM);
 427   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 428   COPY_REG (48, IA64_RNAT_REGNUM);
 429   COPY_REG (49, IA64_CCV_REGNUM);
 430   COPY_REG (50, IA64_UNAT_REGNUM);
 431   COPY_REG (51, IA64_FPSR_REGNUM);
 432   COPY_REG (52, IA64_PFS_REGNUM);
 433   COPY_REG (53, IA64_LC_REGNUM);
 434   COPY_REG (54, IA64_EC_REGNUM);
 435 }
 436
 437 /*  Given a pointer to a floating point register set in /proc format
 438    (fpregset_t *), unpack the register contents and supply them as gdb's
 439    idea of the current floating point register values. */
 440
 441 void
 442 supply_fpregset (fpregsetp)
 443      fpregset_t *fpregsetp;
 444 {
 445   register int regi;
 446   char *from;
 447
 448   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 449     {
 450       from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 451       supply_register (regi, from);
 452     }
 453 }
 454
 455 /*  Given a pointer to a floating point register set in /proc format
 456    (fpregset_t *), update the register specified by REGNO from gdb's idea
 457    of the current floating point register set.  If REGNO is -1, update
 458    them all. */
 459
 460 void
 461 fill_fpregset (fpregsetp, regno)
 462      fpregset_t *fpregsetp;
 463      int regno;
 464 {
 465   int regi;
 466   char *to;
 467   char *from;
 468
 469   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 470     {
 471       if ((regno == -1) || (regno == regi))
 472         {
 473           from = (char *) &registers[REGISTER_BYTE (regi)];
 474           to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 475           memcpy (to, from, REGISTER_RAW_SIZE (regi));
 476         }
 477     }
 478 }
 479
 480 #define IA64_PSR_DB (1UL << 24)
 481 #define IA64_PSR_DD (1UL << 39)
 482
 483 static void
 484 enable_watchpoints_in_psr (int pid)
 485 {
 486   CORE_ADDR psr;
 487
 488   psr = read_register_pid (IA64_PSR_REGNUM, pid);
 489   if (!(psr & IA64_PSR_DB))
 490     {
 491       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 492                                    watchpoints and breakpoints. */
 493       write_register_pid (IA64_PSR_REGNUM, psr, pid);
 494     }
 495 }
 496
 497 static long
 498 fetch_debug_register (int pid, int idx)
 499 {
 500   long val;
 501   int tid;
 502
 503   tid = TIDGET(pid);
 504   if (tid == 0)
 505     tid = pid;
 506
 507   val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);
 508
 509   return val;
 510 }
 511
 512 static void
 513 store_debug_register (int pid, int idx, long val)
 514 {
 515   int tid;
 516
 517   tid = TIDGET(pid);
 518   if (tid == 0)
 519     tid = pid;
 520
 521   (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
 522 }
 523
 524 static void
 525 fetch_debug_register_pair (int pid, int idx, long *dbr_addr, long *dbr_mask)
 526 {
 527   if (dbr_addr)
 528     *dbr_addr = fetch_debug_register (pid, 2 * idx);
 529   if (dbr_mask)
 530     *dbr_mask = fetch_debug_register (pid, 2 * idx + 1);
 531 }
 532
 533 static void
 534 store_debug_register_pair (int pid, int idx, long *dbr_addr, long *dbr_mask)
 535 {
 536   if (dbr_addr)
 537     store_debug_register (pid, 2 * idx, *dbr_addr);
 538   if (dbr_mask)
 539     store_debug_register (pid, 2 * idx + 1, *dbr_mask);
 540 }
 541
 542 static int
 543 is_power_of_2 (int val)
 544 {
 545   int i, onecount;
 546
 547   onecount = 0;
 548   for (i = 0; i < 8 * sizeof (val); i++)
 549     if (val & (1 << i))
 550       onecount++;
 551
 552   return onecount <= 1;
 553 }
 554
 555 int
 556 ia64_linux_insert_watchpoint (int pid, CORE_ADDR addr, int len, int rw)
 557 {
 558   int idx;
 559   long dbr_addr, dbr_mask;
 560   int max_watchpoints = 4;
 561
 562   if (len <= 0 || !is_power_of_2 (len))
 563     return -1;
 564
 565   for (idx = 0; idx < max_watchpoints; idx++)
 566     {
 567       fetch_debug_register_pair (pid, idx, NULL, &dbr_mask);
 568       if ((dbr_mask & (0x3UL << 62)) == 0)
 569         {
 570           /* Exit loop if both r and w bits clear */
 571           break;
 572         }
 573     }
 574
 575   if (idx == max_watchpoints)
 576     return -1;
 577
 578   dbr_addr = (long) addr;
 579   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 580   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 581   switch (rw)
 582     {
 583     case hw_write:
 584       dbr_mask |= (1L << 62);                   /* Set w bit */
 585       break;
 586     case hw_read:
 587       dbr_mask |= (1L << 63);                   /* Set r bit */
 588       break;
 589     case hw_access:
 590       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 591       break;
 592     default:
 593       return -1;
 594     }
 595
 596   store_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask);
 597   enable_watchpoints_in_psr (pid);
 598
 599   return 0;
 600 }
 601
 602 int
 603 ia64_linux_remove_watchpoint (int pid, CORE_ADDR addr, int len)
 604 {
 605   int idx;
 606   long dbr_addr, dbr_mask;
 607   int max_watchpoints = 4;
 608
 609   if (len <= 0 || !is_power_of_2 (len))
 610     return -1;
 611
 612   for (idx = 0; idx < max_watchpoints; idx++)
 613     {
 614       fetch_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask);
 615       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 616         {
 617           dbr_addr = 0;
 618           dbr_mask = 0;
 619           store_debug_register_pair (pid, idx, &dbr_addr, &dbr_mask);
 620           return 0;
 621         }
 622     }
 623   return -1;
 624 }
 625
 626 CORE_ADDR
 627 ia64_linux_stopped_by_watchpoint (int pid)
 628 {
 629   CORE_ADDR psr;
 630   int tid;
 631   struct siginfo siginfo;
 632
 633   tid = TIDGET(pid);
 634   if (tid == 0)
 635     tid = pid;
 636
 637   errno = 0;
 638   ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);
 639
 640   if (errno != 0 || siginfo.si_code != 4 /* TRAP_HWBKPT */)
 641     return 0;
 642
 643   psr = read_register_pid (IA64_PSR_REGNUM, pid);
 644   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 645                            for the next instruction */
 646   write_register_pid (IA64_PSR_REGNUM, psr, pid);
 647
 648   return (CORE_ADDR) siginfo.si_addr;
 649 }