gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999-2018 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "target.h"
  24 #include "gdbcore.h"
  25 #include "regcache.h"
  26 #include "ia64-tdep.h"
  27 #include "linux-nat.h"
  28
  29 #include <signal.h>
  30 #include "nat/gdb_ptrace.h"
  31 #include "gdb_wait.h"
  32 #ifdef HAVE_SYS_REG_H
  33 #include <sys/reg.h>
  34 #endif
  35 #include <sys/syscall.h>
  36 #include <sys/user.h>
  37
  38 #include <asm/ptrace_offsets.h>
  39 #include <sys/procfs.h>
  40
  41 /* Prototypes for supply_gregset etc.  */
  42 #include "gregset.h"
  43
  44 #include "inf-ptrace.h"
  45
  46 class ia64_linux_nat_target final : public linux_nat_target
  47 {
  48 public:
  49   /* Add our register access methods.  */
  50   void fetch_registers (struct regcache *, int) override;
  51   void store_registers (struct regcache *, int) override;
  52
  53   enum target_xfer_status xfer_partial (enum target_object object,
  54                                         const char *annex,
  55                                         gdb_byte *readbuf,
  56                                         const gdb_byte *writebuf,
  57                                         ULONGEST offset, ULONGEST len,
  58                                         ULONGEST *xfered_len) override;
  59
  60   const struct target_desc *read_description () override;
  61
  62   /* Override watchpoint routines.  */
  63
  64   /* The IA-64 architecture can step over a watch point (without
  65      triggering it again) if the "dd" (data debug fault disable) bit
  66      in the processor status word is set.
  67
  68      This PSR bit is set in
  69      ia64_linux_nat_target::stopped_by_watchpoint when the code there
  70      has determined that a hardware watchpoint has indeed been hit.
  71      The CPU will then be able to execute one instruction without
  72      triggering a watchpoint.  */
  73   bool have_steppable_watchpoint () { return 1; }
  74
  75   int can_use_hw_breakpoint (enum bptype, int, int) override;
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78   int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  79                          struct expression *) override;
  80   int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  81                          struct expression *) override;
  82 };
  83
  84 static ia64_linux_nat_target the_ia64_linux_nat_target;
  85
  86 /* These must match the order of the register names.
  87
  88    Some sort of lookup table is needed because the offsets associated
  89    with the registers are all over the board.  */
  90
  91 static int u_offsets[] =
  92   {
  93     /* general registers */
  94     -1,         /* gr0 not available; i.e, it's always zero.  */
  95     PT_R1,
  96     PT_R2,
  97     PT_R3,
  98     PT_R4,
  99     PT_R5,
 100     PT_R6,
 101     PT_R7,
 102     PT_R8,
 103     PT_R9,
 104     PT_R10,
 105     PT_R11,
 106     PT_R12,
 107     PT_R13,
 108     PT_R14,
 109     PT_R15,
 110     PT_R16,
 111     PT_R17,
 112     PT_R18,
 113     PT_R19,
 114     PT_R20,
 115     PT_R21,
 116     PT_R22,
 117     PT_R23,
 118     PT_R24,
 119     PT_R25,
 120     PT_R26,
 121     PT_R27,
 122     PT_R28,
 123     PT_R29,
 124     PT_R30,
 125     PT_R31,
 126     /* gr32 through gr127 not directly available via the ptrace interface.  */
 127     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 128     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 129     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 130     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 131     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 132     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 133     /* Floating point registers */
 134     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0).  */
 135     PT_F2,
 136     PT_F3,
 137     PT_F4,
 138     PT_F5,
 139     PT_F6,
 140     PT_F7,
 141     PT_F8,
 142     PT_F9,
 143     PT_F10,
 144     PT_F11,
 145     PT_F12,
 146     PT_F13,
 147     PT_F14,
 148     PT_F15,
 149     PT_F16,
 150     PT_F17,
 151     PT_F18,
 152     PT_F19,
 153     PT_F20,
 154     PT_F21,
 155     PT_F22,
 156     PT_F23,
 157     PT_F24,
 158     PT_F25,
 159     PT_F26,
 160     PT_F27,
 161     PT_F28,
 162     PT_F29,
 163     PT_F30,
 164     PT_F31,
 165     PT_F32,
 166     PT_F33,
 167     PT_F34,
 168     PT_F35,
 169     PT_F36,
 170     PT_F37,
 171     PT_F38,
 172     PT_F39,
 173     PT_F40,
 174     PT_F41,
 175     PT_F42,
 176     PT_F43,
 177     PT_F44,
 178     PT_F45,
 179     PT_F46,
 180     PT_F47,
 181     PT_F48,
 182     PT_F49,
 183     PT_F50,
 184     PT_F51,
 185     PT_F52,
 186     PT_F53,
 187     PT_F54,
 188     PT_F55,
 189     PT_F56,
 190     PT_F57,
 191     PT_F58,
 192     PT_F59,
 193     PT_F60,
 194     PT_F61,
 195     PT_F62,
 196     PT_F63,
 197     PT_F64,
 198     PT_F65,
 199     PT_F66,
 200     PT_F67,
 201     PT_F68,
 202     PT_F69,
 203     PT_F70,
 204     PT_F71,
 205     PT_F72,
 206     PT_F73,
 207     PT_F74,
 208     PT_F75,
 209     PT_F76,
 210     PT_F77,
 211     PT_F78,
 212     PT_F79,
 213     PT_F80,
 214     PT_F81,
 215     PT_F82,
 216     PT_F83,
 217     PT_F84,
 218     PT_F85,
 219     PT_F86,
 220     PT_F87,
 221     PT_F88,
 222     PT_F89,
 223     PT_F90,
 224     PT_F91,
 225     PT_F92,
 226     PT_F93,
 227     PT_F94,
 228     PT_F95,
 229     PT_F96,
 230     PT_F97,
 231     PT_F98,
 232     PT_F99,
 233     PT_F100,
 234     PT_F101,
 235     PT_F102,
 236     PT_F103,
 237     PT_F104,
 238     PT_F105,
 239     PT_F106,
 240     PT_F107,
 241     PT_F108,
 242     PT_F109,
 243     PT_F110,
 244     PT_F111,
 245     PT_F112,
 246     PT_F113,
 247     PT_F114,
 248     PT_F115,
 249     PT_F116,
 250     PT_F117,
 251     PT_F118,
 252     PT_F119,
 253     PT_F120,
 254     PT_F121,
 255     PT_F122,
 256     PT_F123,
 257     PT_F124,
 258     PT_F125,
 259     PT_F126,
 260     PT_F127,
 261     /* Predicate registers - we don't fetch these individually.  */
 262     -1, -1, -1, -1, -1, -1, -1, -1,
 263     -1, -1, -1, -1, -1, -1, -1, -1,
 264     -1, -1, -1, -1, -1, -1, -1, -1,
 265     -1, -1, -1, -1, -1, -1, -1, -1,
 266     -1, -1, -1, -1, -1, -1, -1, -1,
 267     -1, -1, -1, -1, -1, -1, -1, -1,
 268     -1, -1, -1, -1, -1, -1, -1, -1,
 269     -1, -1, -1, -1, -1, -1, -1, -1,
 270     /* branch registers */
 271     PT_B0,
 272     PT_B1,
 273     PT_B2,
 274     PT_B3,
 275     PT_B4,
 276     PT_B5,
 277     PT_B6,
 278     PT_B7,
 279     /* Virtual frame pointer and virtual return address pointer.  */
 280     -1, -1,
 281     /* other registers */
 282     PT_PR,
 283     PT_CR_IIP,  /* ip */
 284     PT_CR_IPSR, /* psr */
 285     PT_CFM,     /* cfm */
 286     /* kernel registers not visible via ptrace interface (?)  */
 287     -1, -1, -1, -1, -1, -1, -1, -1,
 288     /* hole */
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     PT_AR_RSC,
 291     PT_AR_BSP,
 292     PT_AR_BSPSTORE,
 293     PT_AR_RNAT,
 294     -1,
 295     -1,         /* Not available: FCR, IA32 floating control register.  */
 296     -1, -1,
 297     -1,         /* Not available: EFLAG */
 298     -1,         /* Not available: CSD */
 299     -1,         /* Not available: SSD */
 300     -1,         /* Not available: CFLG */
 301     -1,         /* Not available: FSR */
 302     -1,         /* Not available: FIR */
 303     -1,         /* Not available: FDR */
 304     -1,
 305     PT_AR_CCV,
 306     -1, -1, -1,
 307     PT_AR_UNAT,
 308     -1, -1, -1,
 309     PT_AR_FPSR,
 310     -1, -1, -1,
 311     -1,         /* Not available: ITC */
 312     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 313     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 314     PT_AR_PFS,
 315     PT_AR_LC,
 316     PT_AR_EC,
 317     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 318     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 319     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 320     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 321     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 322     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 323     -1,
 324     /* nat bits - not fetched directly; instead we obtain these bits from
 325        either rnat or unat or from memory.  */
 326     -1, -1, -1, -1, -1, -1, -1, -1,
 327     -1, -1, -1, -1, -1, -1, -1, -1,
 328     -1, -1, -1, -1, -1, -1, -1, -1,
 329     -1, -1, -1, -1, -1, -1, -1, -1,
 330     -1, -1, -1, -1, -1, -1, -1, -1,
 331     -1, -1, -1, -1, -1, -1, -1, -1,
 332     -1, -1, -1, -1, -1, -1, -1, -1,
 333     -1, -1, -1, -1, -1, -1, -1, -1,
 334     -1, -1, -1, -1, -1, -1, -1, -1,
 335     -1, -1, -1, -1, -1, -1, -1, -1,
 336     -1, -1, -1, -1, -1, -1, -1, -1,
 337     -1, -1, -1, -1, -1, -1, -1, -1,
 338     -1, -1, -1, -1, -1, -1, -1, -1,
 339     -1, -1, -1, -1, -1, -1, -1, -1,
 340     -1, -1, -1, -1, -1, -1, -1, -1,
 341     -1, -1, -1, -1, -1, -1, -1, -1,
 342   };
 343
 344 static CORE_ADDR
 345 ia64_register_addr (struct gdbarch *gdbarch, int regno)
 346 {
 347   CORE_ADDR addr;
 348
 349   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 350     error (_("Invalid register number %d."), regno);
 351
 352   if (u_offsets[regno] == -1)
 353     addr = 0;
 354   else
 355     addr = (CORE_ADDR) u_offsets[regno];
 356
 357   return addr;
 358 }
 359
 360 static int
 361 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
 362 {
 363   return regno < 0
 364          || regno >= gdbarch_num_regs (gdbarch)
 365          || u_offsets[regno] == -1;
 366 }
 367
 368 static int
 369 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
 370 {
 371   /* Rationale behind not permitting stores to bspstore...
 372
 373      The IA-64 architecture provides bspstore and bsp which refer
 374      memory locations in the RSE's backing store.  bspstore is the
 375      next location which will be written when the RSE needs to write
 376      to memory.  bsp is the address at which r32 in the current frame
 377      would be found if it were written to the backing store.
 378
 379      The IA-64 architecture provides read-only access to bsp and
 380      read/write access to bspstore (but only when the RSE is in
 381      the enforced lazy mode).  It should be noted that stores
 382      to bspstore also affect the value of bsp.  Changing bspstore
 383      does not affect the number of dirty entries between bspstore
 384      and bsp, so changing bspstore by N words will also cause bsp
 385      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 386      depending upon where the NaT collection bits fall.)
 387
 388      OTOH, the Linux kernel provides read/write access to bsp (and
 389      currently read/write access to bspstore as well).  But it
 390      is definitely the case that if you change one, the other
 391      will change at the same time.  It is more useful to gdb to
 392      be able to change bsp.  So in order to prevent strange and
 393      undesirable things from happening when a dummy stack frame
 394      is popped (after calling an inferior function), we allow
 395      bspstore to be read, but not written.  (Note that popping
 396      a (generic) dummy stack frame causes all registers that
 397      were previously read from the inferior process to be written
 398      back.)  */
 399
 400   return regno < 0
 401          || regno >= gdbarch_num_regs (gdbarch)
 402          || u_offsets[regno] == -1
 403          || regno == IA64_BSPSTORE_REGNUM;
 404 }
 405
 406 void
 407 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
 408 {
 409   int regi;
 410   const greg_t *regp = (const greg_t *) gregsetp;
 411
 412   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 413     {
 414       regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
 415     }
 416
 417   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 418      somehow...  */
 419
 420   regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
 421
 422   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 423     {
 424       regcache_raw_supply (regcache, regi,
 425                            regp + 34 + (regi - IA64_BR0_REGNUM));
 426     }
 427
 428   regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
 429   regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
 430   regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
 431   regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
 432   regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
 433   regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
 434   regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
 435   regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
 436   regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
 437   regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
 438   regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
 439   regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
 440   regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
 441 }
 442
 443 void
 444 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
 445 {
 446   int regi;
 447   greg_t *regp = (greg_t *) gregsetp;
 448
 449 #define COPY_REG(_idx_,_regi_) \
 450   if ((regno == -1) || regno == _regi_) \
 451     regcache_raw_collect (regcache, _regi_, regp + _idx_)
 452
 453   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 454     {
 455       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 456     }
 457
 458   /* FIXME: NAT collection bits at index 32?  */
 459
 460   COPY_REG (33, IA64_PR_REGNUM);
 461
 462   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 463     {
 464       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 465     }
 466
 467   COPY_REG (42, IA64_IP_REGNUM);
 468   COPY_REG (43, IA64_CFM_REGNUM);
 469   COPY_REG (44, IA64_PSR_REGNUM);
 470   COPY_REG (45, IA64_RSC_REGNUM);
 471   COPY_REG (46, IA64_BSP_REGNUM);
 472   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 473   COPY_REG (48, IA64_RNAT_REGNUM);
 474   COPY_REG (49, IA64_CCV_REGNUM);
 475   COPY_REG (50, IA64_UNAT_REGNUM);
 476   COPY_REG (51, IA64_FPSR_REGNUM);
 477   COPY_REG (52, IA64_PFS_REGNUM);
 478   COPY_REG (53, IA64_LC_REGNUM);
 479   COPY_REG (54, IA64_EC_REGNUM);
 480 }
 481
 482 /*  Given a pointer to a floating point register set in /proc format
 483    (fpregset_t *), unpack the register contents and supply them as gdb's
 484    idea of the current floating point register values.  */
 485
 486 void
 487 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
 488 {
 489   int regi;
 490   const char *from;
 491   const gdb_byte f_zero[16] = { 0 };
 492   const gdb_byte f_one[16] =
 493     { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 494
 495   /* Kernel generated cores have fr1==0 instead of 1.0.  Older GDBs
 496      did the same.  So ignore whatever might be recorded in fpregset_t
 497      for fr0/fr1 and always supply their expected values.  */
 498
 499   /* fr0 is always read as zero.  */
 500   regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero);
 501   /* fr1 is always read as one (1.0).  */
 502   regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one);
 503
 504   for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 505     {
 506       from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 507       regcache_raw_supply (regcache, regi, from);
 508     }
 509 }
 510
 511 /*  Given a pointer to a floating point register set in /proc format
 512    (fpregset_t *), update the register specified by REGNO from gdb's idea
 513    of the current floating point register set.  If REGNO is -1, update
 514    them all.  */
 515
 516 void
 517 fill_fpregset (const struct regcache *regcache,
 518                fpregset_t *fpregsetp, int regno)
 519 {
 520   int regi;
 521
 522   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 523     {
 524       if ((regno == -1) || (regno == regi))
 525         regcache_raw_collect (regcache, regi,
 526                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 527     }
 528 }
 529
 530 #define IA64_PSR_DB (1UL << 24)
 531 #define IA64_PSR_DD (1UL << 39)
 532
 533 static void
 534 enable_watchpoints_in_psr (ptid_t ptid)
 535 {
 536   struct regcache *regcache = get_thread_regcache (ptid);
 537   ULONGEST psr;
 538
 539   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 540   if (!(psr & IA64_PSR_DB))
 541     {
 542       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 543                                    watchpoints and breakpoints.  */
 544       regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 545     }
 546 }
 547
 548 static long debug_registers[8];
 549
 550 static void
 551 store_debug_register (ptid_t ptid, int idx, long val)
 552 {
 553   int tid;
 554
 555   tid = ptid_get_lwp (ptid);
 556   if (tid == 0)
 557     tid = ptid_get_pid (ptid);
 558
 559   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 560 }
 561
 562 static void
 563 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
 564                            long *dbr_mask)
 565 {
 566   if (dbr_addr)
 567     store_debug_register (ptid, 2 * idx, *dbr_addr);
 568   if (dbr_mask)
 569     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 570 }
 571
 572 static int
 573 is_power_of_2 (int val)
 574 {
 575   int i, onecount;
 576
 577   onecount = 0;
 578   for (i = 0; i < 8 * sizeof (val); i++)
 579     if (val & (1 << i))
 580       onecount++;
 581
 582   return onecount <= 1;
 583 }
 584
 585 int
 586 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
 587                                           enum target_hw_bp_type type,
 588                                           struct expression *cond)
 589 {
 590   struct lwp_info *lp;
 591   int idx;
 592   long dbr_addr, dbr_mask;
 593   int max_watchpoints = 4;
 594
 595   if (len <= 0 || !is_power_of_2 (len))
 596     return -1;
 597
 598   for (idx = 0; idx < max_watchpoints; idx++)
 599     {
 600       dbr_mask = debug_registers[idx * 2 + 1];
 601       if ((dbr_mask & (0x3UL << 62)) == 0)
 602         {
 603           /* Exit loop if both r and w bits clear.  */
 604           break;
 605         }
 606     }
 607
 608   if (idx == max_watchpoints)
 609     return -1;
 610
 611   dbr_addr = (long) addr;
 612   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 613   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 614   switch (type)
 615     {
 616     case hw_write:
 617       dbr_mask |= (1L << 62);                   /* Set w bit */
 618       break;
 619     case hw_read:
 620       dbr_mask |= (1L << 63);                   /* Set r bit */
 621       break;
 622     case hw_access:
 623       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 624       break;
 625     default:
 626       return -1;
 627     }
 628
 629   debug_registers[2 * idx] = dbr_addr;
 630   debug_registers[2 * idx + 1] = dbr_mask;
 631   ALL_LWPS (lp)
 632     {
 633       store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 634       enable_watchpoints_in_psr (lp->ptid);
 635     }
 636
 637   return 0;
 638 }
 639
 640 int
 641 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
 642                                           enum target_hw_bp_type type,
 643                                           struct expression *cond)
 644 {
 645   int idx;
 646   long dbr_addr, dbr_mask;
 647   int max_watchpoints = 4;
 648
 649   if (len <= 0 || !is_power_of_2 (len))
 650     return -1;
 651
 652   for (idx = 0; idx < max_watchpoints; idx++)
 653     {
 654       dbr_addr = debug_registers[2 * idx];
 655       dbr_mask = debug_registers[2 * idx + 1];
 656       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 657         {
 658           struct lwp_info *lp;
 659
 660           debug_registers[2 * idx] = 0;
 661           debug_registers[2 * idx + 1] = 0;
 662           dbr_addr = 0;
 663           dbr_mask = 0;
 664
 665           ALL_LWPS (lp)
 666             store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 667
 668           return 0;
 669         }
 670     }
 671   return -1;
 672 }
 673
 674 static void
 675 ia64_linux_new_thread (struct lwp_info *lp)
 676 {
 677   int i, any;
 678
 679   any = 0;
 680   for (i = 0; i < 8; i++)
 681     {
 682       if (debug_registers[i] != 0)
 683         any = 1;
 684       store_debug_register (lp->ptid, i, debug_registers[i]);
 685     }
 686
 687   if (any)
 688     enable_watchpoints_in_psr (lp->ptid);
 689 }
 690
 691 bool
 692 ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 693 {
 694   CORE_ADDR psr;
 695   siginfo_t siginfo;
 696   struct regcache *regcache = get_current_regcache ();
 697
 698   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 699     return false;
 700
 701   if (siginfo.si_signo != SIGTRAP
 702       || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 703     return false;
 704
 705   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 706   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 707                            for the next instruction.  */
 708   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 709
 710   *addr_p = (CORE_ADDR) siginfo.si_addr;
 711   return true;
 712 }
 713
 714 bool
 715 ia64_linux_nat_target::stopped_by_watchpoint ()
 716 {
 717   CORE_ADDR addr;
 718   return stopped_data_address (&addr);
 719 }
 720
 721 static int
 722 ia64_linux_can_use_hw_breakpoint (struct target_ops *self,
 723                                   enum bptype type,
 724                                   int cnt, int othertype)
 725 {
 726   return 1;
 727 }
 728
 729
 730 /* Fetch register REGNUM from the inferior.  */
 731
 732 static void
 733 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
 734 {
 735   struct gdbarch *gdbarch = regcache->arch ();
 736   CORE_ADDR addr;
 737   size_t size;
 738   PTRACE_TYPE_RET *buf;
 739   pid_t pid;
 740   int i;
 741
 742   /* r0 cannot be fetched but is always zero.  */
 743   if (regnum == IA64_GR0_REGNUM)
 744     {
 745       const gdb_byte zero[8] = { 0 };
 746
 747       gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
 748       regcache_raw_supply (regcache, regnum, zero);
 749       return;
 750     }
 751
 752   /* fr0 cannot be fetched but is always zero.  */
 753   if (regnum == IA64_FR0_REGNUM)
 754     {
 755       const gdb_byte f_zero[16] = { 0 };
 756
 757       gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
 758       regcache_raw_supply (regcache, regnum, f_zero);
 759       return;
 760     }
 761
 762   /* fr1 cannot be fetched but is always one (1.0).  */
 763   if (regnum == IA64_FR1_REGNUM)
 764     {
 765       const gdb_byte f_one[16] =
 766         { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 767
 768       gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
 769       regcache_raw_supply (regcache, regnum, f_one);
 770       return;
 771     }
 772
 773   if (ia64_cannot_fetch_register (gdbarch, regnum))
 774     {
 775       regcache_raw_supply (regcache, regnum, NULL);
 776       return;
 777     }
 778
 779   pid = get_ptrace_pid (regcache_get_ptid (regcache));
 780
 781   /* This isn't really an address, but ptrace thinks of it as one.  */
 782   addr = ia64_register_addr (gdbarch, regnum);
 783   size = register_size (gdbarch, regnum);
 784
 785   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 786   buf = (PTRACE_TYPE_RET *) alloca (size);
 787
 788   /* Read the register contents from the inferior a chunk at a time.  */
 789   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 790     {
 791       errno = 0;
 792       buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
 793       if (errno != 0)
 794         error (_("Couldn't read register %s (#%d): %s."),
 795                gdbarch_register_name (gdbarch, regnum),
 796                regnum, safe_strerror (errno));
 797
 798       addr += sizeof (PTRACE_TYPE_RET);
 799     }
 800   regcache_raw_supply (regcache, regnum, buf);
 801 }
 802
 803 /* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
 804    for all registers.  */
 805
 806 void
 807 ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 808 {
 809   if (regnum == -1)
 810     for (regnum = 0;
 811          regnum < gdbarch_num_regs (regcache->arch ());
 812          regnum++)
 813       ia64_linux_fetch_register (regcache, regnum);
 814   else
 815     ia64_linux_fetch_register (regcache, regnum);
 816 }
 817
 818 /* Store register REGNUM into the inferior.  */
 819
 820 static void
 821 ia64_linux_store_register (const struct regcache *regcache, int regnum)
 822 {
 823   struct gdbarch *gdbarch = regcache->arch ();
 824   CORE_ADDR addr;
 825   size_t size;
 826   PTRACE_TYPE_RET *buf;
 827   pid_t pid;
 828   int i;
 829
 830   if (ia64_cannot_store_register (gdbarch, regnum))
 831     return;
 832
 833   pid = get_ptrace_pid (regcache_get_ptid (regcache));
 834
 835   /* This isn't really an address, but ptrace thinks of it as one.  */
 836   addr = ia64_register_addr (gdbarch, regnum);
 837   size = register_size (gdbarch, regnum);
 838
 839   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 840   buf = (PTRACE_TYPE_RET *) alloca (size);
 841
 842   /* Write the register contents into the inferior a chunk at a time.  */
 843   regcache_raw_collect (regcache, regnum, buf);
 844   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 845     {
 846       errno = 0;
 847       ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
 848       if (errno != 0)
 849         error (_("Couldn't write register %s (#%d): %s."),
 850                gdbarch_register_name (gdbarch, regnum),
 851                regnum, safe_strerror (errno));
 852
 853       addr += sizeof (PTRACE_TYPE_RET);
 854     }
 855 }
 856
 857 /* Store register REGNUM back into the inferior.  If REGNUM is -1, do
 858    this for all registers.  */
 859
 860 void
 861 ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 862 {
 863   if (regnum == -1)
 864     for (regnum = 0;
 865          regnum < gdbarch_num_regs (regcache->arch ());
 866          regnum++)
 867       ia64_linux_store_register (regcache, regnum);
 868   else
 869     ia64_linux_store_register (regcache, regnum);
 870 }
 871
 872 /* Implement the xfer_partial target_ops method.  */
 873
 874 enum target_xfer_status
 875 ia64_linux_nat_target::xfer_partial (enum target_object object,
 876                                      const char *annex,
 877                                      gdb_byte *readbuf, const gdb_byte *writebuf,
 878                                      ULONGEST offset, ULONGEST len,
 879                                      ULONGEST *xfered_len)
 880 {
 881   if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
 882     {
 883       static long gate_table_size;
 884       gdb_byte *tmp_buf;
 885       long res;
 886
 887       /* Probe for the table size once.  */
 888       if (gate_table_size == 0)
 889         gate_table_size = syscall (__NR_getunwind, NULL, 0);
 890       if (gate_table_size < 0)
 891         return TARGET_XFER_E_IO;
 892
 893       if (offset >= gate_table_size)
 894         return TARGET_XFER_EOF;
 895
 896       tmp_buf = (gdb_byte *) alloca (gate_table_size);
 897       res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
 898       if (res < 0)
 899         return TARGET_XFER_E_IO;
 900       gdb_assert (res == gate_table_size);
 901
 902       if (offset + len > gate_table_size)
 903         len = gate_table_size - offset;
 904
 905       memcpy (readbuf, tmp_buf + offset, len);
 906       *xfered_len = len;
 907       return TARGET_XFER_OK;
 908     }
 909
 910   return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
 911                                          offset, len, xfered_len);
 912 }
 913
 914 /* For break.b instruction ia64 CPU forgets the immediate value and generates
 915    SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
 916    ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
 917    difference for the signals here.  */
 918
 919 static int
 920 ia64_linux_status_is_event (int status)
 921 {
 922   return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
 923                                  || WSTOPSIG (status) == SIGILL);
 924 }
 925
 926 void
 927 _initialize_ia64_linux_nat (void)
 928 {
 929   struct target_ops *t = &the_ia64_linux_nat_target;
 930
 931   /* Register the target.  */
 932   linux_target = &the_ia64_linux_nat_target;
 933   add_target (t);
 934   linux_nat_set_new_thread (t, ia64_linux_new_thread);
 935   linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
 936 }