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* frv-tdep.c (frv_register_byte): Delete.
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23 #include "inferior.h"
24 #include "symfile.h" /* for entry_point_address */
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39 #include "dis-asm.h"
40
41 /* Hook for determining the global pointer when calling functions in
42 the inferior under AIX. The initialization code in ia64-aix-nat.c
43 sets this hook to the address of a function which will find the
44 global pointer for a given address.
45
46 The generic code which uses the dynamic section in the inferior for
47 finding the global pointer is not of much use on AIX since the
48 values obtained from the inferior have not been relocated. */
49
50 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
51
52 /* An enumeration of the different IA-64 instruction types. */
53
54 typedef enum instruction_type
55 {
56 A, /* Integer ALU ; I-unit or M-unit */
57 I, /* Non-ALU integer; I-unit */
58 M, /* Memory ; M-unit */
59 F, /* Floating-point ; F-unit */
60 B, /* Branch ; B-unit */
61 L, /* Extended (L+X) ; I-unit */
62 X, /* Extended (L+X) ; I-unit */
63 undefined /* undefined or reserved */
64 } instruction_type;
65
66 /* We represent IA-64 PC addresses as the value of the instruction
67 pointer or'd with some bit combination in the low nibble which
68 represents the slot number in the bundle addressed by the
69 instruction pointer. The problem is that the Linux kernel
70 multiplies its slot numbers (for exceptions) by one while the
71 disassembler multiplies its slot numbers by 6. In addition, I've
72 heard it said that the simulator uses 1 as the multiplier.
73
74 I've fixed the disassembler so that the bytes_per_line field will
75 be the slot multiplier. If bytes_per_line comes in as zero, it
76 is set to six (which is how it was set up initially). -- objdump
77 displays pretty disassembly dumps with this value. For our purposes,
78 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
79 never want to also display the raw bytes the way objdump does. */
80
81 #define SLOT_MULTIPLIER 1
82
83 /* Length in bytes of an instruction bundle */
84
85 #define BUNDLE_LEN 16
86
87 /* FIXME: These extern declarations should go in ia64-tdep.h. */
88 extern CORE_ADDR ia64_linux_sigcontext_register_address (CORE_ADDR, int);
89 extern CORE_ADDR ia64_aix_sigcontext_register_address (CORE_ADDR, int);
90
91 static gdbarch_init_ftype ia64_gdbarch_init;
92
93 static gdbarch_register_name_ftype ia64_register_name;
94 static gdbarch_register_type_ftype ia64_register_type;
95 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
96 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
97 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
98 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
99 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
100 static struct type *is_float_or_hfa_type (struct type *t);
101
102 static struct type *builtin_type_ia64_ext;
103
104 #define NUM_IA64_RAW_REGS 462
105
106 static int sp_regnum = IA64_GR12_REGNUM;
107 static int fp_regnum = IA64_VFP_REGNUM;
108 static int lr_regnum = IA64_VRAP_REGNUM;
109
110 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
111 they may not be accessible via the ptrace register get/set interfaces. */
112 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
113 V127_REGNUM = V32_REGNUM + 95,
114 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
115
116 /* Array of register names; There should be ia64_num_regs strings in
117 the initializer. */
118
119 static char *ia64_register_names[] =
120 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136
137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
141 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
142 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
143 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
144 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
145 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
146 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
147 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
148 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
149 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
150 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
151 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
152 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
153
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162
163 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
164
165 "vfp", "vrap",
166
167 "pr", "ip", "psr", "cfm",
168
169 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
170 "", "", "", "", "", "", "", "",
171 "rsc", "bsp", "bspstore", "rnat",
172 "", "fcr", "", "",
173 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
174 "ccv", "", "", "", "unat", "", "", "",
175 "fpsr", "", "", "", "itc",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "",
178 "pfs", "lc", "ec",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "",
186 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
187 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
188 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
189 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
190 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
191 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
192 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
193 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
194 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
195 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
196 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
197 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
198 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
199 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
200 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
201 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
202
203 "bof",
204
205 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
206 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
207 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
208 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
209 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
210 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
211 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
212 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
213 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
214 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
215 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
216 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
217
218 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
219 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
220 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
221 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
222 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
223 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
224 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
225 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
226 };
227
228 struct ia64_frame_cache
229 {
230 CORE_ADDR base; /* frame pointer base for frame */
231 CORE_ADDR pc; /* function start pc for frame */
232 CORE_ADDR saved_sp; /* stack pointer for frame */
233 CORE_ADDR bsp; /* points at r32 for the current frame */
234 CORE_ADDR cfm; /* cfm value for current frame */
235 CORE_ADDR prev_cfm; /* cfm value for previous frame */
236 int frameless;
237 int sof; /* Size of frame (decoded from cfm value) */
238 int sol; /* Size of locals (decoded from cfm value) */
239 int sor; /* Number of rotating registers. (decoded from cfm value) */
240 CORE_ADDR after_prologue;
241 /* Address of first instruction after the last
242 prologue instruction; Note that there may
243 be instructions from the function's body
244 intermingled with the prologue. */
245 int mem_stack_frame_size;
246 /* Size of the memory stack frame (may be zero),
247 or -1 if it has not been determined yet. */
248 int fp_reg; /* Register number (if any) used a frame pointer
249 for this frame. 0 if no register is being used
250 as the frame pointer. */
251
252 /* Saved registers. */
253 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
254
255 };
256
257 struct gdbarch_tdep
258 {
259 int os_ident; /* From the ELF header, one of the ELFOSABI_
260 constants: ELFOSABI_LINUX, ELFOSABI_AIX,
261 etc. */
262 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
263 /* OS specific function which, given a frame address
264 and register number, returns the offset to the
265 given register from the start of the frame. */
266 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
267 };
268
269 #define SIGCONTEXT_REGISTER_ADDRESS \
270 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
271 #define FIND_GLOBAL_POINTER \
272 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
273
274 int
275 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
276 struct reggroup *group)
277 {
278 int vector_p;
279 int float_p;
280 int raw_p;
281 if (group == all_reggroup)
282 return 1;
283 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
284 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
285 raw_p = regnum < NUM_IA64_RAW_REGS;
286 if (group == float_reggroup)
287 return float_p;
288 if (group == vector_reggroup)
289 return vector_p;
290 if (group == general_reggroup)
291 return (!vector_p && !float_p);
292 if (group == save_reggroup || group == restore_reggroup)
293 return raw_p;
294 return 0;
295 }
296
297 static const char *
298 ia64_register_name (int reg)
299 {
300 return ia64_register_names[reg];
301 }
302
303 struct type *
304 ia64_register_type (struct gdbarch *arch, int reg)
305 {
306 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
307 return builtin_type_ia64_ext;
308 else
309 return builtin_type_long;
310 }
311
312 static int
313 ia64_dwarf_reg_to_regnum (int reg)
314 {
315 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
316 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
317 return reg;
318 }
319
320 static int
321 floatformat_valid (fmt, from)
322 const struct floatformat *fmt;
323 const char *from;
324 {
325 return 1;
326 }
327
328 const struct floatformat floatformat_ia64_ext =
329 {
330 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
331 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
332 };
333
334
335 /* Read the given register from a sigcontext structure in the
336 specified frame. */
337
338 static CORE_ADDR
339 read_sigcontext_register (struct frame_info *frame, int regnum)
340 {
341 CORE_ADDR regaddr;
342
343 if (frame == NULL)
344 internal_error (__FILE__, __LINE__,
345 "read_sigcontext_register: NULL frame");
346 if (!(get_frame_type (frame) == SIGTRAMP_FRAME))
347 internal_error (__FILE__, __LINE__,
348 "read_sigcontext_register: frame not a signal trampoline");
349 if (SIGCONTEXT_REGISTER_ADDRESS == 0)
350 internal_error (__FILE__, __LINE__,
351 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
352
353 regaddr = SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame), regnum);
354 if (regaddr)
355 return read_memory_integer (regaddr, register_size (current_gdbarch, regnum));
356 else
357 internal_error (__FILE__, __LINE__,
358 "read_sigcontext_register: Register %d not in struct sigcontext", regnum);
359 }
360
361 /* Extract ``len'' bits from an instruction bundle starting at
362 bit ``from''. */
363
364 static long long
365 extract_bit_field (char *bundle, int from, int len)
366 {
367 long long result = 0LL;
368 int to = from + len;
369 int from_byte = from / 8;
370 int to_byte = to / 8;
371 unsigned char *b = (unsigned char *) bundle;
372 unsigned char c;
373 int lshift;
374 int i;
375
376 c = b[from_byte];
377 if (from_byte == to_byte)
378 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
379 result = c >> (from % 8);
380 lshift = 8 - (from % 8);
381
382 for (i = from_byte+1; i < to_byte; i++)
383 {
384 result |= ((long long) b[i]) << lshift;
385 lshift += 8;
386 }
387
388 if (from_byte < to_byte && (to % 8 != 0))
389 {
390 c = b[to_byte];
391 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
392 result |= ((long long) c) << lshift;
393 }
394
395 return result;
396 }
397
398 /* Replace the specified bits in an instruction bundle */
399
400 static void
401 replace_bit_field (char *bundle, long long val, int from, int len)
402 {
403 int to = from + len;
404 int from_byte = from / 8;
405 int to_byte = to / 8;
406 unsigned char *b = (unsigned char *) bundle;
407 unsigned char c;
408
409 if (from_byte == to_byte)
410 {
411 unsigned char left, right;
412 c = b[from_byte];
413 left = (c >> (to % 8)) << (to % 8);
414 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
415 c = (unsigned char) (val & 0xff);
416 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
417 c |= right | left;
418 b[from_byte] = c;
419 }
420 else
421 {
422 int i;
423 c = b[from_byte];
424 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
425 c = c | (val << (from % 8));
426 b[from_byte] = c;
427 val >>= 8 - from % 8;
428
429 for (i = from_byte+1; i < to_byte; i++)
430 {
431 c = val & 0xff;
432 val >>= 8;
433 b[i] = c;
434 }
435
436 if (to % 8 != 0)
437 {
438 unsigned char cv = (unsigned char) val;
439 c = b[to_byte];
440 c = c >> (to % 8) << (to % 8);
441 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
442 b[to_byte] = c;
443 }
444 }
445 }
446
447 /* Return the contents of slot N (for N = 0, 1, or 2) in
448 and instruction bundle */
449
450 static long long
451 slotN_contents (char *bundle, int slotnum)
452 {
453 return extract_bit_field (bundle, 5+41*slotnum, 41);
454 }
455
456 /* Store an instruction in an instruction bundle */
457
458 static void
459 replace_slotN_contents (char *bundle, long long instr, int slotnum)
460 {
461 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
462 }
463
464 static enum instruction_type template_encoding_table[32][3] =
465 {
466 { M, I, I }, /* 00 */
467 { M, I, I }, /* 01 */
468 { M, I, I }, /* 02 */
469 { M, I, I }, /* 03 */
470 { M, L, X }, /* 04 */
471 { M, L, X }, /* 05 */
472 { undefined, undefined, undefined }, /* 06 */
473 { undefined, undefined, undefined }, /* 07 */
474 { M, M, I }, /* 08 */
475 { M, M, I }, /* 09 */
476 { M, M, I }, /* 0A */
477 { M, M, I }, /* 0B */
478 { M, F, I }, /* 0C */
479 { M, F, I }, /* 0D */
480 { M, M, F }, /* 0E */
481 { M, M, F }, /* 0F */
482 { M, I, B }, /* 10 */
483 { M, I, B }, /* 11 */
484 { M, B, B }, /* 12 */
485 { M, B, B }, /* 13 */
486 { undefined, undefined, undefined }, /* 14 */
487 { undefined, undefined, undefined }, /* 15 */
488 { B, B, B }, /* 16 */
489 { B, B, B }, /* 17 */
490 { M, M, B }, /* 18 */
491 { M, M, B }, /* 19 */
492 { undefined, undefined, undefined }, /* 1A */
493 { undefined, undefined, undefined }, /* 1B */
494 { M, F, B }, /* 1C */
495 { M, F, B }, /* 1D */
496 { undefined, undefined, undefined }, /* 1E */
497 { undefined, undefined, undefined }, /* 1F */
498 };
499
500 /* Fetch and (partially) decode an instruction at ADDR and return the
501 address of the next instruction to fetch. */
502
503 static CORE_ADDR
504 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
505 {
506 char bundle[BUNDLE_LEN];
507 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
508 long long template;
509 int val;
510
511 /* Warn about slot numbers greater than 2. We used to generate
512 an error here on the assumption that the user entered an invalid
513 address. But, sometimes GDB itself requests an invalid address.
514 This can (easily) happen when execution stops in a function for
515 which there are no symbols. The prologue scanner will attempt to
516 find the beginning of the function - if the nearest symbol
517 happens to not be aligned on a bundle boundary (16 bytes), the
518 resulting starting address will cause GDB to think that the slot
519 number is too large.
520
521 So we warn about it and set the slot number to zero. It is
522 not necessarily a fatal condition, particularly if debugging
523 at the assembly language level. */
524 if (slotnum > 2)
525 {
526 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
527 "Using slot 0 instead");
528 slotnum = 0;
529 }
530
531 addr &= ~0x0f;
532
533 val = target_read_memory (addr, bundle, BUNDLE_LEN);
534
535 if (val != 0)
536 return 0;
537
538 *instr = slotN_contents (bundle, slotnum);
539 template = extract_bit_field (bundle, 0, 5);
540 *it = template_encoding_table[(int)template][slotnum];
541
542 if (slotnum == 2 || (slotnum == 1 && *it == L))
543 addr += 16;
544 else
545 addr += (slotnum + 1) * SLOT_MULTIPLIER;
546
547 return addr;
548 }
549
550 /* There are 5 different break instructions (break.i, break.b,
551 break.m, break.f, and break.x), but they all have the same
552 encoding. (The five bit template in the low five bits of the
553 instruction bundle distinguishes one from another.)
554
555 The runtime architecture manual specifies that break instructions
556 used for debugging purposes must have the upper two bits of the 21
557 bit immediate set to a 0 and a 1 respectively. A breakpoint
558 instruction encodes the most significant bit of its 21 bit
559 immediate at bit 36 of the 41 bit instruction. The penultimate msb
560 is at bit 25 which leads to the pattern below.
561
562 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
563 it turns out that 0x80000 was used as the syscall break in the early
564 simulators. So I changed the pattern slightly to do "break.i 0x080001"
565 instead. But that didn't work either (I later found out that this
566 pattern was used by the simulator that I was using.) So I ended up
567 using the pattern seen below. */
568
569 #if 0
570 #define IA64_BREAKPOINT 0x00002000040LL
571 #endif
572 #define IA64_BREAKPOINT 0x00003333300LL
573
574 static int
575 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
576 {
577 char bundle[BUNDLE_LEN];
578 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
579 long long instr;
580 int val;
581 int template;
582
583 if (slotnum > 2)
584 error("Can't insert breakpoint for slot numbers greater than 2.");
585
586 addr &= ~0x0f;
587
588 val = target_read_memory (addr, bundle, BUNDLE_LEN);
589
590 /* Check for L type instruction in 2nd slot, if present then
591 bump up the slot number to the 3rd slot */
592 template = extract_bit_field (bundle, 0, 5);
593 if (slotnum == 1 && template_encoding_table[template][1] == L)
594 {
595 slotnum = 2;
596 }
597
598 instr = slotN_contents (bundle, slotnum);
599 memcpy(contents_cache, &instr, sizeof(instr));
600 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
601 if (val == 0)
602 target_write_memory (addr, bundle, BUNDLE_LEN);
603
604 return val;
605 }
606
607 static int
608 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
609 {
610 char bundle[BUNDLE_LEN];
611 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
612 long long instr;
613 int val;
614 int template;
615
616 addr &= ~0x0f;
617
618 val = target_read_memory (addr, bundle, BUNDLE_LEN);
619
620 /* Check for L type instruction in 2nd slot, if present then
621 bump up the slot number to the 3rd slot */
622 template = extract_bit_field (bundle, 0, 5);
623 if (slotnum == 1 && template_encoding_table[template][1] == L)
624 {
625 slotnum = 2;
626 }
627
628 memcpy (&instr, contents_cache, sizeof instr);
629 replace_slotN_contents (bundle, instr, slotnum);
630 if (val == 0)
631 target_write_memory (addr, bundle, BUNDLE_LEN);
632
633 return val;
634 }
635
636 /* We don't really want to use this, but remote.c needs to call it in order
637 to figure out if Z-packets are supported or not. Oh, well. */
638 const unsigned char *
639 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
640 {
641 static unsigned char breakpoint[] =
642 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
643 *lenptr = sizeof (breakpoint);
644 #if 0
645 *pcptr &= ~0x0f;
646 #endif
647 return breakpoint;
648 }
649
650 static CORE_ADDR
651 ia64_read_fp (void)
652 {
653 /* We won't necessarily have a frame pointer and even if we do, it
654 winds up being extraordinarly messy when attempting to find the
655 frame chain. So for the purposes of creating frames (which is
656 all deprecated_read_fp() is used for), simply use the stack
657 pointer value instead. */
658 gdb_assert (SP_REGNUM >= 0);
659 return read_register (SP_REGNUM);
660 }
661
662 static CORE_ADDR
663 ia64_read_pc (ptid_t ptid)
664 {
665 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
666 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
667 int slot_num = (psr_value >> 41) & 3;
668
669 return pc_value | (slot_num * SLOT_MULTIPLIER);
670 }
671
672 static void
673 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
674 {
675 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
676 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
677 psr_value &= ~(3LL << 41);
678 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
679
680 new_pc &= ~0xfLL;
681
682 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
683 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
684 }
685
686 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
687
688 /* Returns the address of the slot that's NSLOTS slots away from
689 the address ADDR. NSLOTS may be positive or negative. */
690 static CORE_ADDR
691 rse_address_add(CORE_ADDR addr, int nslots)
692 {
693 CORE_ADDR new_addr;
694 int mandatory_nat_slots = nslots / 63;
695 int direction = nslots < 0 ? -1 : 1;
696
697 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
698
699 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
700 new_addr += 8 * direction;
701
702 if (IS_NaT_COLLECTION_ADDR(new_addr))
703 new_addr += 8 * direction;
704
705 return new_addr;
706 }
707
708 static void
709 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
710 int regnum, void *buf)
711 {
712 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
713 {
714 ULONGEST bsp;
715 ULONGEST cfm;
716 CORE_ADDR reg;
717 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
718 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
719
720 /* The bsp points at the end of the register frame so we
721 subtract the size of frame from it to get start of register frame. */
722 bsp = rse_address_add (bsp, -(cfm & 0x7f));
723
724 if ((cfm & 0x7f) > regnum - V32_REGNUM)
725 {
726 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
727 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
728 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
729 }
730 else
731 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
732 }
733 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
734 {
735 ULONGEST unatN_val;
736 ULONGEST unat;
737 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
738 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
739 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
740 }
741 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
742 {
743 ULONGEST natN_val = 0;
744 ULONGEST bsp;
745 ULONGEST cfm;
746 CORE_ADDR gr_addr = 0;
747 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
748 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
749
750 /* The bsp points at the end of the register frame so we
751 subtract the size of frame from it to get start of register frame. */
752 bsp = rse_address_add (bsp, -(cfm & 0x7f));
753
754 if ((cfm & 0x7f) > regnum - V32_REGNUM)
755 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
756
757 if (gr_addr != 0)
758 {
759 /* Compute address of nat collection bits. */
760 CORE_ADDR nat_addr = gr_addr | 0x1f8;
761 CORE_ADDR nat_collection;
762 int nat_bit;
763 /* If our nat collection address is bigger than bsp, we have to get
764 the nat collection from rnat. Otherwise, we fetch the nat
765 collection from the computed address. */
766 if (nat_addr >= bsp)
767 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
768 else
769 nat_collection = read_memory_integer (nat_addr, 8);
770 nat_bit = (gr_addr >> 3) & 0x3f;
771 natN_val = (nat_collection >> nat_bit) & 1;
772 }
773
774 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
775 }
776 else if (regnum == VBOF_REGNUM)
777 {
778 /* A virtual register frame start is provided for user convenience.
779 It can be calculated as the bsp - sof (sizeof frame). */
780 ULONGEST bsp, vbsp;
781 ULONGEST cfm;
782 CORE_ADDR reg;
783 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
784 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
785
786 /* The bsp points at the end of the register frame so we
787 subtract the size of frame from it to get beginning of frame. */
788 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
789 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
790 }
791 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
792 {
793 ULONGEST pr;
794 ULONGEST cfm;
795 ULONGEST prN_val;
796 CORE_ADDR reg;
797 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
798 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
799
800 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
801 {
802 /* Fetch predicate register rename base from current frame
803 marker for this frame. */
804 int rrb_pr = (cfm >> 32) & 0x3f;
805
806 /* Adjust the register number to account for register rotation. */
807 regnum = VP16_REGNUM
808 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
809 }
810 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
811 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
812 }
813 else
814 memset (buf, 0, register_size (current_gdbarch, regnum));
815 }
816
817 static void
818 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
819 int regnum, const void *buf)
820 {
821 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
822 {
823 ULONGEST bsp;
824 ULONGEST cfm;
825 CORE_ADDR reg;
826 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
827 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
828
829 bsp = rse_address_add (bsp, -(cfm & 0x7f));
830
831 if ((cfm & 0x7f) > regnum - V32_REGNUM)
832 {
833 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
834 write_memory (reg_addr, (void *)buf, 8);
835 }
836 }
837 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
838 {
839 ULONGEST unatN_val, unat, unatN_mask;
840 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
841 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
842 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
843 if (unatN_val == 0)
844 unat &= ~unatN_mask;
845 else if (unatN_val == 1)
846 unat |= unatN_mask;
847 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
848 }
849 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
850 {
851 ULONGEST natN_val;
852 ULONGEST bsp;
853 ULONGEST cfm;
854 CORE_ADDR gr_addr = 0;
855 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
856 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
857
858 /* The bsp points at the end of the register frame so we
859 subtract the size of frame from it to get start of register frame. */
860 bsp = rse_address_add (bsp, -(cfm & 0x7f));
861
862 if ((cfm & 0x7f) > regnum - V32_REGNUM)
863 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
864
865 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
866
867 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
868 {
869 /* Compute address of nat collection bits. */
870 CORE_ADDR nat_addr = gr_addr | 0x1f8;
871 CORE_ADDR nat_collection;
872 int natN_bit = (gr_addr >> 3) & 0x3f;
873 ULONGEST natN_mask = (1LL << natN_bit);
874 /* If our nat collection address is bigger than bsp, we have to get
875 the nat collection from rnat. Otherwise, we fetch the nat
876 collection from the computed address. */
877 if (nat_addr >= bsp)
878 {
879 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
880 if (natN_val)
881 nat_collection |= natN_mask;
882 else
883 nat_collection &= ~natN_mask;
884 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
885 }
886 else
887 {
888 char nat_buf[8];
889 nat_collection = read_memory_integer (nat_addr, 8);
890 if (natN_val)
891 nat_collection |= natN_mask;
892 else
893 nat_collection &= ~natN_mask;
894 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
895 write_memory (nat_addr, nat_buf, 8);
896 }
897 }
898 }
899 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
900 {
901 ULONGEST pr;
902 ULONGEST cfm;
903 ULONGEST prN_val;
904 ULONGEST prN_mask;
905
906 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
907 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
908
909 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
910 {
911 /* Fetch predicate register rename base from current frame
912 marker for this frame. */
913 int rrb_pr = (cfm >> 32) & 0x3f;
914
915 /* Adjust the register number to account for register rotation. */
916 regnum = VP16_REGNUM
917 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
918 }
919 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
920 prN_mask = (1LL << (regnum - VP0_REGNUM));
921 if (prN_val == 0)
922 pr &= ~prN_mask;
923 else if (prN_val == 1)
924 pr |= prN_mask;
925 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
926 }
927 }
928
929 /* The ia64 needs to convert between various ieee floating-point formats
930 and the special ia64 floating point register format. */
931
932 static int
933 ia64_convert_register_p (int regno, struct type *type)
934 {
935 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
936 }
937
938 static void
939 ia64_register_to_value (struct frame_info *frame, int regnum,
940 struct type *valtype, void *out)
941 {
942 char in[MAX_REGISTER_SIZE];
943 frame_register_read (frame, regnum, in);
944 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
945 }
946
947 static void
948 ia64_value_to_register (struct frame_info *frame, int regnum,
949 struct type *valtype, const void *in)
950 {
951 char out[MAX_REGISTER_SIZE];
952 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
953 put_frame_register (frame, regnum, out);
954 }
955
956
957 /* Limit the number of skipped non-prologue instructions since examining
958 of the prologue is expensive. */
959 static int max_skip_non_prologue_insns = 40;
960
961 /* Given PC representing the starting address of a function, and
962 LIM_PC which is the (sloppy) limit to which to scan when looking
963 for a prologue, attempt to further refine this limit by using
964 the line data in the symbol table. If successful, a better guess
965 on where the prologue ends is returned, otherwise the previous
966 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
967 which will be set to indicate whether the returned limit may be
968 used with no further scanning in the event that the function is
969 frameless. */
970
971 static CORE_ADDR
972 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
973 {
974 struct symtab_and_line prologue_sal;
975 CORE_ADDR start_pc = pc;
976
977 /* Start off not trusting the limit. */
978 *trust_limit = 0;
979
980 prologue_sal = find_pc_line (pc, 0);
981 if (prologue_sal.line != 0)
982 {
983 int i;
984 CORE_ADDR addr = prologue_sal.end;
985
986 /* Handle the case in which compiler's optimizer/scheduler
987 has moved instructions into the prologue. We scan ahead
988 in the function looking for address ranges whose corresponding
989 line number is less than or equal to the first one that we
990 found for the function. (It can be less than when the
991 scheduler puts a body instruction before the first prologue
992 instruction.) */
993 for (i = 2 * max_skip_non_prologue_insns;
994 i > 0 && (lim_pc == 0 || addr < lim_pc);
995 i--)
996 {
997 struct symtab_and_line sal;
998
999 sal = find_pc_line (addr, 0);
1000 if (sal.line == 0)
1001 break;
1002 if (sal.line <= prologue_sal.line
1003 && sal.symtab == prologue_sal.symtab)
1004 {
1005 prologue_sal = sal;
1006 }
1007 addr = sal.end;
1008 }
1009
1010 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1011 {
1012 lim_pc = prologue_sal.end;
1013 if (start_pc == get_pc_function_start (lim_pc))
1014 *trust_limit = 1;
1015 }
1016 }
1017 return lim_pc;
1018 }
1019
1020 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1021 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1022 || (14 <= (_regnum_) && (_regnum_) <= 31))
1023 #define imm9(_instr_) \
1024 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1025 | (((_instr_) & 0x00008000000LL) >> 20) \
1026 | (((_instr_) & 0x00000001fc0LL) >> 6))
1027
1028 /* Allocate and initialize a frame cache. */
1029
1030 static struct ia64_frame_cache *
1031 ia64_alloc_frame_cache (void)
1032 {
1033 struct ia64_frame_cache *cache;
1034 int i;
1035
1036 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1037
1038 /* Base address. */
1039 cache->base = 0;
1040 cache->pc = 0;
1041 cache->cfm = 0;
1042 cache->prev_cfm = 0;
1043 cache->sof = 0;
1044 cache->sol = 0;
1045 cache->sor = 0;
1046 cache->bsp = 0;
1047 cache->fp_reg = 0;
1048 cache->frameless = 1;
1049
1050 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1051 cache->saved_regs[i] = 0;
1052
1053 return cache;
1054 }
1055
1056 static CORE_ADDR
1057 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1058 {
1059 CORE_ADDR next_pc;
1060 CORE_ADDR last_prologue_pc = pc;
1061 instruction_type it;
1062 long long instr;
1063 int cfm_reg = 0;
1064 int ret_reg = 0;
1065 int fp_reg = 0;
1066 int unat_save_reg = 0;
1067 int pr_save_reg = 0;
1068 int mem_stack_frame_size = 0;
1069 int spill_reg = 0;
1070 CORE_ADDR spill_addr = 0;
1071 char instores[8];
1072 char infpstores[8];
1073 char reg_contents[256];
1074 int trust_limit;
1075 int frameless = 1;
1076 int i;
1077 CORE_ADDR addr;
1078 char buf[8];
1079 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1080
1081 memset (instores, 0, sizeof instores);
1082 memset (infpstores, 0, sizeof infpstores);
1083 memset (reg_contents, 0, sizeof reg_contents);
1084
1085 if (cache->after_prologue != 0
1086 && cache->after_prologue <= lim_pc)
1087 return cache->after_prologue;
1088
1089 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1090 next_pc = fetch_instruction (pc, &it, &instr);
1091
1092 /* We want to check if we have a recognizable function start before we
1093 look ahead for a prologue. */
1094 if (pc < lim_pc && next_pc
1095 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1096 {
1097 /* alloc - start of a regular function. */
1098 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1099 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1100 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1101 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1102
1103 /* Verify that the current cfm matches what we think is the
1104 function start. If we have somehow jumped within a function,
1105 we do not want to interpret the prologue and calculate the
1106 addresses of various registers such as the return address.
1107 We will instead treat the frame as frameless. */
1108 if (!next_frame ||
1109 (sof == (cache->cfm & 0x7f) &&
1110 sol == ((cache->cfm >> 7) & 0x7f)))
1111 frameless = 0;
1112
1113 cfm_reg = rN;
1114 last_prologue_pc = next_pc;
1115 pc = next_pc;
1116 }
1117 else
1118 {
1119 /* Look for a leaf routine. */
1120 if (pc < lim_pc && next_pc
1121 && (it == I || it == M)
1122 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1123 {
1124 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1125 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1126 | ((instr & 0x001f8000000LL) >> 20)
1127 | ((instr & 0x000000fe000LL) >> 13));
1128 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1129 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1130 int qp = (int) (instr & 0x0000000003fLL);
1131 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1132 {
1133 /* mov r2, r12 - beginning of leaf routine */
1134 fp_reg = rN;
1135 last_prologue_pc = next_pc;
1136 }
1137 }
1138
1139 /* If we don't recognize a regular function or leaf routine, we are
1140 done. */
1141 if (!fp_reg)
1142 {
1143 pc = lim_pc;
1144 if (trust_limit)
1145 last_prologue_pc = lim_pc;
1146 }
1147 }
1148
1149 /* Loop, looking for prologue instructions, keeping track of
1150 where preserved registers were spilled. */
1151 while (pc < lim_pc)
1152 {
1153 next_pc = fetch_instruction (pc, &it, &instr);
1154 if (next_pc == 0)
1155 break;
1156
1157 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000))
1158 {
1159 /* Exit loop upon hitting a non-nop branch instruction. */
1160 if (trust_limit)
1161 lim_pc = pc;
1162 break;
1163 }
1164 else if (((instr & 0x3fLL) != 0LL) &&
1165 (frameless || ret_reg != 0))
1166 {
1167 /* Exit loop upon hitting a predicated instruction if
1168 we already have the return register or if we are frameless. */
1169 if (trust_limit)
1170 lim_pc = pc;
1171 break;
1172 }
1173 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1174 {
1175 /* Move from BR */
1176 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1177 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1178 int qp = (int) (instr & 0x0000000003f);
1179
1180 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1181 {
1182 ret_reg = rN;
1183 last_prologue_pc = next_pc;
1184 }
1185 }
1186 else if ((it == I || it == M)
1187 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1188 {
1189 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1190 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1191 | ((instr & 0x001f8000000LL) >> 20)
1192 | ((instr & 0x000000fe000LL) >> 13));
1193 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1194 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1195 int qp = (int) (instr & 0x0000000003fLL);
1196
1197 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1198 {
1199 /* mov rN, r12 */
1200 fp_reg = rN;
1201 last_prologue_pc = next_pc;
1202 }
1203 else if (qp == 0 && rN == 12 && rM == 12)
1204 {
1205 /* adds r12, -mem_stack_frame_size, r12 */
1206 mem_stack_frame_size -= imm;
1207 last_prologue_pc = next_pc;
1208 }
1209 else if (qp == 0 && rN == 2
1210 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1211 {
1212 char buf[MAX_REGISTER_SIZE];
1213 CORE_ADDR saved_sp = 0;
1214 /* adds r2, spilloffset, rFramePointer
1215 or
1216 adds r2, spilloffset, r12
1217
1218 Get ready for stf.spill or st8.spill instructions.
1219 The address to start spilling at is loaded into r2.
1220 FIXME: Why r2? That's what gcc currently uses; it
1221 could well be different for other compilers. */
1222
1223 /* Hmm... whether or not this will work will depend on
1224 where the pc is. If it's still early in the prologue
1225 this'll be wrong. FIXME */
1226 if (next_frame)
1227 {
1228 frame_unwind_register (next_frame, sp_regnum, buf);
1229 saved_sp = extract_unsigned_integer (buf, 8);
1230 }
1231 spill_addr = saved_sp
1232 + (rM == 12 ? 0 : mem_stack_frame_size)
1233 + imm;
1234 spill_reg = rN;
1235 last_prologue_pc = next_pc;
1236 }
1237 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1238 rN < 256 && imm == 0)
1239 {
1240 /* mov rN, rM where rM is an input register */
1241 reg_contents[rN] = rM;
1242 last_prologue_pc = next_pc;
1243 }
1244 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1245 rM == 2)
1246 {
1247 /* mov r12, r2 */
1248 last_prologue_pc = next_pc;
1249 break;
1250 }
1251 }
1252 else if (it == M
1253 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1254 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1255 {
1256 /* stf.spill [rN] = fM, imm9
1257 or
1258 stf.spill [rN] = fM */
1259
1260 int imm = imm9(instr);
1261 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1262 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1263 int qp = (int) (instr & 0x0000000003fLL);
1264 if (qp == 0 && rN == spill_reg && spill_addr != 0
1265 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1266 {
1267 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1268
1269 if ((instr & 0x1efc0000000) == 0x0eec0000000)
1270 spill_addr += imm;
1271 else
1272 spill_addr = 0; /* last one; must be done */
1273 last_prologue_pc = next_pc;
1274 }
1275 }
1276 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1277 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1278 {
1279 /* mov.m rN = arM
1280 or
1281 mov.i rN = arM */
1282
1283 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1284 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1285 int qp = (int) (instr & 0x0000000003fLL);
1286 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1287 {
1288 /* We have something like "mov.m r3 = ar.unat". Remember the
1289 r3 (or whatever) and watch for a store of this register... */
1290 unat_save_reg = rN;
1291 last_prologue_pc = next_pc;
1292 }
1293 }
1294 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1295 {
1296 /* mov rN = pr */
1297 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1298 int qp = (int) (instr & 0x0000000003fLL);
1299 if (qp == 0 && isScratch (rN))
1300 {
1301 pr_save_reg = rN;
1302 last_prologue_pc = next_pc;
1303 }
1304 }
1305 else if (it == M
1306 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1307 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1308 {
1309 /* st8 [rN] = rM
1310 or
1311 st8 [rN] = rM, imm9 */
1312 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1313 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1314 int qp = (int) (instr & 0x0000000003fLL);
1315 int indirect = rM < 256 ? reg_contents[rM] : 0;
1316 if (qp == 0 && rN == spill_reg && spill_addr != 0
1317 && (rM == unat_save_reg || rM == pr_save_reg))
1318 {
1319 /* We've found a spill of either the UNAT register or the PR
1320 register. (Well, not exactly; what we've actually found is
1321 a spill of the register that UNAT or PR was moved to).
1322 Record that fact and move on... */
1323 if (rM == unat_save_reg)
1324 {
1325 /* Track UNAT register */
1326 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1327 unat_save_reg = 0;
1328 }
1329 else
1330 {
1331 /* Track PR register */
1332 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1333 pr_save_reg = 0;
1334 }
1335 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1336 /* st8 [rN] = rM, imm9 */
1337 spill_addr += imm9(instr);
1338 else
1339 spill_addr = 0; /* must be done spilling */
1340 last_prologue_pc = next_pc;
1341 }
1342 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1343 {
1344 /* Allow up to one store of each input register. */
1345 instores[rM-32] = 1;
1346 last_prologue_pc = next_pc;
1347 }
1348 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1349 !instores[indirect-32])
1350 {
1351 /* Allow an indirect store of an input register. */
1352 instores[indirect-32] = 1;
1353 last_prologue_pc = next_pc;
1354 }
1355 }
1356 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1357 {
1358 /* One of
1359 st1 [rN] = rM
1360 st2 [rN] = rM
1361 st4 [rN] = rM
1362 st8 [rN] = rM
1363 Note that the st8 case is handled in the clause above.
1364
1365 Advance over stores of input registers. One store per input
1366 register is permitted. */
1367 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1368 int qp = (int) (instr & 0x0000000003fLL);
1369 int indirect = rM < 256 ? reg_contents[rM] : 0;
1370 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1371 {
1372 instores[rM-32] = 1;
1373 last_prologue_pc = next_pc;
1374 }
1375 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1376 !instores[indirect-32])
1377 {
1378 /* Allow an indirect store of an input register. */
1379 instores[indirect-32] = 1;
1380 last_prologue_pc = next_pc;
1381 }
1382 }
1383 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1384 {
1385 /* Either
1386 stfs [rN] = fM
1387 or
1388 stfd [rN] = fM
1389
1390 Advance over stores of floating point input registers. Again
1391 one store per register is permitted */
1392 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1393 int qp = (int) (instr & 0x0000000003fLL);
1394 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1395 {
1396 infpstores[fM-8] = 1;
1397 last_prologue_pc = next_pc;
1398 }
1399 }
1400 else if (it == M
1401 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1402 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1403 {
1404 /* st8.spill [rN] = rM
1405 or
1406 st8.spill [rN] = rM, imm9 */
1407 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1408 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1409 int qp = (int) (instr & 0x0000000003fLL);
1410 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1411 {
1412 /* We've found a spill of one of the preserved general purpose
1413 regs. Record the spill address and advance the spill
1414 register if appropriate. */
1415 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1416 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1417 /* st8.spill [rN] = rM, imm9 */
1418 spill_addr += imm9(instr);
1419 else
1420 spill_addr = 0; /* Done spilling */
1421 last_prologue_pc = next_pc;
1422 }
1423 }
1424
1425 pc = next_pc;
1426 }
1427
1428 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1429 registers for the previous frame which will be needed later. */
1430
1431 if (!frameless && next_frame)
1432 {
1433 /* Extract the size of the rotating portion of the stack
1434 frame and the register rename base from the current
1435 frame marker. */
1436 cfm = cache->cfm;
1437 sor = cache->sor;
1438 sof = cache->sof;
1439 sol = cache->sol;
1440 rrb_gr = (cfm >> 18) & 0x7f;
1441
1442 /* Find the bof (beginning of frame). */
1443 bof = rse_address_add (cache->bsp, -sof);
1444
1445 for (i = 0, addr = bof;
1446 i < sof;
1447 i++, addr += 8)
1448 {
1449 if (IS_NaT_COLLECTION_ADDR (addr))
1450 {
1451 addr += 8;
1452 }
1453 if (i+32 == cfm_reg)
1454 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1455 if (i+32 == ret_reg)
1456 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1457 if (i+32 == fp_reg)
1458 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1459 }
1460
1461 /* For the previous argument registers we require the previous bof.
1462 If we can't find the previous cfm, then we can do nothing. */
1463 cfm = 0;
1464 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1465 {
1466 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1467 }
1468 else if (cfm_reg != 0)
1469 {
1470 frame_unwind_register (next_frame, cfm_reg, buf);
1471 cfm = extract_unsigned_integer (buf, 8);
1472 }
1473 cache->prev_cfm = cfm;
1474
1475 if (cfm != 0)
1476 {
1477 sor = ((cfm >> 14) & 0xf) * 8;
1478 sof = (cfm & 0x7f);
1479 sol = (cfm >> 7) & 0x7f;
1480 rrb_gr = (cfm >> 18) & 0x7f;
1481
1482 /* The previous bof only requires subtraction of the sol (size of locals)
1483 due to the overlap between output and input of subsequent frames. */
1484 bof = rse_address_add (bof, -sol);
1485
1486 for (i = 0, addr = bof;
1487 i < sof;
1488 i++, addr += 8)
1489 {
1490 if (IS_NaT_COLLECTION_ADDR (addr))
1491 {
1492 addr += 8;
1493 }
1494 if (i < sor)
1495 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1496 = addr;
1497 else
1498 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1499 }
1500
1501 }
1502 }
1503
1504 /* Try and trust the lim_pc value whenever possible. */
1505 if (trust_limit && lim_pc >= last_prologue_pc)
1506 last_prologue_pc = lim_pc;
1507
1508 cache->frameless = frameless;
1509 cache->after_prologue = last_prologue_pc;
1510 cache->mem_stack_frame_size = mem_stack_frame_size;
1511 cache->fp_reg = fp_reg;
1512
1513 return last_prologue_pc;
1514 }
1515
1516 CORE_ADDR
1517 ia64_skip_prologue (CORE_ADDR pc)
1518 {
1519 struct ia64_frame_cache cache;
1520 cache.base = 0;
1521 cache.after_prologue = 0;
1522 cache.cfm = 0;
1523 cache.bsp = 0;
1524
1525 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1526 return examine_prologue (pc, pc+1024, 0, &cache);
1527 }
1528
1529
1530 /* Normal frames. */
1531
1532 static struct ia64_frame_cache *
1533 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1534 {
1535 struct ia64_frame_cache *cache;
1536 char buf[8];
1537 CORE_ADDR cfm, sof, sol, bsp, psr;
1538 int i;
1539
1540 if (*this_cache)
1541 return *this_cache;
1542
1543 cache = ia64_alloc_frame_cache ();
1544 *this_cache = cache;
1545
1546 frame_unwind_register (next_frame, sp_regnum, buf);
1547 cache->saved_sp = extract_unsigned_integer (buf, 8);
1548
1549 /* We always want the bsp to point to the end of frame.
1550 This way, we can always get the beginning of frame (bof)
1551 by subtracting frame size. */
1552 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1553 cache->bsp = extract_unsigned_integer (buf, 8);
1554
1555 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1556 psr = extract_unsigned_integer (buf, 8);
1557
1558 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1559 cfm = extract_unsigned_integer (buf, 8);
1560
1561 cache->sof = (cfm & 0x7f);
1562 cache->sol = (cfm >> 7) & 0x7f;
1563 cache->sor = ((cfm >> 14) & 0xf) * 8;
1564
1565 cache->cfm = cfm;
1566
1567 cache->pc = frame_func_unwind (next_frame);
1568
1569 if (cache->pc != 0)
1570 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1571
1572 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1573
1574 return cache;
1575 }
1576
1577 static void
1578 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1579 struct frame_id *this_id)
1580 {
1581 struct ia64_frame_cache *cache =
1582 ia64_frame_cache (next_frame, this_cache);
1583
1584 /* This marks the outermost frame. */
1585 if (cache->base == 0)
1586 return;
1587
1588 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1589 if (gdbarch_debug >= 1)
1590 fprintf_unfiltered (gdb_stdlog,
1591 "regular frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1592 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
1593 }
1594
1595 static void
1596 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1597 int regnum, int *optimizedp,
1598 enum lval_type *lvalp, CORE_ADDR *addrp,
1599 int *realnump, void *valuep)
1600 {
1601 struct ia64_frame_cache *cache =
1602 ia64_frame_cache (next_frame, this_cache);
1603 char dummy_valp[MAX_REGISTER_SIZE];
1604 char buf[8];
1605
1606 gdb_assert (regnum >= 0);
1607
1608 if (!target_has_registers)
1609 error ("No registers.");
1610
1611 *optimizedp = 0;
1612 *addrp = 0;
1613 *lvalp = not_lval;
1614 *realnump = -1;
1615
1616 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1617 when valuep is not supplied. */
1618 if (!valuep)
1619 valuep = dummy_valp;
1620
1621 memset (valuep, 0, register_size (current_gdbarch, regnum));
1622
1623 if (regnum == SP_REGNUM)
1624 {
1625 /* Handle SP values for all frames but the topmost. */
1626 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1627 cache->base);
1628 }
1629 else if (regnum == IA64_BSP_REGNUM)
1630 {
1631 char cfm_valuep[MAX_REGISTER_SIZE];
1632 int cfm_optim;
1633 int cfm_realnum;
1634 enum lval_type cfm_lval;
1635 CORE_ADDR cfm_addr;
1636 CORE_ADDR bsp, prev_cfm, prev_bsp;
1637
1638 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1639 This corresponds to what the hardware bsp register will be if we pop the frame
1640 back which is why we might have been called. We know the beginning of the current
1641 frame is cache->bsp - cache->sof. This value in the previous frame points to
1642 the start of the output registers. We can calculate the end of that frame by adding
1643 the size of output (sof (size of frame) - sol (size of locals)). */
1644 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1645 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1646 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1647
1648 bsp = rse_address_add (cache->bsp, -(cache->sof));
1649 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1650
1651 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1652 prev_bsp);
1653 }
1654 else if (regnum == IA64_CFM_REGNUM)
1655 {
1656 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1657
1658 if (addr != 0)
1659 {
1660 *lvalp = lval_memory;
1661 *addrp = addr;
1662 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1663 }
1664 else if (cache->prev_cfm)
1665 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1666 else if (cache->frameless)
1667 {
1668 CORE_ADDR cfm = 0;
1669 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1670 }
1671 }
1672 else if (regnum == IA64_VFP_REGNUM)
1673 {
1674 /* If the function in question uses an automatic register (r32-r127)
1675 for the frame pointer, it'll be found by ia64_find_saved_register()
1676 above. If the function lacks one of these frame pointers, we can
1677 still provide a value since we know the size of the frame. */
1678 CORE_ADDR vfp = cache->base;
1679 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
1680 }
1681 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1682 {
1683 char pr_valuep[MAX_REGISTER_SIZE];
1684 int pr_optim;
1685 int pr_realnum;
1686 enum lval_type pr_lval;
1687 CORE_ADDR pr_addr;
1688 ULONGEST prN_val;
1689 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1690 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1691 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1692 {
1693 /* Fetch predicate register rename base from current frame
1694 marker for this frame. */
1695 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1696
1697 /* Adjust the register number to account for register rotation. */
1698 regnum = VP16_REGNUM
1699 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1700 }
1701 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1702 regnum - VP0_REGNUM, 1);
1703 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
1704 }
1705 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1706 {
1707 char unat_valuep[MAX_REGISTER_SIZE];
1708 int unat_optim;
1709 int unat_realnum;
1710 enum lval_type unat_lval;
1711 CORE_ADDR unat_addr;
1712 ULONGEST unatN_val;
1713 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1714 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1715 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1716 regnum - IA64_NAT0_REGNUM, 1);
1717 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1718 unatN_val);
1719 }
1720 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1721 {
1722 int natval = 0;
1723 /* Find address of general register corresponding to nat bit we're
1724 interested in. */
1725 CORE_ADDR gr_addr;
1726
1727 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1728 + IA64_GR0_REGNUM];
1729 if (gr_addr != 0)
1730 {
1731 /* Compute address of nat collection bits. */
1732 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1733 CORE_ADDR bsp;
1734 CORE_ADDR nat_collection;
1735 int nat_bit;
1736 /* If our nat collection address is bigger than bsp, we have to get
1737 the nat collection from rnat. Otherwise, we fetch the nat
1738 collection from the computed address. */
1739 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1740 bsp = extract_unsigned_integer (buf, 8);
1741 if (nat_addr >= bsp)
1742 {
1743 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1744 nat_collection = extract_unsigned_integer (buf, 8);
1745 }
1746 else
1747 nat_collection = read_memory_integer (nat_addr, 8);
1748 nat_bit = (gr_addr >> 3) & 0x3f;
1749 natval = (nat_collection >> nat_bit) & 1;
1750 }
1751
1752 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
1753 }
1754 else if (regnum == IA64_IP_REGNUM)
1755 {
1756 CORE_ADDR pc = 0;
1757 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1758
1759 if (addr != 0)
1760 {
1761 *lvalp = lval_memory;
1762 *addrp = addr;
1763 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1764 pc = extract_unsigned_integer (buf, 8);
1765 }
1766 else if (cache->frameless)
1767 {
1768 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1769 pc = extract_unsigned_integer (buf, 8);
1770 }
1771 pc &= ~0xf;
1772 store_unsigned_integer (valuep, 8, pc);
1773 }
1774 else if (regnum == IA64_PSR_REGNUM)
1775 {
1776 /* We don't know how to get the complete previous PSR, but we need it for
1777 the slot information when we unwind the pc (pc is formed of IP register
1778 plus slot information from PSR). To get the previous slot information,
1779 we mask it off the return address. */
1780 ULONGEST slot_num = 0;
1781 CORE_ADDR pc= 0;
1782 CORE_ADDR psr = 0;
1783 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1784
1785 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1786 psr = extract_unsigned_integer (buf, 8);
1787
1788 if (addr != 0)
1789 {
1790 *lvalp = lval_memory;
1791 *addrp = addr;
1792 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1793 pc = extract_unsigned_integer (buf, 8);
1794 }
1795 else if (cache->frameless)
1796 {
1797 CORE_ADDR pc;
1798 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1799 pc = extract_unsigned_integer (buf, 8);
1800 }
1801 psr &= ~(3LL << 41);
1802 slot_num = pc & 0x3LL;
1803 psr |= (CORE_ADDR)slot_num << 41;
1804 store_unsigned_integer (valuep, 8, psr);
1805 }
1806 else if (regnum == IA64_BR0_REGNUM)
1807 {
1808 CORE_ADDR br0 = 0;
1809 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1810 if (addr != 0)
1811 {
1812 *lvalp = lval_memory;
1813 *addrp = addr;
1814 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1815 br0 = extract_unsigned_integer (buf, 8);
1816 }
1817 store_unsigned_integer (valuep, 8, br0);
1818 }
1819 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1820 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1821 {
1822 CORE_ADDR addr = 0;
1823 if (regnum >= V32_REGNUM)
1824 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1825 addr = cache->saved_regs[regnum];
1826 if (addr != 0)
1827 {
1828 *lvalp = lval_memory;
1829 *addrp = addr;
1830 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1831 }
1832 else if (cache->frameless)
1833 {
1834 char r_valuep[MAX_REGISTER_SIZE];
1835 int r_optim;
1836 int r_realnum;
1837 enum lval_type r_lval;
1838 CORE_ADDR r_addr;
1839 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1840 CORE_ADDR addr = 0;
1841 if (regnum >= V32_REGNUM)
1842 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1843 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1844 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1845 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1846 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1847 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1848 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1849 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1850
1851 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1852 *lvalp = lval_memory;
1853 *addrp = addr;
1854 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1855 }
1856 }
1857 else
1858 {
1859 CORE_ADDR addr = 0;
1860 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1861 {
1862 /* Fetch floating point register rename base from current
1863 frame marker for this frame. */
1864 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1865
1866 /* Adjust the floating point register number to account for
1867 register rotation. */
1868 regnum = IA64_FR32_REGNUM
1869 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1870 }
1871
1872 /* If we have stored a memory address, access the register. */
1873 addr = cache->saved_regs[regnum];
1874 if (addr != 0)
1875 {
1876 *lvalp = lval_memory;
1877 *addrp = addr;
1878 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1879 }
1880 /* Otherwise, punt and get the current value of the register. */
1881 else
1882 frame_unwind_register (next_frame, regnum, valuep);
1883 }
1884
1885 if (gdbarch_debug >= 1)
1886 fprintf_unfiltered (gdb_stdlog,
1887 "regular prev register <%d> <%s> is %lx\n", regnum,
1888 (((unsigned) regnum <= IA64_NAT127_REGNUM)
1889 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
1890 }
1891
1892 static const struct frame_unwind ia64_frame_unwind =
1893 {
1894 NORMAL_FRAME,
1895 &ia64_frame_this_id,
1896 &ia64_frame_prev_register
1897 };
1898
1899 static const struct frame_unwind *
1900 ia64_frame_sniffer (struct frame_info *next_frame)
1901 {
1902 return &ia64_frame_unwind;
1903 }
1904
1905 /* Signal trampolines. */
1906
1907 static void
1908 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1909 {
1910 if (SIGCONTEXT_REGISTER_ADDRESS)
1911 {
1912 int regno;
1913
1914 cache->saved_regs[IA64_VRAP_REGNUM] =
1915 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1916 cache->saved_regs[IA64_CFM_REGNUM] =
1917 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1918 cache->saved_regs[IA64_PSR_REGNUM] =
1919 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1920 cache->saved_regs[IA64_BSP_REGNUM] =
1921 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
1922 cache->saved_regs[IA64_RNAT_REGNUM] =
1923 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1924 cache->saved_regs[IA64_CCV_REGNUM] =
1925 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1926 cache->saved_regs[IA64_UNAT_REGNUM] =
1927 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1928 cache->saved_regs[IA64_FPSR_REGNUM] =
1929 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1930 cache->saved_regs[IA64_PFS_REGNUM] =
1931 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1932 cache->saved_regs[IA64_LC_REGNUM] =
1933 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1934 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1935 cache->saved_regs[regno] =
1936 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1937 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1938 cache->saved_regs[regno] =
1939 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1940 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
1941 cache->saved_regs[regno] =
1942 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1943 }
1944 }
1945
1946 static struct ia64_frame_cache *
1947 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1948 {
1949 struct ia64_frame_cache *cache;
1950 CORE_ADDR addr;
1951 char buf[8];
1952 int i;
1953
1954 if (*this_cache)
1955 return *this_cache;
1956
1957 cache = ia64_alloc_frame_cache ();
1958
1959 frame_unwind_register (next_frame, sp_regnum, buf);
1960 /* Note that frame size is hard-coded below. We cannot calculate it
1961 via prologue examination. */
1962 cache->base = extract_unsigned_integer (buf, 8) + 16;
1963
1964 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1965 cache->bsp = extract_unsigned_integer (buf, 8);
1966
1967 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1968 cache->cfm = extract_unsigned_integer (buf, 8);
1969 cache->sof = cache->cfm & 0x7f;
1970
1971 ia64_sigtramp_frame_init_saved_regs (cache);
1972
1973 *this_cache = cache;
1974 return cache;
1975 }
1976
1977 static void
1978 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1979 void **this_cache, struct frame_id *this_id)
1980 {
1981 struct ia64_frame_cache *cache =
1982 ia64_sigtramp_frame_cache (next_frame, this_cache);
1983
1984 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1985 if (gdbarch_debug >= 1)
1986 fprintf_unfiltered (gdb_stdlog,
1987 "sigtramp frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1988 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
1989 }
1990
1991 static void
1992 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1993 void **this_cache,
1994 int regnum, int *optimizedp,
1995 enum lval_type *lvalp, CORE_ADDR *addrp,
1996 int *realnump, void *valuep)
1997 {
1998 char dummy_valp[MAX_REGISTER_SIZE];
1999 char buf[MAX_REGISTER_SIZE];
2000
2001 struct ia64_frame_cache *cache =
2002 ia64_sigtramp_frame_cache (next_frame, this_cache);
2003
2004 gdb_assert (regnum >= 0);
2005
2006 if (!target_has_registers)
2007 error ("No registers.");
2008
2009 *optimizedp = 0;
2010 *addrp = 0;
2011 *lvalp = not_lval;
2012 *realnump = -1;
2013
2014 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2015 when valuep is not supplied. */
2016 if (!valuep)
2017 valuep = dummy_valp;
2018
2019 memset (valuep, 0, register_size (current_gdbarch, regnum));
2020
2021 if (regnum == IA64_IP_REGNUM)
2022 {
2023 CORE_ADDR pc = 0;
2024 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2025
2026 if (addr != 0)
2027 {
2028 *lvalp = lval_memory;
2029 *addrp = addr;
2030 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2031 pc = extract_unsigned_integer (buf, 8);
2032 }
2033 pc &= ~0xf;
2034 store_unsigned_integer (valuep, 8, pc);
2035 }
2036 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2037 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2038 {
2039 CORE_ADDR addr = 0;
2040 if (regnum >= V32_REGNUM)
2041 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2042 addr = cache->saved_regs[regnum];
2043 if (addr != 0)
2044 {
2045 *lvalp = lval_memory;
2046 *addrp = addr;
2047 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2048 }
2049 }
2050 else
2051 {
2052 /* All other registers not listed above. */
2053 CORE_ADDR addr = cache->saved_regs[regnum];
2054 if (addr != 0)
2055 {
2056 *lvalp = lval_memory;
2057 *addrp = addr;
2058 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2059 }
2060 }
2061
2062 if (gdbarch_debug >= 1)
2063 fprintf_unfiltered (gdb_stdlog,
2064 "sigtramp prev register <%s> is %lx\n",
2065 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2066 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
2067 }
2068
2069 static const struct frame_unwind ia64_sigtramp_frame_unwind =
2070 {
2071 SIGTRAMP_FRAME,
2072 ia64_sigtramp_frame_this_id,
2073 ia64_sigtramp_frame_prev_register
2074 };
2075
2076 static const struct frame_unwind *
2077 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2078 {
2079 char *name;
2080 CORE_ADDR pc = frame_pc_unwind (next_frame);
2081
2082 find_pc_partial_function (pc, &name, NULL, NULL);
2083 if (PC_IN_SIGTRAMP (pc, name))
2084 return &ia64_sigtramp_frame_unwind;
2085
2086 return NULL;
2087 }
2088 \f
2089
2090 static CORE_ADDR
2091 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2092 {
2093 struct ia64_frame_cache *cache =
2094 ia64_frame_cache (next_frame, this_cache);
2095
2096 return cache->base;
2097 }
2098
2099 static const struct frame_base ia64_frame_base =
2100 {
2101 &ia64_frame_unwind,
2102 ia64_frame_base_address,
2103 ia64_frame_base_address,
2104 ia64_frame_base_address
2105 };
2106
2107 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
2108 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
2109 and TYPE is the type (which is known to be struct, union or array). */
2110 int
2111 ia64_use_struct_convention (int gcc_p, struct type *type)
2112 {
2113 struct type *float_elt_type;
2114
2115 /* HFAs are structures (or arrays) consisting entirely of floating
2116 point values of the same length. Up to 8 of these are returned
2117 in registers. Don't use the struct convention when this is the
2118 case. */
2119 float_elt_type = is_float_or_hfa_type (type);
2120 if (float_elt_type != NULL
2121 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2122 return 0;
2123
2124 /* Other structs of length 32 or less are returned in r8-r11.
2125 Don't use the struct convention for those either. */
2126 return TYPE_LENGTH (type) > 32;
2127 }
2128
2129 void
2130 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2131 {
2132 struct type *float_elt_type;
2133
2134 float_elt_type = is_float_or_hfa_type (type);
2135 if (float_elt_type != NULL)
2136 {
2137 char from[MAX_REGISTER_SIZE];
2138 int offset = 0;
2139 int regnum = IA64_FR8_REGNUM;
2140 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2141
2142 while (n-- > 0)
2143 {
2144 regcache_cooked_read (regcache, regnum, from);
2145 convert_typed_floating (from, builtin_type_ia64_ext,
2146 (char *)valbuf + offset, float_elt_type);
2147 offset += TYPE_LENGTH (float_elt_type);
2148 regnum++;
2149 }
2150 }
2151 else
2152 {
2153 ULONGEST val;
2154 int offset = 0;
2155 int regnum = IA64_GR8_REGNUM;
2156 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2157 int n = TYPE_LENGTH (type) / reglen;
2158 int m = TYPE_LENGTH (type) % reglen;
2159
2160 while (n-- > 0)
2161 {
2162 ULONGEST val;
2163 regcache_cooked_read_unsigned (regcache, regnum, &val);
2164 memcpy ((char *)valbuf + offset, &val, reglen);
2165 offset += reglen;
2166 regnum++;
2167 }
2168
2169 if (m)
2170 {
2171 regcache_cooked_read_unsigned (regcache, regnum, &val);
2172 memcpy ((char *)valbuf + offset, &val, m);
2173 }
2174 }
2175 }
2176
2177 CORE_ADDR
2178 ia64_extract_struct_value_address (struct regcache *regcache)
2179 {
2180 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2181 return 0;
2182 }
2183
2184
2185 static int
2186 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2187 {
2188 switch (TYPE_CODE (t))
2189 {
2190 case TYPE_CODE_FLT:
2191 if (*etp)
2192 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2193 else
2194 {
2195 *etp = t;
2196 return 1;
2197 }
2198 break;
2199 case TYPE_CODE_ARRAY:
2200 return
2201 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2202 etp);
2203 break;
2204 case TYPE_CODE_STRUCT:
2205 {
2206 int i;
2207
2208 for (i = 0; i < TYPE_NFIELDS (t); i++)
2209 if (!is_float_or_hfa_type_recurse
2210 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2211 return 0;
2212 return 1;
2213 }
2214 break;
2215 default:
2216 return 0;
2217 break;
2218 }
2219 }
2220
2221 /* Determine if the given type is one of the floating point types or
2222 and HFA (which is a struct, array, or combination thereof whose
2223 bottom-most elements are all of the same floating point type). */
2224
2225 static struct type *
2226 is_float_or_hfa_type (struct type *t)
2227 {
2228 struct type *et = 0;
2229
2230 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2231 }
2232
2233
2234 /* Return 1 if the alignment of T is such that the next even slot
2235 should be used. Return 0, if the next available slot should
2236 be used. (See section 8.5.1 of the IA-64 Software Conventions
2237 and Runtime manual). */
2238
2239 static int
2240 slot_alignment_is_next_even (struct type *t)
2241 {
2242 switch (TYPE_CODE (t))
2243 {
2244 case TYPE_CODE_INT:
2245 case TYPE_CODE_FLT:
2246 if (TYPE_LENGTH (t) > 8)
2247 return 1;
2248 else
2249 return 0;
2250 case TYPE_CODE_ARRAY:
2251 return
2252 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2253 case TYPE_CODE_STRUCT:
2254 {
2255 int i;
2256
2257 for (i = 0; i < TYPE_NFIELDS (t); i++)
2258 if (slot_alignment_is_next_even
2259 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2260 return 1;
2261 return 0;
2262 }
2263 default:
2264 return 0;
2265 }
2266 }
2267
2268 /* Attempt to find (and return) the global pointer for the given
2269 function.
2270
2271 This is a rather nasty bit of code searchs for the .dynamic section
2272 in the objfile corresponding to the pc of the function we're trying
2273 to call. Once it finds the addresses at which the .dynamic section
2274 lives in the child process, it scans the Elf64_Dyn entries for a
2275 DT_PLTGOT tag. If it finds one of these, the corresponding
2276 d_un.d_ptr value is the global pointer. */
2277
2278 static CORE_ADDR
2279 generic_elf_find_global_pointer (CORE_ADDR faddr)
2280 {
2281 struct obj_section *faddr_sect;
2282
2283 faddr_sect = find_pc_section (faddr);
2284 if (faddr_sect != NULL)
2285 {
2286 struct obj_section *osect;
2287
2288 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2289 {
2290 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2291 break;
2292 }
2293
2294 if (osect < faddr_sect->objfile->sections_end)
2295 {
2296 CORE_ADDR addr;
2297
2298 addr = osect->addr;
2299 while (addr < osect->endaddr)
2300 {
2301 int status;
2302 LONGEST tag;
2303 char buf[8];
2304
2305 status = target_read_memory (addr, buf, sizeof (buf));
2306 if (status != 0)
2307 break;
2308 tag = extract_signed_integer (buf, sizeof (buf));
2309
2310 if (tag == DT_PLTGOT)
2311 {
2312 CORE_ADDR global_pointer;
2313
2314 status = target_read_memory (addr + 8, buf, sizeof (buf));
2315 if (status != 0)
2316 break;
2317 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2318
2319 /* The payoff... */
2320 return global_pointer;
2321 }
2322
2323 if (tag == DT_NULL)
2324 break;
2325
2326 addr += 16;
2327 }
2328 }
2329 }
2330 return 0;
2331 }
2332
2333 /* Given a function's address, attempt to find (and return) the
2334 corresponding (canonical) function descriptor. Return 0 if
2335 not found. */
2336 static CORE_ADDR
2337 find_extant_func_descr (CORE_ADDR faddr)
2338 {
2339 struct obj_section *faddr_sect;
2340
2341 /* Return early if faddr is already a function descriptor. */
2342 faddr_sect = find_pc_section (faddr);
2343 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2344 return faddr;
2345
2346 if (faddr_sect != NULL)
2347 {
2348 struct obj_section *osect;
2349 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2350 {
2351 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2352 break;
2353 }
2354
2355 if (osect < faddr_sect->objfile->sections_end)
2356 {
2357 CORE_ADDR addr;
2358
2359 addr = osect->addr;
2360 while (addr < osect->endaddr)
2361 {
2362 int status;
2363 LONGEST faddr2;
2364 char buf[8];
2365
2366 status = target_read_memory (addr, buf, sizeof (buf));
2367 if (status != 0)
2368 break;
2369 faddr2 = extract_signed_integer (buf, sizeof (buf));
2370
2371 if (faddr == faddr2)
2372 return addr;
2373
2374 addr += 16;
2375 }
2376 }
2377 }
2378 return 0;
2379 }
2380
2381 /* Attempt to find a function descriptor corresponding to the
2382 given address. If none is found, construct one on the
2383 stack using the address at fdaptr. */
2384
2385 static CORE_ADDR
2386 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2387 {
2388 CORE_ADDR fdesc;
2389
2390 fdesc = find_extant_func_descr (faddr);
2391
2392 if (fdesc == 0)
2393 {
2394 CORE_ADDR global_pointer;
2395 char buf[16];
2396
2397 fdesc = *fdaptr;
2398 *fdaptr += 16;
2399
2400 global_pointer = FIND_GLOBAL_POINTER (faddr);
2401
2402 if (global_pointer == 0)
2403 global_pointer = read_register (IA64_GR1_REGNUM);
2404
2405 store_unsigned_integer (buf, 8, faddr);
2406 store_unsigned_integer (buf + 8, 8, global_pointer);
2407
2408 write_memory (fdesc, buf, 16);
2409 }
2410
2411 return fdesc;
2412 }
2413
2414 /* Use the following routine when printing out function pointers
2415 so the user can see the function address rather than just the
2416 function descriptor. */
2417 static CORE_ADDR
2418 ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
2419 struct target_ops *targ)
2420 {
2421 struct obj_section *s;
2422
2423 s = find_pc_section (addr);
2424
2425 /* check if ADDR points to a function descriptor. */
2426 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2427 return read_memory_unsigned_integer (addr, 8);
2428
2429 return addr;
2430 }
2431
2432 static CORE_ADDR
2433 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2434 {
2435 return sp & ~0xfLL;
2436 }
2437
2438 static CORE_ADDR
2439 ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2440 struct regcache *regcache, CORE_ADDR bp_addr,
2441 int nargs, struct value **args, CORE_ADDR sp,
2442 int struct_return, CORE_ADDR struct_addr)
2443 {
2444 int argno;
2445 struct value *arg;
2446 struct type *type;
2447 int len, argoffset;
2448 int nslots, rseslots, memslots, slotnum, nfuncargs;
2449 int floatreg;
2450 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
2451
2452 nslots = 0;
2453 nfuncargs = 0;
2454 /* Count the number of slots needed for the arguments. */
2455 for (argno = 0; argno < nargs; argno++)
2456 {
2457 arg = args[argno];
2458 type = check_typedef (VALUE_TYPE (arg));
2459 len = TYPE_LENGTH (type);
2460
2461 if ((nslots & 1) && slot_alignment_is_next_even (type))
2462 nslots++;
2463
2464 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
2465 nfuncargs++;
2466
2467 nslots += (len + 7) / 8;
2468 }
2469
2470 /* Divvy up the slots between the RSE and the memory stack. */
2471 rseslots = (nslots > 8) ? 8 : nslots;
2472 memslots = nslots - rseslots;
2473
2474 /* Allocate a new RSE frame. */
2475 cfm = read_register (IA64_CFM_REGNUM);
2476
2477 bsp = read_register (IA64_BSP_REGNUM);
2478 new_bsp = rse_address_add (bsp, rseslots);
2479 write_register (IA64_BSP_REGNUM, new_bsp);
2480
2481 pfs = read_register (IA64_PFS_REGNUM);
2482 pfs &= 0xc000000000000000LL;
2483 pfs |= (cfm & 0xffffffffffffLL);
2484 write_register (IA64_PFS_REGNUM, pfs);
2485
2486 cfm &= 0xc000000000000000LL;
2487 cfm |= rseslots;
2488 write_register (IA64_CFM_REGNUM, cfm);
2489
2490 /* We will attempt to find function descriptors in the .opd segment,
2491 but if we can't we'll construct them ourselves. That being the
2492 case, we'll need to reserve space on the stack for them. */
2493 funcdescaddr = sp - nfuncargs * 16;
2494 funcdescaddr &= ~0xfLL;
2495
2496 /* Adjust the stack pointer to it's new value. The calling conventions
2497 require us to have 16 bytes of scratch, plus whatever space is
2498 necessary for the memory slots and our function descriptors. */
2499 sp = sp - 16 - (memslots + nfuncargs) * 8;
2500 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
2501
2502 /* Place the arguments where they belong. The arguments will be
2503 either placed in the RSE backing store or on the memory stack.
2504 In addition, floating point arguments or HFAs are placed in
2505 floating point registers. */
2506 slotnum = 0;
2507 floatreg = IA64_FR8_REGNUM;
2508 for (argno = 0; argno < nargs; argno++)
2509 {
2510 struct type *float_elt_type;
2511
2512 arg = args[argno];
2513 type = check_typedef (VALUE_TYPE (arg));
2514 len = TYPE_LENGTH (type);
2515
2516 /* Special handling for function parameters. */
2517 if (len == 8
2518 && TYPE_CODE (type) == TYPE_CODE_PTR
2519 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
2520 {
2521 char val_buf[8];
2522
2523 store_unsigned_integer (val_buf, 8,
2524 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
2525 &funcdescaddr));
2526 if (slotnum < rseslots)
2527 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2528 else
2529 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2530 slotnum++;
2531 continue;
2532 }
2533
2534 /* Normal slots. */
2535
2536 /* Skip odd slot if necessary... */
2537 if ((slotnum & 1) && slot_alignment_is_next_even (type))
2538 slotnum++;
2539
2540 argoffset = 0;
2541 while (len > 0)
2542 {
2543 char val_buf[8];
2544
2545 memset (val_buf, 0, 8);
2546 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
2547
2548 if (slotnum < rseslots)
2549 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2550 else
2551 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2552
2553 argoffset += 8;
2554 len -= 8;
2555 slotnum++;
2556 }
2557
2558 /* Handle floating point types (including HFAs). */
2559 float_elt_type = is_float_or_hfa_type (type);
2560 if (float_elt_type != NULL)
2561 {
2562 argoffset = 0;
2563 len = TYPE_LENGTH (type);
2564 while (len > 0 && floatreg < IA64_FR16_REGNUM)
2565 {
2566 char to[MAX_REGISTER_SIZE];
2567 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
2568 to, builtin_type_ia64_ext);
2569 regcache_cooked_write (regcache, floatreg, (void *)to);
2570 floatreg++;
2571 argoffset += TYPE_LENGTH (float_elt_type);
2572 len -= TYPE_LENGTH (float_elt_type);
2573 }
2574 }
2575 }
2576
2577 /* Store the struct return value in r8 if necessary. */
2578 if (struct_return)
2579 {
2580 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
2581 }
2582
2583 global_pointer = FIND_GLOBAL_POINTER (func_addr);
2584
2585 if (global_pointer != 0)
2586 write_register (IA64_GR1_REGNUM, global_pointer);
2587
2588 write_register (IA64_BR0_REGNUM, bp_addr);
2589
2590 write_register (sp_regnum, sp);
2591
2592 return sp;
2593 }
2594
2595 static struct frame_id
2596 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2597 {
2598 char buf[8];
2599 CORE_ADDR sp, bsp;
2600
2601 frame_unwind_register (next_frame, sp_regnum, buf);
2602 sp = extract_unsigned_integer (buf, 8);
2603
2604 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2605 bsp = extract_unsigned_integer (buf, 8);
2606
2607 if (gdbarch_debug >= 1)
2608 fprintf_unfiltered (gdb_stdlog,
2609 "dummy frame id: code %lx, stack %lx, special %lx\n",
2610 frame_pc_unwind (next_frame), sp, bsp);
2611
2612 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
2613 }
2614
2615 static CORE_ADDR
2616 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2617 {
2618 char buf[8];
2619 CORE_ADDR ip, psr, pc;
2620
2621 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2622 ip = extract_unsigned_integer (buf, 8);
2623 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2624 psr = extract_unsigned_integer (buf, 8);
2625
2626 pc = (ip & ~0xf) | ((psr >> 41) & 3);
2627 return pc;
2628 }
2629
2630 static void
2631 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
2632 {
2633 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2634 {
2635 char to[MAX_REGISTER_SIZE];
2636 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
2637 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
2638 target_store_registers (IA64_FR8_REGNUM);
2639 }
2640 else
2641 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
2642 }
2643
2644 static void
2645 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
2646 struct regcache *regcache,
2647 CORE_ADDR memaddr, int nr_bytes,
2648 CORE_ADDR *targ_addr, int *targ_len)
2649 {
2650 *targ_addr = memaddr;
2651 *targ_len = nr_bytes;
2652 }
2653
2654 static void
2655 process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2656 {
2657 int *os_ident_ptr = obj;
2658 const char *name;
2659 unsigned int sectsize;
2660
2661 name = bfd_get_section_name (abfd, sect);
2662 sectsize = bfd_section_size (abfd, sect);
2663 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2664 {
2665 unsigned int name_length, data_length, note_type;
2666 char *note = alloca (sectsize);
2667
2668 bfd_get_section_contents (abfd, sect, note,
2669 (file_ptr) 0, (bfd_size_type) sectsize);
2670
2671 name_length = bfd_h_get_32 (abfd, note);
2672 data_length = bfd_h_get_32 (abfd, note + 4);
2673 note_type = bfd_h_get_32 (abfd, note + 8);
2674
2675 if (name_length == 4 && data_length == 16 && note_type == 1
2676 && strcmp (note + 12, "GNU") == 0)
2677 {
2678 int os_number = bfd_h_get_32 (abfd, note + 16);
2679
2680 /* The case numbers are from abi-tags in glibc. */
2681 switch (os_number)
2682 {
2683 case 0 :
2684 *os_ident_ptr = ELFOSABI_LINUX;
2685 break;
2686 case 1 :
2687 *os_ident_ptr = ELFOSABI_HURD;
2688 break;
2689 case 2 :
2690 *os_ident_ptr = ELFOSABI_SOLARIS;
2691 break;
2692 default :
2693 internal_error (__FILE__, __LINE__,
2694 "process_note_abi_sections: unknown OS number %d", os_number);
2695 break;
2696 }
2697 }
2698 }
2699 }
2700
2701 static int
2702 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
2703 {
2704 info->bytes_per_line = SLOT_MULTIPLIER;
2705 return print_insn_ia64 (memaddr, info);
2706 }
2707
2708 static struct gdbarch *
2709 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2710 {
2711 struct gdbarch *gdbarch;
2712 struct gdbarch_tdep *tdep;
2713 int os_ident;
2714
2715 if (info.abfd != NULL
2716 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2717 {
2718 os_ident = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2719
2720 /* If os_ident is 0, it is not necessarily the case that we're
2721 on a SYSV system. (ELFOSABI_NONE is defined to be 0.)
2722 GNU/Linux uses a note section to record OS/ABI info, but
2723 leaves e_ident[EI_OSABI] zero. So we have to check for note
2724 sections too. */
2725 if (os_ident == 0)
2726 {
2727 bfd_map_over_sections (info.abfd,
2728 process_note_abi_tag_sections,
2729 &os_ident);
2730 }
2731 }
2732 else
2733 os_ident = -1;
2734
2735 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2736 arches != NULL;
2737 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2738 {
2739 tdep = gdbarch_tdep (arches->gdbarch);
2740 if (tdep &&tdep->os_ident == os_ident)
2741 return arches->gdbarch;
2742 }
2743
2744 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2745 gdbarch = gdbarch_alloc (&info, tdep);
2746 tdep->os_ident = os_ident;
2747
2748 /* Set the method of obtaining the sigcontext addresses at which
2749 registers are saved. The method of checking to see if
2750 native_find_global_pointer is nonzero to indicate that we're
2751 on AIX is kind of hokey, but I can't think of a better way
2752 to do it. */
2753 if (os_ident == ELFOSABI_LINUX)
2754 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
2755 else if (native_find_global_pointer != 0)
2756 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
2757 else
2758 tdep->sigcontext_register_address = 0;
2759
2760 /* We know that GNU/Linux won't have to resort to the
2761 native_find_global_pointer hackery. But that's the only one we
2762 know about so far, so if native_find_global_pointer is set to
2763 something non-zero, then use it. Otherwise fall back to using
2764 generic_elf_find_global_pointer. This arrangement should (in
2765 theory) allow us to cross debug GNU/Linux binaries from an AIX
2766 machine. */
2767 if (os_ident == ELFOSABI_LINUX)
2768 tdep->find_global_pointer = generic_elf_find_global_pointer;
2769 else if (native_find_global_pointer != 0)
2770 tdep->find_global_pointer = native_find_global_pointer;
2771 else
2772 tdep->find_global_pointer = generic_elf_find_global_pointer;
2773
2774 /* Define the ia64 floating-point format to gdb. */
2775 builtin_type_ia64_ext =
2776 init_type (TYPE_CODE_FLT, 128 / 8,
2777 0, "builtin_type_ia64_ext", NULL);
2778 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
2779
2780 set_gdbarch_short_bit (gdbarch, 16);
2781 set_gdbarch_int_bit (gdbarch, 32);
2782 set_gdbarch_long_bit (gdbarch, 64);
2783 set_gdbarch_long_long_bit (gdbarch, 64);
2784 set_gdbarch_float_bit (gdbarch, 32);
2785 set_gdbarch_double_bit (gdbarch, 64);
2786 set_gdbarch_long_double_bit (gdbarch, 128);
2787 set_gdbarch_ptr_bit (gdbarch, 64);
2788
2789 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
2790 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
2791 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
2792 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
2793
2794 set_gdbarch_register_name (gdbarch, ia64_register_name);
2795 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2796 gets a number of extra failures. */
2797 set_gdbarch_deprecated_register_size (gdbarch, 8);
2798 set_gdbarch_register_type (gdbarch, ia64_register_type);
2799
2800 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
2801 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
2802 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
2803 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
2804 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
2805 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
2806 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
2807
2808 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
2809
2810 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
2811 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
2812
2813 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
2814 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
2815
2816 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
2817 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
2818 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
2819 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
2820 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
2821
2822 /* Settings for calling functions in the inferior. */
2823 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
2824 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
2825 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
2826
2827 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
2828 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
2829 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
2830 frame_base_set_default (gdbarch, &ia64_frame_base);
2831
2832 /* Settings that should be unnecessary. */
2833 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2834
2835 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2836 set_gdbarch_function_start_offset (gdbarch, 0);
2837 set_gdbarch_frame_args_skip (gdbarch, 0);
2838
2839 set_gdbarch_remote_translate_xfer_address (
2840 gdbarch, ia64_remote_translate_xfer_address);
2841
2842 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
2843 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
2844
2845 return gdbarch;
2846 }
2847
2848 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
2849
2850 void
2851 _initialize_ia64_tdep (void)
2852 {
2853 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
2854 }
GDB Binutils - Deliverables
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