* m32c-tdep.c (m32c_decode_srcdest4): Initialize fields in sd
[deliverable/binutils-gdb.git] / gdb / m32c-tdep.c
1 /* Renesas M32C target-dependent code for GDB, the GNU debugger.
2
3 Copyright 2004, 2005 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23
24 #include <stdarg.h>
25
26 #if defined (HAVE_STRING_H)
27 #include <string.h>
28 #endif
29
30 #include "gdb_assert.h"
31 #include "elf-bfd.h"
32 #include "elf/m32c.h"
33 #include "gdb/sim-m32c.h"
34 #include "dis-asm.h"
35 #include "gdbtypes.h"
36 #include "regcache.h"
37 #include "arch-utils.h"
38 #include "frame.h"
39 #include "frame-unwind.h"
40 #include "dwarf2-frame.h"
41 #include "dwarf2expr.h"
42 #include "symtab.h"
43 #include "gdbcore.h"
44 #include "value.h"
45 #include "reggroups.h"
46 #include "prologue-value.h"
47 #include "target.h"
48
49 \f
50 /* The m32c tdep structure. */
51
52 static struct reggroup *m32c_dma_reggroup;
53
54 struct m32c_reg;
55
56 /* The type of a function that moves the value of REG between CACHE or
57 BUF --- in either direction. */
58 typedef void (m32c_move_reg_t) (struct m32c_reg *reg,
59 struct regcache *cache,
60 void *buf);
61
62 struct m32c_reg
63 {
64 /* The name of this register. */
65 const char *name;
66
67 /* Its type. */
68 struct type *type;
69
70 /* The architecture this register belongs to. */
71 struct gdbarch *arch;
72
73 /* Its GDB register number. */
74 int num;
75
76 /* Its sim register number. */
77 int sim_num;
78
79 /* Its DWARF register number, or -1 if it doesn't have one. */
80 int dwarf_num;
81
82 /* Register group memberships. */
83 unsigned int general_p : 1;
84 unsigned int dma_p : 1;
85 unsigned int system_p : 1;
86 unsigned int save_restore_p : 1;
87
88 /* Functions to read its value from a regcache, and write its value
89 to a regcache. */
90 m32c_move_reg_t *read, *write;
91
92 /* Data for READ and WRITE functions. The exact meaning depends on
93 the specific functions selected; see the comments for those
94 functions. */
95 struct m32c_reg *rx, *ry;
96 int n;
97 };
98
99
100 /* An overestimate of the number of raw and pseudoregisters we will
101 have. The exact answer depends on the variant of the architecture
102 at hand, but we can use this to declare statically allocated
103 arrays, and bump it up when needed. */
104 #define M32C_MAX_NUM_REGS (75)
105
106 /* The largest assigned DWARF register number. */
107 #define M32C_MAX_DWARF_REGNUM (40)
108
109
110 struct gdbarch_tdep
111 {
112 /* All the registers for this variant, indexed by GDB register
113 number, and the number of registers present. */
114 struct m32c_reg regs[M32C_MAX_NUM_REGS];
115
116 /* The number of valid registers. */
117 int num_regs;
118
119 /* Interesting registers. These are pointers into REGS. */
120 struct m32c_reg *pc, *flg;
121 struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1;
122 struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0;
123 struct m32c_reg *sb, *fb, *sp;
124
125 /* A table indexed by DWARF register numbers, pointing into
126 REGS. */
127 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1];
128
129 /* Types for this architecture. We can't use the builtin_type_foo
130 types, because they're not initialized when building a gdbarch
131 structure. */
132 struct type *voyd, *ptr_voyd, *func_voyd;
133 struct type *uint8, *uint16;
134 struct type *int8, *int16, *int32, *int64;
135
136 /* The types for data address and code address registers. */
137 struct type *data_addr_reg_type, *code_addr_reg_type;
138
139 /* The number of bytes a return address pushed by a 'jsr' instruction
140 occupies on the stack. */
141 int ret_addr_bytes;
142
143 /* The number of bytes an address register occupies on the stack
144 when saved by an 'enter' or 'pushm' instruction. */
145 int push_addr_bytes;
146 };
147
148 \f
149 /* Types. */
150
151 static void
152 make_types (struct gdbarch *arch)
153 {
154 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
155 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
156 int data_addr_reg_bits, code_addr_reg_bits;
157 char type_name[50];
158
159 #if 0
160 /* This is used to clip CORE_ADDR values, so this value is
161 appropriate both on the m32c, where pointers are 32 bits long,
162 and on the m16c, where pointers are sixteen bits long, but there
163 may be code above the 64k boundary. */
164 set_gdbarch_addr_bit (arch, 24);
165 #else
166 /* GCC uses 32 bits for addrs in the dwarf info, even though
167 only 16/24 bits are used. Setting addr_bit to 24 causes
168 errors in reading the dwarf addresses. */
169 set_gdbarch_addr_bit (arch, 32);
170 #endif
171
172 set_gdbarch_int_bit (arch, 16);
173 switch (mach)
174 {
175 case bfd_mach_m16c:
176 data_addr_reg_bits = 16;
177 code_addr_reg_bits = 24;
178 set_gdbarch_ptr_bit (arch, 16);
179 tdep->ret_addr_bytes = 3;
180 tdep->push_addr_bytes = 2;
181 break;
182
183 case bfd_mach_m32c:
184 data_addr_reg_bits = 24;
185 code_addr_reg_bits = 24;
186 set_gdbarch_ptr_bit (arch, 32);
187 tdep->ret_addr_bytes = 4;
188 tdep->push_addr_bytes = 4;
189 break;
190
191 default:
192 gdb_assert (0);
193 }
194
195 /* The builtin_type_mumble variables are sometimes uninitialized when
196 this is called, so we avoid using them. */
197 tdep->voyd = init_type (TYPE_CODE_VOID, 1, 0, "void", NULL);
198 tdep->ptr_voyd = init_type (TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / 8,
199 TYPE_FLAG_UNSIGNED, NULL, NULL);
200 TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd;
201 tdep->func_voyd = lookup_function_type (tdep->voyd);
202
203 sprintf (type_name, "%s_data_addr_t",
204 gdbarch_bfd_arch_info (arch)->printable_name);
205 tdep->data_addr_reg_type
206 = init_type (TYPE_CODE_PTR, data_addr_reg_bits / 8,
207 TYPE_FLAG_UNSIGNED, xstrdup (type_name), NULL);
208 TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd;
209
210 sprintf (type_name, "%s_code_addr_t",
211 gdbarch_bfd_arch_info (arch)->printable_name);
212 tdep->code_addr_reg_type
213 = init_type (TYPE_CODE_PTR, code_addr_reg_bits / 8,
214 TYPE_FLAG_UNSIGNED, xstrdup (type_name), NULL);
215 TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd;
216
217 tdep->uint8 = init_type (TYPE_CODE_INT, 1, TYPE_FLAG_UNSIGNED,
218 "uint8_t", NULL);
219 tdep->uint16 = init_type (TYPE_CODE_INT, 2, TYPE_FLAG_UNSIGNED,
220 "uint16_t", NULL);
221 tdep->int8 = init_type (TYPE_CODE_INT, 1, 0, "int8_t", NULL);
222 tdep->int16 = init_type (TYPE_CODE_INT, 2, 0, "int16_t", NULL);
223 tdep->int32 = init_type (TYPE_CODE_INT, 4, 0, "int32_t", NULL);
224 tdep->int64 = init_type (TYPE_CODE_INT, 8, 0, "int64_t", NULL);
225 }
226
227
228 \f
229 /* Register set. */
230
231 static const char *
232 m32c_register_name (int num)
233 {
234 return gdbarch_tdep (current_gdbarch)->regs[num].name;
235 }
236
237
238 static struct type *
239 m32c_register_type (struct gdbarch *arch, int reg_nr)
240 {
241 return gdbarch_tdep (arch)->regs[reg_nr].type;
242 }
243
244
245 static int
246 m32c_register_sim_regno (int reg_nr)
247 {
248 return gdbarch_tdep (current_gdbarch)->regs[reg_nr].sim_num;
249 }
250
251
252 static int
253 m32c_debug_info_reg_to_regnum (int reg_nr)
254 {
255 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
256 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM
257 && tdep->dwarf_regs[reg_nr])
258 return tdep->dwarf_regs[reg_nr]->num;
259 else
260 /* The DWARF CFI code expects to see -1 for invalid register
261 numbers. */
262 return -1;
263 }
264
265
266 int
267 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
268 struct reggroup *group)
269 {
270 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
271 struct m32c_reg *reg = &tdep->regs[regnum];
272
273 /* The anonymous raw registers aren't in any groups. */
274 if (! reg->name)
275 return 0;
276
277 if (group == all_reggroup)
278 return 1;
279
280 if (group == general_reggroup
281 && reg->general_p)
282 return 1;
283
284 if (group == m32c_dma_reggroup
285 && reg->dma_p)
286 return 1;
287
288 if (group == system_reggroup
289 && reg->system_p)
290 return 1;
291
292 /* Since the m32c DWARF register numbers refer to cooked registers, not
293 raw registers, and frame_pop depends on the save and restore groups
294 containing registers the DWARF CFI will actually mention, our save
295 and restore groups are cooked registers, not raw registers. (This is
296 why we can't use the default reggroup function.) */
297 if ((group == save_reggroup
298 || group == restore_reggroup)
299 && reg->save_restore_p)
300 return 1;
301
302 return 0;
303 }
304
305
306 /* Register move functions. We declare them here using
307 m32c_move_reg_t to check the types. */
308 static m32c_move_reg_t m32c_raw_read, m32c_raw_write;
309 static m32c_move_reg_t m32c_banked_read, m32c_banked_write;
310 static m32c_move_reg_t m32c_sb_read, m32c_sb_write;
311 static m32c_move_reg_t m32c_part_read, m32c_part_write;
312 static m32c_move_reg_t m32c_cat_read, m32c_cat_write;
313 static m32c_move_reg_t m32c_r3r2r1r0_read, m32c_r3r2r1r0_write;
314
315
316 /* Copy the value of the raw register REG from CACHE to BUF. */
317 static void
318 m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
319 {
320 regcache_raw_read (cache, reg->num, buf);
321 }
322
323
324 /* Copy the value of the raw register REG from BUF to CACHE. */
325 static void
326 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
327 {
328 regcache_raw_write (cache, reg->num, (const void *) buf);
329 }
330
331
332 /* Return the value of the 'flg' register in CACHE. */
333 static int
334 m32c_read_flg (struct regcache *cache)
335 {
336 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache));
337 ULONGEST flg;
338 regcache_raw_read_unsigned (cache, tdep->flg->num, &flg);
339 return flg & 0xffff;
340 }
341
342
343 /* Evaluate the real register number of a banked register. */
344 static struct m32c_reg *
345 m32c_banked_register (struct m32c_reg *reg, struct regcache *cache)
346 {
347 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx);
348 }
349
350
351 /* Move the value of a banked register from CACHE to BUF.
352 If the value of the 'flg' register in CACHE has any of the bits
353 masked in REG->n set, then read REG->ry. Otherwise, read
354 REG->rx. */
355 static void
356 m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
357 {
358 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
359 regcache_raw_read (cache, bank_reg->num, buf);
360 }
361
362
363 /* Move the value of a banked register from BUF to CACHE.
364 If the value of the 'flg' register in CACHE has any of the bits
365 masked in REG->n set, then write REG->ry. Otherwise, write
366 REG->rx. */
367 static void
368 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
369 {
370 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
371 regcache_raw_write (cache, bank_reg->num, (const void *) buf);
372 }
373
374
375 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a
376 banked register; on bfd_mach_m16c, it's not. */
377 static void
378 m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
379 {
380 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
381 m32c_raw_read (reg->rx, cache, buf);
382 else
383 m32c_banked_read (reg, cache, buf);
384 }
385
386
387 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a
388 banked register; on bfd_mach_m16c, it's not. */
389 static void
390 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
391 {
392 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
393 m32c_raw_write (reg->rx, cache, buf);
394 else
395 m32c_banked_write (reg, cache, buf);
396 }
397
398
399 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P
400 and *LEN_P to the offset and length, in bytes, of the part REG
401 occupies in its underlying register. The offset is from the
402 lower-addressed end, regardless of the architecture's endianness.
403 (The M32C family is always little-endian, but let's keep those
404 assumptions out of here.) */
405 static void
406 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p)
407 {
408 /* The length of the containing register, of which REG is one part. */
409 int containing_len = TYPE_LENGTH (reg->rx->type);
410
411 /* The length of one "element" in our imaginary array. */
412 int elt_len = TYPE_LENGTH (reg->type);
413
414 /* The offset of REG's "element" from the least significant end of
415 the containing register. */
416 int elt_offset = reg->n * elt_len;
417
418 /* If we extend off the end, trim the length of the element. */
419 if (elt_offset + elt_len > containing_len)
420 {
421 elt_len = containing_len - elt_offset;
422 /* We shouldn't be declaring partial registers that go off the
423 end of their containing registers. */
424 gdb_assert (elt_len > 0);
425 }
426
427 /* Flip the offset around if we're big-endian. */
428 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
429 elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len;
430
431 *offset_p = elt_offset;
432 *len_p = elt_len;
433 }
434
435
436 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE
437 to BUF. Treating the value of the register REG->rx as an array of
438 REG->type values, where higher indices refer to more significant
439 bits, read the value of the REG->n'th element. */
440 static void
441 m32c_part_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
442 {
443 int offset, len;
444 memset (buf, 0, TYPE_LENGTH (reg->type));
445 m32c_find_part (reg, &offset, &len);
446 regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf);
447 }
448
449
450 /* Move the value of a banked register from BUF to CACHE.
451 Treating the value of the register REG->rx as an array of REG->type
452 values, where higher indices refer to more significant bits, write
453 the value of the REG->n'th element. */
454 static void
455 m32c_part_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
456 {
457 int offset, len;
458 m32c_find_part (reg, &offset, &len);
459 regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf);
460 }
461
462
463 /* Move the value of REG from CACHE to BUF. REG's value is the
464 concatenation of the values of the registers REG->rx and REG->ry,
465 with REG->rx contributing the more significant bits. */
466 static void
467 m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
468 {
469 int high_bytes = TYPE_LENGTH (reg->rx->type);
470 int low_bytes = TYPE_LENGTH (reg->ry->type);
471 /* For address arithmetic. */
472 unsigned char *cbuf = buf;
473
474 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
475
476 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
477 {
478 regcache_cooked_read (cache, reg->rx->num, cbuf);
479 regcache_cooked_read (cache, reg->ry->num, cbuf + high_bytes);
480 }
481 else
482 {
483 regcache_cooked_read (cache, reg->rx->num, cbuf + low_bytes);
484 regcache_cooked_read (cache, reg->ry->num, cbuf);
485 }
486 }
487
488
489 /* Move the value of REG from CACHE to BUF. REG's value is the
490 concatenation of the values of the registers REG->rx and REG->ry,
491 with REG->rx contributing the more significant bits. */
492 static void
493 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
494 {
495 int high_bytes = TYPE_LENGTH (reg->rx->type);
496 int low_bytes = TYPE_LENGTH (reg->ry->type);
497 /* For address arithmetic. */
498 unsigned char *cbuf = buf;
499
500 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
501
502 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
503 {
504 regcache_cooked_write (cache, reg->rx->num, cbuf);
505 regcache_cooked_write (cache, reg->ry->num, cbuf + high_bytes);
506 }
507 else
508 {
509 regcache_cooked_write (cache, reg->rx->num, cbuf + low_bytes);
510 regcache_cooked_write (cache, reg->ry->num, cbuf);
511 }
512 }
513
514
515 /* Copy the value of the raw register REG from CACHE to BUF. REG is
516 the concatenation (from most significant to least) of r3, r2, r1,
517 and r0. */
518 static void
519 m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
520 {
521 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
522 int len = TYPE_LENGTH (tdep->r0->type);
523
524 /* For address arithmetic. */
525 unsigned char *cbuf = buf;
526
527 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
528 {
529 regcache_cooked_read (cache, tdep->r0->num, cbuf + len * 3);
530 regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 2);
531 regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 1);
532 regcache_cooked_read (cache, tdep->r3->num, cbuf);
533 }
534 else
535 {
536 regcache_cooked_read (cache, tdep->r0->num, cbuf);
537 regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 1);
538 regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 2);
539 regcache_cooked_read (cache, tdep->r3->num, cbuf + len * 3);
540 }
541 }
542
543
544 /* Copy the value of the raw register REG from BUF to CACHE. REG is
545 the concatenation (from most significant to least) of r3, r2, r1,
546 and r0. */
547 static void
548 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
549 {
550 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
551 int len = TYPE_LENGTH (tdep->r0->type);
552
553 /* For address arithmetic. */
554 unsigned char *cbuf = buf;
555
556 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
557 {
558 regcache_cooked_write (cache, tdep->r0->num, cbuf + len * 3);
559 regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 2);
560 regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 1);
561 regcache_cooked_write (cache, tdep->r3->num, cbuf);
562 }
563 else
564 {
565 regcache_cooked_write (cache, tdep->r0->num, cbuf);
566 regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 1);
567 regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 2);
568 regcache_cooked_write (cache, tdep->r3->num, cbuf + len * 3);
569 }
570 }
571
572
573 static void
574 m32c_pseudo_register_read (struct gdbarch *arch,
575 struct regcache *cache,
576 int cookednum,
577 gdb_byte *buf)
578 {
579 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
580 struct m32c_reg *reg;
581
582 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
583 gdb_assert (arch == get_regcache_arch (cache));
584 gdb_assert (arch == tdep->regs[cookednum].arch);
585 reg = &tdep->regs[cookednum];
586
587 reg->read (reg, cache, buf);
588 }
589
590
591 static void
592 m32c_pseudo_register_write (struct gdbarch *arch,
593 struct regcache *cache,
594 int cookednum,
595 const gdb_byte *buf)
596 {
597 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
598 struct m32c_reg *reg;
599
600 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
601 gdb_assert (arch == get_regcache_arch (cache));
602 gdb_assert (arch == tdep->regs[cookednum].arch);
603 reg = &tdep->regs[cookednum];
604
605 reg->write (reg, cache, (void *) buf);
606 }
607
608
609 /* Add a register with the given fields to the end of ARCH's table.
610 Return a pointer to the newly added register. */
611 static struct m32c_reg *
612 add_reg (struct gdbarch *arch,
613 const char *name,
614 struct type *type,
615 int sim_num,
616 m32c_move_reg_t *read,
617 m32c_move_reg_t *write,
618 struct m32c_reg *rx,
619 struct m32c_reg *ry,
620 int n)
621 {
622 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
623 struct m32c_reg *r = &tdep->regs[tdep->num_regs];
624
625 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS);
626
627 r->name = name;
628 r->type = type;
629 r->arch = arch;
630 r->num = tdep->num_regs;
631 r->sim_num = sim_num;
632 r->dwarf_num = -1;
633 r->general_p = 0;
634 r->dma_p = 0;
635 r->system_p = 0;
636 r->save_restore_p = 0;
637 r->read = read;
638 r->write = write;
639 r->rx = rx;
640 r->ry = ry;
641 r->n = n;
642
643 tdep->num_regs++;
644
645 return r;
646 }
647
648
649 /* Record NUM as REG's DWARF register number. */
650 static void
651 set_dwarf_regnum (struct m32c_reg *reg, int num)
652 {
653 gdb_assert (num < M32C_MAX_NUM_REGS);
654
655 /* Update the reg->DWARF mapping. Only count the first number
656 assigned to this register. */
657 if (reg->dwarf_num == -1)
658 reg->dwarf_num = num;
659
660 /* Update the DWARF->reg mapping. */
661 gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg;
662 }
663
664
665 /* Mark REG as a general-purpose register, and return it. */
666 static struct m32c_reg *
667 mark_general (struct m32c_reg *reg)
668 {
669 reg->general_p = 1;
670 return reg;
671 }
672
673
674 /* Mark REG as a DMA register, and return it. */
675 static struct m32c_reg *
676 mark_dma (struct m32c_reg *reg)
677 {
678 reg->dma_p = 1;
679 return reg;
680 }
681
682
683 /* Mark REG as a SYSTEM register, and return it. */
684 static struct m32c_reg *
685 mark_system (struct m32c_reg *reg)
686 {
687 reg->system_p = 1;
688 return reg;
689 }
690
691
692 /* Mark REG as a save-restore register, and return it. */
693 static struct m32c_reg *
694 mark_save_restore (struct m32c_reg *reg)
695 {
696 reg->save_restore_p = 1;
697 return reg;
698 }
699
700
701 #define FLAGBIT_B 0x0010
702 #define FLAGBIT_U 0x0080
703
704 /* Handy macros for declaring registers. These all evaluate to
705 pointers to the register declared. Macros that define two
706 registers evaluate to a pointer to the first. */
707
708 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */
709 #define R(name, type, sim_num) \
710 (add_reg (arch, (name), (type), (sim_num), \
711 m32c_raw_read, m32c_raw_write, NULL, NULL, 0))
712
713 /* The simulator register number for a raw register named NAME. */
714 #define SIM(name) (m32c_sim_reg_ ## name)
715
716 /* A raw unsigned 16-bit data register named NAME.
717 NAME should be an identifier, not a string. */
718 #define R16U(name) \
719 (R(#name, tdep->uint16, SIM (name)))
720
721 /* A raw data address register named NAME.
722 NAME should be an identifier, not a string. */
723 #define RA(name) \
724 (R(#name, tdep->data_addr_reg_type, SIM (name)))
725
726 /* A raw code address register named NAME. NAME should
727 be an identifier, not a string. */
728 #define RC(name) \
729 (R(#name, tdep->code_addr_reg_type, SIM (name)))
730
731 /* A pair of raw registers named NAME0 and NAME1, with type TYPE.
732 NAME should be an identifier, not a string. */
733 #define RP(name, type) \
734 (R(#name "0", (type), SIM (name ## 0)), \
735 R(#name "1", (type), SIM (name ## 1)) - 1)
736
737 /* A raw banked general-purpose data register named NAME.
738 NAME should be an identifier, not a string. */
739 #define RBD(name) \
740 (R(NULL, tdep->int16, SIM (name ## _bank0)), \
741 R(NULL, tdep->int16, SIM (name ## _bank1)) - 1)
742
743 /* A raw banked data address register named NAME.
744 NAME should be an identifier, not a string. */
745 #define RBA(name) \
746 (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \
747 R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1)
748
749 /* A cooked register named NAME referring to a raw banked register
750 from the bank selected by the current value of FLG. RAW_PAIR
751 should be a pointer to the first register in the banked pair.
752 NAME must be an identifier, not a string. */
753 #define CB(name, raw_pair) \
754 (add_reg (arch, #name, (raw_pair)->type, 0, \
755 m32c_banked_read, m32c_banked_write, \
756 (raw_pair), (raw_pair + 1), FLAGBIT_B))
757
758 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that
759 access the top and bottom halves of the register pointed to by
760 NAME. NAME should be an identifier. */
761 #define CHL(name, type) \
762 (add_reg (arch, #name "h", (type), 0, \
763 m32c_part_read, m32c_part_write, name, NULL, 1), \
764 add_reg (arch, #name "l", (type), 0, \
765 m32c_part_read, m32c_part_write, name, NULL, 0) - 1)
766
767 /* A register constructed by concatenating the two registers HIGH and
768 LOW, whose name is HIGHLOW and whose type is TYPE. */
769 #define CCAT(high, low, type) \
770 (add_reg (arch, #high #low, (type), 0, \
771 m32c_cat_read, m32c_cat_write, (high), (low), 0))
772
773 /* Abbreviations for marking register group membership. */
774 #define G(reg) (mark_general (reg))
775 #define S(reg) (mark_system (reg))
776 #define DMA(reg) (mark_dma (reg))
777
778
779 /* Construct the register set for ARCH. */
780 static void
781 make_regs (struct gdbarch *arch)
782 {
783 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
784 int mach = gdbarch_bfd_arch_info (arch)->mach;
785
786 struct m32c_reg *raw_r0_pair = RBD (r0);
787 struct m32c_reg *raw_r1_pair = RBD (r1);
788 struct m32c_reg *raw_r2_pair = RBD (r2);
789 struct m32c_reg *raw_r3_pair = RBD (r3);
790 struct m32c_reg *raw_a0_pair = RBA (a0);
791 struct m32c_reg *raw_a1_pair = RBA (a1);
792 struct m32c_reg *raw_fb_pair = RBA (fb);
793
794 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
795 We always declare both raw registers, and deal with the distinction
796 in the pseudoregister. */
797 struct m32c_reg *raw_sb_pair = RBA (sb);
798
799 struct m32c_reg *usp = S (RA (usp));
800 struct m32c_reg *isp = S (RA (isp));
801 struct m32c_reg *intb = S (RC (intb));
802 struct m32c_reg *pc = G (RC (pc));
803 struct m32c_reg *flg = G (R16U (flg));
804
805 if (mach == bfd_mach_m32c)
806 {
807 struct m32c_reg *svf = S (R16U (svf));
808 struct m32c_reg *svp = S (RC (svp));
809 struct m32c_reg *vct = S (RC (vct));
810
811 struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8));
812 struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16));
813 struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16));
814 struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type));
815 struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type));
816 struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type));
817 }
818
819 int num_raw_regs = tdep->num_regs;
820
821 struct m32c_reg *r0 = G (CB (r0, raw_r0_pair));
822 struct m32c_reg *r1 = G (CB (r1, raw_r1_pair));
823 struct m32c_reg *r2 = G (CB (r2, raw_r2_pair));
824 struct m32c_reg *r3 = G (CB (r3, raw_r3_pair));
825 struct m32c_reg *a0 = G (CB (a0, raw_a0_pair));
826 struct m32c_reg *a1 = G (CB (a1, raw_a1_pair));
827 struct m32c_reg *fb = G (CB (fb, raw_fb_pair));
828
829 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
830 Specify custom read/write functions that do the right thing. */
831 struct m32c_reg *sb
832 = G (add_reg (arch, "sb", raw_sb_pair->type, 0,
833 m32c_sb_read, m32c_sb_write,
834 raw_sb_pair, raw_sb_pair + 1, 0));
835
836 /* The current sp is either usp or isp, depending on the value of
837 the FLG register's U bit. */
838 struct m32c_reg *sp
839 = G (add_reg (arch, "sp", usp->type, 0,
840 m32c_banked_read, m32c_banked_write, isp, usp, FLAGBIT_U));
841
842 struct m32c_reg *r0hl = CHL (r0, tdep->int8);
843 struct m32c_reg *r1hl = CHL (r1, tdep->int8);
844 struct m32c_reg *r2hl = CHL (r2, tdep->int8);
845 struct m32c_reg *r3hl = CHL (r3, tdep->int8);
846 struct m32c_reg *intbhl = CHL (intb, tdep->int16);
847
848 struct m32c_reg *r2r0 = CCAT (r2, r0, tdep->int32);
849 struct m32c_reg *r3r1 = CCAT (r3, r1, tdep->int32);
850 struct m32c_reg *r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64);
851
852 struct m32c_reg *r3r2r1r0
853 = add_reg (arch, "r3r2r1r0", tdep->int64, 0,
854 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0);
855
856 struct m32c_reg *a1a0;
857 if (mach == bfd_mach_m16c)
858 a1a0 = CCAT (a1, a0, tdep->int32);
859 else
860 a1a0 = NULL;
861
862 int num_cooked_regs = tdep->num_regs - num_raw_regs;
863
864 tdep->pc = pc;
865 tdep->flg = flg;
866 tdep->r0 = r0;
867 tdep->r1 = r1;
868 tdep->r2 = r2;
869 tdep->r3 = r3;
870 tdep->r2r0 = r2r0;
871 tdep->r3r2r1r0 = r3r2r1r0;
872 tdep->r3r1r2r0 = r3r1r2r0;
873 tdep->a0 = a0;
874 tdep->a1 = a1;
875 tdep->sb = sb;
876 tdep->fb = fb;
877 tdep->sp = sp;
878
879 /* Set up the DWARF register table. */
880 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs));
881 set_dwarf_regnum (r0hl + 1, 0x01);
882 set_dwarf_regnum (r0hl + 0, 0x02);
883 set_dwarf_regnum (r1hl + 1, 0x03);
884 set_dwarf_regnum (r1hl + 0, 0x04);
885 set_dwarf_regnum (r0, 0x05);
886 set_dwarf_regnum (r1, 0x06);
887 set_dwarf_regnum (r2, 0x07);
888 set_dwarf_regnum (r3, 0x08);
889 set_dwarf_regnum (a0, 0x09);
890 set_dwarf_regnum (a1, 0x0a);
891 set_dwarf_regnum (fb, 0x0b);
892 set_dwarf_regnum (sp, 0x0c);
893 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */
894 set_dwarf_regnum (sb, 0x13);
895 set_dwarf_regnum (r2r0, 0x15);
896 set_dwarf_regnum (r3r1, 0x16);
897 if (a1a0)
898 set_dwarf_regnum (a1a0, 0x17);
899
900 /* Enumerate the save/restore register group.
901
902 The regcache_save and regcache_restore functions apply their read
903 function to each register in this group.
904
905 Since frame_pop supplies frame_unwind_register as its read
906 function, the registers meaningful to the Dwarf unwinder need to
907 be in this group.
908
909 On the other hand, when we make inferior calls, save_inferior_status
910 and restore_inferior_status use them to preserve the current register
911 values across the inferior call. For this, you'd kind of like to
912 preserve all the raw registers, to protect the interrupted code from
913 any sort of bank switching the callee might have done. But we handle
914 those cases so badly anyway --- for example, it matters whether we
915 restore FLG before or after we restore the general-purpose registers,
916 but there's no way to express that --- that it isn't worth worrying
917 about.
918
919 We omit control registers like inthl: if you call a function that
920 changes those, it's probably because you wanted that change to be
921 visible to the interrupted code. */
922 mark_save_restore (r0);
923 mark_save_restore (r1);
924 mark_save_restore (r2);
925 mark_save_restore (r3);
926 mark_save_restore (a0);
927 mark_save_restore (a1);
928 mark_save_restore (sb);
929 mark_save_restore (fb);
930 mark_save_restore (sp);
931 mark_save_restore (pc);
932 mark_save_restore (flg);
933
934 set_gdbarch_num_regs (arch, num_raw_regs);
935 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs);
936 set_gdbarch_pc_regnum (arch, pc->num);
937 set_gdbarch_sp_regnum (arch, sp->num);
938 set_gdbarch_register_name (arch, m32c_register_name);
939 set_gdbarch_register_type (arch, m32c_register_type);
940 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read);
941 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write);
942 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno);
943 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
944 set_gdbarch_dwarf_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
945 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
946 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p);
947
948 reggroup_add (arch, general_reggroup);
949 reggroup_add (arch, all_reggroup);
950 reggroup_add (arch, save_reggroup);
951 reggroup_add (arch, restore_reggroup);
952 reggroup_add (arch, system_reggroup);
953 reggroup_add (arch, m32c_dma_reggroup);
954 }
955
956
957 \f
958 /* Breakpoints. */
959
960 static const unsigned char *
961 m32c_breakpoint_from_pc (CORE_ADDR *pc, int *len)
962 {
963 static unsigned char break_insn[] = { 0x00 }; /* brk */
964
965 *len = sizeof (break_insn);
966 return break_insn;
967 }
968
969
970 \f
971 /* Prologue analysis. */
972
973 struct m32c_prologue
974 {
975 /* For consistency with the DWARF 2 .debug_frame info generated by
976 GCC, a frame's CFA is the address immediately after the saved
977 return address. */
978
979 /* The architecture for which we generated this prologue info. */
980 struct gdbarch *arch;
981
982 enum {
983 /* This function uses a frame pointer. */
984 prologue_with_frame_ptr,
985
986 /* This function has no frame pointer. */
987 prologue_sans_frame_ptr,
988
989 /* This function sets up the stack, so its frame is the first
990 frame on the stack. */
991 prologue_first_frame
992
993 } kind;
994
995 /* If KIND is prologue_with_frame_ptr, this is the offset from the
996 CFA to where the frame pointer points. This is always zero or
997 negative. */
998 LONGEST frame_ptr_offset;
999
1000 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to
1001 the stack pointer --- always zero or negative.
1002
1003 Calling this a "size" is a bit misleading, but given that the
1004 stack grows downwards, using offsets for everything keeps one
1005 from going completely sign-crazy: you never change anything's
1006 sign for an ADD instruction; always change the second operand's
1007 sign for a SUB instruction; and everything takes care of
1008 itself.
1009
1010 Functions that use alloca don't have a constant frame size. But
1011 they always have frame pointers, so we must use that to find the
1012 CFA (and perhaps to unwind the stack pointer). */
1013 LONGEST frame_size;
1014
1015 /* The address of the first instruction at which the frame has been
1016 set up and the arguments are where the debug info says they are
1017 --- as best as we can tell. */
1018 CORE_ADDR prologue_end;
1019
1020 /* reg_offset[R] is the offset from the CFA at which register R is
1021 saved, or 1 if register R has not been saved. (Real values are
1022 always zero or negative.) */
1023 LONGEST reg_offset[M32C_MAX_NUM_REGS];
1024 };
1025
1026
1027 /* The longest I've seen, anyway. */
1028 #define M32C_MAX_INSN_LEN (9)
1029
1030 /* Processor state, for the prologue analyzer. */
1031 struct m32c_pv_state
1032 {
1033 struct gdbarch *arch;
1034 pv_t r0, r1, r2, r3;
1035 pv_t a0, a1;
1036 pv_t sb, fb, sp;
1037 pv_t pc;
1038 struct pv_area *stack;
1039
1040 /* Bytes from the current PC, the address they were read from,
1041 and the address of the next unconsumed byte. */
1042 gdb_byte insn[M32C_MAX_INSN_LEN];
1043 CORE_ADDR scan_pc, next_addr;
1044 };
1045
1046
1047 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if
1048 all went well, or non-zero if simulating the action would trash our
1049 state. */
1050 static int
1051 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size)
1052 {
1053 if (pv_area_store_would_trash (state->stack, state->sp))
1054 return 1;
1055
1056 state->sp = pv_add_constant (state->sp, -size);
1057 pv_area_store (state->stack, state->sp, size, value);
1058
1059 return 0;
1060 }
1061
1062
1063 /* A source or destination location for an m16c or m32c
1064 instruction. */
1065 struct srcdest
1066 {
1067 /* If srcdest_reg, the location is a register pointed to by REG.
1068 If srcdest_partial_reg, the location is part of a register pointed
1069 to by REG. We don't try to handle this too well.
1070 If srcdest_mem, the location is memory whose address is ADDR. */
1071 enum { srcdest_reg, srcdest_partial_reg, srcdest_mem } kind;
1072 pv_t *reg, addr;
1073 };
1074
1075
1076 /* Return the SIZE-byte value at LOC in STATE. */
1077 static pv_t
1078 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size)
1079 {
1080 if (loc.kind == srcdest_mem)
1081 return pv_area_fetch (state->stack, loc.addr, size);
1082 else if (loc.kind == srcdest_partial_reg)
1083 return pv_unknown ();
1084 else
1085 return *loc.reg;
1086 }
1087
1088
1089 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if
1090 all went well, or non-zero if simulating the store would trash our
1091 state. */
1092 static int
1093 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc,
1094 pv_t value, int size)
1095 {
1096 if (loc.kind == srcdest_mem)
1097 {
1098 if (pv_area_store_would_trash (state->stack, loc.addr))
1099 return 1;
1100 pv_area_store (state->stack, loc.addr, size, value);
1101 }
1102 else if (loc.kind == srcdest_partial_reg)
1103 *loc.reg = pv_unknown ();
1104 else
1105 *loc.reg = value;
1106
1107 return 0;
1108 }
1109
1110
1111 static int
1112 m32c_sign_ext (int v, int bits)
1113 {
1114 int mask = 1 << (bits - 1);
1115 return (v ^ mask) - mask;
1116 }
1117
1118 static unsigned int
1119 m32c_next_byte (struct m32c_pv_state *st)
1120 {
1121 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn));
1122 return st->insn[st->next_addr++ - st->scan_pc];
1123 }
1124
1125 static int
1126 m32c_udisp8 (struct m32c_pv_state *st)
1127 {
1128 return m32c_next_byte (st);
1129 }
1130
1131
1132 static int
1133 m32c_sdisp8 (struct m32c_pv_state *st)
1134 {
1135 return m32c_sign_ext (m32c_next_byte (st), 8);
1136 }
1137
1138
1139 static int
1140 m32c_udisp16 (struct m32c_pv_state *st)
1141 {
1142 int low = m32c_next_byte (st);
1143 int high = m32c_next_byte (st);
1144
1145 return low + (high << 8);
1146 }
1147
1148
1149 static int
1150 m32c_sdisp16 (struct m32c_pv_state *st)
1151 {
1152 int low = m32c_next_byte (st);
1153 int high = m32c_next_byte (st);
1154
1155 return m32c_sign_ext (low + (high << 8), 16);
1156 }
1157
1158
1159 static int
1160 m32c_udisp24 (struct m32c_pv_state *st)
1161 {
1162 int low = m32c_next_byte (st);
1163 int mid = m32c_next_byte (st);
1164 int high = m32c_next_byte (st);
1165
1166 return low + (mid << 8) + (high << 16);
1167 }
1168
1169
1170 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */
1171 static int
1172 m32c_get_src23 (unsigned char *i)
1173 {
1174 return (((i[0] & 0x70) >> 2)
1175 | ((i[1] & 0x30) >> 4));
1176 }
1177
1178
1179 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */
1180 static int
1181 m32c_get_dest23 (unsigned char *i)
1182 {
1183 return (((i[0] & 0x0e) << 1)
1184 | ((i[1] & 0xc0) >> 6));
1185 }
1186
1187
1188 static struct srcdest
1189 m32c_decode_srcdest4 (struct m32c_pv_state *st,
1190 int code, int size)
1191 {
1192 struct srcdest sd;
1193
1194 if (code < 6)
1195 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg);
1196 else
1197 sd.kind = srcdest_mem;
1198
1199 sd.addr = pv_unknown ();
1200 sd.reg = 0;
1201
1202 switch (code)
1203 {
1204 case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break;
1205 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break;
1206 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break;
1207 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break;
1208
1209 case 0x4: sd.reg = &st->a0; break;
1210 case 0x5: sd.reg = &st->a1; break;
1211
1212 case 0x6: sd.addr = st->a0; break;
1213 case 0x7: sd.addr = st->a1; break;
1214
1215 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1216 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1217 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1218 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1219
1220 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1221 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1222 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1223 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1224
1225 default:
1226 gdb_assert (0);
1227 }
1228
1229 return sd;
1230 }
1231
1232
1233 static struct srcdest
1234 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind)
1235 {
1236 struct srcdest sd;
1237
1238 sd.addr = pv_unknown ();
1239 sd.reg = 0;
1240
1241 switch (code)
1242 {
1243 case 0x12:
1244 case 0x13:
1245 case 0x10:
1246 case 0x11:
1247 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg;
1248 break;
1249
1250 case 0x02:
1251 case 0x03:
1252 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg;
1253 break;
1254
1255 default:
1256 sd.kind = srcdest_mem;
1257 break;
1258
1259 }
1260
1261 switch (code)
1262 {
1263 case 0x12: sd.reg = &st->r0; break;
1264 case 0x13: sd.reg = &st->r1; break;
1265 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break;
1266 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break;
1267 case 0x02: sd.reg = &st->a0; break;
1268 case 0x03: sd.reg = &st->a1; break;
1269
1270 case 0x00: sd.addr = st->a0; break;
1271 case 0x01: sd.addr = st->a1; break;
1272 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1273 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1274 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1275 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1276 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1277 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1278 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1279 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break;
1280 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break;
1281 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break;
1282 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1283 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break;
1284 default:
1285 gdb_assert (0);
1286 }
1287
1288 if (ind)
1289 {
1290 sd.addr = m32c_srcdest_fetch (st, sd, 4);
1291 sd.kind = srcdest_mem;
1292 }
1293
1294 return sd;
1295 }
1296
1297
1298 /* The r16c and r32c machines have instructions with similar
1299 semantics, but completely different machine language encodings. So
1300 we break out the semantics into their own functions, and leave
1301 machine-specific decoding in m32c_analyze_prologue.
1302
1303 The following functions all expect their arguments already decoded,
1304 and they all return zero if analysis should continue past this
1305 instruction, or non-zero if analysis should stop. */
1306
1307
1308 /* Simulate an 'enter SIZE' instruction in STATE. */
1309 static int
1310 m32c_pv_enter (struct m32c_pv_state *state, int size)
1311 {
1312 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1313
1314 /* If simulating this store would require us to forget
1315 everything we know about the stack frame in the name of
1316 accuracy, it would be better to just quit now. */
1317 if (pv_area_store_would_trash (state->stack, state->sp))
1318 return 1;
1319
1320 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes))
1321 return 1;
1322 state->fb = state->sp;
1323 state->sp = pv_add_constant (state->sp, -size);
1324
1325 return 0;
1326 }
1327
1328
1329 static int
1330 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg,
1331 int bit, int src, int size)
1332 {
1333 if (bit & src)
1334 {
1335 if (m32c_pv_push (state, reg, size))
1336 return 1;
1337 }
1338
1339 return 0;
1340 }
1341
1342
1343 /* Simulate a 'pushm SRC' instruction in STATE. */
1344 static int
1345 m32c_pv_pushm (struct m32c_pv_state *state, int src)
1346 {
1347 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1348
1349 /* The bits in SRC indicating which registers to save are:
1350 r0 r1 r2 r3 a0 a1 sb fb */
1351 return
1352 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes)
1353 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes)
1354 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes)
1355 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes)
1356 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2)
1357 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2)
1358 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2)
1359 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2));
1360 }
1361
1362 /* Return non-zero if VALUE is the first incoming argument register. */
1363
1364 static int
1365 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value)
1366 {
1367 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1368 return (value.kind == pvk_register
1369 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1370 ? (value.reg == tdep->r1->num)
1371 : (value.reg == tdep->r0->num))
1372 && value.k == 0);
1373 }
1374
1375 /* Return non-zero if VALUE is an incoming argument register. */
1376
1377 static int
1378 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value)
1379 {
1380 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1381 return (value.kind == pvk_register
1382 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1383 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num)
1384 : (value.reg == tdep->r0->num))
1385 && value.k == 0);
1386 }
1387
1388 /* Return non-zero if a store of VALUE to LOC is probably spilling an
1389 argument register to its stack slot in STATE. Such instructions
1390 should be included in the prologue, if possible.
1391
1392 The store is a spill if:
1393 - the value being stored is the original value of an argument register;
1394 - the value has not already been stored somewhere in STACK; and
1395 - LOC is a stack slot (e.g., a memory location whose address is
1396 relative to the original value of the SP). */
1397
1398 static int
1399 m32c_is_arg_spill (struct m32c_pv_state *st,
1400 struct srcdest loc,
1401 pv_t value)
1402 {
1403 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1404
1405 return (m32c_is_arg_reg (st, value)
1406 && loc.kind == srcdest_mem
1407 && pv_is_register (loc.addr, tdep->sp->num)
1408 && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0));
1409 }
1410
1411 /* Return non-zero if a store of VALUE to LOC is probably
1412 copying the struct return address into an address register
1413 for immediate use. This is basically a "spill" into the
1414 address register, instead of onto the stack.
1415
1416 The prerequisites are:
1417 - value being stored is original value of the FIRST arg register;
1418 - value has not already been stored on stack; and
1419 - LOC is an address register (a0 or a1). */
1420
1421 static int
1422 m32c_is_struct_return (struct m32c_pv_state *st,
1423 struct srcdest loc,
1424 pv_t value)
1425 {
1426 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1427
1428 return (m32c_is_1st_arg_reg (st, value)
1429 && !pv_area_find_reg (st->stack, st->arch, value.reg, 0)
1430 && loc.kind == srcdest_reg
1431 && (pv_is_register (*loc.reg, tdep->a0->num)
1432 || pv_is_register (*loc.reg, tdep->a1->num)));
1433 }
1434
1435 /* Return non-zero if a 'pushm' saving the registers indicated by SRC
1436 was a register save:
1437 - all the named registers should have their original values, and
1438 - the stack pointer should be at a constant offset from the
1439 original stack pointer. */
1440 static int
1441 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src)
1442 {
1443 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1444 /* The bits in SRC indicating which registers to save are:
1445 r0 r1 r2 r3 a0 a1 sb fb */
1446 return
1447 (pv_is_register (st->sp, tdep->sp->num)
1448 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0))
1449 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0))
1450 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0))
1451 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0))
1452 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0))
1453 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0))
1454 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0))
1455 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0)));
1456 }
1457
1458
1459 /* Function for finding saved registers in a 'struct pv_area'; we pass
1460 this to pv_area_scan.
1461
1462 If VALUE is a saved register, ADDR says it was saved at a constant
1463 offset from the frame base, and SIZE indicates that the whole
1464 register was saved, record its offset in RESULT_UNTYPED. */
1465 static void
1466 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1467 {
1468 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped;
1469 struct gdbarch *arch = prologue->arch;
1470 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1471
1472 /* Is this the unchanged value of some register being saved on the
1473 stack? */
1474 if (value.kind == pvk_register
1475 && value.k == 0
1476 && pv_is_register (addr, tdep->sp->num))
1477 {
1478 /* Some registers require special handling: they're saved as a
1479 larger value than the register itself. */
1480 CORE_ADDR saved_size = register_size (arch, value.reg);
1481
1482 if (value.reg == tdep->pc->num)
1483 saved_size = tdep->ret_addr_bytes;
1484 else if (gdbarch_register_type (arch, value.reg)
1485 == tdep->data_addr_reg_type)
1486 saved_size = tdep->push_addr_bytes;
1487
1488 if (size == saved_size)
1489 {
1490 /* Find which end of the saved value corresponds to our
1491 register. */
1492 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
1493 prologue->reg_offset[value.reg]
1494 = (addr.k + saved_size - register_size (arch, value.reg));
1495 else
1496 prologue->reg_offset[value.reg] = addr.k;
1497 }
1498 }
1499 }
1500
1501
1502 /* Analyze the function prologue for ARCH at START, going no further
1503 than LIMIT, and place a description of what we found in
1504 PROLOGUE. */
1505 void
1506 m32c_analyze_prologue (struct gdbarch *arch,
1507 CORE_ADDR start, CORE_ADDR limit,
1508 struct m32c_prologue *prologue)
1509 {
1510 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1511 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
1512 CORE_ADDR after_last_frame_related_insn;
1513 struct cleanup *back_to;
1514 struct m32c_pv_state st;
1515
1516 st.arch = arch;
1517 st.r0 = pv_register (tdep->r0->num, 0);
1518 st.r1 = pv_register (tdep->r1->num, 0);
1519 st.r2 = pv_register (tdep->r2->num, 0);
1520 st.r3 = pv_register (tdep->r3->num, 0);
1521 st.a0 = pv_register (tdep->a0->num, 0);
1522 st.a1 = pv_register (tdep->a1->num, 0);
1523 st.sb = pv_register (tdep->sb->num, 0);
1524 st.fb = pv_register (tdep->fb->num, 0);
1525 st.sp = pv_register (tdep->sp->num, 0);
1526 st.pc = pv_register (tdep->pc->num, 0);
1527 st.stack = make_pv_area (tdep->sp->num);
1528 back_to = make_cleanup_free_pv_area (st.stack);
1529
1530 /* Record that the call instruction has saved the return address on
1531 the stack. */
1532 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes);
1533
1534 memset (prologue, 0, sizeof (*prologue));
1535 prologue->arch = arch;
1536 {
1537 int i;
1538 for (i = 0; i < M32C_MAX_NUM_REGS; i++)
1539 prologue->reg_offset[i] = 1;
1540 }
1541
1542 st.scan_pc = after_last_frame_related_insn = start;
1543
1544 while (st.scan_pc < limit)
1545 {
1546 pv_t pre_insn_fb = st.fb;
1547 pv_t pre_insn_sp = st.sp;
1548
1549 /* In theory we could get in trouble by trying to read ahead
1550 here, when we only know we're expecting one byte. In
1551 practice I doubt anyone will care, and it makes the rest of
1552 the code easier. */
1553 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn)))
1554 /* If we can't fetch the instruction from memory, stop here
1555 and hope for the best. */
1556 break;
1557 st.next_addr = st.scan_pc;
1558
1559 /* The assembly instructions are written as they appear in the
1560 section of the processor manuals that describe the
1561 instruction encodings.
1562
1563 When a single assembly language instruction has several
1564 different machine-language encodings, the manual
1565 distinguishes them by a number in parens, before the
1566 mnemonic. Those numbers are included, as well.
1567
1568 The srcdest decoding instructions have the same names as the
1569 analogous functions in the simulator. */
1570 if (mach == bfd_mach_m16c)
1571 {
1572 /* (1) ENTER #imm8 */
1573 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2)
1574 {
1575 if (m32c_pv_enter (&st, st.insn[2]))
1576 break;
1577 st.next_addr += 3;
1578 }
1579 /* (1) PUSHM src */
1580 else if (st.insn[0] == 0xec)
1581 {
1582 int src = st.insn[1];
1583 if (m32c_pv_pushm (&st, src))
1584 break;
1585 st.next_addr += 2;
1586
1587 if (m32c_pushm_is_reg_save (&st, src))
1588 after_last_frame_related_insn = st.next_addr;
1589 }
1590
1591 /* (6) MOV.size:G src, dest */
1592 else if ((st.insn[0] & 0xfe) == 0x72)
1593 {
1594 int size = (st.insn[0] & 0x01) ? 2 : 1;
1595
1596 st.next_addr += 2;
1597
1598 struct srcdest src
1599 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size);
1600 struct srcdest dest
1601 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size);
1602 pv_t src_value = m32c_srcdest_fetch (&st, src, size);
1603
1604 if (m32c_is_arg_spill (&st, dest, src_value))
1605 after_last_frame_related_insn = st.next_addr;
1606 else if (m32c_is_struct_return (&st, dest, src_value))
1607 after_last_frame_related_insn = st.next_addr;
1608
1609 if (m32c_srcdest_store (&st, dest, src_value, size))
1610 break;
1611 }
1612
1613 /* (1) LDC #IMM16, sp */
1614 else if (st.insn[0] == 0xeb
1615 && st.insn[1] == 0x50)
1616 {
1617 st.next_addr += 2;
1618 st.sp = pv_constant (m32c_udisp16 (&st));
1619 }
1620
1621 else
1622 /* We've hit some instruction we don't know how to simulate.
1623 Strictly speaking, we should set every value we're
1624 tracking to "unknown". But we'll be optimistic, assume
1625 that we have enough information already, and stop
1626 analysis here. */
1627 break;
1628 }
1629 else
1630 {
1631 int src_indirect = 0;
1632 int dest_indirect = 0;
1633 int i = 0;
1634
1635 gdb_assert (mach == bfd_mach_m32c);
1636
1637 /* Check for prefix bytes indicating indirect addressing. */
1638 if (st.insn[0] == 0x41)
1639 {
1640 src_indirect = 1;
1641 i++;
1642 }
1643 else if (st.insn[0] == 0x09)
1644 {
1645 dest_indirect = 1;
1646 i++;
1647 }
1648 else if (st.insn[0] == 0x49)
1649 {
1650 src_indirect = dest_indirect = 1;
1651 i++;
1652 }
1653
1654 /* (1) ENTER #imm8 */
1655 if (st.insn[i] == 0xec)
1656 {
1657 if (m32c_pv_enter (&st, st.insn[i + 1]))
1658 break;
1659 st.next_addr += 2;
1660 }
1661
1662 /* (1) PUSHM src */
1663 else if (st.insn[i] == 0x8f)
1664 {
1665 int src = st.insn[i + 1];
1666 if (m32c_pv_pushm (&st, src))
1667 break;
1668 st.next_addr += 2;
1669
1670 if (m32c_pushm_is_reg_save (&st, src))
1671 after_last_frame_related_insn = st.next_addr;
1672 }
1673
1674 /* (7) MOV.size:G src, dest */
1675 else if ((st.insn[i] & 0x80) == 0x80
1676 && (st.insn[i + 1] & 0x0f) == 0x0b
1677 && m32c_get_src23 (&st.insn[i]) < 20
1678 && m32c_get_dest23 (&st.insn[i]) < 20)
1679 {
1680 int bw = st.insn[i] & 0x01;
1681 int size = bw ? 2 : 1;
1682
1683 st.next_addr += 2;
1684
1685 struct srcdest src
1686 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]),
1687 size, src_indirect);
1688 struct srcdest dest
1689 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]),
1690 size, dest_indirect);
1691 pv_t src_value = m32c_srcdest_fetch (&st, src, size);
1692
1693 if (m32c_is_arg_spill (&st, dest, src_value))
1694 after_last_frame_related_insn = st.next_addr;
1695
1696 if (m32c_srcdest_store (&st, dest, src_value, size))
1697 break;
1698 }
1699 /* (2) LDC #IMM24, sp */
1700 else if (st.insn[i] == 0xd5
1701 && st.insn[i + 1] == 0x29)
1702 {
1703 st.next_addr += 2;
1704 st.sp = pv_constant (m32c_udisp24 (&st));
1705 }
1706 else
1707 /* We've hit some instruction we don't know how to simulate.
1708 Strictly speaking, we should set every value we're
1709 tracking to "unknown". But we'll be optimistic, assume
1710 that we have enough information already, and stop
1711 analysis here. */
1712 break;
1713 }
1714
1715 /* If this instruction changed the FB or decreased the SP (i.e.,
1716 allocated more stack space), then this may be a good place to
1717 declare the prologue finished. However, there are some
1718 exceptions:
1719
1720 - If the instruction just changed the FB back to its original
1721 value, then that's probably a restore instruction. The
1722 prologue should definitely end before that.
1723
1724 - If the instruction increased the value of the SP (that is,
1725 shrunk the frame), then it's probably part of a frame
1726 teardown sequence, and the prologue should end before
1727 that. */
1728
1729 if (! pv_is_identical (st.fb, pre_insn_fb))
1730 {
1731 if (! pv_is_register_k (st.fb, tdep->fb->num, 0))
1732 after_last_frame_related_insn = st.next_addr;
1733 }
1734 else if (! pv_is_identical (st.sp, pre_insn_sp))
1735 {
1736 /* The comparison of the constants looks odd, there, because
1737 .k is unsigned. All it really means is that the SP is
1738 lower than it was before the instruction. */
1739 if ( pv_is_register (pre_insn_sp, tdep->sp->num)
1740 && pv_is_register (st.sp, tdep->sp->num)
1741 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k)))
1742 after_last_frame_related_insn = st.next_addr;
1743 }
1744
1745 st.scan_pc = st.next_addr;
1746 }
1747
1748 /* Did we load a constant value into the stack pointer? */
1749 if (pv_is_constant (st.sp))
1750 prologue->kind = prologue_first_frame;
1751
1752 /* Alternatively, did we initialize the frame pointer? Remember
1753 that the CFA is the address after the return address. */
1754 if (pv_is_register (st.fb, tdep->sp->num))
1755 {
1756 prologue->kind = prologue_with_frame_ptr;
1757 prologue->frame_ptr_offset = st.fb.k;
1758 }
1759
1760 /* Is the frame size a known constant? Remember that frame_size is
1761 actually the offset from the CFA to the SP (i.e., a negative
1762 value). */
1763 else if (pv_is_register (st.sp, tdep->sp->num))
1764 {
1765 prologue->kind = prologue_sans_frame_ptr;
1766 prologue->frame_size = st.sp.k;
1767 }
1768
1769 /* We haven't been able to make sense of this function's frame. Treat
1770 it as the first frame. */
1771 else
1772 prologue->kind = prologue_first_frame;
1773
1774 /* Record where all the registers were saved. */
1775 pv_area_scan (st.stack, check_for_saved, (void *) prologue);
1776
1777 prologue->prologue_end = after_last_frame_related_insn;
1778
1779 do_cleanups (back_to);
1780 }
1781
1782
1783 static CORE_ADDR
1784 m32c_skip_prologue (CORE_ADDR ip)
1785 {
1786 char *name;
1787 CORE_ADDR func_addr, func_end, sal_end;
1788 struct m32c_prologue p;
1789
1790 /* Try to find the extent of the function that contains IP. */
1791 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end))
1792 return ip;
1793
1794 /* Find end by prologue analysis. */
1795 m32c_analyze_prologue (current_gdbarch, ip, func_end, &p);
1796 /* Find end by line info. */
1797 sal_end = skip_prologue_using_sal (ip);
1798 /* Return whichever is lower. */
1799 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end)
1800 return sal_end;
1801 else
1802 return p.prologue_end;
1803 }
1804
1805
1806 \f
1807 /* Stack unwinding. */
1808
1809 static struct m32c_prologue *
1810 m32c_analyze_frame_prologue (struct frame_info *next_frame,
1811 void **this_prologue_cache)
1812 {
1813 if (! *this_prologue_cache)
1814 {
1815 CORE_ADDR func_start = frame_func_unwind (next_frame);
1816 CORE_ADDR stop_addr = frame_pc_unwind (next_frame);
1817
1818 /* If we couldn't find any function containing the PC, then
1819 just initialize the prologue cache, but don't do anything. */
1820 if (! func_start)
1821 stop_addr = func_start;
1822
1823 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue);
1824 m32c_analyze_prologue (get_frame_arch (next_frame),
1825 func_start, stop_addr, *this_prologue_cache);
1826 }
1827
1828 return *this_prologue_cache;
1829 }
1830
1831
1832 static CORE_ADDR
1833 m32c_frame_base (struct frame_info *next_frame,
1834 void **this_prologue_cache)
1835 {
1836 struct m32c_prologue *p
1837 = m32c_analyze_frame_prologue (next_frame, this_prologue_cache);
1838 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1839
1840 /* In functions that use alloca, the distance between the stack
1841 pointer and the frame base varies dynamically, so we can't use
1842 the SP plus static information like prologue analysis to find the
1843 frame base. However, such functions must have a frame pointer,
1844 to be able to restore the SP on exit. So whenever we do have a
1845 frame pointer, use that to find the base. */
1846 switch (p->kind)
1847 {
1848 case prologue_with_frame_ptr:
1849 {
1850 CORE_ADDR fb
1851 = frame_unwind_register_unsigned (next_frame, tdep->fb->num);
1852 return fb - p->frame_ptr_offset;
1853 }
1854
1855 case prologue_sans_frame_ptr:
1856 {
1857 CORE_ADDR sp
1858 = frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1859 return sp - p->frame_size;
1860 }
1861
1862 case prologue_first_frame:
1863 return 0;
1864
1865 default:
1866 gdb_assert (0);
1867 }
1868 }
1869
1870
1871 static void
1872 m32c_this_id (struct frame_info *next_frame,
1873 void **this_prologue_cache,
1874 struct frame_id *this_id)
1875 {
1876 CORE_ADDR base = m32c_frame_base (next_frame, this_prologue_cache);
1877
1878 if (base)
1879 *this_id = frame_id_build (base, frame_func_unwind (next_frame));
1880 /* Otherwise, leave it unset, and that will terminate the backtrace. */
1881 }
1882
1883
1884 static void
1885 m32c_prev_register (struct frame_info *next_frame,
1886 void **this_prologue_cache,
1887 int regnum, int *optimizedp,
1888 enum lval_type *lvalp, CORE_ADDR *addrp,
1889 int *realnump, gdb_byte *bufferp)
1890 {
1891 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1892 struct m32c_prologue *p
1893 = m32c_analyze_frame_prologue (next_frame, this_prologue_cache);
1894 CORE_ADDR frame_base = m32c_frame_base (next_frame, this_prologue_cache);
1895 int reg_size = register_size (get_frame_arch (next_frame), regnum);
1896
1897 if (regnum == tdep->sp->num)
1898 {
1899 *optimizedp = 0;
1900 *lvalp = not_lval;
1901 *addrp = 0;
1902 *realnump = -1;
1903 if (bufferp)
1904 store_unsigned_integer (bufferp, reg_size, frame_base);
1905 }
1906
1907 /* If prologue analysis says we saved this register somewhere,
1908 return a description of the stack slot holding it. */
1909 else if (p->reg_offset[regnum] != 1)
1910 {
1911 *optimizedp = 0;
1912 *lvalp = lval_memory;
1913 *addrp = frame_base + p->reg_offset[regnum];
1914 *realnump = -1;
1915 if (bufferp)
1916 get_frame_memory (next_frame, *addrp, bufferp, reg_size);
1917 }
1918
1919 /* Otherwise, presume we haven't changed the value of this
1920 register, and get it from the next frame. */
1921 else
1922 frame_register_unwind (next_frame, regnum,
1923 optimizedp, lvalp, addrp, realnump, bufferp);
1924 }
1925
1926
1927 static const struct frame_unwind m32c_unwind = {
1928 NORMAL_FRAME,
1929 m32c_this_id,
1930 m32c_prev_register
1931 };
1932
1933
1934 static const struct frame_unwind *
1935 m32c_frame_sniffer (struct frame_info *next_frame)
1936 {
1937 return &m32c_unwind;
1938 }
1939
1940
1941 static CORE_ADDR
1942 m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1943 {
1944 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1945 return frame_unwind_register_unsigned (next_frame, tdep->pc->num);
1946 }
1947
1948
1949 static CORE_ADDR
1950 m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1951 {
1952 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1953 return frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1954 }
1955
1956 \f
1957 /* Inferior calls. */
1958
1959 /* The calling conventions, according to GCC:
1960
1961 r8c, m16c
1962 ---------
1963 First arg may be passed in r1l or r1 if it (1) fits (QImode or
1964 HImode), (2) is named, and (3) is an integer or pointer type (no
1965 structs, floats, etc). Otherwise, it's passed on the stack.
1966
1967 Second arg may be passed in r2, same restrictions (but not QImode),
1968 even if the first arg is passed on the stack.
1969
1970 Third and further args are passed on the stack. No padding is
1971 used, stack "alignment" is 8 bits.
1972
1973 m32cm, m32c
1974 -----------
1975
1976 First arg may be passed in r0l or r0, same restrictions as above.
1977
1978 Second and further args are passed on the stack. Padding is used
1979 after QImode parameters (i.e. lower-addressed byte is the value,
1980 higher-addressed byte is the padding), stack "alignment" is 16
1981 bits. */
1982
1983
1984 /* Return true if TYPE is a type that can be passed in registers. (We
1985 ignore the size, and pay attention only to the type code;
1986 acceptable sizes depends on which register is being considered to
1987 hold it.) */
1988 static int
1989 m32c_reg_arg_type (struct type *type)
1990 {
1991 enum type_code code = TYPE_CODE (type);
1992
1993 return (code == TYPE_CODE_INT
1994 || code == TYPE_CODE_ENUM
1995 || code == TYPE_CODE_PTR
1996 || code == TYPE_CODE_REF
1997 || code == TYPE_CODE_BOOL
1998 || code == TYPE_CODE_CHAR);
1999 }
2000
2001
2002 static CORE_ADDR
2003 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2004 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2005 struct value **args, CORE_ADDR sp, int struct_return,
2006 CORE_ADDR struct_addr)
2007 {
2008 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2009 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2010 CORE_ADDR cfa;
2011 int i;
2012
2013 /* The number of arguments given in this function's prototype, or
2014 zero if it has a non-prototyped function type. The m32c ABI
2015 passes arguments mentioned in the prototype differently from
2016 those in the ellipsis of a varargs function, or from those passed
2017 to a non-prototyped function. */
2018 int num_prototyped_args = 0;
2019
2020 {
2021 struct type *func_type = value_type (function);
2022
2023 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC ||
2024 TYPE_CODE (func_type) == TYPE_CODE_METHOD);
2025
2026 #if 0
2027 /* The ABI description in gcc/config/m32c/m32c.abi says that
2028 we need to handle prototyped and non-prototyped functions
2029 separately, but the code in GCC doesn't actually do so. */
2030 if (TYPE_PROTOTYPED (func_type))
2031 #endif
2032 num_prototyped_args = TYPE_NFIELDS (func_type);
2033 }
2034
2035 /* First, if the function returns an aggregate by value, push a
2036 pointer to a buffer for it. This doesn't affect the way
2037 subsequent arguments are allocated to registers. */
2038 if (struct_return)
2039 {
2040 int ptr_len = TYPE_LENGTH (tdep->ptr_voyd);
2041 sp -= ptr_len;
2042 write_memory_unsigned_integer (sp, ptr_len, struct_addr);
2043 }
2044
2045 /* Push the arguments. */
2046 for (i = nargs - 1; i >= 0; i--)
2047 {
2048 struct value *arg = args[i];
2049 const gdb_byte *arg_bits = value_contents (arg);
2050 struct type *arg_type = value_type (arg);
2051 ULONGEST arg_size = TYPE_LENGTH (arg_type);
2052
2053 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */
2054 if (i == 0
2055 && arg_size <= 2
2056 && i < num_prototyped_args
2057 && m32c_reg_arg_type (arg_type))
2058 {
2059 /* Extract and re-store as an integer as a terse way to make
2060 sure it ends up in the least significant end of r1. (GDB
2061 should avoid assuming endianness, even on uni-endian
2062 processors.) */
2063 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size);
2064 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0;
2065 regcache_cooked_write_unsigned (regcache, reg->num, u);
2066 }
2067
2068 /* Can it go in r2? */
2069 else if (mach == bfd_mach_m16c
2070 && i == 1
2071 && arg_size == 2
2072 && i < num_prototyped_args
2073 && m32c_reg_arg_type (arg_type))
2074 regcache_cooked_write (regcache, tdep->r2->num, arg_bits);
2075
2076 /* Everything else goes on the stack. */
2077 else
2078 {
2079 sp -= arg_size;
2080
2081 /* Align the stack. */
2082 if (mach == bfd_mach_m32c)
2083 sp &= ~1;
2084
2085 write_memory (sp, arg_bits, arg_size);
2086 }
2087 }
2088
2089 /* This is the CFA we use to identify the dummy frame. */
2090 cfa = sp;
2091
2092 /* Push the return address. */
2093 sp -= tdep->ret_addr_bytes;
2094 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, bp_addr);
2095
2096 /* Update the stack pointer. */
2097 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp);
2098
2099 /* We need to borrow an odd trick from the i386 target here.
2100
2101 The value we return from this function gets used as the stack
2102 address (the CFA) for the dummy frame's ID. The obvious thing is
2103 to return the new TOS. However, that points at the return
2104 address, saved on the stack, which is inconsistent with the CFA's
2105 described by GCC's DWARF 2 .debug_frame information: DWARF 2
2106 .debug_frame info uses the address immediately after the saved
2107 return address. So you end up with a dummy frame whose CFA
2108 points at the return address, but the frame for the function
2109 being called has a CFA pointing after the return address: the
2110 younger CFA is *greater than* the older CFA. The sanity checks
2111 in frame.c don't like that.
2112
2113 So we try to be consistent with the CFA's used by DWARF 2.
2114 Having a dummy frame and a real frame with the *same* CFA is
2115 tolerable. */
2116 return cfa;
2117 }
2118
2119
2120 static struct frame_id
2121 m32c_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2122 {
2123 /* This needs to return a frame ID whose PC is the return address
2124 passed to m32c_push_dummy_call, and whose stack_addr is the SP
2125 m32c_push_dummy_call returned.
2126
2127 m32c_unwind_sp gives us the CFA, which is the value the SP had
2128 before the return address was pushed. */
2129 return frame_id_build (m32c_unwind_sp (gdbarch, next_frame),
2130 frame_pc_unwind (next_frame));
2131 }
2132
2133
2134 \f
2135 /* Return values. */
2136
2137 /* Return value conventions, according to GCC:
2138
2139 r8c, m16c
2140 ---------
2141
2142 QImode in r0l
2143 HImode in r0
2144 SImode in r2r0
2145 near pointer in r0
2146 far pointer in r2r0
2147
2148 Aggregate values (regardless of size) are returned by pushing a
2149 pointer to a temporary area on the stack after the args are pushed.
2150 The function fills in this area with the value. Note that this
2151 pointer on the stack does not affect how register arguments, if any,
2152 are configured.
2153
2154 m32cm, m32c
2155 -----------
2156 Same. */
2157
2158 /* Return non-zero if values of type TYPE are returned by storing them
2159 in a buffer whose address is passed on the stack, ahead of the
2160 other arguments. */
2161 static int
2162 m32c_return_by_passed_buf (struct type *type)
2163 {
2164 enum type_code code = TYPE_CODE (type);
2165
2166 return (code == TYPE_CODE_STRUCT
2167 || code == TYPE_CODE_UNION);
2168 }
2169
2170 static enum return_value_convention
2171 m32c_return_value (struct gdbarch *gdbarch,
2172 struct type *valtype,
2173 struct regcache *regcache,
2174 gdb_byte *readbuf,
2175 const gdb_byte *writebuf)
2176 {
2177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2178 enum return_value_convention conv;
2179 ULONGEST valtype_len = TYPE_LENGTH (valtype);
2180
2181 if (m32c_return_by_passed_buf (valtype))
2182 conv = RETURN_VALUE_STRUCT_CONVENTION;
2183 else
2184 conv = RETURN_VALUE_REGISTER_CONVENTION;
2185
2186 if (readbuf)
2187 {
2188 /* We should never be called to find values being returned by
2189 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located,
2190 unless we made the call ourselves. */
2191 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2192
2193 gdb_assert (valtype_len <= 8);
2194
2195 /* Anything that fits in r0 is returned there. */
2196 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2197 {
2198 ULONGEST u;
2199 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u);
2200 store_unsigned_integer (readbuf, valtype_len, u);
2201 }
2202 else
2203 {
2204 /* Everything else is passed in mem0, using as many bytes as
2205 needed. This is not what the Renesas tools do, but it's
2206 what GCC does at the moment. */
2207 struct minimal_symbol *mem0
2208 = lookup_minimal_symbol ("mem0", NULL, NULL);
2209
2210 if (! mem0)
2211 error ("The return value is stored in memory at 'mem0', "
2212 "but GDB cannot find\n"
2213 "its address.");
2214 read_memory (SYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len);
2215 }
2216 }
2217
2218 if (writebuf)
2219 {
2220 /* We should never be called to store values to be returned
2221 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of
2222 finding the buffer, unless we made the call ourselves. */
2223 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2224
2225 gdb_assert (valtype_len <= 8);
2226
2227 /* Anything that fits in r0 is returned there. */
2228 if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2229 {
2230 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len);
2231 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u);
2232 }
2233 else
2234 {
2235 /* Everything else is passed in mem0, using as many bytes as
2236 needed. This is not what the Renesas tools do, but it's
2237 what GCC does at the moment. */
2238 struct minimal_symbol *mem0
2239 = lookup_minimal_symbol ("mem0", NULL, NULL);
2240
2241 if (! mem0)
2242 error ("The return value is stored in memory at 'mem0', "
2243 "but GDB cannot find\n"
2244 " its address.");
2245 write_memory (SYMBOL_VALUE_ADDRESS (mem0),
2246 (char *) writebuf, valtype_len);
2247 }
2248 }
2249
2250 return conv;
2251 }
2252
2253
2254 \f
2255 /* Trampolines. */
2256
2257 /* The m16c and m32c use a trampoline function for indirect function
2258 calls. An indirect call looks like this:
2259
2260 ... push arguments ...
2261 ... push target function address ...
2262 jsr.a m32c_jsri16
2263
2264 The code for m32c_jsri16 looks like this:
2265
2266 m32c_jsri16:
2267
2268 # Save return address.
2269 pop.w m32c_jsri_ret
2270 pop.b m32c_jsri_ret+2
2271
2272 # Store target function address.
2273 pop.w m32c_jsri_addr
2274
2275 # Re-push return address.
2276 push.b m32c_jsri_ret+2
2277 push.w m32c_jsri_ret
2278
2279 # Call the target function.
2280 jmpi.a m32c_jsri_addr
2281
2282 Without further information, GDB will treat calls to m32c_jsri16
2283 like calls to any other function. Since m32c_jsri16 doesn't have
2284 debugging information, that normally means that GDB sets a step-
2285 resume breakpoint and lets the program continue --- which is not
2286 what the user wanted. (Giving the trampoline debugging info
2287 doesn't help: the user expects the program to stop in the function
2288 their program is calling, not in some trampoline code they've never
2289 seen before.)
2290
2291 The SKIP_TRAMPOLINE_CODE gdbarch method tells GDB how to step
2292 through such trampoline functions transparently to the user. When
2293 given the address of a trampoline function's first instruction,
2294 SKIP_TRAMPOLINE_CODE should return the address of the first
2295 instruction of the function really being called. If GDB decides it
2296 wants to step into that function, it will set a breakpoint there
2297 and silently continue to it.
2298
2299 We recognize the trampoline by name, and extract the target address
2300 directly from the stack. This isn't great, but recognizing by its
2301 code sequence seems more fragile. */
2302
2303 static CORE_ADDR
2304 m32c_skip_trampoline_code (CORE_ADDR stop_pc)
2305 {
2306 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2307
2308 /* It would be nicer to simply look up the addresses of known
2309 trampolines once, and then compare stop_pc with them. However,
2310 we'd need to ensure that that cached address got invalidated when
2311 someone loaded a new executable, and I'm not quite sure of the
2312 best way to do that. find_pc_partial_function does do some
2313 caching, so we'll see how this goes. */
2314 char *name;
2315 CORE_ADDR start, end;
2316
2317 if (find_pc_partial_function (stop_pc, &name, &start, &end))
2318 {
2319 /* Are we stopped at the beginning of the trampoline function? */
2320 if (strcmp (name, "m32c_jsri16") == 0
2321 && stop_pc == start)
2322 {
2323 /* Get the stack pointer. The return address is at the top,
2324 and the target function's address is just below that. We
2325 know it's a two-byte address, since the trampoline is
2326 m32c_jsri*16*. */
2327 CORE_ADDR sp = get_frame_sp (get_current_frame ());
2328 CORE_ADDR target
2329 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, 2);
2330
2331 /* What we have now is the address of a jump instruction.
2332 What we need is the destination of that jump.
2333 The opcode is 1 byte, and the destination is the next 3 bytes.
2334 */
2335 target = read_memory_unsigned_integer (target + 1, 3);
2336 return target;
2337 }
2338 }
2339
2340 return 0;
2341 }
2342
2343
2344 /* Address/pointer conversions. */
2345
2346 /* On the m16c, there is a 24-bit address space, but only a very few
2347 instructions can generate addresses larger than 0xffff: jumps,
2348 jumps to subroutines, and the lde/std (load/store extended)
2349 instructions.
2350
2351 Since GCC can only support one size of pointer, we can't have
2352 distinct 'near' and 'far' pointer types; we have to pick one size
2353 for everything. If we wanted to use 24-bit pointers, then GCC
2354 would have to use lde and ste for all memory references, which
2355 would be terrible for performance and code size. So the GNU
2356 toolchain uses 16-bit pointers for everything, and gives up the
2357 ability to have pointers point outside the first 64k of memory.
2358
2359 However, as a special hack, we let the linker place functions at
2360 addresses above 0xffff, as long as it also places a trampoline in
2361 the low 64k for every function whose address is taken. Each
2362 trampoline consists of a single jmp.a instruction that jumps to the
2363 function's real entry point. Pointers to functions can be 16 bits
2364 long, even though the functions themselves are at higher addresses:
2365 the pointers refer to the trampolines, not the functions.
2366
2367 This complicates things for GDB, however: given the address of a
2368 function (from debug info or linker symbols, say) which could be
2369 anywhere in the 24-bit address space, how can we find an
2370 appropriate 16-bit value to use as a pointer to it?
2371
2372 If the linker has not generated a trampoline for the function,
2373 we're out of luck. Well, I guess we could malloc some space and
2374 write a jmp.a instruction to it, but I'm not going to get into that
2375 at the moment.
2376
2377 If the linker has generated a trampoline for the function, then it
2378 also emitted a symbol for the trampoline: if the function's linker
2379 symbol is named NAME, then the function's trampoline's linker
2380 symbol is named NAME.plt.
2381
2382 So, given a code address:
2383 - We try to find a linker symbol at that address.
2384 - If we find such a symbol named NAME, we look for a linker symbol
2385 named NAME.plt.
2386 - If we find such a symbol, we assume it is a trampoline, and use
2387 its address as the pointer value.
2388
2389 And, given a function pointer:
2390 - We try to find a linker symbol at that address named NAME.plt.
2391 - If we find such a symbol, we look for a linker symbol named NAME.
2392 - If we find that, we provide that as the function's address.
2393 - If any of the above steps fail, we return the original address
2394 unchanged; it might really be a function in the low 64k.
2395
2396 See? You *knew* there was a reason you wanted to be a computer
2397 programmer! :) */
2398
2399 static void
2400 m32c_m16c_address_to_pointer (struct type *type, gdb_byte *buf, CORE_ADDR addr)
2401 {
2402 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2403 TYPE_CODE (type) == TYPE_CODE_REF);
2404
2405 enum type_code target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2406
2407 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2408 {
2409 /* Try to find a linker symbol at this address. */
2410 struct minimal_symbol *func_msym = lookup_minimal_symbol_by_pc (addr);
2411
2412 if (! func_msym)
2413 error ("Cannot convert code address %s to function pointer:\n"
2414 "couldn't find a symbol at that address, to find trampoline.",
2415 paddr_nz (addr));
2416
2417 char *func_name = SYMBOL_LINKAGE_NAME (func_msym);
2418 char *tramp_name = xmalloc (strlen (func_name) + 5);
2419 strcpy (tramp_name, func_name);
2420 strcat (tramp_name, ".plt");
2421
2422 /* Try to find a linker symbol for the trampoline. */
2423 struct minimal_symbol *tramp_msym
2424 = lookup_minimal_symbol (tramp_name, NULL, NULL);
2425
2426 /* We've either got another copy of the name now, or don't need
2427 the name any more. */
2428 xfree (tramp_name);
2429
2430 if (! tramp_msym)
2431 error ("Cannot convert code address %s to function pointer:\n"
2432 "couldn't find trampoline named '%s.plt'.",
2433 paddr_nz (addr), func_name);
2434
2435 /* The trampoline's address is our pointer. */
2436 addr = SYMBOL_VALUE_ADDRESS (tramp_msym);
2437 }
2438
2439 store_unsigned_integer (buf, TYPE_LENGTH (type), addr);
2440 }
2441
2442
2443 static CORE_ADDR
2444 m32c_m16c_pointer_to_address (struct type *type, const gdb_byte *buf)
2445 {
2446 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2447 TYPE_CODE (type) == TYPE_CODE_REF);
2448
2449 CORE_ADDR ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
2450
2451 enum type_code target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2452
2453 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2454 {
2455 /* See if there is a minimal symbol at that address whose name is
2456 "NAME.plt". */
2457 struct minimal_symbol *ptr_msym = lookup_minimal_symbol_by_pc (ptr);
2458
2459 if (ptr_msym)
2460 {
2461 char *ptr_msym_name = SYMBOL_LINKAGE_NAME (ptr_msym);
2462 int len = strlen (ptr_msym_name);
2463
2464 if (len > 4
2465 && strcmp (ptr_msym_name + len - 4, ".plt") == 0)
2466 {
2467 /* We have a .plt symbol; try to find the symbol for the
2468 corresponding function.
2469
2470 Since the trampoline contains a jump instruction, we
2471 could also just extract the jump's target address. I
2472 don't see much advantage one way or the other. */
2473 char *func_name = xmalloc (len - 4 + 1);
2474 memcpy (func_name, ptr_msym_name, len - 4);
2475 func_name[len - 4] = '\0';
2476 struct minimal_symbol *func_msym
2477 = lookup_minimal_symbol (func_name, NULL, NULL);
2478
2479 /* If we do have such a symbol, return its value as the
2480 function's true address. */
2481 if (func_msym)
2482 ptr = SYMBOL_VALUE_ADDRESS (func_msym);
2483 }
2484 }
2485 }
2486
2487 return ptr;
2488 }
2489
2490 void
2491 m32c_virtual_frame_pointer (CORE_ADDR pc,
2492 int *frame_regnum,
2493 LONGEST *frame_offset)
2494 {
2495 char *name;
2496 CORE_ADDR func_addr, func_end, sal_end;
2497 struct m32c_prologue p;
2498
2499 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2500
2501 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
2502 internal_error (__FILE__, __LINE__, _("No virtual frame pointer available"));
2503
2504 m32c_analyze_prologue (current_gdbarch, func_addr, pc, &p);
2505 switch (p.kind)
2506 {
2507 case prologue_with_frame_ptr:
2508 *frame_regnum = m32c_banked_register (tdep->fb, current_regcache)->num;
2509 *frame_offset = p.frame_ptr_offset;
2510 break;
2511 case prologue_sans_frame_ptr:
2512 *frame_regnum = m32c_banked_register (tdep->sp, current_regcache)->num;
2513 *frame_offset = p.frame_size;
2514 break;
2515 default:
2516 *frame_regnum = m32c_banked_register (tdep->sp, current_regcache)->num;
2517 *frame_offset = 0;
2518 break;
2519 }
2520 /* Sanity check */
2521 if (*frame_regnum > NUM_REGS)
2522 internal_error (__FILE__, __LINE__, _("No virtual frame pointer available"));
2523 }
2524
2525 \f
2526 /* Initialization. */
2527
2528 static struct gdbarch *
2529 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2530 {
2531 struct gdbarch *arch;
2532 struct gdbarch_tdep *tdep;
2533 unsigned long mach = info.bfd_arch_info->mach;
2534
2535 /* Find a candidate among the list of architectures we've created
2536 already. */
2537 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2538 arches != NULL;
2539 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2540 return arches->gdbarch;
2541
2542 tdep = xcalloc (1, sizeof (*tdep));
2543 arch = gdbarch_alloc (&info, tdep);
2544
2545 /* Essential types. */
2546 make_types (arch);
2547
2548 /* Address/pointer conversions. */
2549 if (mach == bfd_mach_m16c)
2550 {
2551 set_gdbarch_address_to_pointer (arch, m32c_m16c_address_to_pointer);
2552 set_gdbarch_pointer_to_address (arch, m32c_m16c_pointer_to_address);
2553 }
2554
2555 /* Register set. */
2556 make_regs (arch);
2557
2558 /* Disassembly. */
2559 set_gdbarch_print_insn (arch, print_insn_m32c);
2560
2561 /* Breakpoints. */
2562 set_gdbarch_breakpoint_from_pc (arch, m32c_breakpoint_from_pc);
2563
2564 /* Prologue analysis and unwinding. */
2565 set_gdbarch_inner_than (arch, core_addr_lessthan);
2566 set_gdbarch_skip_prologue (arch, m32c_skip_prologue);
2567 set_gdbarch_unwind_pc (arch, m32c_unwind_pc);
2568 set_gdbarch_unwind_sp (arch, m32c_unwind_sp);
2569 #if 0
2570 /* I'm dropping the dwarf2 sniffer because it has a few problems.
2571 They may be in the dwarf2 cfi code in GDB, or they may be in
2572 the debug info emitted by the upstream toolchain. I don't
2573 know which, but I do know that the prologue analyzer works better.
2574 MVS 04/13/06
2575 */
2576 frame_unwind_append_sniffer (arch, dwarf2_frame_sniffer);
2577 #endif
2578 frame_unwind_append_sniffer (arch, m32c_frame_sniffer);
2579
2580 /* Inferior calls. */
2581 set_gdbarch_push_dummy_call (arch, m32c_push_dummy_call);
2582 set_gdbarch_return_value (arch, m32c_return_value);
2583 set_gdbarch_unwind_dummy_id (arch, m32c_unwind_dummy_id);
2584
2585 /* Trampolines. */
2586 set_gdbarch_skip_trampoline_code (arch, m32c_skip_trampoline_code);
2587
2588 set_gdbarch_virtual_frame_pointer (arch, m32c_virtual_frame_pointer);
2589
2590 return arch;
2591 }
2592
2593
2594 void
2595 _initialize_m32c_tdep (void)
2596 {
2597 register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init);
2598
2599 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP);
2600 }
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