gdb/m32r-tdep.c

   1 /* Target-dependent code for Renesas M32R, for GDB.
   2
   3    Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
   4    Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "frame.h"
  25 #include "frame-unwind.h"
  26 #include "frame-base.h"
  27 #include "symtab.h"
  28 #include "gdbtypes.h"
  29 #include "gdbcmd.h"
  30 #include "gdbcore.h"
  31 #include "gdb_string.h"
  32 #include "value.h"
  33 #include "inferior.h"
  34 #include "symfile.h"
  35 #include "objfiles.h"
  36 #include "language.h"
  37 #include "arch-utils.h"
  38 #include "regcache.h"
  39 #include "trad-frame.h"
  40 #include "dis-asm.h"
  41
  42 #include "gdb_assert.h"
  43
  44 struct gdbarch_tdep
  45 {
  46   /* gdbarch target dependent data here. Currently unused for M32R. */
  47 };
  48
  49 /* m32r register names. */
  50
  51 enum
  52 {
  53   R0_REGNUM = 0,
  54   R3_REGNUM = 3,
  55   M32R_FP_REGNUM = 13,
  56   LR_REGNUM = 14,
  57   M32R_SP_REGNUM = 15,
  58   PSW_REGNUM = 16,
  59   M32R_PC_REGNUM = 21,
  60   /* m32r calling convention. */
  61   ARG1_REGNUM = R0_REGNUM,
  62   ARGN_REGNUM = R3_REGNUM,
  63   RET1_REGNUM = R0_REGNUM,
  64 };
  65
  66 /* Local functions */
  67
  68 extern void _initialize_m32r_tdep (void);
  69
  70 static CORE_ADDR
  71 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  72 {
  73   /* Align to the size of an instruction (so that they can safely be
  74      pushed onto the stack.  */
  75   return sp & ~3;
  76 }
  77
  78 /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
  79    EXTRACT_RETURN_VALUE?  GCC_P is true if compiled with gcc and TYPE
  80    is the type (which is known to be struct, union or array).
  81
  82    The m32r returns anything less than 8 bytes in size in
  83    registers. */
  84
  85 static int
  86 m32r_use_struct_convention (int gcc_p, struct type *type)
  87 {
  88   return (TYPE_LENGTH (type) > 8);
  89 }
  90
  91
  92 /* BREAKPOINT */
  93 #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00}
  94 #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70}
  95 #define M32R_BE_BREAKPOINT16 {0x10, 0xf1}
  96 #define M32R_LE_BREAKPOINT16 {0xf1, 0x10}
  97
  98 static int
  99 m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
 100 {
 101   int val;
 102   unsigned char *bp;
 103   int bplen;
 104
 105   bplen = (addr & 3) ? 2 : 4;
 106
 107   /* Save the memory contents.  */
 108   val = target_read_memory (addr, contents_cache, bplen);
 109   if (val != 0)
 110     return val;                 /* return error */
 111
 112   /* Determine appropriate breakpoint contents and size for this address.  */
 113   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 114     {
 115       if (((addr & 3) == 0)
 116           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
 117         {
 118           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 119           bp = insn;
 120           bplen = sizeof (insn);
 121         }
 122       else
 123         {
 124           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 125           bp = insn;
 126           bplen = sizeof (insn);
 127         }
 128     }
 129   else
 130     {                           /* little-endian */
 131       if (((addr & 3) == 0)
 132           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 133         {
 134           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 135           bp = insn;
 136           bplen = sizeof (insn);
 137         }
 138       else
 139         {
 140           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 141           bp = insn;
 142           bplen = sizeof (insn);
 143         }
 144     }
 145
 146   /* Write the breakpoint.  */
 147   val = target_write_memory (addr, (char *) bp, bplen);
 148   return val;
 149 }
 150
 151 static int
 152 m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
 153 {
 154   int val;
 155   int bplen;
 156
 157   /* Determine appropriate breakpoint contents and size for this address.  */
 158   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 159     {
 160       if (((addr & 3) == 0)
 161           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
 162         {
 163           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 164           bplen = sizeof (insn);
 165         }
 166       else
 167         {
 168           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 169           bplen = sizeof (insn);
 170         }
 171     }
 172   else
 173     {
 174       /* little-endian */
 175       if (((addr & 3) == 0)
 176           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 177         {
 178           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 179           bplen = sizeof (insn);
 180         }
 181       else
 182         {
 183           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 184           bplen = sizeof (insn);
 185         }
 186     }
 187
 188   /* Write contents.  */
 189   val = target_write_memory (addr, contents_cache, bplen);
 190   return val;
 191 }
 192
 193 static const unsigned char *
 194 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 195 {
 196   unsigned char *bp;
 197
 198   /* Determine appropriate breakpoint.  */
 199   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 200     {
 201       if ((*pcptr & 3) == 0)
 202         {
 203           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 204           bp = insn;
 205           *lenptr = sizeof (insn);
 206         }
 207       else
 208         {
 209           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 210           bp = insn;
 211           *lenptr = sizeof (insn);
 212         }
 213     }
 214   else
 215     {
 216       if ((*pcptr & 3) == 0)
 217         {
 218           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 219           bp = insn;
 220           *lenptr = sizeof (insn);
 221         }
 222       else
 223         {
 224           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 225           bp = insn;
 226           *lenptr = sizeof (insn);
 227         }
 228     }
 229
 230   return bp;
 231 }
 232
 233
 234 char *m32r_register_names[] = {
 235   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 236   "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
 237   "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
 238   "evb"
 239 };
 240
 241 static int
 242 m32r_num_regs (void)
 243 {
 244   return (sizeof (m32r_register_names) / sizeof (m32r_register_names[0]));
 245 }
 246
 247 static const char *
 248 m32r_register_name (int reg_nr)
 249 {
 250   if (reg_nr < 0)
 251     return NULL;
 252   if (reg_nr >= m32r_num_regs ())
 253     return NULL;
 254   return m32r_register_names[reg_nr];
 255 }
 256
 257
 258 /* Return the GDB type object for the "standard" data type
 259    of data in register N.  */
 260
 261 static struct type *
 262 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
 263 {
 264   if (reg_nr == M32R_PC_REGNUM)
 265     return builtin_type_void_func_ptr;
 266   else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
 267     return builtin_type_void_data_ptr;
 268   else
 269     return builtin_type_int32;
 270 }
 271
 272
 273 /* Write into appropriate registers a function return value
 274    of type TYPE, given in virtual format.
 275
 276    Things always get returned in RET1_REGNUM, RET2_REGNUM. */
 277
 278 static void
 279 m32r_store_return_value (struct type *type, struct regcache *regcache,
 280                          const void *valbuf)
 281 {
 282   CORE_ADDR regval;
 283   int len = TYPE_LENGTH (type);
 284
 285   regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
 286   regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
 287
 288   if (len > 4)
 289     {
 290       regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4);
 291       regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
 292     }
 293 }
 294
 295 /* Extract from an array REGBUF containing the (raw) register state
 296    the address in which a function should return its structure value,
 297    as a CORE_ADDR (or an expression that can be used as one).  */
 298
 299 static CORE_ADDR
 300 m32r_extract_struct_value_address (struct regcache *regcache)
 301 {
 302   ULONGEST addr;
 303   regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr);
 304   return addr;
 305 }
 306
 307
 308 /* This is required by skip_prologue. The results of decoding a prologue
 309    should be cached because this thrashing is getting nuts.  */
 310
 311 static void
 312 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
 313                  CORE_ADDR *pl_endptr)
 314 {
 315   unsigned long framesize;
 316   int insn;
 317   int op1;
 318   int maybe_one_more = 0;
 319   CORE_ADDR after_prologue = 0;
 320   CORE_ADDR after_stack_adjust = 0;
 321   CORE_ADDR current_pc;
 322
 323   framesize = 0;
 324   after_prologue = 0;
 325
 326   for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
 327     {
 328       insn = read_memory_unsigned_integer (current_pc, 2);
 329
 330       /* If this is a 32 bit instruction, we dont want to examine its
 331          immediate data as though it were an instruction */
 332       if (current_pc & 0x02)
 333         {
 334           /* Clear the parallel execution bit from 16 bit instruction */
 335           if (maybe_one_more)
 336             {
 337               /* The last instruction was a branch, usually terminates
 338                  the series, but if this is a parallel instruction,
 339                  it may be a stack framing instruction */
 340               if (!(insn & 0x8000))
 341                 {
 342                   /* nope, we are really done */
 343                   break;
 344                 }
 345             }
 346           /* decode this instruction further */
 347           insn &= 0x7fff;
 348         }
 349       else
 350         {
 351           if (maybe_one_more)
 352             break;              /* This isnt the one more */
 353           if (insn & 0x8000)
 354             {
 355               if (current_pc == scan_limit)
 356                 scan_limit += 2;        /* extend the search */
 357               current_pc += 2;  /* skip the immediate data */
 358               if (insn == 0x8faf)       /* add3 sp, sp, xxxx */
 359                 /* add 16 bit sign-extended offset */
 360                 {
 361                   framesize +=
 362                     -((short) read_memory_unsigned_integer (current_pc, 2));
 363                 }
 364               else
 365                 {
 366                   if (((insn >> 8) == 0xe4)     /* ld24 r4, xxxxxx; sub sp, r4 */
 367                       && read_memory_unsigned_integer (current_pc + 2,
 368                                                        2) == 0x0f24)
 369                     /* subtract 24 bit sign-extended negative-offset */
 370                     {
 371                       insn = read_memory_unsigned_integer (current_pc - 2, 4);
 372                       if (insn & 0x00800000)    /* sign extend */
 373                         insn |= 0xff000000;     /* negative */
 374                       else
 375                         insn &= 0x00ffffff;     /* positive */
 376                       framesize += insn;
 377                     }
 378                 }
 379               after_prologue = current_pc;
 380               continue;
 381             }
 382         }
 383       op1 = insn & 0xf000;      /* isolate just the first nibble */
 384
 385       if ((insn & 0xf0ff) == 0x207f)
 386         {                       /* st reg, @-sp */
 387           int regno;
 388           framesize += 4;
 389           regno = ((insn >> 8) & 0xf);
 390           after_prologue = 0;
 391           continue;
 392         }
 393       if ((insn >> 8) == 0x4f)  /* addi sp, xx */
 394         /* add 8 bit sign-extended offset */
 395         {
 396           int stack_adjust = (char) (insn & 0xff);
 397
 398           /* there are probably two of these stack adjustments:
 399              1) A negative one in the prologue, and
 400              2) A positive one in the epilogue.
 401              We are only interested in the first one.  */
 402
 403           if (stack_adjust < 0)
 404             {
 405               framesize -= stack_adjust;
 406               after_prologue = 0;
 407               /* A frameless function may have no "mv fp, sp".
 408                  In that case, this is the end of the prologue.  */
 409               after_stack_adjust = current_pc + 2;
 410             }
 411           continue;
 412         }
 413       if (insn == 0x1d8f)
 414         {                       /* mv fp, sp */
 415           after_prologue = current_pc + 2;
 416           break;                /* end of stack adjustments */
 417         }
 418       /* Nop looks like a branch, continue explicitly */
 419       if (insn == 0x7000)
 420         {
 421           after_prologue = current_pc + 2;
 422           continue;             /* nop occurs between pushes */
 423         }
 424       /* End of prolog if any of these are branch instructions */
 425       if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
 426         {
 427           after_prologue = current_pc;
 428           maybe_one_more = 1;
 429           continue;
 430         }
 431       /* Some of the branch instructions are mixed with other types */
 432       if (op1 == 0x1000)
 433         {
 434           int subop = insn & 0x0ff0;
 435           if ((subop == 0x0ec0) || (subop == 0x0fc0))
 436             {
 437               after_prologue = current_pc;
 438               maybe_one_more = 1;
 439               continue;         /* jmp , jl */
 440             }
 441         }
 442     }
 443
 444   if (current_pc >= scan_limit)
 445     {
 446       if (pl_endptr)
 447         {
 448           if (after_stack_adjust != 0)
 449             /* We did not find a "mv fp,sp", but we DID find
 450                a stack_adjust.  Is it safe to use that as the
 451                end of the prologue?  I just don't know. */
 452             {
 453               *pl_endptr = after_stack_adjust;
 454             }
 455           else
 456             /* We reached the end of the loop without finding the end
 457                of the prologue.  No way to win -- we should report failure.
 458                The way we do that is to return the original start_pc.
 459                GDB will set a breakpoint at the start of the function (etc.) */
 460             *pl_endptr = start_pc;
 461         }
 462       return;
 463     }
 464   if (after_prologue == 0)
 465     after_prologue = current_pc;
 466
 467   if (pl_endptr)
 468     *pl_endptr = after_prologue;
 469 }                               /*  decode_prologue */
 470
 471 /* Function: skip_prologue
 472    Find end of function prologue */
 473
 474 #define DEFAULT_SEARCH_LIMIT 44
 475
 476 CORE_ADDR
 477 m32r_skip_prologue (CORE_ADDR pc)
 478 {
 479   CORE_ADDR func_addr, func_end;
 480   struct symtab_and_line sal;
 481
 482   /* See what the symbol table says */
 483
 484   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 485     {
 486       sal = find_pc_line (func_addr, 0);
 487
 488       if (sal.line != 0 && sal.end <= func_end)
 489         {
 490           func_end = sal.end;
 491         }
 492       else
 493         /* Either there's no line info, or the line after the prologue is after
 494            the end of the function.  In this case, there probably isn't a
 495            prologue.  */
 496         {
 497           func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
 498         }
 499     }
 500   else
 501     func_end = pc + DEFAULT_SEARCH_LIMIT;
 502   decode_prologue (pc, func_end, &sal.end);
 503   return sal.end;
 504 }
 505
 506
 507 struct m32r_unwind_cache
 508 {
 509   /* The previous frame's inner most stack address.  Used as this
 510      frame ID's stack_addr.  */
 511   CORE_ADDR prev_sp;
 512   /* The frame's base, optionally used by the high-level debug info.  */
 513   CORE_ADDR base;
 514   int size;
 515   /* How far the SP and r13 (FP) have been offset from the start of
 516      the stack frame (as defined by the previous frame's stack
 517      pointer).  */
 518   LONGEST sp_offset;
 519   LONGEST r13_offset;
 520   int uses_frame;
 521   /* Table indicating the location of each and every register.  */
 522   struct trad_frame_saved_reg *saved_regs;
 523 };
 524
 525 /* Put here the code to store, into fi->saved_regs, the addresses of
 526    the saved registers of frame described by FRAME_INFO.  This
 527    includes special registers such as pc and fp saved in special ways
 528    in the stack frame.  sp is even more special: the address we return
 529    for it IS the sp for the next frame. */
 530
 531 static struct m32r_unwind_cache *
 532 m32r_frame_unwind_cache (struct frame_info *next_frame,
 533                          void **this_prologue_cache)
 534 {
 535   CORE_ADDR pc;
 536   ULONGEST prev_sp;
 537   ULONGEST this_base;
 538   unsigned long op;
 539   int i;
 540   struct m32r_unwind_cache *info;
 541
 542   if ((*this_prologue_cache))
 543     return (*this_prologue_cache);
 544
 545   info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
 546   (*this_prologue_cache) = info;
 547   info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
 548
 549   info->size = 0;
 550   info->sp_offset = 0;
 551
 552   info->uses_frame = 0;
 553   for (pc = frame_func_unwind (next_frame);
 554        pc > 0 && pc < frame_pc_unwind (next_frame); pc += 2)
 555     {
 556       if ((pc & 2) == 0)
 557         {
 558           op = get_frame_memory_unsigned (next_frame, pc, 4);
 559           if ((op & 0x80000000) == 0x80000000)
 560             {
 561               /* 32-bit instruction */
 562               if ((op & 0xffff0000) == 0x8faf0000)
 563                 {
 564                   /* add3 sp,sp,xxxx */
 565                   short n = op & 0xffff;
 566                   info->sp_offset += n;
 567                 }
 568               else if (((op >> 8) == 0xe4)      /* ld24 r4, xxxxxx; sub sp, r4 */
 569                        && get_frame_memory_unsigned (next_frame, pc + 4,
 570                                                      2) == 0x0f24)
 571                 {
 572                   unsigned long n = op & 0xffffff;
 573                   info->sp_offset += n;
 574                   pc += 2;
 575                 }
 576               else
 577                 break;
 578
 579               pc += 2;
 580               continue;
 581             }
 582         }
 583
 584       /* 16-bit instructions */
 585       op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
 586       if ((op & 0xf0ff) == 0x207f)
 587         {
 588           /* st rn, @-sp */
 589           int regno = ((op >> 8) & 0xf);
 590           info->sp_offset -= 4;
 591           info->saved_regs[regno].addr = info->sp_offset;
 592         }
 593       else if ((op & 0xff00) == 0x4f00)
 594         {
 595           /* addi sp, xx */
 596           int n = (char) (op & 0xff);
 597           info->sp_offset += n;
 598         }
 599       else if (op == 0x1d8f)
 600         {
 601           /* mv fp, sp */
 602           info->uses_frame = 1;
 603           info->r13_offset = info->sp_offset;
 604         }
 605       else if (op == 0x7000)
 606         /* nop */
 607         continue;
 608       else
 609         break;
 610     }
 611
 612   info->size = -info->sp_offset;
 613
 614   /* Compute the previous frame's stack pointer (which is also the
 615      frame's ID's stack address), and this frame's base pointer.  */
 616   if (info->uses_frame)
 617     {
 618       /* The SP was moved to the FP.  This indicates that a new frame
 619          was created.  Get THIS frame's FP value by unwinding it from
 620          the next frame.  */
 621       this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
 622       /* The FP points at the last saved register.  Adjust the FP back
 623          to before the first saved register giving the SP.  */
 624       prev_sp = this_base + info->size;
 625     }
 626   else
 627     {
 628       /* Assume that the FP is this frame's SP but with that pushed
 629          stack space added back.  */
 630       this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 631       prev_sp = this_base + info->size;
 632     }
 633
 634   /* Convert that SP/BASE into real addresses.  */
 635   info->prev_sp = prev_sp;
 636   info->base = this_base;
 637
 638   /* Adjust all the saved registers so that they contain addresses and
 639      not offsets.  */
 640   for (i = 0; i < NUM_REGS - 1; i++)
 641     if (trad_frame_addr_p (info->saved_regs, i))
 642       info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
 643
 644   /* The call instruction moves the caller's PC in the callee's LR.
 645      Since this is an unwind, do the reverse.  Copy the location of LR
 646      into PC (the address / regnum) so that a request for PC will be
 647      converted into a request for the LR.  */
 648   info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
 649
 650   /* The previous frame's SP needed to be computed.  Save the computed
 651      value.  */
 652   trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
 653
 654   return info;
 655 }
 656
 657 static CORE_ADDR
 658 m32r_read_pc (ptid_t ptid)
 659 {
 660   ptid_t save_ptid;
 661   ULONGEST pc;
 662
 663   save_ptid = inferior_ptid;
 664   inferior_ptid = ptid;
 665   regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc);
 666   inferior_ptid = save_ptid;
 667   return pc;
 668 }
 669
 670 static void
 671 m32r_write_pc (CORE_ADDR val, ptid_t ptid)
 672 {
 673   ptid_t save_ptid;
 674
 675   save_ptid = inferior_ptid;
 676   inferior_ptid = ptid;
 677   write_register (M32R_PC_REGNUM, val);
 678   inferior_ptid = save_ptid;
 679 }
 680
 681 static CORE_ADDR
 682 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 683 {
 684   return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 685 }
 686
 687
 688 static CORE_ADDR
 689 m32r_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
 690                       struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
 691                       struct value **args, CORE_ADDR sp, int struct_return,
 692                       CORE_ADDR struct_addr)
 693 {
 694   int stack_offset, stack_alloc;
 695   int argreg = ARG1_REGNUM;
 696   int argnum;
 697   struct type *type;
 698   enum type_code typecode;
 699   CORE_ADDR regval;
 700   char *val;
 701   char valbuf[MAX_REGISTER_SIZE];
 702   int len;
 703   int odd_sized_struct;
 704
 705   /* first force sp to a 4-byte alignment */
 706   sp = sp & ~3;
 707
 708   /* Set the return address.  For the m32r, the return breakpoint is
 709      always at BP_ADDR.  */
 710   regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
 711
 712   /* If STRUCT_RETURN is true, then the struct return address (in
 713      STRUCT_ADDR) will consume the first argument-passing register.
 714      Both adjust the register count and store that value.  */
 715   if (struct_return)
 716     {
 717       regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
 718       argreg++;
 719     }
 720
 721   /* Now make sure there's space on the stack */
 722   for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
 723     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
 724   sp -= stack_alloc;            /* make room on stack for args */
 725
 726   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 727     {
 728       type = VALUE_TYPE (args[argnum]);
 729       typecode = TYPE_CODE (type);
 730       len = TYPE_LENGTH (type);
 731
 732       memset (valbuf, 0, sizeof (valbuf));
 733
 734       /* Passes structures that do not fit in 2 registers by reference.  */
 735       if (len > 8
 736           && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
 737         {
 738           store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
 739           typecode = TYPE_CODE_PTR;
 740           len = 4;
 741           val = valbuf;
 742         }
 743       else if (len < 4)
 744         {
 745           /* value gets right-justified in the register or stack word */
 746           memcpy (valbuf + (register_size (gdbarch, argreg) - len),
 747                   (char *) VALUE_CONTENTS (args[argnum]), len);
 748           val = valbuf;
 749         }
 750       else
 751         val = (char *) VALUE_CONTENTS (args[argnum]);
 752
 753       while (len > 0)
 754         {
 755           if (argreg > ARGN_REGNUM)
 756             {
 757               /* must go on the stack */
 758               write_memory (sp + stack_offset, val, 4);
 759               stack_offset += 4;
 760             }
 761           else if (argreg <= ARGN_REGNUM)
 762             {
 763               /* there's room in a register */
 764               regval =
 765                 extract_unsigned_integer (val,
 766                                           register_size (gdbarch, argreg));
 767               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 768             }
 769
 770           /* Store the value 4 bytes at a time.  This means that things
 771              larger than 4 bytes may go partly in registers and partly
 772              on the stack.  */
 773           len -= register_size (gdbarch, argreg);
 774           val += register_size (gdbarch, argreg);
 775         }
 776     }
 777
 778   /* Finally, update the SP register.  */
 779   regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
 780
 781   return sp;
 782 }
 783
 784
 785 /* Given a return value in `regbuf' with a type `valtype',
 786    extract and copy its value into `valbuf'.  */
 787
 788 static void
 789 m32r_extract_return_value (struct type *type, struct regcache *regcache,
 790                            void *dst)
 791 {
 792   bfd_byte *valbuf = dst;
 793   int len = TYPE_LENGTH (type);
 794   ULONGEST tmp;
 795
 796   /* By using store_unsigned_integer we avoid having to do
 797      anything special for small big-endian values.  */
 798   regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
 799   store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
 800
 801   /* Ignore return values more than 8 bytes in size because the m32r
 802      returns anything more than 8 bytes in the stack. */
 803   if (len > 4)
 804     {
 805       regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
 806       store_unsigned_integer (valbuf + len - 4, 4, tmp);
 807     }
 808 }
 809
 810
 811 static CORE_ADDR
 812 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 813 {
 814   return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
 815 }
 816
 817 /* Given a GDB frame, determine the address of the calling function's
 818    frame.  This will be used to create a new GDB frame struct.  */
 819
 820 static void
 821 m32r_frame_this_id (struct frame_info *next_frame,
 822                     void **this_prologue_cache, struct frame_id *this_id)
 823 {
 824   struct m32r_unwind_cache *info
 825     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 826   CORE_ADDR base;
 827   CORE_ADDR func;
 828   struct minimal_symbol *msym_stack;
 829   struct frame_id id;
 830
 831   /* The FUNC is easy.  */
 832   func = frame_func_unwind (next_frame);
 833
 834   /* Check if the stack is empty.  */
 835   msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
 836   if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
 837     return;
 838
 839   /* Hopefully the prologue analysis either correctly determined the
 840      frame's base (which is the SP from the previous frame), or set
 841      that base to "NULL".  */
 842   base = info->prev_sp;
 843   if (base == 0)
 844     return;
 845
 846   id = frame_id_build (base, func);
 847
 848   /* Check that we're not going round in circles with the same frame
 849      ID (but avoid applying the test to sentinel frames which do go
 850      round in circles).  Can't use frame_id_eq() as that doesn't yet
 851      compare the frame's PC value.  */
 852   if (frame_relative_level (next_frame) >= 0
 853       && get_frame_type (next_frame) != DUMMY_FRAME
 854       && frame_id_eq (get_frame_id (next_frame), id))
 855     return;
 856
 857   (*this_id) = id;
 858 }
 859
 860 static void
 861 m32r_frame_prev_register (struct frame_info *next_frame,
 862                           void **this_prologue_cache,
 863                           int regnum, int *optimizedp,
 864                           enum lval_type *lvalp, CORE_ADDR *addrp,
 865                           int *realnump, void *bufferp)
 866 {
 867   struct m32r_unwind_cache *info
 868     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 869   trad_frame_prev_register (next_frame, info->saved_regs, regnum,
 870                             optimizedp, lvalp, addrp, realnump, bufferp);
 871 }
 872
 873 static const struct frame_unwind m32r_frame_unwind = {
 874   NORMAL_FRAME,
 875   m32r_frame_this_id,
 876   m32r_frame_prev_register
 877 };
 878
 879 static const struct frame_unwind *
 880 m32r_frame_sniffer (struct frame_info *next_frame)
 881 {
 882   return &m32r_frame_unwind;
 883 }
 884
 885 static CORE_ADDR
 886 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
 887 {
 888   struct m32r_unwind_cache *info
 889     = m32r_frame_unwind_cache (next_frame, this_cache);
 890   return info->base;
 891 }
 892
 893 static const struct frame_base m32r_frame_base = {
 894   &m32r_frame_unwind,
 895   m32r_frame_base_address,
 896   m32r_frame_base_address,
 897   m32r_frame_base_address
 898 };
 899
 900 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
 901    dummy frame.  The frame ID's base needs to match the TOS value
 902    saved by save_dummy_frame_tos(), and the PC match the dummy frame's
 903    breakpoint.  */
 904
 905 static struct frame_id
 906 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
 907 {
 908   return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
 909                          frame_pc_unwind (next_frame));
 910 }
 911
 912
 913 static gdbarch_init_ftype m32r_gdbarch_init;
 914
 915 static struct gdbarch *
 916 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 917 {
 918   struct gdbarch *gdbarch;
 919   struct gdbarch_tdep *tdep;
 920
 921   /* If there is already a candidate, use it.  */
 922   arches = gdbarch_list_lookup_by_info (arches, &info);
 923   if (arches != NULL)
 924     return arches->gdbarch;
 925
 926   /* Allocate space for the new architecture.  */
 927   tdep = XMALLOC (struct gdbarch_tdep);
 928   gdbarch = gdbarch_alloc (&info, tdep);
 929
 930   set_gdbarch_read_pc (gdbarch, m32r_read_pc);
 931   set_gdbarch_write_pc (gdbarch, m32r_write_pc);
 932   set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
 933
 934   set_gdbarch_num_regs (gdbarch, m32r_num_regs ());
 935   set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
 936   set_gdbarch_register_name (gdbarch, m32r_register_name);
 937   set_gdbarch_register_type (gdbarch, m32r_register_type);
 938
 939   set_gdbarch_extract_return_value (gdbarch, m32r_extract_return_value);
 940   set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
 941   set_gdbarch_store_return_value (gdbarch, m32r_store_return_value);
 942   set_gdbarch_deprecated_extract_struct_value_address (gdbarch, m32r_extract_struct_value_address);
 943   set_gdbarch_use_struct_convention (gdbarch, m32r_use_struct_convention);
 944
 945   set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
 946   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 947   set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
 948   set_gdbarch_memory_insert_breakpoint (gdbarch,
 949                                         m32r_memory_insert_breakpoint);
 950   set_gdbarch_memory_remove_breakpoint (gdbarch,
 951                                         m32r_memory_remove_breakpoint);
 952
 953   set_gdbarch_frame_args_skip (gdbarch, 0);
 954   set_gdbarch_frameless_function_invocation (gdbarch,
 955                                              frameless_look_for_prologue);
 956
 957   set_gdbarch_frame_align (gdbarch, m32r_frame_align);
 958
 959   frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
 960   frame_base_set_default (gdbarch, &m32r_frame_base);
 961
 962   /* Methods for saving / extracting a dummy frame's ID.  The ID's
 963      stack address must match the SP value returned by
 964      PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos.  */
 965   set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
 966
 967   /* Return the unwound PC value.  */
 968   set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
 969
 970   set_gdbarch_print_insn (gdbarch, print_insn_m32r);
 971
 972   return gdbarch;
 973 }
 974
 975 void
 976 _initialize_m32r_tdep (void)
 977 {
 978   register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);
 979 }