gdb/m32r-tdep.c

   1 /* Target-dependent code for Renesas M32R, for GDB.
   2
   3    Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
   4    Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "frame.h"
  25 #include "frame-unwind.h"
  26 #include "frame-base.h"
  27 #include "symtab.h"
  28 #include "gdbtypes.h"
  29 #include "gdbcmd.h"
  30 #include "gdbcore.h"
  31 #include "gdb_string.h"
  32 #include "value.h"
  33 #include "inferior.h"
  34 #include "symfile.h"
  35 #include "objfiles.h"
  36 #include "language.h"
  37 #include "arch-utils.h"
  38 #include "regcache.h"
  39 #include "trad-frame.h"
  40 #include "dis-asm.h"
  41
  42 #include "gdb_assert.h"
  43
  44 #include "m32r-tdep.h"
  45
  46 /* Local functions */
  47
  48 extern void _initialize_m32r_tdep (void);
  49
  50 static CORE_ADDR
  51 m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  52 {
  53   /* Align to the size of an instruction (so that they can safely be
  54      pushed onto the stack.  */
  55   return sp & ~3;
  56 }
  57
  58
  59 /* BREAKPOINT */
  60 #define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00}
  61 #define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70}
  62 #define M32R_BE_BREAKPOINT16 {0x10, 0xf1}
  63 #define M32R_LE_BREAKPOINT16 {0xf1, 0x10}
  64
  65 static int
  66 m32r_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
  67 {
  68   int val;
  69   unsigned char *bp;
  70   int bplen;
  71
  72   bplen = (addr & 3) ? 2 : 4;
  73
  74   /* Save the memory contents.  */
  75   val = target_read_memory (addr, contents_cache, bplen);
  76   if (val != 0)
  77     return val;                 /* return error */
  78
  79   /* Determine appropriate breakpoint contents and size for this address.  */
  80   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
  81     {
  82       if (((addr & 3) == 0)
  83           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
  84         {
  85           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
  86           bp = insn;
  87           bplen = sizeof (insn);
  88         }
  89       else
  90         {
  91           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
  92           bp = insn;
  93           bplen = sizeof (insn);
  94         }
  95     }
  96   else
  97     {                           /* little-endian */
  98       if (((addr & 3) == 0)
  99           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 100         {
 101           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 102           bp = insn;
 103           bplen = sizeof (insn);
 104         }
 105       else
 106         {
 107           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 108           bp = insn;
 109           bplen = sizeof (insn);
 110         }
 111     }
 112
 113   /* Write the breakpoint.  */
 114   val = target_write_memory (addr, (char *) bp, bplen);
 115   return val;
 116 }
 117
 118 static int
 119 m32r_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
 120 {
 121   int val;
 122   int bplen;
 123
 124   /* Determine appropriate breakpoint contents and size for this address.  */
 125   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 126     {
 127       if (((addr & 3) == 0)
 128           && ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80)))
 129         {
 130           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 131           bplen = sizeof (insn);
 132         }
 133       else
 134         {
 135           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 136           bplen = sizeof (insn);
 137         }
 138     }
 139   else
 140     {
 141       /* little-endian */
 142       if (((addr & 3) == 0)
 143           && ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80)))
 144         {
 145           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 146           bplen = sizeof (insn);
 147         }
 148       else
 149         {
 150           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 151           bplen = sizeof (insn);
 152         }
 153     }
 154
 155   /* Write contents.  */
 156   val = target_write_memory (addr, contents_cache, bplen);
 157   return val;
 158 }
 159
 160 static const unsigned char *
 161 m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 162 {
 163   unsigned char *bp;
 164
 165   /* Determine appropriate breakpoint.  */
 166   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 167     {
 168       if ((*pcptr & 3) == 0)
 169         {
 170           static unsigned char insn[] = M32R_BE_BREAKPOINT32;
 171           bp = insn;
 172           *lenptr = sizeof (insn);
 173         }
 174       else
 175         {
 176           static unsigned char insn[] = M32R_BE_BREAKPOINT16;
 177           bp = insn;
 178           *lenptr = sizeof (insn);
 179         }
 180     }
 181   else
 182     {
 183       if ((*pcptr & 3) == 0)
 184         {
 185           static unsigned char insn[] = M32R_LE_BREAKPOINT32;
 186           bp = insn;
 187           *lenptr = sizeof (insn);
 188         }
 189       else
 190         {
 191           static unsigned char insn[] = M32R_LE_BREAKPOINT16;
 192           bp = insn;
 193           *lenptr = sizeof (insn);
 194         }
 195     }
 196
 197   return bp;
 198 }
 199
 200
 201 char *m32r_register_names[] = {
 202   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 203   "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
 204   "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
 205   "evb"
 206 };
 207
 208 static const char *
 209 m32r_register_name (int reg_nr)
 210 {
 211   if (reg_nr < 0)
 212     return NULL;
 213   if (reg_nr >= M32R_NUM_REGS)
 214     return NULL;
 215   return m32r_register_names[reg_nr];
 216 }
 217
 218
 219 /* Return the GDB type object for the "standard" data type
 220    of data in register N.  */
 221
 222 static struct type *
 223 m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
 224 {
 225   if (reg_nr == M32R_PC_REGNUM)
 226     return builtin_type_void_func_ptr;
 227   else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
 228     return builtin_type_void_data_ptr;
 229   else
 230     return builtin_type_int32;
 231 }
 232
 233
 234 /* Write into appropriate registers a function return value
 235    of type TYPE, given in virtual format.
 236
 237    Things always get returned in RET1_REGNUM, RET2_REGNUM. */
 238
 239 static void
 240 m32r_store_return_value (struct type *type, struct regcache *regcache,
 241                          const void *valbuf)
 242 {
 243   CORE_ADDR regval;
 244   int len = TYPE_LENGTH (type);
 245
 246   regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len);
 247   regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);
 248
 249   if (len > 4)
 250     {
 251       regval = extract_unsigned_integer ((char *) valbuf + 4, len - 4);
 252       regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
 253     }
 254 }
 255
 256 /* This is required by skip_prologue. The results of decoding a prologue
 257    should be cached because this thrashing is getting nuts.  */
 258
 259 static int
 260 decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit,
 261                  CORE_ADDR *pl_endptr, unsigned long *framelength)
 262 {
 263   unsigned long framesize;
 264   int insn;
 265   int op1;
 266   CORE_ADDR after_prologue = 0;
 267   CORE_ADDR after_push = 0;
 268   CORE_ADDR after_stack_adjust = 0;
 269   CORE_ADDR current_pc;
 270   LONGEST return_value;
 271
 272   framesize = 0;
 273   after_prologue = 0;
 274
 275   for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
 276     {
 277       /* Check if current pc's location is readable. */
 278       if (!safe_read_memory_integer (current_pc, 2, &return_value))
 279         return -1;
 280
 281       insn = read_memory_unsigned_integer (current_pc, 2);
 282
 283       if (insn == 0x0000)
 284         break;
 285
 286       /* If this is a 32 bit instruction, we dont want to examine its
 287          immediate data as though it were an instruction */
 288       if (current_pc & 0x02)
 289         {
 290           /* decode this instruction further */
 291           insn &= 0x7fff;
 292         }
 293       else
 294         {
 295           if (insn & 0x8000)
 296             {
 297               if (current_pc == scan_limit)
 298                 scan_limit += 2;        /* extend the search */
 299
 300               current_pc += 2;  /* skip the immediate data */
 301
 302               /* Check if current pc's location is readable. */
 303               if (!safe_read_memory_integer (current_pc, 2, &return_value))
 304                 return -1;
 305
 306               if (insn == 0x8faf)       /* add3 sp, sp, xxxx */
 307                 /* add 16 bit sign-extended offset */
 308                 {
 309                   framesize +=
 310                     -((short) read_memory_unsigned_integer (current_pc, 2));
 311                 }
 312               else
 313                 {
 314                   if (((insn >> 8) == 0xe4)     /* ld24 r4, xxxxxx; sub sp, r4 */
 315                       && safe_read_memory_integer (current_pc + 2, 2,
 316                                                    &return_value)
 317                       && read_memory_unsigned_integer (current_pc + 2,
 318                                                        2) == 0x0f24)
 319                     /* subtract 24 bit sign-extended negative-offset */
 320                     {
 321                       insn = read_memory_unsigned_integer (current_pc - 2, 4);
 322                       if (insn & 0x00800000)    /* sign extend */
 323                         insn |= 0xff000000;     /* negative */
 324                       else
 325                         insn &= 0x00ffffff;     /* positive */
 326                       framesize += insn;
 327                     }
 328                 }
 329               after_push = current_pc + 2;
 330               continue;
 331             }
 332         }
 333       op1 = insn & 0xf000;      /* isolate just the first nibble */
 334
 335       if ((insn & 0xf0ff) == 0x207f)
 336         {                       /* st reg, @-sp */
 337           int regno;
 338           framesize += 4;
 339           regno = ((insn >> 8) & 0xf);
 340           after_prologue = 0;
 341           continue;
 342         }
 343       if ((insn >> 8) == 0x4f)  /* addi sp, xx */
 344         /* add 8 bit sign-extended offset */
 345         {
 346           int stack_adjust = (char) (insn & 0xff);
 347
 348           /* there are probably two of these stack adjustments:
 349              1) A negative one in the prologue, and
 350              2) A positive one in the epilogue.
 351              We are only interested in the first one.  */
 352
 353           if (stack_adjust < 0)
 354             {
 355               framesize -= stack_adjust;
 356               after_prologue = 0;
 357               /* A frameless function may have no "mv fp, sp".
 358                  In that case, this is the end of the prologue.  */
 359               after_stack_adjust = current_pc + 2;
 360             }
 361           continue;
 362         }
 363       if (insn == 0x1d8f)
 364         {                       /* mv fp, sp */
 365           after_prologue = current_pc + 2;
 366           break;                /* end of stack adjustments */
 367         }
 368
 369       /* Nop looks like a branch, continue explicitly */
 370       if (insn == 0x7000)
 371         {
 372           after_prologue = current_pc + 2;
 373           continue;             /* nop occurs between pushes */
 374         }
 375       /* End of prolog if any of these are trap instructions */
 376       if ((insn & 0xfff0) == 0x10f0)
 377         {
 378           after_prologue = current_pc;
 379           break;
 380         }
 381       /* End of prolog if any of these are branch instructions */
 382       if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
 383         {
 384           after_prologue = current_pc;
 385           continue;
 386         }
 387       /* Some of the branch instructions are mixed with other types */
 388       if (op1 == 0x1000)
 389         {
 390           int subop = insn & 0x0ff0;
 391           if ((subop == 0x0ec0) || (subop == 0x0fc0))
 392             {
 393               after_prologue = current_pc;
 394               continue;         /* jmp , jl */
 395             }
 396         }
 397     }
 398
 399   if (framelength)
 400     *framelength = framesize;
 401
 402   if (current_pc >= scan_limit)
 403     {
 404       if (pl_endptr)
 405         {
 406           if (after_stack_adjust != 0)
 407             /* We did not find a "mv fp,sp", but we DID find
 408                a stack_adjust.  Is it safe to use that as the
 409                end of the prologue?  I just don't know. */
 410             {
 411               *pl_endptr = after_stack_adjust;
 412             }
 413           else if (after_push != 0)
 414             /* We did not find a "mv fp,sp", but we DID find
 415                a push.  Is it safe to use that as the
 416                end of the prologue?  I just don't know. */
 417             {
 418               *pl_endptr = after_push;
 419             }
 420           else
 421             /* We reached the end of the loop without finding the end
 422                of the prologue.  No way to win -- we should report failure.
 423                The way we do that is to return the original start_pc.
 424                GDB will set a breakpoint at the start of the function (etc.) */
 425             *pl_endptr = start_pc;
 426         }
 427       return 0;
 428     }
 429
 430   if (after_prologue == 0)
 431     after_prologue = current_pc;
 432
 433   if (pl_endptr)
 434     *pl_endptr = after_prologue;
 435
 436   return 0;
 437 }                               /*  decode_prologue */
 438
 439 /* Function: skip_prologue
 440    Find end of function prologue */
 441
 442 #define DEFAULT_SEARCH_LIMIT 128
 443
 444 CORE_ADDR
 445 m32r_skip_prologue (CORE_ADDR pc)
 446 {
 447   CORE_ADDR func_addr, func_end;
 448   struct symtab_and_line sal;
 449   LONGEST return_value;
 450
 451   /* See what the symbol table says */
 452
 453   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 454     {
 455       sal = find_pc_line (func_addr, 0);
 456
 457       if (sal.line != 0 && sal.end <= func_end)
 458         {
 459           func_end = sal.end;
 460         }
 461       else
 462         /* Either there's no line info, or the line after the prologue is after
 463            the end of the function.  In this case, there probably isn't a
 464            prologue.  */
 465         {
 466           func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
 467         }
 468     }
 469   else
 470     func_end = pc + DEFAULT_SEARCH_LIMIT;
 471
 472   /* If pc's location is not readable, just quit. */
 473   if (!safe_read_memory_integer (pc, 4, &return_value))
 474     return pc;
 475
 476   /* Find the end of prologue.  */
 477   if (decode_prologue (pc, func_end, &sal.end, NULL) < 0)
 478     return pc;
 479
 480   return sal.end;
 481 }
 482
 483 struct m32r_unwind_cache
 484 {
 485   /* The previous frame's inner most stack address.  Used as this
 486      frame ID's stack_addr.  */
 487   CORE_ADDR prev_sp;
 488   /* The frame's base, optionally used by the high-level debug info.  */
 489   CORE_ADDR base;
 490   int size;
 491   /* How far the SP and r13 (FP) have been offset from the start of
 492      the stack frame (as defined by the previous frame's stack
 493      pointer).  */
 494   LONGEST sp_offset;
 495   LONGEST r13_offset;
 496   int uses_frame;
 497   /* Table indicating the location of each and every register.  */
 498   struct trad_frame_saved_reg *saved_regs;
 499 };
 500
 501 /* Put here the code to store, into fi->saved_regs, the addresses of
 502    the saved registers of frame described by FRAME_INFO.  This
 503    includes special registers such as pc and fp saved in special ways
 504    in the stack frame.  sp is even more special: the address we return
 505    for it IS the sp for the next frame. */
 506
 507 static struct m32r_unwind_cache *
 508 m32r_frame_unwind_cache (struct frame_info *next_frame,
 509                          void **this_prologue_cache)
 510 {
 511   CORE_ADDR pc, scan_limit;
 512   ULONGEST prev_sp;
 513   ULONGEST this_base;
 514   unsigned long op, op2;
 515   int i;
 516   struct m32r_unwind_cache *info;
 517
 518
 519   if ((*this_prologue_cache))
 520     return (*this_prologue_cache);
 521
 522   info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
 523   (*this_prologue_cache) = info;
 524   info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
 525
 526   info->size = 0;
 527   info->sp_offset = 0;
 528   info->uses_frame = 0;
 529
 530   scan_limit = frame_pc_unwind (next_frame);
 531   for (pc = frame_func_unwind (next_frame);
 532        pc > 0 && pc < scan_limit; pc += 2)
 533     {
 534       if ((pc & 2) == 0)
 535         {
 536           op = get_frame_memory_unsigned (next_frame, pc, 4);
 537           if ((op & 0x80000000) == 0x80000000)
 538             {
 539               /* 32-bit instruction */
 540               if ((op & 0xffff0000) == 0x8faf0000)
 541                 {
 542                   /* add3 sp,sp,xxxx */
 543                   short n = op & 0xffff;
 544                   info->sp_offset += n;
 545                 }
 546               else if (((op >> 8) == 0xe4)
 547                        && get_frame_memory_unsigned (next_frame, pc + 2,
 548                                                      2) == 0x0f24)
 549                 {
 550                   /* ld24 r4, xxxxxx; sub sp, r4 */
 551                   unsigned long n = op & 0xffffff;
 552                   info->sp_offset += n;
 553                   pc += 2;      /* skip sub instruction */
 554                 }
 555
 556               if (pc == scan_limit)
 557                 scan_limit += 2;        /* extend the search */
 558               pc += 2;          /* skip the immediate data */
 559               continue;
 560             }
 561         }
 562
 563       /* 16-bit instructions */
 564       op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff;
 565       if ((op & 0xf0ff) == 0x207f)
 566         {
 567           /* st rn, @-sp */
 568           int regno = ((op >> 8) & 0xf);
 569           info->sp_offset -= 4;
 570           info->saved_regs[regno].addr = info->sp_offset;
 571         }
 572       else if ((op & 0xff00) == 0x4f00)
 573         {
 574           /* addi sp, xx */
 575           int n = (char) (op & 0xff);
 576           info->sp_offset += n;
 577         }
 578       else if (op == 0x1d8f)
 579         {
 580           /* mv fp, sp */
 581           info->uses_frame = 1;
 582           info->r13_offset = info->sp_offset;
 583           break;                /* end of stack adjustments */
 584         }
 585       else if ((op & 0xfff0) == 0x10f0)
 586         {
 587           /* end of prologue if this is a trap instruction */
 588           break;                /* end of stack adjustments */
 589         }
 590     }
 591
 592   info->size = -info->sp_offset;
 593
 594   /* Compute the previous frame's stack pointer (which is also the
 595      frame's ID's stack address), and this frame's base pointer.  */
 596   if (info->uses_frame)
 597     {
 598       /* The SP was moved to the FP.  This indicates that a new frame
 599          was created.  Get THIS frame's FP value by unwinding it from
 600          the next frame.  */
 601       this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM);
 602       /* The FP points at the last saved register.  Adjust the FP back
 603          to before the first saved register giving the SP.  */
 604       prev_sp = this_base + info->size;
 605     }
 606   else
 607     {
 608       /* Assume that the FP is this frame's SP but with that pushed
 609          stack space added back.  */
 610       this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 611       prev_sp = this_base + info->size;
 612     }
 613
 614   /* Convert that SP/BASE into real addresses.  */
 615   info->prev_sp = prev_sp;
 616   info->base = this_base;
 617
 618   /* Adjust all the saved registers so that they contain addresses and
 619      not offsets.  */
 620   for (i = 0; i < NUM_REGS - 1; i++)
 621     if (trad_frame_addr_p (info->saved_regs, i))
 622       info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);
 623
 624   /* The call instruction moves the caller's PC in the callee's LR.
 625      Since this is an unwind, do the reverse.  Copy the location of LR
 626      into PC (the address / regnum) so that a request for PC will be
 627      converted into a request for the LR.  */
 628   info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];
 629
 630   /* The previous frame's SP needed to be computed.  Save the computed
 631      value.  */
 632   trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);
 633
 634   return info;
 635 }
 636
 637 static CORE_ADDR
 638 m32r_read_pc (ptid_t ptid)
 639 {
 640   ptid_t save_ptid;
 641   ULONGEST pc;
 642
 643   save_ptid = inferior_ptid;
 644   inferior_ptid = ptid;
 645   regcache_cooked_read_unsigned (current_regcache, M32R_PC_REGNUM, &pc);
 646   inferior_ptid = save_ptid;
 647   return pc;
 648 }
 649
 650 static void
 651 m32r_write_pc (CORE_ADDR val, ptid_t ptid)
 652 {
 653   ptid_t save_ptid;
 654
 655   save_ptid = inferior_ptid;
 656   inferior_ptid = ptid;
 657   write_register (M32R_PC_REGNUM, val);
 658   inferior_ptid = save_ptid;
 659 }
 660
 661 static CORE_ADDR
 662 m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
 663 {
 664   return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
 665 }
 666
 667
 668 static CORE_ADDR
 669 m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 670                       struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
 671                       struct value **args, CORE_ADDR sp, int struct_return,
 672                       CORE_ADDR struct_addr)
 673 {
 674   int stack_offset, stack_alloc;
 675   int argreg = ARG1_REGNUM;
 676   int argnum;
 677   struct type *type;
 678   enum type_code typecode;
 679   CORE_ADDR regval;
 680   char *val;
 681   char valbuf[MAX_REGISTER_SIZE];
 682   int len;
 683   int odd_sized_struct;
 684
 685   /* first force sp to a 4-byte alignment */
 686   sp = sp & ~3;
 687
 688   /* Set the return address.  For the m32r, the return breakpoint is
 689      always at BP_ADDR.  */
 690   regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);
 691
 692   /* If STRUCT_RETURN is true, then the struct return address (in
 693      STRUCT_ADDR) will consume the first argument-passing register.
 694      Both adjust the register count and store that value.  */
 695   if (struct_return)
 696     {
 697       regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
 698       argreg++;
 699     }
 700
 701   /* Now make sure there's space on the stack */
 702   for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
 703     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
 704   sp -= stack_alloc;            /* make room on stack for args */
 705
 706   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 707     {
 708       type = VALUE_TYPE (args[argnum]);
 709       typecode = TYPE_CODE (type);
 710       len = TYPE_LENGTH (type);
 711
 712       memset (valbuf, 0, sizeof (valbuf));
 713
 714       /* Passes structures that do not fit in 2 registers by reference.  */
 715       if (len > 8
 716           && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
 717         {
 718           store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum]));
 719           typecode = TYPE_CODE_PTR;
 720           len = 4;
 721           val = valbuf;
 722         }
 723       else if (len < 4)
 724         {
 725           /* value gets right-justified in the register or stack word */
 726           memcpy (valbuf + (register_size (gdbarch, argreg) - len),
 727                   (char *) VALUE_CONTENTS (args[argnum]), len);
 728           val = valbuf;
 729         }
 730       else
 731         val = (char *) VALUE_CONTENTS (args[argnum]);
 732
 733       while (len > 0)
 734         {
 735           if (argreg > ARGN_REGNUM)
 736             {
 737               /* must go on the stack */
 738               write_memory (sp + stack_offset, val, 4);
 739               stack_offset += 4;
 740             }
 741           else if (argreg <= ARGN_REGNUM)
 742             {
 743               /* there's room in a register */
 744               regval =
 745                 extract_unsigned_integer (val,
 746                                           register_size (gdbarch, argreg));
 747               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 748             }
 749
 750           /* Store the value 4 bytes at a time.  This means that things
 751              larger than 4 bytes may go partly in registers and partly
 752              on the stack.  */
 753           len -= register_size (gdbarch, argreg);
 754           val += register_size (gdbarch, argreg);
 755         }
 756     }
 757
 758   /* Finally, update the SP register.  */
 759   regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);
 760
 761   return sp;
 762 }
 763
 764
 765 /* Given a return value in `regbuf' with a type `valtype',
 766    extract and copy its value into `valbuf'.  */
 767
 768 static void
 769 m32r_extract_return_value (struct type *type, struct regcache *regcache,
 770                            void *dst)
 771 {
 772   bfd_byte *valbuf = dst;
 773   int len = TYPE_LENGTH (type);
 774   ULONGEST tmp;
 775
 776   /* By using store_unsigned_integer we avoid having to do
 777      anything special for small big-endian values.  */
 778   regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
 779   store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp);
 780
 781   /* Ignore return values more than 8 bytes in size because the m32r
 782      returns anything more than 8 bytes in the stack. */
 783   if (len > 4)
 784     {
 785       regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
 786       store_unsigned_integer (valbuf + len - 4, 4, tmp);
 787     }
 788 }
 789
 790 enum return_value_convention
 791 m32r_return_value (struct gdbarch *gdbarch, struct type *valtype,
 792                    struct regcache *regcache, void *readbuf,
 793                    const void *writebuf)
 794 {
 795   if (TYPE_LENGTH (valtype) > 8)
 796     return RETURN_VALUE_STRUCT_CONVENTION;
 797   else
 798     {
 799       if (readbuf != NULL)
 800         m32r_extract_return_value (valtype, regcache, readbuf);
 801       if (writebuf != NULL)
 802         m32r_store_return_value (valtype, regcache, writebuf);
 803       return RETURN_VALUE_REGISTER_CONVENTION;
 804     }
 805 }
 806
 807
 808
 809 static CORE_ADDR
 810 m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 811 {
 812   return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
 813 }
 814
 815 /* Given a GDB frame, determine the address of the calling function's
 816    frame.  This will be used to create a new GDB frame struct.  */
 817
 818 static void
 819 m32r_frame_this_id (struct frame_info *next_frame,
 820                     void **this_prologue_cache, struct frame_id *this_id)
 821 {
 822   struct m32r_unwind_cache *info
 823     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 824   CORE_ADDR base;
 825   CORE_ADDR func;
 826   struct minimal_symbol *msym_stack;
 827   struct frame_id id;
 828
 829   /* The FUNC is easy.  */
 830   func = frame_func_unwind (next_frame);
 831
 832   /* Check if the stack is empty.  */
 833   msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
 834   if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
 835     return;
 836
 837   /* Hopefully the prologue analysis either correctly determined the
 838      frame's base (which is the SP from the previous frame), or set
 839      that base to "NULL".  */
 840   base = info->prev_sp;
 841   if (base == 0)
 842     return;
 843
 844   id = frame_id_build (base, func);
 845   (*this_id) = id;
 846 }
 847
 848 static void
 849 m32r_frame_prev_register (struct frame_info *next_frame,
 850                           void **this_prologue_cache,
 851                           int regnum, int *optimizedp,
 852                           enum lval_type *lvalp, CORE_ADDR *addrp,
 853                           int *realnump, void *bufferp)
 854 {
 855   struct m32r_unwind_cache *info
 856     = m32r_frame_unwind_cache (next_frame, this_prologue_cache);
 857   trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
 858                                 optimizedp, lvalp, addrp, realnump, bufferp);
 859 }
 860
 861 static const struct frame_unwind m32r_frame_unwind = {
 862   NORMAL_FRAME,
 863   m32r_frame_this_id,
 864   m32r_frame_prev_register
 865 };
 866
 867 static const struct frame_unwind *
 868 m32r_frame_sniffer (struct frame_info *next_frame)
 869 {
 870   return &m32r_frame_unwind;
 871 }
 872
 873 static CORE_ADDR
 874 m32r_frame_base_address (struct frame_info *next_frame, void **this_cache)
 875 {
 876   struct m32r_unwind_cache *info
 877     = m32r_frame_unwind_cache (next_frame, this_cache);
 878   return info->base;
 879 }
 880
 881 static const struct frame_base m32r_frame_base = {
 882   &m32r_frame_unwind,
 883   m32r_frame_base_address,
 884   m32r_frame_base_address,
 885   m32r_frame_base_address
 886 };
 887
 888 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
 889    dummy frame.  The frame ID's base needs to match the TOS value
 890    saved by save_dummy_frame_tos(), and the PC match the dummy frame's
 891    breakpoint.  */
 892
 893 static struct frame_id
 894 m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
 895 {
 896   return frame_id_build (m32r_unwind_sp (gdbarch, next_frame),
 897                          frame_pc_unwind (next_frame));
 898 }
 899
 900
 901 static gdbarch_init_ftype m32r_gdbarch_init;
 902
 903 static struct gdbarch *
 904 m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 905 {
 906   struct gdbarch *gdbarch;
 907   struct gdbarch_tdep *tdep;
 908
 909   /* If there is already a candidate, use it.  */
 910   arches = gdbarch_list_lookup_by_info (arches, &info);
 911   if (arches != NULL)
 912     return arches->gdbarch;
 913
 914   /* Allocate space for the new architecture.  */
 915   tdep = XMALLOC (struct gdbarch_tdep);
 916   gdbarch = gdbarch_alloc (&info, tdep);
 917
 918   set_gdbarch_read_pc (gdbarch, m32r_read_pc);
 919   set_gdbarch_write_pc (gdbarch, m32r_write_pc);
 920   set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);
 921
 922   set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
 923   set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
 924   set_gdbarch_register_name (gdbarch, m32r_register_name);
 925   set_gdbarch_register_type (gdbarch, m32r_register_type);
 926
 927   set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
 928   set_gdbarch_return_value (gdbarch, m32r_return_value);
 929
 930   set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
 931   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 932   set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
 933   set_gdbarch_memory_insert_breakpoint (gdbarch,
 934                                         m32r_memory_insert_breakpoint);
 935   set_gdbarch_memory_remove_breakpoint (gdbarch,
 936                                         m32r_memory_remove_breakpoint);
 937
 938   set_gdbarch_frame_align (gdbarch, m32r_frame_align);
 939
 940   frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer);
 941   frame_base_set_default (gdbarch, &m32r_frame_base);
 942
 943   /* Methods for saving / extracting a dummy frame's ID.  The ID's
 944      stack address must match the SP value returned by
 945      PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos.  */
 946   set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id);
 947
 948   /* Return the unwound PC value.  */
 949   set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);
 950
 951   set_gdbarch_print_insn (gdbarch, print_insn_m32r);
 952
 953   return gdbarch;
 954 }
 955
 956 void
 957 _initialize_m32r_tdep (void)
 958 {
 959   register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);
 960 }