gdb/mips-linux-tdep.c

   1 /* Target-dependent code for GNU/Linux on MIPS processors.
   2
   3    Copyright (C) 2001, 2002, 2004, 2005, 2006
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  21    Boston, MA 02110-1301, USA.  */
  22
  23 #include "defs.h"
  24 #include "gdbcore.h"
  25 #include "target.h"
  26 #include "solib-svr4.h"
  27 #include "osabi.h"
  28 #include "mips-tdep.h"
  29 #include "gdb_string.h"
  30 #include "gdb_assert.h"
  31 #include "frame.h"
  32 #include "regcache.h"
  33 #include "trad-frame.h"
  34 #include "tramp-frame.h"
  35
  36 /* Copied from <asm/elf.h>.  */
  37 #define ELF_NGREG       45
  38 #define ELF_NFPREG      33
  39
  40 typedef unsigned char elf_greg_t[4];
  41 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
  42
  43 typedef unsigned char elf_fpreg_t[8];
  44 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  45
  46 /* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
  47 #define FPR_BASE        32
  48 #define PC              64
  49 #define CAUSE           65
  50 #define BADVADDR        66
  51 #define MMHI            67
  52 #define MMLO            68
  53 #define FPC_CSR         69
  54 #define FPC_EIR         70
  55
  56 #define EF_REG0                 6
  57 #define EF_REG31                37
  58 #define EF_LO                   38
  59 #define EF_HI                   39
  60 #define EF_CP0_EPC              40
  61 #define EF_CP0_BADVADDR         41
  62 #define EF_CP0_STATUS           42
  63 #define EF_CP0_CAUSE            43
  64
  65 #define EF_SIZE                 180
  66
  67 /* Figure out where the longjmp will land.
  68    We expect the first arg to be a pointer to the jmp_buf structure
  69    from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
  70    at.  The pc is copied into PC.  This routine returns 1 on
  71    success.  */
  72
  73 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
  74 #define MIPS_LINUX_JB_PC 0
  75
  76 static int
  77 mips_linux_get_longjmp_target (CORE_ADDR *pc)
  78 {
  79   CORE_ADDR jb_addr;
  80   char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
  81
  82   jb_addr = read_register (MIPS_A0_REGNUM);
  83
  84   if (target_read_memory (jb_addr
  85                           + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
  86                           buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
  87     return 0;
  88
  89   *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
  90
  91   return 1;
  92 }
  93
  94 /* Transform the bits comprising a 32-bit register to the right size
  95    for regcache_raw_supply().  This is needed when mips_isa_regsize()
  96    is 8.  */
  97
  98 static void
  99 supply_32bit_reg (int regnum, const void *addr)
 100 {
 101   char buf[MAX_REGISTER_SIZE];
 102   store_signed_integer (buf, register_size (current_gdbarch, regnum),
 103                         extract_signed_integer (addr, 4));
 104   regcache_raw_supply (current_regcache, regnum, buf);
 105 }
 106
 107 /* Unpack an elf_gregset_t into GDB's register cache.  */
 108
 109 void
 110 supply_gregset (elf_gregset_t *gregsetp)
 111 {
 112   int regi;
 113   elf_greg_t *regp = *gregsetp;
 114   char zerobuf[MAX_REGISTER_SIZE];
 115
 116   memset (zerobuf, 0, MAX_REGISTER_SIZE);
 117
 118   for (regi = EF_REG0; regi <= EF_REG31; regi++)
 119     supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
 120
 121   supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
 122                     (char *)(regp + EF_LO));
 123   supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
 124                     (char *)(regp + EF_HI));
 125
 126   supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
 127                     (char *)(regp + EF_CP0_EPC));
 128   supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
 129                     (char *)(regp + EF_CP0_BADVADDR));
 130   supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
 131   supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
 132                     (char *)(regp + EF_CP0_CAUSE));
 133
 134   /* Fill inaccessible registers with zero.  */
 135   regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
 136   for (regi = MIPS_FIRST_EMBED_REGNUM;
 137        regi < MIPS_LAST_EMBED_REGNUM;
 138        regi++)
 139     regcache_raw_supply (current_regcache, regi, zerobuf);
 140 }
 141
 142 /* Pack our registers (or one register) into an elf_gregset_t.  */
 143
 144 void
 145 fill_gregset (elf_gregset_t *gregsetp, int regno)
 146 {
 147   int regaddr, regi;
 148   elf_greg_t *regp = *gregsetp;
 149   void *dst;
 150
 151   if (regno == -1)
 152     {
 153       memset (regp, 0, sizeof (elf_gregset_t));
 154       for (regi = 0; regi < 32; regi++)
 155         fill_gregset (gregsetp, regi);
 156       fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
 157       fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
 158       fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
 159       fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
 160       fill_gregset (gregsetp, MIPS_PS_REGNUM);
 161       fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
 162
 163       return;
 164    }
 165
 166   if (regno < 32)
 167     {
 168       dst = regp + regno + EF_REG0;
 169       regcache_raw_collect (current_regcache, regno, dst);
 170       return;
 171     }
 172
 173   if (regno == mips_regnum (current_gdbarch)->lo)
 174     regaddr = EF_LO;
 175   else if (regno == mips_regnum (current_gdbarch)->hi)
 176     regaddr = EF_HI;
 177   else if (regno == mips_regnum (current_gdbarch)->pc)
 178     regaddr = EF_CP0_EPC;
 179   else if (regno == mips_regnum (current_gdbarch)->badvaddr)
 180     regaddr = EF_CP0_BADVADDR;
 181   else if (regno == MIPS_PS_REGNUM)
 182     regaddr = EF_CP0_STATUS;
 183   else if (regno == mips_regnum (current_gdbarch)->cause)
 184     regaddr = EF_CP0_CAUSE;
 185   else
 186     regaddr = -1;
 187
 188   if (regaddr != -1)
 189     {
 190       dst = regp + regaddr;
 191       regcache_raw_collect (current_regcache, regno, dst);
 192     }
 193 }
 194
 195 /* Likewise, unpack an elf_fpregset_t.  */
 196
 197 void
 198 supply_fpregset (elf_fpregset_t *fpregsetp)
 199 {
 200   int regi;
 201   char zerobuf[MAX_REGISTER_SIZE];
 202
 203   memset (zerobuf, 0, MAX_REGISTER_SIZE);
 204
 205   for (regi = 0; regi < 32; regi++)
 206     regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
 207                          (char *)(*fpregsetp + regi));
 208
 209   regcache_raw_supply (current_regcache,
 210                        mips_regnum (current_gdbarch)->fp_control_status,
 211                        (char *)(*fpregsetp + 32));
 212
 213   /* FIXME: how can we supply FCRIR?  The ABI doesn't tell us.  */
 214   regcache_raw_supply (current_regcache,
 215                        mips_regnum (current_gdbarch)->fp_implementation_revision,
 216                        zerobuf);
 217 }
 218
 219 /* Likewise, pack one or all floating point registers into an
 220    elf_fpregset_t.  */
 221
 222 void
 223 fill_fpregset (elf_fpregset_t *fpregsetp, int regno)
 224 {
 225   char *from, *to;
 226
 227   if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
 228     {
 229       to = (char *) (*fpregsetp + regno - FP0_REGNUM);
 230       regcache_raw_collect (current_regcache, regno, to);
 231     }
 232   else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
 233     {
 234       to = (char *) (*fpregsetp + 32);
 235       regcache_raw_collect (current_regcache, regno, to);
 236     }
 237   else if (regno == -1)
 238     {
 239       int regi;
 240
 241       for (regi = 0; regi < 32; regi++)
 242         fill_fpregset (fpregsetp, FP0_REGNUM + regi);
 243       fill_fpregset (fpregsetp,
 244                      mips_regnum (current_gdbarch)->fp_control_status);
 245     }
 246 }
 247
 248 /* Map gdb internal register number to ptrace ``address''.
 249    These ``addresses'' are normally defined in <asm/ptrace.h>.  */
 250
 251 static CORE_ADDR
 252 mips_linux_register_addr (int regno, CORE_ADDR blockend)
 253 {
 254   int regaddr;
 255
 256   if (regno < 0 || regno >= NUM_REGS)
 257     error (_("Bogon register number %d."), regno);
 258
 259   if (regno < 32)
 260     regaddr = regno;
 261   else if ((regno >= mips_regnum (current_gdbarch)->fp0)
 262            && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
 263     regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
 264   else if (regno == mips_regnum (current_gdbarch)->pc)
 265     regaddr = PC;
 266   else if (regno == mips_regnum (current_gdbarch)->cause)
 267     regaddr = CAUSE;
 268   else if (regno == mips_regnum (current_gdbarch)->badvaddr)
 269     regaddr = BADVADDR;
 270   else if (regno == mips_regnum (current_gdbarch)->lo)
 271     regaddr = MMLO;
 272   else if (regno == mips_regnum (current_gdbarch)->hi)
 273     regaddr = MMHI;
 274   else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
 275     regaddr = FPC_CSR;
 276   else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
 277     regaddr = FPC_EIR;
 278   else
 279     error (_("Unknowable register number %d."), regno);
 280
 281   return regaddr;
 282 }
 283
 284 /* Support for 64-bit ABIs.  */
 285
 286 /* Copied from <asm/elf.h>.  */
 287 #define MIPS64_ELF_NGREG       45
 288 #define MIPS64_ELF_NFPREG      33
 289
 290 typedef unsigned char mips64_elf_greg_t[8];
 291 typedef mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG];
 292
 293 typedef unsigned char mips64_elf_fpreg_t[8];
 294 typedef mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG];
 295
 296 /* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
 297 #define MIPS64_FPR_BASE                 32
 298 #define MIPS64_PC                       64
 299 #define MIPS64_CAUSE                    65
 300 #define MIPS64_BADVADDR                 66
 301 #define MIPS64_MMHI                     67
 302 #define MIPS64_MMLO                     68
 303 #define MIPS64_FPC_CSR                  69
 304 #define MIPS64_FPC_EIR                  70
 305
 306 #define MIPS64_EF_REG0                   0
 307 #define MIPS64_EF_REG31                 31
 308 #define MIPS64_EF_LO                    32
 309 #define MIPS64_EF_HI                    33
 310 #define MIPS64_EF_CP0_EPC               34
 311 #define MIPS64_EF_CP0_BADVADDR          35
 312 #define MIPS64_EF_CP0_STATUS            36
 313 #define MIPS64_EF_CP0_CAUSE             37
 314
 315 #define MIPS64_EF_SIZE                  304
 316
 317 /* Figure out where the longjmp will land.
 318    We expect the first arg to be a pointer to the jmp_buf structure
 319    from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
 320    at.  The pc is copied into PC.  This routine returns 1 on
 321    success.  */
 322
 323 /* Details about jmp_buf.  */
 324
 325 #define MIPS64_LINUX_JB_PC 0
 326
 327 static int
 328 mips64_linux_get_longjmp_target (CORE_ADDR *pc)
 329 {
 330   CORE_ADDR jb_addr;
 331   void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
 332   int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
 333
 334   jb_addr = read_register (MIPS_A0_REGNUM);
 335
 336   if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
 337                           buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
 338     return 0;
 339
 340   *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 341
 342   return 1;
 343 }
 344
 345 /* Unpack an elf_gregset_t into GDB's register cache.  */
 346
 347 static void
 348 mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
 349 {
 350   int regi;
 351   mips64_elf_greg_t *regp = *gregsetp;
 352   char zerobuf[MAX_REGISTER_SIZE];
 353
 354   memset (zerobuf, 0, MAX_REGISTER_SIZE);
 355
 356   for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
 357     regcache_raw_supply (current_regcache, (regi - MIPS64_EF_REG0),
 358                          (char *)(regp + regi));
 359
 360   regcache_raw_supply (current_regcache,
 361                        mips_regnum (current_gdbarch)->lo,
 362                        (char *) (regp + MIPS64_EF_LO));
 363   regcache_raw_supply (current_regcache,
 364                        mips_regnum (current_gdbarch)->hi,
 365                        (char *) (regp + MIPS64_EF_HI));
 366
 367   regcache_raw_supply (current_regcache,
 368                        mips_regnum (current_gdbarch)->pc,
 369                        (char *) (regp + MIPS64_EF_CP0_EPC));
 370   regcache_raw_supply (current_regcache,
 371                        mips_regnum (current_gdbarch)->badvaddr,
 372                        (char *) (regp + MIPS64_EF_CP0_BADVADDR));
 373   regcache_raw_supply (current_regcache, MIPS_PS_REGNUM,
 374                        (char *) (regp + MIPS64_EF_CP0_STATUS));
 375   regcache_raw_supply (current_regcache,
 376                        mips_regnum (current_gdbarch)->cause,
 377                        (char *) (regp + MIPS64_EF_CP0_CAUSE));
 378
 379   /* Fill inaccessible registers with zero.  */
 380   regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
 381   for (regi = MIPS_FIRST_EMBED_REGNUM;
 382        regi < MIPS_LAST_EMBED_REGNUM;
 383        regi++)
 384     regcache_raw_supply (current_regcache, regi, zerobuf);
 385 }
 386
 387 /* Pack our registers (or one register) into an elf_gregset_t.  */
 388
 389 static void
 390 mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
 391 {
 392   int regaddr, regi;
 393   mips64_elf_greg_t *regp = *gregsetp;
 394   void *src, *dst;
 395
 396   if (regno == -1)
 397     {
 398       memset (regp, 0, sizeof (mips64_elf_gregset_t));
 399       for (regi = 0; regi < 32; regi++)
 400         mips64_fill_gregset (gregsetp, regi);
 401       mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
 402       mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
 403       mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
 404       mips64_fill_gregset (gregsetp,
 405                            mips_regnum (current_gdbarch)->badvaddr);
 406       mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
 407       mips64_fill_gregset (gregsetp,
 408                            mips_regnum (current_gdbarch)->cause);
 409
 410       return;
 411    }
 412
 413   if (regno < 32)
 414     {
 415       dst = regp + regno + MIPS64_EF_REG0;
 416       regcache_raw_collect (current_regcache, regno, dst);
 417       return;
 418     }
 419
 420   if (regno == mips_regnum (current_gdbarch)->lo)
 421     regaddr = MIPS64_EF_LO;
 422   else if (regno == mips_regnum (current_gdbarch)->hi)
 423     regaddr = MIPS64_EF_HI;
 424   else if (regno == mips_regnum (current_gdbarch)->pc)
 425     regaddr = MIPS64_EF_CP0_EPC;
 426   else if (regno == mips_regnum (current_gdbarch)->badvaddr)
 427     regaddr = MIPS64_EF_CP0_BADVADDR;
 428   else if (regno == MIPS_PS_REGNUM)
 429     regaddr = MIPS64_EF_CP0_STATUS;
 430   else if (regno == mips_regnum (current_gdbarch)->cause)
 431     regaddr = MIPS64_EF_CP0_CAUSE;
 432   else
 433     regaddr = -1;
 434
 435   if (regaddr != -1)
 436     {
 437       dst = regp + regaddr;
 438       regcache_raw_collect (current_regcache, regno, dst);
 439     }
 440 }
 441
 442 /* Likewise, unpack an elf_fpregset_t.  */
 443
 444 static void
 445 mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
 446 {
 447   int regi;
 448   char zerobuf[MAX_REGISTER_SIZE];
 449
 450   memset (zerobuf, 0, MAX_REGISTER_SIZE);
 451
 452   for (regi = 0; regi < 32; regi++)
 453     regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
 454                          (char *)(*fpregsetp + regi));
 455
 456   regcache_raw_supply (current_regcache,
 457                        mips_regnum (current_gdbarch)->fp_control_status,
 458                        (char *)(*fpregsetp + 32));
 459
 460   /* FIXME: how can we supply FCRIR?  The ABI doesn't tell us.  */
 461   regcache_raw_supply (current_regcache,
 462                        mips_regnum (current_gdbarch)->fp_implementation_revision,
 463                        zerobuf);
 464 }
 465
 466 /* Likewise, pack one or all floating point registers into an
 467    elf_fpregset_t.  */
 468
 469 static void
 470 mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
 471 {
 472   char *from, *to;
 473
 474   if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
 475     {
 476       to = (char *) (*fpregsetp + regno - FP0_REGNUM);
 477       regcache_raw_collect (current_regcache, regno, to);
 478     }
 479   else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
 480     {
 481       to = (char *) (*fpregsetp + 32);
 482       regcache_raw_collect (current_regcache, regno, to);
 483     }
 484   else if (regno == -1)
 485     {
 486       int regi;
 487
 488       for (regi = 0; regi < 32; regi++)
 489         mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
 490       mips64_fill_fpregset(fpregsetp,
 491                            mips_regnum (current_gdbarch)->fp_control_status);
 492     }
 493 }
 494
 495
 496 /* Map gdb internal register number to ptrace ``address''.
 497    These ``addresses'' are normally defined in <asm/ptrace.h>.  */
 498
 499 static CORE_ADDR
 500 mips64_linux_register_addr (int regno, CORE_ADDR blockend)
 501 {
 502   int regaddr;
 503
 504   if (regno < 0 || regno >= NUM_REGS)
 505     error (_("Bogon register number %d."), regno);
 506
 507   if (regno < 32)
 508     regaddr = regno;
 509   else if ((regno >= mips_regnum (current_gdbarch)->fp0)
 510            && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
 511     regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
 512   else if (regno == mips_regnum (current_gdbarch)->pc)
 513     regaddr = MIPS64_PC;
 514   else if (regno == mips_regnum (current_gdbarch)->cause)
 515     regaddr = MIPS64_CAUSE;
 516   else if (regno == mips_regnum (current_gdbarch)->badvaddr)
 517     regaddr = MIPS64_BADVADDR;
 518   else if (regno == mips_regnum (current_gdbarch)->lo)
 519     regaddr = MIPS64_MMLO;
 520   else if (regno == mips_regnum (current_gdbarch)->hi)
 521     regaddr = MIPS64_MMHI;
 522   else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
 523     regaddr = MIPS64_FPC_CSR;
 524   else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
 525     regaddr = MIPS64_FPC_EIR;
 526   else
 527     error (_("Unknowable register number %d."), regno);
 528
 529   return regaddr;
 530 }
 531
 532 /*  Use a local version of this function to get the correct types for
 533     regsets, until multi-arch core support is ready.  */
 534
 535 static void
 536 fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
 537                       int which, CORE_ADDR reg_addr)
 538 {
 539   elf_gregset_t gregset;
 540   elf_fpregset_t fpregset;
 541   mips64_elf_gregset_t gregset64;
 542   mips64_elf_fpregset_t fpregset64;
 543
 544   if (which == 0)
 545     {
 546       if (core_reg_size == sizeof (gregset))
 547         {
 548           memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
 549           supply_gregset (&gregset);
 550         }
 551       else if (core_reg_size == sizeof (gregset64))
 552         {
 553           memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
 554           mips64_supply_gregset (&gregset64);
 555         }
 556       else
 557         {
 558           warning (_("wrong size gregset struct in core file"));
 559         }
 560     }
 561   else if (which == 2)
 562     {
 563       if (core_reg_size == sizeof (fpregset))
 564         {
 565           memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
 566           supply_fpregset (&fpregset);
 567         }
 568       else if (core_reg_size == sizeof (fpregset64))
 569         {
 570           memcpy ((char *) &fpregset64, core_reg_sect,
 571                   sizeof (fpregset64));
 572           mips64_supply_fpregset (&fpregset64);
 573         }
 574       else
 575         {
 576           warning (_("wrong size fpregset struct in core file"));
 577         }
 578     }
 579 }
 580
 581 /* Register that we are able to handle ELF file formats using standard
 582    procfs "regset" structures.  */
 583
 584 static struct core_fns regset_core_fns =
 585 {
 586   bfd_target_elf_flavour,               /* core_flavour */
 587   default_check_format,                 /* check_format */
 588   default_core_sniffer,                 /* core_sniffer */
 589   fetch_core_registers,                 /* core_read_registers */
 590   NULL                                  /* next */
 591 };
 592
 593 /* Handle for obtaining pointer to the current register_addr()
 594    function for a given architecture.  */
 595 static struct gdbarch_data *register_addr_data;
 596
 597 CORE_ADDR
 598 register_addr (int regno, CORE_ADDR blockend)
 599 {
 600   CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
 601     gdbarch_data (current_gdbarch, register_addr_data);
 602
 603   gdb_assert (register_addr_ptr != 0);
 604
 605   return register_addr_ptr (regno, blockend);
 606 }
 607
 608 static void
 609 set_mips_linux_register_addr (struct gdbarch *gdbarch,
 610                               CORE_ADDR (*register_addr_ptr) (int,
 611                                                               CORE_ADDR))
 612 {
 613   deprecated_set_gdbarch_data (gdbarch, register_addr_data,
 614                                register_addr_ptr);
 615 }
 616
 617 static void *
 618 init_register_addr_data (struct gdbarch *gdbarch)
 619 {
 620   return 0;
 621 }
 622
 623 /* Check the code at PC for a dynamic linker lazy resolution stub.
 624    Because they aren't in the .plt section, we pattern-match on the
 625    code generated by GNU ld.  They look like this:
 626
 627    lw t9,0x8010(gp)
 628    addu t7,ra
 629    jalr t9,ra
 630    addiu t8,zero,INDEX
 631
 632    (with the appropriate doubleword instructions for N64).  Also
 633    return the dynamic symbol index used in the last instruction.  */
 634
 635 static int
 636 mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
 637 {
 638   unsigned char buf[28], *p;
 639   ULONGEST insn, insn1;
 640   int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
 641
 642   read_memory (pc - 12, buf, 28);
 643
 644   if (n64)
 645     {
 646       /* ld t9,0x8010(gp) */
 647       insn1 = 0xdf998010;
 648     }
 649   else
 650     {
 651       /* lw t9,0x8010(gp) */
 652       insn1 = 0x8f998010;
 653     }
 654
 655   p = buf + 12;
 656   while (p >= buf)
 657     {
 658       insn = extract_unsigned_integer (p, 4);
 659       if (insn == insn1)
 660         break;
 661       p -= 4;
 662     }
 663   if (p < buf)
 664     return 0;
 665
 666   insn = extract_unsigned_integer (p + 4, 4);
 667   if (n64)
 668     {
 669       /* daddu t7,ra */
 670       if (insn != 0x03e0782d)
 671         return 0;
 672     }
 673   else
 674     {
 675       /* addu t7,ra */
 676       if (insn != 0x03e07821)
 677         return 0;
 678     }
 679
 680   insn = extract_unsigned_integer (p + 8, 4);
 681   /* jalr t9,ra */
 682   if (insn != 0x0320f809)
 683     return 0;
 684
 685   insn = extract_unsigned_integer (p + 12, 4);
 686   if (n64)
 687     {
 688       /* daddiu t8,zero,0 */
 689       if ((insn & 0xffff0000) != 0x64180000)
 690         return 0;
 691     }
 692   else
 693     {
 694       /* addiu t8,zero,0 */
 695       if ((insn & 0xffff0000) != 0x24180000)
 696         return 0;
 697     }
 698
 699   return (insn & 0xffff);
 700 }
 701
 702 /* Return non-zero iff PC belongs to the dynamic linker resolution
 703    code or to a stub.  */
 704
 705 int
 706 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
 707 {
 708   /* Check whether PC is in the dynamic linker.  This also checks
 709      whether it is in the .plt section, which MIPS does not use.  */
 710   if (in_solib_dynsym_resolve_code (pc))
 711     return 1;
 712
 713   /* Pattern match for the stub.  It would be nice if there were a
 714      more efficient way to avoid this check.  */
 715   if (mips_linux_in_dynsym_stub (pc, NULL))
 716     return 1;
 717
 718   return 0;
 719 }
 720
 721 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
 722    and glibc_skip_solib_resolver in glibc-tdep.c.  The normal glibc
 723    implementation of this triggers at "fixup" from the same objfile as
 724    "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
 725    "__dl_runtime_resolve" directly.  An unresolved PLT entry will
 726    point to _dl_runtime_resolve, which will first call
 727    __dl_runtime_resolve, and then pass control to the resolved
 728    function.  */
 729
 730 static CORE_ADDR
 731 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
 732 {
 733   struct minimal_symbol *resolver;
 734
 735   resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
 736
 737   if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
 738     return frame_pc_unwind (get_current_frame ());
 739
 740   return 0;
 741 }
 742
 743 /* Signal trampoline support.  There are four supported layouts for a
 744    signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
 745    n64 rt_sigframe.  We handle them all independently; not the most
 746    efficient way, but simplest.  First, declare all the unwinders.  */
 747
 748 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
 749                                           struct frame_info *next_frame,
 750                                           struct trad_frame_cache *this_cache,
 751                                           CORE_ADDR func);
 752
 753 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
 754                                              struct frame_info *next_frame,
 755                                              struct trad_frame_cache *this_cache,
 756                                              CORE_ADDR func);
 757
 758 #define MIPS_NR_LINUX 4000
 759 #define MIPS_NR_N64_LINUX 5000
 760 #define MIPS_NR_N32_LINUX 6000
 761
 762 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
 763 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
 764 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
 765 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
 766
 767 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
 768 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
 769 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
 770 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
 771 #define MIPS_INST_SYSCALL 0x0000000c
 772
 773 static const struct tramp_frame mips_linux_o32_sigframe = {
 774   SIGTRAMP_FRAME,
 775   4,
 776   {
 777     { MIPS_INST_LI_V0_SIGRETURN, -1 },
 778     { MIPS_INST_SYSCALL, -1 },
 779     { TRAMP_SENTINEL_INSN, -1 }
 780   },
 781   mips_linux_o32_sigframe_init
 782 };
 783
 784 static const struct tramp_frame mips_linux_o32_rt_sigframe = {
 785   SIGTRAMP_FRAME,
 786   4,
 787   {
 788     { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
 789     { MIPS_INST_SYSCALL, -1 },
 790     { TRAMP_SENTINEL_INSN, -1 } },
 791   mips_linux_o32_sigframe_init
 792 };
 793
 794 static const struct tramp_frame mips_linux_n32_rt_sigframe = {
 795   SIGTRAMP_FRAME,
 796   4,
 797   {
 798     { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
 799     { MIPS_INST_SYSCALL, -1 },
 800     { TRAMP_SENTINEL_INSN, -1 }
 801   },
 802   mips_linux_n32n64_sigframe_init
 803 };
 804
 805 static const struct tramp_frame mips_linux_n64_rt_sigframe = {
 806   SIGTRAMP_FRAME,
 807   4,
 808   { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
 809     MIPS_INST_SYSCALL,
 810     TRAMP_SENTINEL_INSN },
 811   mips_linux_n32n64_sigframe_init
 812 };
 813
 814 /* *INDENT-OFF* */
 815 /* The unwinder for o32 signal frames.  The legacy structures look
 816    like this:
 817
 818    struct sigframe {
 819      u32 sf_ass[4];            [argument save space for o32]
 820      u32 sf_code[2];           [signal trampoline]
 821      struct sigcontext sf_sc;
 822      sigset_t sf_mask;
 823    };
 824
 825    struct sigcontext {
 826         unsigned int       sc_regmask;          [Unused]
 827         unsigned int       sc_status;
 828         unsigned long long sc_pc;
 829         unsigned long long sc_regs[32];
 830         unsigned long long sc_fpregs[32];
 831         unsigned int       sc_ownedfp;
 832         unsigned int       sc_fpc_csr;
 833         unsigned int       sc_fpc_eir;          [Unused]
 834         unsigned int       sc_used_math;
 835         unsigned int       sc_ssflags;          [Unused]
 836         [Alignment hole of four bytes]
 837         unsigned long long sc_mdhi;
 838         unsigned long long sc_mdlo;
 839
 840         unsigned int       sc_cause;            [Unused]
 841         unsigned int       sc_badvaddr;         [Unused]
 842
 843         unsigned long      sc_sigset[4];        [kernel's sigset_t]
 844    };
 845
 846    The RT signal frames look like this:
 847
 848    struct rt_sigframe {
 849      u32 rs_ass[4];            [argument save space for o32]
 850      u32 rs_code[2]            [signal trampoline]
 851      struct siginfo rs_info;
 852      struct ucontext rs_uc;
 853    };
 854
 855    struct ucontext {
 856      unsigned long     uc_flags;
 857      struct ucontext  *uc_link;
 858      stack_t           uc_stack;
 859      [Alignment hole of four bytes]
 860      struct sigcontext uc_mcontext;
 861      sigset_t          uc_sigmask;
 862    };  */
 863 /* *INDENT-ON* */
 864
 865 #define SIGFRAME_CODE_OFFSET         (4 * 4)
 866 #define SIGFRAME_SIGCONTEXT_OFFSET   (6 * 4)
 867
 868 #define RTSIGFRAME_SIGINFO_SIZE      128
 869 #define STACK_T_SIZE                 (3 * 4)
 870 #define UCONTEXT_SIGCONTEXT_OFFSET   (2 * 4 + STACK_T_SIZE + 4)
 871 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
 872                                       + RTSIGFRAME_SIGINFO_SIZE \
 873                                       + UCONTEXT_SIGCONTEXT_OFFSET)
 874
 875 #define SIGCONTEXT_PC       (1 * 8)
 876 #define SIGCONTEXT_REGS     (2 * 8)
 877 #define SIGCONTEXT_FPREGS   (34 * 8)
 878 #define SIGCONTEXT_FPCSR    (66 * 8 + 4)
 879 #define SIGCONTEXT_HI       (69 * 8)
 880 #define SIGCONTEXT_LO       (70 * 8)
 881 #define SIGCONTEXT_CAUSE    (71 * 8 + 0)
 882 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
 883
 884 #define SIGCONTEXT_REG_SIZE 8
 885
 886 static void
 887 mips_linux_o32_sigframe_init (const struct tramp_frame *self,
 888                               struct frame_info *next_frame,
 889                               struct trad_frame_cache *this_cache,
 890                               CORE_ADDR func)
 891 {
 892   int ireg, reg_position;
 893   CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
 894   const struct mips_regnum *regs = mips_regnum (current_gdbarch);
 895   CORE_ADDR regs_base;
 896
 897   if (self == &mips_linux_o32_sigframe)
 898     sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
 899   else
 900     sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
 901
 902   /* I'm not proud of this hack.  Eventually we will have the
 903      infrastructure to indicate the size of saved registers on a
 904      per-frame basis, but right now we don't; the kernel saves eight
 905      bytes but we only want four.  Use regs_base to access any
 906      64-bit fields.  */
 907   if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 908     regs_base = sigcontext_base + 4;
 909   else
 910     regs_base = sigcontext_base;
 911
 912 #if 0
 913   trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
 914                            regs_base + SIGCONTEXT_REGS);
 915 #endif
 916
 917   for (ireg = 1; ireg < 32; ireg++)
 918     trad_frame_set_reg_addr (this_cache,
 919                              ireg + MIPS_ZERO_REGNUM + NUM_REGS,
 920                              regs_base + SIGCONTEXT_REGS
 921                              + ireg * SIGCONTEXT_REG_SIZE);
 922
 923   /* The way that floating point registers are saved, unfortunately,
 924      depends on the architecture the kernel is built for.  For the r3000 and
 925      tx39, four bytes of each register are at the beginning of each of the
 926      32 eight byte slots.  For everything else, the registers are saved
 927      using double precision; only the even-numbered slots are initialized,
 928      and the high bits are the odd-numbered register.  Assume the latter
 929      layout, since we can't tell, and it's much more common.  Which bits are
 930      the "high" bits depends on endianness.  */
 931   for (ireg = 0; ireg < 32; ireg++)
 932     if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
 933       trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
 934                                sigcontext_base + SIGCONTEXT_FPREGS + 4
 935                                + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
 936     else
 937       trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
 938                                sigcontext_base + SIGCONTEXT_FPREGS
 939                                + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
 940
 941   trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
 942                            regs_base + SIGCONTEXT_PC);
 943
 944   trad_frame_set_reg_addr (this_cache,
 945                            regs->fp_control_status + NUM_REGS,
 946                            sigcontext_base + SIGCONTEXT_FPCSR);
 947   trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
 948                            regs_base + SIGCONTEXT_HI);
 949   trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
 950                            regs_base + SIGCONTEXT_LO);
 951   trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
 952                            sigcontext_base + SIGCONTEXT_CAUSE);
 953   trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
 954                            sigcontext_base + SIGCONTEXT_BADVADDR);
 955
 956   /* Choice of the bottom of the sigframe is somewhat arbitrary.  */
 957   trad_frame_set_id (this_cache,
 958                      frame_id_build (func - SIGFRAME_CODE_OFFSET,
 959                                      func));
 960 }
 961
 962 /* *INDENT-OFF* */
 963 /* For N32/N64 things look different.  There is no non-rt signal frame.
 964
 965   struct rt_sigframe_n32 {
 966     u32 rs_ass[4];                  [ argument save space for o32 ]
 967     u32 rs_code[2];                 [ signal trampoline ]
 968     struct siginfo rs_info;
 969     struct ucontextn32 rs_uc;
 970   };
 971
 972   struct ucontextn32 {
 973     u32                 uc_flags;
 974     s32                 uc_link;
 975     stack32_t           uc_stack;
 976     struct sigcontext   uc_mcontext;
 977     sigset_t            uc_sigmask;   [ mask last for extensibility ]
 978   };
 979
 980   struct rt_sigframe_n32 {
 981     u32 rs_ass[4];                  [ argument save space for o32 ]
 982     u32 rs_code[2];                 [ signal trampoline ]
 983     struct siginfo rs_info;
 984     struct ucontext rs_uc;
 985   };
 986
 987   struct ucontext {
 988     unsigned long     uc_flags;
 989     struct ucontext  *uc_link;
 990     stack_t           uc_stack;
 991     struct sigcontext uc_mcontext;
 992     sigset_t          uc_sigmask;   [ mask last for extensibility ]
 993   };
 994
 995   And the sigcontext is different (this is for both n32 and n64):
 996
 997   struct sigcontext {
 998     unsigned long long sc_regs[32];
 999     unsigned long long sc_fpregs[32];
1000     unsigned long long sc_mdhi;
1001     unsigned long long sc_mdlo;
1002     unsigned long long sc_pc;
1003     unsigned int       sc_status;
1004     unsigned int       sc_fpc_csr;
1005     unsigned int       sc_fpc_eir;
1006     unsigned int       sc_used_math;
1007     unsigned int       sc_cause;
1008     unsigned int       sc_badvaddr;
1009   };  */
1010 /* *INDENT-ON* */
1011
1012 #define N32_STACK_T_SIZE                STACK_T_SIZE
1013 #define N64_STACK_T_SIZE                (2 * 8 + 4)
1014 #define N32_UCONTEXT_SIGCONTEXT_OFFSET  (2 * 4 + N32_STACK_T_SIZE + 4)
1015 #define N64_UCONTEXT_SIGCONTEXT_OFFSET  (2 * 8 + N64_STACK_T_SIZE + 4)
1016 #define N32_SIGFRAME_SIGCONTEXT_OFFSET  (SIGFRAME_SIGCONTEXT_OFFSET \
1017                                          + RTSIGFRAME_SIGINFO_SIZE \
1018                                          + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1019 #define N64_SIGFRAME_SIGCONTEXT_OFFSET  (SIGFRAME_SIGCONTEXT_OFFSET \
1020                                          + RTSIGFRAME_SIGINFO_SIZE \
1021                                          + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1022
1023 #define N64_SIGCONTEXT_REGS     (0 * 8)
1024 #define N64_SIGCONTEXT_FPREGS   (32 * 8)
1025 #define N64_SIGCONTEXT_HI       (64 * 8)
1026 #define N64_SIGCONTEXT_LO       (65 * 8)
1027 #define N64_SIGCONTEXT_PC       (66 * 8)
1028 #define N64_SIGCONTEXT_FPCSR    (67 * 8 + 1 * 4)
1029 #define N64_SIGCONTEXT_FIR      (67 * 8 + 2 * 4)
1030 #define N64_SIGCONTEXT_CAUSE    (67 * 8 + 4 * 4)
1031 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1032
1033 #define N64_SIGCONTEXT_REG_SIZE 8
1034
1035 static void
1036 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1037                                  struct frame_info *next_frame,
1038                                  struct trad_frame_cache *this_cache,
1039                                  CORE_ADDR func)
1040 {
1041   int ireg, reg_position;
1042   CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1043   const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1044
1045   if (self == &mips_linux_n32_rt_sigframe)
1046     sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1047   else
1048     sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
1049
1050 #if 0
1051   trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1052                            sigcontext_base + N64_SIGCONTEXT_REGS);
1053 #endif
1054
1055   for (ireg = 1; ireg < 32; ireg++)
1056     trad_frame_set_reg_addr (this_cache,
1057                              ireg + MIPS_ZERO_REGNUM + NUM_REGS,
1058                              sigcontext_base + N64_SIGCONTEXT_REGS
1059                              + ireg * N64_SIGCONTEXT_REG_SIZE);
1060
1061   for (ireg = 0; ireg < 32; ireg++)
1062     trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1063                              sigcontext_base + N64_SIGCONTEXT_FPREGS
1064                              + ireg * N64_SIGCONTEXT_REG_SIZE);
1065
1066   trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1067                            sigcontext_base + N64_SIGCONTEXT_PC);
1068
1069   trad_frame_set_reg_addr (this_cache,
1070                            regs->fp_control_status + NUM_REGS,
1071                            sigcontext_base + N64_SIGCONTEXT_FPCSR);
1072   trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1073                            sigcontext_base + N64_SIGCONTEXT_HI);
1074   trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1075                            sigcontext_base + N64_SIGCONTEXT_LO);
1076   trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1077                            sigcontext_base + N64_SIGCONTEXT_CAUSE);
1078   trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1079                            sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1080
1081   /* Choice of the bottom of the sigframe is somewhat arbitrary.  */
1082   trad_frame_set_id (this_cache,
1083                      frame_id_build (func - SIGFRAME_CODE_OFFSET,
1084                                      func));
1085 }
1086
1087 /* Initialize one of the GNU/Linux OS ABIs.  */
1088
1089 static void
1090 mips_linux_init_abi (struct gdbarch_info info,
1091                      struct gdbarch *gdbarch)
1092 {
1093   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1094   enum mips_abi abi = mips_abi (gdbarch);
1095
1096   switch (abi)
1097     {
1098       case MIPS_ABI_O32:
1099         set_gdbarch_get_longjmp_target (gdbarch,
1100                                         mips_linux_get_longjmp_target);
1101         set_solib_svr4_fetch_link_map_offsets
1102           (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1103         set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
1104         tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1105         tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
1106         break;
1107       case MIPS_ABI_N32:
1108         set_gdbarch_get_longjmp_target (gdbarch,
1109                                         mips_linux_get_longjmp_target);
1110         set_solib_svr4_fetch_link_map_offsets
1111           (gdbarch, svr4_ilp32_fetch_link_map_offsets);
1112         set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
1113         tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
1114         break;
1115       case MIPS_ABI_N64:
1116         set_gdbarch_get_longjmp_target (gdbarch,
1117                                         mips64_linux_get_longjmp_target);
1118         set_solib_svr4_fetch_link_map_offsets
1119           (gdbarch, svr4_lp64_fetch_link_map_offsets);
1120         set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
1121         tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
1122         break;
1123       default:
1124         internal_error (__FILE__, __LINE__, _("can't handle ABI"));
1125         break;
1126     }
1127
1128   set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1129
1130   set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
1131
1132   /* Enable TLS support.  */
1133   set_gdbarch_fetch_tls_load_module_address (gdbarch,
1134                                              svr4_fetch_objfile_link_map);
1135 }
1136
1137 void
1138 _initialize_mips_linux_tdep (void)
1139 {
1140   const struct bfd_arch_info *arch_info;
1141
1142   register_addr_data =
1143     gdbarch_data_register_post_init (init_register_addr_data);
1144
1145   for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1146        arch_info != NULL;
1147        arch_info = arch_info->next)
1148     {
1149       gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1150                               GDB_OSABI_LINUX,
1151                               mips_linux_init_abi);
1152     }
1153
1154   deprecated_add_core_fns (&regset_core_fns);
1155 }