1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
37 #include "solib-svr4.h"
40 #include "mips-linux-tdep.h"
42 static struct target_so_ops mips_svr4_so_ops
;
44 /* Figure out where the longjmp will land.
45 We expect the first arg to be a pointer to the jmp_buf structure
46 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
47 at. The pc is copied into PC. This routine returns 1 on
50 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
51 #define MIPS_LINUX_JB_PC 0
54 mips_linux_get_longjmp_target (CORE_ADDR
*pc
)
57 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
59 jb_addr
= read_register (MIPS_A0_REGNUM
);
61 if (target_read_memory (jb_addr
62 + MIPS_LINUX_JB_PC
* MIPS_LINUX_JB_ELEMENT_SIZE
,
63 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
66 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
71 /* Transform the bits comprising a 32-bit register to the right size
72 for regcache_raw_supply(). This is needed when mips_isa_regsize()
76 supply_32bit_reg (struct regcache
*regcache
, int regnum
, const void *addr
)
78 gdb_byte buf
[MAX_REGISTER_SIZE
];
79 store_signed_integer (buf
, register_size (current_gdbarch
, regnum
),
80 extract_signed_integer (addr
, 4));
81 regcache_raw_supply (regcache
, regnum
, buf
);
84 /* Unpack an elf_gregset_t into GDB's register cache. */
87 mips_supply_gregset (struct regcache
*regcache
,
88 const mips_elf_gregset_t
*gregsetp
)
91 const mips_elf_greg_t
*regp
= *gregsetp
;
92 char zerobuf
[MAX_REGISTER_SIZE
];
94 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
96 for (regi
= EF_REG0
; regi
<= EF_REG31
; regi
++)
97 supply_32bit_reg (regcache
, regi
- EF_REG0
, regp
+ regi
);
99 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->lo
,
101 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->hi
,
104 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->pc
,
106 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->badvaddr
,
107 regp
+ EF_CP0_BADVADDR
);
108 supply_32bit_reg (regcache
, MIPS_PS_REGNUM
, regp
+ EF_CP0_STATUS
);
109 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->cause
,
110 regp
+ EF_CP0_CAUSE
);
112 /* Fill inaccessible registers with zero. */
113 regcache_raw_supply (regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
114 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
115 regi
< MIPS_LAST_EMBED_REGNUM
;
117 regcache_raw_supply (regcache
, regi
, zerobuf
);
120 /* Pack our registers (or one register) into an elf_gregset_t. */
123 mips_fill_gregset (const struct regcache
*regcache
,
124 mips_elf_gregset_t
*gregsetp
, int regno
)
127 mips_elf_greg_t
*regp
= *gregsetp
;
132 memset (regp
, 0, sizeof (mips_elf_gregset_t
));
133 for (regi
= 0; regi
< 32; regi
++)
134 mips_fill_gregset (regcache
, gregsetp
, regi
);
135 mips_fill_gregset (regcache
, gregsetp
,
136 mips_regnum (current_gdbarch
)->lo
);
137 mips_fill_gregset (regcache
, gregsetp
,
138 mips_regnum (current_gdbarch
)->hi
);
139 mips_fill_gregset (regcache
, gregsetp
,
140 mips_regnum (current_gdbarch
)->pc
);
141 mips_fill_gregset (regcache
, gregsetp
,
142 mips_regnum (current_gdbarch
)->badvaddr
);
143 mips_fill_gregset (regcache
, gregsetp
, MIPS_PS_REGNUM
);
144 mips_fill_gregset (regcache
, gregsetp
,
145 mips_regnum (current_gdbarch
)->cause
);
151 dst
= regp
+ regno
+ EF_REG0
;
152 regcache_raw_collect (regcache
, regno
, dst
);
156 if (regno
== mips_regnum (current_gdbarch
)->lo
)
158 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
160 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
161 regaddr
= EF_CP0_EPC
;
162 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
163 regaddr
= EF_CP0_BADVADDR
;
164 else if (regno
== MIPS_PS_REGNUM
)
165 regaddr
= EF_CP0_STATUS
;
166 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
167 regaddr
= EF_CP0_CAUSE
;
173 dst
= regp
+ regaddr
;
174 regcache_raw_collect (regcache
, regno
, dst
);
178 /* Likewise, unpack an elf_fpregset_t. */
181 mips_supply_fpregset (struct regcache
*regcache
,
182 const mips_elf_fpregset_t
*fpregsetp
)
185 char zerobuf
[MAX_REGISTER_SIZE
];
187 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
189 for (regi
= 0; regi
< 32; regi
++)
190 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
, *fpregsetp
+ regi
);
192 regcache_raw_supply (regcache
,
193 mips_regnum (current_gdbarch
)->fp_control_status
,
196 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
197 regcache_raw_supply (regcache
,
198 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
202 /* Likewise, pack one or all floating point registers into an
206 mips_fill_fpregset (const struct regcache
*regcache
,
207 mips_elf_fpregset_t
*fpregsetp
, int regno
)
211 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
213 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
214 regcache_raw_collect (regcache
, regno
, to
);
216 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
218 to
= (char *) (*fpregsetp
+ 32);
219 regcache_raw_collect (regcache
, regno
, to
);
221 else if (regno
== -1)
225 for (regi
= 0; regi
< 32; regi
++)
226 mips_fill_fpregset (regcache
, fpregsetp
, FP0_REGNUM
+ regi
);
227 mips_fill_fpregset (regcache
, fpregsetp
,
228 mips_regnum (current_gdbarch
)->fp_control_status
);
232 /* Support for 64-bit ABIs. */
234 /* Figure out where the longjmp will land.
235 We expect the first arg to be a pointer to the jmp_buf structure
236 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
237 at. The pc is copied into PC. This routine returns 1 on
240 /* Details about jmp_buf. */
242 #define MIPS64_LINUX_JB_PC 0
245 mips64_linux_get_longjmp_target (CORE_ADDR
*pc
)
248 void *buf
= alloca (TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
249 int element_size
= TARGET_PTR_BIT
== 32 ? 4 : 8;
251 jb_addr
= read_register (MIPS_A0_REGNUM
);
253 if (target_read_memory (jb_addr
+ MIPS64_LINUX_JB_PC
* element_size
,
254 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
257 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
262 /* Register set support functions. These operate on standard 64-bit
263 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
264 target will still use the 64-bit format for PTRACE_GETREGS. */
266 /* Supply a 64-bit register. */
269 supply_64bit_reg (struct regcache
*regcache
, int regnum
,
272 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
273 && register_size (current_gdbarch
, regnum
) == 4)
274 regcache_raw_supply (regcache
, regnum
, buf
+ 4);
276 regcache_raw_supply (regcache
, regnum
, buf
);
279 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
282 mips64_supply_gregset (struct regcache
*regcache
,
283 const mips64_elf_gregset_t
*gregsetp
)
286 const mips64_elf_greg_t
*regp
= *gregsetp
;
287 gdb_byte zerobuf
[MAX_REGISTER_SIZE
];
289 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
291 for (regi
= MIPS64_EF_REG0
; regi
<= MIPS64_EF_REG31
; regi
++)
292 supply_64bit_reg (regcache
, regi
- MIPS64_EF_REG0
,
293 (const gdb_byte
*)(regp
+ regi
));
295 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->lo
,
296 (const gdb_byte
*) (regp
+ MIPS64_EF_LO
));
297 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->hi
,
298 (const gdb_byte
*) (regp
+ MIPS64_EF_HI
));
300 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->pc
,
301 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_EPC
));
302 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->badvaddr
,
303 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_BADVADDR
));
304 supply_64bit_reg (regcache
, MIPS_PS_REGNUM
,
305 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_STATUS
));
306 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->cause
,
307 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_CAUSE
));
309 /* Fill inaccessible registers with zero. */
310 regcache_raw_supply (regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
311 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
312 regi
< MIPS_LAST_EMBED_REGNUM
;
314 regcache_raw_supply (regcache
, regi
, zerobuf
);
317 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
320 mips64_fill_gregset (const struct regcache
*regcache
,
321 mips64_elf_gregset_t
*gregsetp
, int regno
)
324 mips64_elf_greg_t
*regp
= *gregsetp
;
329 memset (regp
, 0, sizeof (mips64_elf_gregset_t
));
330 for (regi
= 0; regi
< 32; regi
++)
331 mips64_fill_gregset (regcache
, gregsetp
, regi
);
332 mips64_fill_gregset (regcache
, gregsetp
,
333 mips_regnum (current_gdbarch
)->lo
);
334 mips64_fill_gregset (regcache
, gregsetp
,
335 mips_regnum (current_gdbarch
)->hi
);
336 mips64_fill_gregset (regcache
, gregsetp
,
337 mips_regnum (current_gdbarch
)->pc
);
338 mips64_fill_gregset (regcache
, gregsetp
,
339 mips_regnum (current_gdbarch
)->badvaddr
);
340 mips64_fill_gregset (regcache
, gregsetp
, MIPS_PS_REGNUM
);
341 mips64_fill_gregset (regcache
, gregsetp
,
342 mips_regnum (current_gdbarch
)->cause
);
347 regaddr
= regno
+ MIPS64_EF_REG0
;
348 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
349 regaddr
= MIPS64_EF_LO
;
350 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
351 regaddr
= MIPS64_EF_HI
;
352 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
353 regaddr
= MIPS64_EF_CP0_EPC
;
354 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
355 regaddr
= MIPS64_EF_CP0_BADVADDR
;
356 else if (regno
== MIPS_PS_REGNUM
)
357 regaddr
= MIPS64_EF_CP0_STATUS
;
358 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
359 regaddr
= MIPS64_EF_CP0_CAUSE
;
365 gdb_byte buf
[MAX_REGISTER_SIZE
];
368 regcache_raw_collect (regcache
, regno
, buf
);
369 val
= extract_signed_integer (buf
,
370 register_size (current_gdbarch
, regno
));
371 dst
= regp
+ regaddr
;
372 store_signed_integer (dst
, 8, val
);
376 /* Likewise, unpack an elf_fpregset_t. */
379 mips64_supply_fpregset (struct regcache
*regcache
,
380 const mips64_elf_fpregset_t
*fpregsetp
)
384 /* See mips_linux_o32_sigframe_init for a description of the
385 peculiar FP register layout. */
386 if (register_size (current_gdbarch
, FP0_REGNUM
) == 4)
387 for (regi
= 0; regi
< 32; regi
++)
389 const gdb_byte
*reg_ptr
= (const gdb_byte
*)(*fpregsetp
+ (regi
& ~1));
390 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
392 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
, reg_ptr
);
395 for (regi
= 0; regi
< 32; regi
++)
396 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
,
397 (const char *)(*fpregsetp
+ regi
));
399 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->fp_control_status
,
400 (const gdb_byte
*)(*fpregsetp
+ 32));
402 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
403 include it - but the result of PTRACE_GETFPREGS does. The best we
404 can do is to assume that its value is present. */
405 supply_32bit_reg (regcache
,
406 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
407 (const gdb_byte
*)(*fpregsetp
+ 32) + 4);
410 /* Likewise, pack one or all floating point registers into an
414 mips64_fill_fpregset (const struct regcache
*regcache
,
415 mips64_elf_fpregset_t
*fpregsetp
, int regno
)
419 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
421 /* See mips_linux_o32_sigframe_init for a description of the
422 peculiar FP register layout. */
423 if (register_size (current_gdbarch
, regno
) == 4)
425 int regi
= regno
- FP0_REGNUM
;
427 to
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
428 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
430 regcache_raw_collect (regcache
, regno
, to
);
434 to
= (gdb_byte
*) (*fpregsetp
+ regno
- FP0_REGNUM
);
435 regcache_raw_collect (regcache
, regno
, to
);
438 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
440 gdb_byte buf
[MAX_REGISTER_SIZE
];
443 regcache_raw_collect (regcache
, regno
, buf
);
444 val
= extract_signed_integer (buf
,
445 register_size (current_gdbarch
, regno
));
446 to
= (gdb_byte
*) (*fpregsetp
+ 32);
447 store_signed_integer (to
, 4, val
);
449 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
451 gdb_byte buf
[MAX_REGISTER_SIZE
];
454 regcache_raw_collect (regcache
, regno
, buf
);
455 val
= extract_signed_integer (buf
,
456 register_size (current_gdbarch
, regno
));
457 to
= (gdb_byte
*) (*fpregsetp
+ 32) + 4;
458 store_signed_integer (to
, 4, val
);
460 else if (regno
== -1)
464 for (regi
= 0; regi
< 32; regi
++)
465 mips64_fill_fpregset (regcache
, fpregsetp
, FP0_REGNUM
+ regi
);
466 mips64_fill_fpregset (regcache
, fpregsetp
,
467 mips_regnum (current_gdbarch
)->fp_control_status
);
468 mips64_fill_fpregset (regcache
, fpregsetp
,
469 (mips_regnum (current_gdbarch
)
470 ->fp_implementation_revision
));
475 /* Use a local version of this function to get the correct types for
476 regsets, until multi-arch core support is ready. */
479 fetch_core_registers (struct regcache
*regcache
,
480 char *core_reg_sect
, unsigned core_reg_size
,
481 int which
, CORE_ADDR reg_addr
)
483 mips_elf_gregset_t gregset
;
484 mips_elf_fpregset_t fpregset
;
485 mips64_elf_gregset_t gregset64
;
486 mips64_elf_fpregset_t fpregset64
;
490 if (core_reg_size
== sizeof (gregset
))
492 memcpy ((char *) &gregset
, core_reg_sect
, sizeof (gregset
));
493 mips_supply_gregset (regcache
,
494 (const mips_elf_gregset_t
*) &gregset
);
496 else if (core_reg_size
== sizeof (gregset64
))
498 memcpy ((char *) &gregset64
, core_reg_sect
, sizeof (gregset64
));
499 mips64_supply_gregset (regcache
,
500 (const mips64_elf_gregset_t
*) &gregset64
);
504 warning (_("wrong size gregset struct in core file"));
509 if (core_reg_size
== sizeof (fpregset
))
511 memcpy ((char *) &fpregset
, core_reg_sect
, sizeof (fpregset
));
512 mips_supply_fpregset (regcache
,
513 (const mips_elf_fpregset_t
*) &fpregset
);
515 else if (core_reg_size
== sizeof (fpregset64
))
517 memcpy ((char *) &fpregset64
, core_reg_sect
,
518 sizeof (fpregset64
));
519 mips64_supply_fpregset (regcache
,
520 (const mips64_elf_fpregset_t
*) &fpregset64
);
524 warning (_("wrong size fpregset struct in core file"));
529 /* Register that we are able to handle ELF file formats using standard
530 procfs "regset" structures. */
532 static struct core_fns regset_core_fns
=
534 bfd_target_elf_flavour
, /* core_flavour */
535 default_check_format
, /* check_format */
536 default_core_sniffer
, /* core_sniffer */
537 fetch_core_registers
, /* core_read_registers */
542 /* Check the code at PC for a dynamic linker lazy resolution stub.
543 Because they aren't in the .plt section, we pattern-match on the
544 code generated by GNU ld. They look like this:
551 (with the appropriate doubleword instructions for N64). Also
552 return the dynamic symbol index used in the last instruction. */
555 mips_linux_in_dynsym_stub (CORE_ADDR pc
, char *name
)
557 unsigned char buf
[28], *p
;
558 ULONGEST insn
, insn1
;
559 int n64
= (mips_abi (current_gdbarch
) == MIPS_ABI_N64
);
561 read_memory (pc
- 12, buf
, 28);
565 /* ld t9,0x8010(gp) */
570 /* lw t9,0x8010(gp) */
577 insn
= extract_unsigned_integer (p
, 4);
585 insn
= extract_unsigned_integer (p
+ 4, 4);
589 if (insn
!= 0x03e0782d)
595 if (insn
!= 0x03e07821)
599 insn
= extract_unsigned_integer (p
+ 8, 4);
601 if (insn
!= 0x0320f809)
604 insn
= extract_unsigned_integer (p
+ 12, 4);
607 /* daddiu t8,zero,0 */
608 if ((insn
& 0xffff0000) != 0x64180000)
613 /* addiu t8,zero,0 */
614 if ((insn
& 0xffff0000) != 0x24180000)
618 return (insn
& 0xffff);
621 /* Return non-zero iff PC belongs to the dynamic linker resolution
622 code or to a stub. */
625 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc
)
627 /* Check whether PC is in the dynamic linker. This also checks
628 whether it is in the .plt section, which MIPS does not use. */
629 if (svr4_in_dynsym_resolve_code (pc
))
632 /* Pattern match for the stub. It would be nice if there were a
633 more efficient way to avoid this check. */
634 if (mips_linux_in_dynsym_stub (pc
, NULL
))
640 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
641 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
642 implementation of this triggers at "fixup" from the same objfile as
643 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
644 "__dl_runtime_resolve" directly. An unresolved PLT entry will
645 point to _dl_runtime_resolve, which will first call
646 __dl_runtime_resolve, and then pass control to the resolved
650 mips_linux_skip_resolver (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
652 struct minimal_symbol
*resolver
;
654 resolver
= lookup_minimal_symbol ("__dl_runtime_resolve", NULL
, NULL
);
656 if (resolver
&& SYMBOL_VALUE_ADDRESS (resolver
) == pc
)
657 return frame_pc_unwind (get_current_frame ());
662 /* Signal trampoline support. There are four supported layouts for a
663 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
664 n64 rt_sigframe. We handle them all independently; not the most
665 efficient way, but simplest. First, declare all the unwinders. */
667 static void mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
668 struct frame_info
*next_frame
,
669 struct trad_frame_cache
*this_cache
,
672 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
673 struct frame_info
*next_frame
,
674 struct trad_frame_cache
*this_cache
,
677 #define MIPS_NR_LINUX 4000
678 #define MIPS_NR_N64_LINUX 5000
679 #define MIPS_NR_N32_LINUX 6000
681 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
682 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
683 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
684 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
686 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
687 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
688 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
689 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
690 #define MIPS_INST_SYSCALL 0x0000000c
692 static const struct tramp_frame mips_linux_o32_sigframe
= {
696 { MIPS_INST_LI_V0_SIGRETURN
, -1 },
697 { MIPS_INST_SYSCALL
, -1 },
698 { TRAMP_SENTINEL_INSN
, -1 }
700 mips_linux_o32_sigframe_init
703 static const struct tramp_frame mips_linux_o32_rt_sigframe
= {
707 { MIPS_INST_LI_V0_RT_SIGRETURN
, -1 },
708 { MIPS_INST_SYSCALL
, -1 },
709 { TRAMP_SENTINEL_INSN
, -1 } },
710 mips_linux_o32_sigframe_init
713 static const struct tramp_frame mips_linux_n32_rt_sigframe
= {
717 { MIPS_INST_LI_V0_N32_RT_SIGRETURN
, -1 },
718 { MIPS_INST_SYSCALL
, -1 },
719 { TRAMP_SENTINEL_INSN
, -1 }
721 mips_linux_n32n64_sigframe_init
724 static const struct tramp_frame mips_linux_n64_rt_sigframe
= {
728 { MIPS_INST_LI_V0_N64_RT_SIGRETURN
, -1 },
729 { MIPS_INST_SYSCALL
, -1 },
730 { TRAMP_SENTINEL_INSN
, -1 }
732 mips_linux_n32n64_sigframe_init
736 /* The unwinder for o32 signal frames. The legacy structures look
740 u32 sf_ass[4]; [argument save space for o32]
741 u32 sf_code[2]; [signal trampoline]
742 struct sigcontext sf_sc;
747 unsigned int sc_regmask; [Unused]
748 unsigned int sc_status;
749 unsigned long long sc_pc;
750 unsigned long long sc_regs[32];
751 unsigned long long sc_fpregs[32];
752 unsigned int sc_ownedfp;
753 unsigned int sc_fpc_csr;
754 unsigned int sc_fpc_eir; [Unused]
755 unsigned int sc_used_math;
756 unsigned int sc_ssflags; [Unused]
757 [Alignment hole of four bytes]
758 unsigned long long sc_mdhi;
759 unsigned long long sc_mdlo;
761 unsigned int sc_cause; [Unused]
762 unsigned int sc_badvaddr; [Unused]
764 unsigned long sc_sigset[4]; [kernel's sigset_t]
767 The RT signal frames look like this:
770 u32 rs_ass[4]; [argument save space for o32]
771 u32 rs_code[2] [signal trampoline]
772 struct siginfo rs_info;
773 struct ucontext rs_uc;
777 unsigned long uc_flags;
778 struct ucontext *uc_link;
780 [Alignment hole of four bytes]
781 struct sigcontext uc_mcontext;
786 #define SIGFRAME_CODE_OFFSET (4 * 4)
787 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
789 #define RTSIGFRAME_SIGINFO_SIZE 128
790 #define STACK_T_SIZE (3 * 4)
791 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
792 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
793 + RTSIGFRAME_SIGINFO_SIZE \
794 + UCONTEXT_SIGCONTEXT_OFFSET)
796 #define SIGCONTEXT_PC (1 * 8)
797 #define SIGCONTEXT_REGS (2 * 8)
798 #define SIGCONTEXT_FPREGS (34 * 8)
799 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
800 #define SIGCONTEXT_HI (69 * 8)
801 #define SIGCONTEXT_LO (70 * 8)
802 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
803 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
805 #define SIGCONTEXT_REG_SIZE 8
808 mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
809 struct frame_info
*next_frame
,
810 struct trad_frame_cache
*this_cache
,
813 int ireg
, reg_position
;
814 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
815 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
818 if (self
== &mips_linux_o32_sigframe
)
819 sigcontext_base
+= SIGFRAME_SIGCONTEXT_OFFSET
;
821 sigcontext_base
+= RTSIGFRAME_SIGCONTEXT_OFFSET
;
823 /* I'm not proud of this hack. Eventually we will have the
824 infrastructure to indicate the size of saved registers on a
825 per-frame basis, but right now we don't; the kernel saves eight
826 bytes but we only want four. Use regs_base to access any
828 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
829 regs_base
= sigcontext_base
+ 4;
831 regs_base
= sigcontext_base
;
834 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
835 + gdbarch_num_regs (current_gdbarch
),
836 regs_base
+ SIGCONTEXT_REGS
);
839 for (ireg
= 1; ireg
< 32; ireg
++)
840 trad_frame_set_reg_addr (this_cache
,
841 ireg
+ MIPS_ZERO_REGNUM
842 + gdbarch_num_regs (current_gdbarch
),
843 regs_base
+ SIGCONTEXT_REGS
844 + ireg
* SIGCONTEXT_REG_SIZE
);
846 /* The way that floating point registers are saved, unfortunately,
847 depends on the architecture the kernel is built for. For the r3000 and
848 tx39, four bytes of each register are at the beginning of each of the
849 32 eight byte slots. For everything else, the registers are saved
850 using double precision; only the even-numbered slots are initialized,
851 and the high bits are the odd-numbered register. Assume the latter
852 layout, since we can't tell, and it's much more common. Which bits are
853 the "high" bits depends on endianness. */
854 for (ireg
= 0; ireg
< 32; ireg
++)
855 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (ireg
& 1))
856 trad_frame_set_reg_addr (this_cache
,
858 gdbarch_num_regs (current_gdbarch
),
859 sigcontext_base
+ SIGCONTEXT_FPREGS
+ 4
860 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
862 trad_frame_set_reg_addr (this_cache
,
864 + gdbarch_num_regs (current_gdbarch
),
865 sigcontext_base
+ SIGCONTEXT_FPREGS
866 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
868 trad_frame_set_reg_addr (this_cache
,
869 regs
->pc
+ gdbarch_num_regs (current_gdbarch
),
870 regs_base
+ SIGCONTEXT_PC
);
872 trad_frame_set_reg_addr (this_cache
,
873 regs
->fp_control_status
874 + gdbarch_num_regs (current_gdbarch
),
875 sigcontext_base
+ SIGCONTEXT_FPCSR
);
876 trad_frame_set_reg_addr (this_cache
,
877 regs
->hi
+ gdbarch_num_regs (current_gdbarch
),
878 regs_base
+ SIGCONTEXT_HI
);
879 trad_frame_set_reg_addr (this_cache
,
880 regs
->lo
+ gdbarch_num_regs (current_gdbarch
),
881 regs_base
+ SIGCONTEXT_LO
);
882 trad_frame_set_reg_addr (this_cache
,
883 regs
->cause
+ gdbarch_num_regs (current_gdbarch
),
884 sigcontext_base
+ SIGCONTEXT_CAUSE
);
885 trad_frame_set_reg_addr (this_cache
,
886 regs
->badvaddr
+ gdbarch_num_regs (current_gdbarch
),
887 sigcontext_base
+ SIGCONTEXT_BADVADDR
);
889 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
890 trad_frame_set_id (this_cache
,
891 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
896 /* For N32/N64 things look different. There is no non-rt signal frame.
898 struct rt_sigframe_n32 {
899 u32 rs_ass[4]; [ argument save space for o32 ]
900 u32 rs_code[2]; [ signal trampoline ]
901 struct siginfo rs_info;
902 struct ucontextn32 rs_uc;
909 struct sigcontext uc_mcontext;
910 sigset_t uc_sigmask; [ mask last for extensibility ]
913 struct rt_sigframe_n32 {
914 u32 rs_ass[4]; [ argument save space for o32 ]
915 u32 rs_code[2]; [ signal trampoline ]
916 struct siginfo rs_info;
917 struct ucontext rs_uc;
921 unsigned long uc_flags;
922 struct ucontext *uc_link;
924 struct sigcontext uc_mcontext;
925 sigset_t uc_sigmask; [ mask last for extensibility ]
928 And the sigcontext is different (this is for both n32 and n64):
931 unsigned long long sc_regs[32];
932 unsigned long long sc_fpregs[32];
933 unsigned long long sc_mdhi;
934 unsigned long long sc_mdlo;
935 unsigned long long sc_pc;
936 unsigned int sc_status;
937 unsigned int sc_fpc_csr;
938 unsigned int sc_fpc_eir;
939 unsigned int sc_used_math;
940 unsigned int sc_cause;
941 unsigned int sc_badvaddr;
945 #define N32_STACK_T_SIZE STACK_T_SIZE
946 #define N64_STACK_T_SIZE (2 * 8 + 4)
947 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
948 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
949 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
950 + RTSIGFRAME_SIGINFO_SIZE \
951 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
952 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
953 + RTSIGFRAME_SIGINFO_SIZE \
954 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
956 #define N64_SIGCONTEXT_REGS (0 * 8)
957 #define N64_SIGCONTEXT_FPREGS (32 * 8)
958 #define N64_SIGCONTEXT_HI (64 * 8)
959 #define N64_SIGCONTEXT_LO (65 * 8)
960 #define N64_SIGCONTEXT_PC (66 * 8)
961 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
962 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
963 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
964 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
966 #define N64_SIGCONTEXT_REG_SIZE 8
969 mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
970 struct frame_info
*next_frame
,
971 struct trad_frame_cache
*this_cache
,
974 int ireg
, reg_position
;
975 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
976 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
978 if (self
== &mips_linux_n32_rt_sigframe
)
979 sigcontext_base
+= N32_SIGFRAME_SIGCONTEXT_OFFSET
;
981 sigcontext_base
+= N64_SIGFRAME_SIGCONTEXT_OFFSET
;
984 trad_frame_set_reg_addr (this_cache
,
986 + gdbarch_num_regs (current_gdbarch
),
987 sigcontext_base
+ N64_SIGCONTEXT_REGS
);
990 for (ireg
= 1; ireg
< 32; ireg
++)
991 trad_frame_set_reg_addr (this_cache
,
992 ireg
+ MIPS_ZERO_REGNUM
993 + gdbarch_num_regs (current_gdbarch
),
994 sigcontext_base
+ N64_SIGCONTEXT_REGS
995 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
997 for (ireg
= 0; ireg
< 32; ireg
++)
998 trad_frame_set_reg_addr (this_cache
,
1000 + gdbarch_num_regs (current_gdbarch
),
1001 sigcontext_base
+ N64_SIGCONTEXT_FPREGS
1002 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1004 trad_frame_set_reg_addr (this_cache
,
1005 regs
->pc
+ gdbarch_num_regs (current_gdbarch
),
1006 sigcontext_base
+ N64_SIGCONTEXT_PC
);
1008 trad_frame_set_reg_addr (this_cache
,
1009 regs
->fp_control_status
1010 + gdbarch_num_regs (current_gdbarch
),
1011 sigcontext_base
+ N64_SIGCONTEXT_FPCSR
);
1012 trad_frame_set_reg_addr (this_cache
,
1013 regs
->hi
+ gdbarch_num_regs (current_gdbarch
),
1014 sigcontext_base
+ N64_SIGCONTEXT_HI
);
1015 trad_frame_set_reg_addr (this_cache
,
1016 regs
->lo
+ gdbarch_num_regs (current_gdbarch
),
1017 sigcontext_base
+ N64_SIGCONTEXT_LO
);
1018 trad_frame_set_reg_addr (this_cache
,
1019 regs
->cause
+ gdbarch_num_regs (current_gdbarch
),
1020 sigcontext_base
+ N64_SIGCONTEXT_CAUSE
);
1021 trad_frame_set_reg_addr (this_cache
,
1022 regs
->badvaddr
+ gdbarch_num_regs (current_gdbarch
),
1023 sigcontext_base
+ N64_SIGCONTEXT_BADVADDR
);
1025 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1026 trad_frame_set_id (this_cache
,
1027 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
1032 /* Initialize one of the GNU/Linux OS ABIs. */
1035 mips_linux_init_abi (struct gdbarch_info info
,
1036 struct gdbarch
*gdbarch
)
1038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1039 enum mips_abi abi
= mips_abi (gdbarch
);
1044 set_gdbarch_get_longjmp_target (gdbarch
,
1045 mips_linux_get_longjmp_target
);
1046 set_solib_svr4_fetch_link_map_offsets
1047 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1048 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_sigframe
);
1049 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_rt_sigframe
);
1052 set_gdbarch_get_longjmp_target (gdbarch
,
1053 mips_linux_get_longjmp_target
);
1054 set_solib_svr4_fetch_link_map_offsets
1055 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1056 set_gdbarch_long_double_bit (gdbarch
, 128);
1057 /* These floatformats should probably be renamed. MIPS uses
1058 the same 128-bit IEEE floating point format that IA-64 uses,
1059 except that the quiet/signalling NaN bit is reversed (GDB
1060 does not distinguish between quiet and signalling NaNs). */
1061 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
1062 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n32_rt_sigframe
);
1065 set_gdbarch_get_longjmp_target (gdbarch
,
1066 mips64_linux_get_longjmp_target
);
1067 set_solib_svr4_fetch_link_map_offsets
1068 (gdbarch
, svr4_lp64_fetch_link_map_offsets
);
1069 set_gdbarch_long_double_bit (gdbarch
, 128);
1070 /* These floatformats should probably be renamed. MIPS uses
1071 the same 128-bit IEEE floating point format that IA-64 uses,
1072 except that the quiet/signalling NaN bit is reversed (GDB
1073 does not distinguish between quiet and signalling NaNs). */
1074 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
1075 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n64_rt_sigframe
);
1078 internal_error (__FILE__
, __LINE__
, _("can't handle ABI"));
1082 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
1083 set_gdbarch_skip_solib_resolver (gdbarch
, mips_linux_skip_resolver
);
1085 set_gdbarch_software_single_step (gdbarch
, mips_software_single_step
);
1087 /* Enable TLS support. */
1088 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1089 svr4_fetch_objfile_link_map
);
1091 /* Initialize this lazily, to avoid an initialization order
1092 dependency on solib-svr4.c's _initialize routine. */
1093 if (mips_svr4_so_ops
.in_dynsym_resolve_code
== NULL
)
1095 mips_svr4_so_ops
= svr4_so_ops
;
1096 mips_svr4_so_ops
.in_dynsym_resolve_code
1097 = mips_linux_in_dynsym_resolve_code
;
1099 set_solib_ops (gdbarch
, &mips_svr4_so_ops
);
1103 _initialize_mips_linux_tdep (void)
1105 const struct bfd_arch_info
*arch_info
;
1107 for (arch_info
= bfd_lookup_arch (bfd_arch_mips
, 0);
1109 arch_info
= arch_info
->next
)
1111 gdbarch_register_osabi (bfd_arch_mips
, arch_info
->mach
,
1113 mips_linux_init_abi
);
1116 deprecated_add_core_fns (®set_core_fns
);