Phase 1 of the ptid_t changes.
[deliverable/binutils-gdb.git] / gdb / mips-tdep.c
1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8
9 This file is part of GDB.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #include "defs.h"
27 #include "gdb_string.h"
28 #include "frame.h"
29 #include "inferior.h"
30 #include "symtab.h"
31 #include "value.h"
32 #include "gdbcmd.h"
33 #include "language.h"
34 #include "gdbcore.h"
35 #include "symfile.h"
36 #include "objfiles.h"
37 #include "gdbtypes.h"
38 #include "target.h"
39 #include "arch-utils.h"
40 #include "regcache.h"
41
42 #include "opcode/mips.h"
43 #include "elf/mips.h"
44 #include "elf-bfd.h"
45 #include "symcat.h"
46
47 /* The sizes of floating point registers. */
48
49 enum
50 {
51 MIPS_FPU_SINGLE_REGSIZE = 4,
52 MIPS_FPU_DOUBLE_REGSIZE = 8
53 };
54
55 /* All the possible MIPS ABIs. */
56
57 enum mips_abi
58 {
59 MIPS_ABI_UNKNOWN,
60 MIPS_ABI_N32,
61 MIPS_ABI_O32,
62 MIPS_ABI_O64,
63 MIPS_ABI_EABI32,
64 MIPS_ABI_EABI64
65 };
66
67 struct frame_extra_info
68 {
69 mips_extra_func_info_t proc_desc;
70 int num_args;
71 };
72
73 /* Various MIPS ISA options (related to stack analysis) can be
74 overridden dynamically. Establish an enum/array for managing
75 them. */
76
77 static const char size_auto[] = "auto";
78 static const char size_32[] = "32";
79 static const char size_64[] = "64";
80
81 static const char *size_enums[] = {
82 size_auto,
83 size_32,
84 size_64,
85 0
86 };
87
88 /* Some MIPS boards don't support floating point while others only
89 support single-precision floating-point operations. See also
90 FP_REGISTER_DOUBLE. */
91
92 enum mips_fpu_type
93 {
94 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
95 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
96 MIPS_FPU_NONE /* No floating point. */
97 };
98
99 #ifndef MIPS_DEFAULT_FPU_TYPE
100 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 #endif
102 static int mips_fpu_type_auto = 1;
103 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
104 #define MIPS_FPU_TYPE mips_fpu_type
105
106 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
107 #ifndef FP_REGISTER_DOUBLE
108 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
109 #endif
110
111 static int mips_debug = 0;
112
113 /* MIPS specific per-architecture information */
114 struct gdbarch_tdep
115 {
116 /* from the elf header */
117 int elf_flags;
118 /* mips options */
119 enum mips_abi mips_abi;
120 const char *mips_abi_string;
121 enum mips_fpu_type mips_fpu_type;
122 int mips_last_arg_regnum;
123 int mips_last_fp_arg_regnum;
124 int mips_default_saved_regsize;
125 int mips_fp_register_double;
126 int mips_regs_have_home_p;
127 int mips_default_stack_argsize;
128 int gdb_target_is_mips64;
129 int default_mask_address_p;
130 };
131
132 #if GDB_MULTI_ARCH
133 #undef MIPS_EABI
134 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
135 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
136 #endif
137
138 #if GDB_MULTI_ARCH
139 #undef MIPS_LAST_FP_ARG_REGNUM
140 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
141 #endif
142
143 #if GDB_MULTI_ARCH
144 #undef MIPS_LAST_ARG_REGNUM
145 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
146 #endif
147
148 #if GDB_MULTI_ARCH
149 #undef MIPS_FPU_TYPE
150 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
151 #endif
152
153 /* Return the currently configured (or set) saved register size. */
154
155 #if GDB_MULTI_ARCH
156 #undef MIPS_DEFAULT_SAVED_REGSIZE
157 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
158 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
159 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
160 #endif
161
162 static const char *mips_saved_regsize_string = size_auto;
163
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
165
166 static unsigned int
167 mips_saved_regsize (void)
168 {
169 if (mips_saved_regsize_string == size_auto)
170 return MIPS_DEFAULT_SAVED_REGSIZE;
171 else if (mips_saved_regsize_string == size_64)
172 return 8;
173 else /* if (mips_saved_regsize_string == size_32) */
174 return 4;
175 }
176
177 /* Indicate that the ABI makes use of double-precision registers
178 provided by the FPU (rather than combining pairs of registers to
179 form double-precision values). Do not use "TARGET_IS_MIPS64" to
180 determine if the ABI is using double-precision registers. See also
181 MIPS_FPU_TYPE. */
182 #if GDB_MULTI_ARCH
183 #undef FP_REGISTER_DOUBLE
184 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
185 #endif
186
187 /* Does the caller allocate a ``home'' for each register used in the
188 function call? The N32 ABI and MIPS_EABI do not, the others do. */
189
190 #if GDB_MULTI_ARCH
191 #undef MIPS_REGS_HAVE_HOME_P
192 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
193 #elif !defined (MIPS_REGS_HAVE_HOME_P)
194 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
195 #endif
196
197 /* The amount of space reserved on the stack for registers. This is
198 different to MIPS_SAVED_REGSIZE as it determines the alignment of
199 data allocated after the registers have run out. */
200
201 #if GDB_MULTI_ARCH
202 #undef MIPS_DEFAULT_STACK_ARGSIZE
203 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
204 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
205 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
206 #endif
207
208 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
209
210 static const char *mips_stack_argsize_string = size_auto;
211
212 static unsigned int
213 mips_stack_argsize (void)
214 {
215 if (mips_stack_argsize_string == size_auto)
216 return MIPS_DEFAULT_STACK_ARGSIZE;
217 else if (mips_stack_argsize_string == size_64)
218 return 8;
219 else /* if (mips_stack_argsize_string == size_32) */
220 return 4;
221 }
222
223 #if GDB_MULTI_ARCH
224 #undef GDB_TARGET_IS_MIPS64
225 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
226 #endif
227
228 #if GDB_MULTI_ARCH
229 #undef MIPS_DEFAULT_MASK_ADDRESS_P
230 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
231 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
232 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
233 #endif
234
235 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
236
237 int gdb_print_insn_mips (bfd_vma, disassemble_info *);
238
239 static void mips_print_register (int, int);
240
241 static mips_extra_func_info_t
242 heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *);
243
244 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
245
246 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
247
248 int mips_set_processor_type (char *);
249
250 static void mips_show_processor_type_command (char *, int);
251
252 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
253
254 static mips_extra_func_info_t
255 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame);
256
257 static CORE_ADDR after_prologue (CORE_ADDR pc,
258 mips_extra_func_info_t proc_desc);
259
260 /* This value is the model of MIPS in use. It is derived from the value
261 of the PrID register. */
262
263 char *mips_processor_type;
264
265 char *tmp_mips_processor_type;
266
267 /* The list of available "set mips " and "show mips " commands */
268
269 static struct cmd_list_element *setmipscmdlist = NULL;
270 static struct cmd_list_element *showmipscmdlist = NULL;
271
272 /* A set of original names, to be used when restoring back to generic
273 registers from a specific set. */
274
275 char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
276 char **mips_processor_reg_names = mips_generic_reg_names;
277
278 char *
279 mips_register_name (int i)
280 {
281 return mips_processor_reg_names[i];
282 }
283 /* *INDENT-OFF* */
284 /* Names of IDT R3041 registers. */
285
286 char *mips_r3041_reg_names[] = {
287 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
288 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
289 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
290 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
291 "sr", "lo", "hi", "bad", "cause","pc",
292 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
293 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
294 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
295 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
296 "fsr", "fir", "fp", "",
297 "", "", "bus", "ccfg", "", "", "", "",
298 "", "", "port", "cmp", "", "", "epc", "prid",
299 };
300
301 /* Names of IDT R3051 registers. */
302
303 char *mips_r3051_reg_names[] = {
304 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
305 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
306 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
307 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
308 "sr", "lo", "hi", "bad", "cause","pc",
309 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
310 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
311 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
312 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
313 "fsr", "fir", "fp", "",
314 "inx", "rand", "elo", "", "ctxt", "", "", "",
315 "", "", "ehi", "", "", "", "epc", "prid",
316 };
317
318 /* Names of IDT R3081 registers. */
319
320 char *mips_r3081_reg_names[] = {
321 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
322 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
323 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
324 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
325 "sr", "lo", "hi", "bad", "cause","pc",
326 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
327 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
328 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
329 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
330 "fsr", "fir", "fp", "",
331 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
332 "", "", "ehi", "", "", "", "epc", "prid",
333 };
334
335 /* Names of LSI 33k registers. */
336
337 char *mips_lsi33k_reg_names[] = {
338 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
339 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
340 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
341 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
342 "epc", "hi", "lo", "sr", "cause","badvaddr",
343 "dcic", "bpc", "bda", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
345 "", "", "", "", "", "", "", "",
346 "", "", "", "", "", "", "", "",
347 "", "", "", "",
348 "", "", "", "", "", "", "", "",
349 "", "", "", "", "", "", "", "",
350 };
351
352 struct {
353 char *name;
354 char **regnames;
355 } mips_processor_type_table[] = {
356 { "generic", mips_generic_reg_names },
357 { "r3041", mips_r3041_reg_names },
358 { "r3051", mips_r3051_reg_names },
359 { "r3071", mips_r3081_reg_names },
360 { "r3081", mips_r3081_reg_names },
361 { "lsi33k", mips_lsi33k_reg_names },
362 { NULL, NULL }
363 };
364 /* *INDENT-ON* */
365
366
367
368
369 /* Table to translate MIPS16 register field to actual register number. */
370 static int mips16_to_32_reg[8] =
371 {16, 17, 2, 3, 4, 5, 6, 7};
372
373 /* Heuristic_proc_start may hunt through the text section for a long
374 time across a 2400 baud serial line. Allows the user to limit this
375 search. */
376
377 static unsigned int heuristic_fence_post = 0;
378
379 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
380 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
381 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
382 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
383 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
384 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
385 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
386 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
387 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
388 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
389 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
390 #define _PROC_MAGIC_ 0x0F0F0F0F
391 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
392 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
393
394 struct linked_proc_info
395 {
396 struct mips_extra_func_info info;
397 struct linked_proc_info *next;
398 }
399 *linked_proc_desc_table = NULL;
400
401 void
402 mips_print_extra_frame_info (struct frame_info *fi)
403 {
404 if (fi
405 && fi->extra_info
406 && fi->extra_info->proc_desc
407 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
408 printf_filtered (" frame pointer is at %s+%s\n",
409 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
410 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
411 }
412
413 /* Convert between RAW and VIRTUAL registers. The RAW register size
414 defines the remote-gdb packet. */
415
416 static int mips64_transfers_32bit_regs_p = 0;
417
418 int
419 mips_register_raw_size (int reg_nr)
420 {
421 if (mips64_transfers_32bit_regs_p)
422 return REGISTER_VIRTUAL_SIZE (reg_nr);
423 else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32
424 && FP_REGISTER_DOUBLE)
425 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
426 registers. */
427 return 8;
428 else
429 return MIPS_REGSIZE;
430 }
431
432 int
433 mips_register_convertible (int reg_nr)
434 {
435 if (mips64_transfers_32bit_regs_p)
436 return 0;
437 else
438 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
439 }
440
441 void
442 mips_register_convert_to_virtual (int n, struct type *virtual_type,
443 char *raw_buf, char *virt_buf)
444 {
445 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
446 memcpy (virt_buf,
447 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
448 TYPE_LENGTH (virtual_type));
449 else
450 memcpy (virt_buf,
451 raw_buf,
452 TYPE_LENGTH (virtual_type));
453 }
454
455 void
456 mips_register_convert_to_raw (struct type *virtual_type, int n,
457 char *virt_buf, char *raw_buf)
458 {
459 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
460 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
461 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
462 virt_buf,
463 TYPE_LENGTH (virtual_type));
464 else
465 memcpy (raw_buf,
466 virt_buf,
467 TYPE_LENGTH (virtual_type));
468 }
469
470 /* Should the upper word of 64-bit addresses be zeroed? */
471 enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO;
472
473 static int
474 mips_mask_address_p (void)
475 {
476 switch (mask_address_var)
477 {
478 case CMD_AUTO_BOOLEAN_TRUE:
479 return 1;
480 case CMD_AUTO_BOOLEAN_FALSE:
481 return 0;
482 break;
483 case CMD_AUTO_BOOLEAN_AUTO:
484 return MIPS_DEFAULT_MASK_ADDRESS_P;
485 default:
486 internal_error (__FILE__, __LINE__,
487 "mips_mask_address_p: bad switch");
488 return -1;
489 }
490 }
491
492 static void
493 show_mask_address (char *cmd, int from_tty)
494 {
495 switch (mask_address_var)
496 {
497 case CMD_AUTO_BOOLEAN_TRUE:
498 printf_filtered ("The 32 bit mips address mask is enabled\n");
499 break;
500 case CMD_AUTO_BOOLEAN_FALSE:
501 printf_filtered ("The 32 bit mips address mask is disabled\n");
502 break;
503 case CMD_AUTO_BOOLEAN_AUTO:
504 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
505 mips_mask_address_p () ? "enabled" : "disabled");
506 break;
507 default:
508 internal_error (__FILE__, __LINE__,
509 "show_mask_address: bad switch");
510 break;
511 }
512 }
513
514 /* Should call_function allocate stack space for a struct return? */
515 int
516 mips_use_struct_convention (int gcc_p, struct type *type)
517 {
518 if (MIPS_EABI)
519 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
520 else
521 return 1; /* Structures are returned by ref in extra arg0 */
522 }
523
524 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
525
526 static int
527 pc_is_mips16 (bfd_vma memaddr)
528 {
529 struct minimal_symbol *sym;
530
531 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
532 if (IS_MIPS16_ADDR (memaddr))
533 return 1;
534
535 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
536 the high bit of the info field. Use this to decide if the function is
537 MIPS16 or normal MIPS. */
538 sym = lookup_minimal_symbol_by_pc (memaddr);
539 if (sym)
540 return MSYMBOL_IS_SPECIAL (sym);
541 else
542 return 0;
543 }
544
545 /* MIPS believes that the PC has a sign extended value. Perhaphs the
546 all registers should be sign extended for simplicity? */
547
548 static CORE_ADDR
549 mips_read_pc (ptid_t ptid)
550 {
551 return read_signed_register_pid (PC_REGNUM, ptid);
552 }
553
554 /* This returns the PC of the first inst after the prologue. If we can't
555 find the prologue, then return 0. */
556
557 static CORE_ADDR
558 after_prologue (CORE_ADDR pc,
559 mips_extra_func_info_t proc_desc)
560 {
561 struct symtab_and_line sal;
562 CORE_ADDR func_addr, func_end;
563
564 if (!proc_desc)
565 proc_desc = find_proc_desc (pc, NULL);
566
567 if (proc_desc)
568 {
569 /* If function is frameless, then we need to do it the hard way. I
570 strongly suspect that frameless always means prologueless... */
571 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
572 && PROC_FRAME_OFFSET (proc_desc) == 0)
573 return 0;
574 }
575
576 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
577 return 0; /* Unknown */
578
579 sal = find_pc_line (func_addr, 0);
580
581 if (sal.end < func_end)
582 return sal.end;
583
584 /* The line after the prologue is after the end of the function. In this
585 case, tell the caller to find the prologue the hard way. */
586
587 return 0;
588 }
589
590 /* Decode a MIPS32 instruction that saves a register in the stack, and
591 set the appropriate bit in the general register mask or float register mask
592 to indicate which register is saved. This is a helper function
593 for mips_find_saved_regs. */
594
595 static void
596 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
597 unsigned long *float_mask)
598 {
599 int reg;
600
601 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
602 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
603 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
604 {
605 /* It might be possible to use the instruction to
606 find the offset, rather than the code below which
607 is based on things being in a certain order in the
608 frame, but figuring out what the instruction's offset
609 is relative to might be a little tricky. */
610 reg = (inst & 0x001f0000) >> 16;
611 *gen_mask |= (1 << reg);
612 }
613 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
614 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
615 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
616
617 {
618 reg = ((inst & 0x001f0000) >> 16);
619 *float_mask |= (1 << reg);
620 }
621 }
622
623 /* Decode a MIPS16 instruction that saves a register in the stack, and
624 set the appropriate bit in the general register or float register mask
625 to indicate which register is saved. This is a helper function
626 for mips_find_saved_regs. */
627
628 static void
629 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
630 {
631 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
632 {
633 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
634 *gen_mask |= (1 << reg);
635 }
636 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
637 {
638 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
639 *gen_mask |= (1 << reg);
640 }
641 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
642 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
643 *gen_mask |= (1 << RA_REGNUM);
644 }
645
646
647 /* Fetch and return instruction from the specified location. If the PC
648 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
649
650 static t_inst
651 mips_fetch_instruction (CORE_ADDR addr)
652 {
653 char buf[MIPS_INSTLEN];
654 int instlen;
655 int status;
656
657 if (pc_is_mips16 (addr))
658 {
659 instlen = MIPS16_INSTLEN;
660 addr = UNMAKE_MIPS16_ADDR (addr);
661 }
662 else
663 instlen = MIPS_INSTLEN;
664 status = read_memory_nobpt (addr, buf, instlen);
665 if (status)
666 memory_error (status, addr);
667 return extract_unsigned_integer (buf, instlen);
668 }
669
670
671 /* These the fields of 32 bit mips instructions */
672 #define mips32_op(x) (x >> 25)
673 #define itype_op(x) (x >> 25)
674 #define itype_rs(x) ((x >> 21)& 0x1f)
675 #define itype_rt(x) ((x >> 16) & 0x1f)
676 #define itype_immediate(x) ( x & 0xffff)
677
678 #define jtype_op(x) (x >> 25)
679 #define jtype_target(x) ( x & 0x03fffff)
680
681 #define rtype_op(x) (x >>25)
682 #define rtype_rs(x) ((x>>21) & 0x1f)
683 #define rtype_rt(x) ((x>>16) & 0x1f)
684 #define rtype_rd(x) ((x>>11) & 0x1f)
685 #define rtype_shamt(x) ((x>>6) & 0x1f)
686 #define rtype_funct(x) (x & 0x3f )
687
688 static CORE_ADDR
689 mips32_relative_offset (unsigned long inst)
690 {
691 long x;
692 x = itype_immediate (inst);
693 if (x & 0x8000) /* sign bit set */
694 {
695 x |= 0xffff0000; /* sign extension */
696 }
697 x = x << 2;
698 return x;
699 }
700
701 /* Determine whate to set a single step breakpoint while considering
702 branch prediction */
703 CORE_ADDR
704 mips32_next_pc (CORE_ADDR pc)
705 {
706 unsigned long inst;
707 int op;
708 inst = mips_fetch_instruction (pc);
709 if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */
710 {
711 if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
712 {
713 op = ((inst >> 25) & 0x03);
714 switch (op)
715 {
716 case 0:
717 goto equal_branch; /* BEQL */
718 case 1:
719 goto neq_branch; /* BNEZ */
720 case 2:
721 goto less_branch; /* BLEZ */
722 case 3:
723 goto greater_branch; /* BGTZ */
724 default:
725 pc += 4;
726 }
727 }
728 else
729 pc += 4; /* Not a branch, next instruction is easy */
730 }
731 else
732 { /* This gets way messy */
733
734 /* Further subdivide into SPECIAL, REGIMM and other */
735 switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */
736 {
737 case 0: /* SPECIAL */
738 op = rtype_funct (inst);
739 switch (op)
740 {
741 case 8: /* JR */
742 case 9: /* JALR */
743 /* Set PC to that address */
744 pc = read_signed_register (rtype_rs (inst));
745 break;
746 default:
747 pc += 4;
748 }
749
750 break; /* end special */
751 case 1: /* REGIMM */
752 {
753 op = jtype_op (inst); /* branch condition */
754 switch (jtype_op (inst))
755 {
756 case 0: /* BLTZ */
757 case 2: /* BLTXL */
758 case 16: /* BLTZALL */
759 case 18: /* BLTZALL */
760 less_branch:
761 if (read_signed_register (itype_rs (inst)) < 0)
762 pc += mips32_relative_offset (inst) + 4;
763 else
764 pc += 8; /* after the delay slot */
765 break;
766 case 1: /* GEZ */
767 case 3: /* BGEZL */
768 case 17: /* BGEZAL */
769 case 19: /* BGEZALL */
770 greater_equal_branch:
771 if (read_signed_register (itype_rs (inst)) >= 0)
772 pc += mips32_relative_offset (inst) + 4;
773 else
774 pc += 8; /* after the delay slot */
775 break;
776 /* All of the other intructions in the REGIMM catagory */
777 default:
778 pc += 4;
779 }
780 }
781 break; /* end REGIMM */
782 case 2: /* J */
783 case 3: /* JAL */
784 {
785 unsigned long reg;
786 reg = jtype_target (inst) << 2;
787 pc = reg + ((pc + 4) & 0xf0000000);
788 /* Whats this mysterious 0xf000000 adjustment ??? */
789 }
790 break;
791 /* FIXME case JALX : */
792 {
793 unsigned long reg;
794 reg = jtype_target (inst) << 2;
795 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
796 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
797 }
798 break; /* The new PC will be alternate mode */
799 case 4: /* BEQ , BEQL */
800 equal_branch:
801 if (read_signed_register (itype_rs (inst)) ==
802 read_signed_register (itype_rt (inst)))
803 pc += mips32_relative_offset (inst) + 4;
804 else
805 pc += 8;
806 break;
807 case 5: /* BNE , BNEL */
808 neq_branch:
809 if (read_signed_register (itype_rs (inst)) !=
810 read_signed_register (itype_rs (inst)))
811 pc += mips32_relative_offset (inst) + 4;
812 else
813 pc += 8;
814 break;
815 case 6: /* BLEZ , BLEZL */
816 less_zero_branch:
817 if (read_signed_register (itype_rs (inst) <= 0))
818 pc += mips32_relative_offset (inst) + 4;
819 else
820 pc += 8;
821 break;
822 case 7:
823 greater_branch: /* BGTZ BGTZL */
824 if (read_signed_register (itype_rs (inst) > 0))
825 pc += mips32_relative_offset (inst) + 4;
826 else
827 pc += 8;
828 break;
829 default:
830 pc += 8;
831 } /* switch */
832 } /* else */
833 return pc;
834 } /* mips32_next_pc */
835
836 /* Decoding the next place to set a breakpoint is irregular for the
837 mips 16 variant, but fortunately, there fewer instructions. We have to cope
838 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
839 We dont want to set a single step instruction on the extend instruction
840 either.
841 */
842
843 /* Lots of mips16 instruction formats */
844 /* Predicting jumps requires itype,ritype,i8type
845 and their extensions extItype,extritype,extI8type
846 */
847 enum mips16_inst_fmts
848 {
849 itype, /* 0 immediate 5,10 */
850 ritype, /* 1 5,3,8 */
851 rrtype, /* 2 5,3,3,5 */
852 rritype, /* 3 5,3,3,5 */
853 rrrtype, /* 4 5,3,3,3,2 */
854 rriatype, /* 5 5,3,3,1,4 */
855 shifttype, /* 6 5,3,3,3,2 */
856 i8type, /* 7 5,3,8 */
857 i8movtype, /* 8 5,3,3,5 */
858 i8mov32rtype, /* 9 5,3,5,3 */
859 i64type, /* 10 5,3,8 */
860 ri64type, /* 11 5,3,3,5 */
861 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
862 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
863 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
864 extRRItype, /* 15 5,5,5,5,3,3,5 */
865 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
866 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
867 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
868 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
869 extRi64type, /* 20 5,6,5,5,3,3,5 */
870 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
871 };
872 /* I am heaping all the fields of the formats into one structure and
873 then, only the fields which are involved in instruction extension */
874 struct upk_mips16
875 {
876 CORE_ADDR offset;
877 unsigned int regx; /* Function in i8 type */
878 unsigned int regy;
879 };
880
881
882 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
883 for the bits which make up the immediatate extension. */
884
885 static CORE_ADDR
886 extended_offset (unsigned int extension)
887 {
888 CORE_ADDR value;
889 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
890 value = value << 6;
891 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
892 value = value << 5;
893 value |= extension & 0x01f; /* extract 4:0 */
894 return value;
895 }
896
897 /* Only call this function if you know that this is an extendable
898 instruction, It wont malfunction, but why make excess remote memory references?
899 If the immediate operands get sign extended or somthing, do it after
900 the extension is performed.
901 */
902 /* FIXME: Every one of these cases needs to worry about sign extension
903 when the offset is to be used in relative addressing */
904
905
906 static unsigned int
907 fetch_mips_16 (CORE_ADDR pc)
908 {
909 char buf[8];
910 pc &= 0xfffffffe; /* clear the low order bit */
911 target_read_memory (pc, buf, 2);
912 return extract_unsigned_integer (buf, 2);
913 }
914
915 static void
916 unpack_mips16 (CORE_ADDR pc,
917 unsigned int extension,
918 unsigned int inst,
919 enum mips16_inst_fmts insn_format,
920 struct upk_mips16 *upk)
921 {
922 CORE_ADDR offset;
923 int regx;
924 int regy;
925 switch (insn_format)
926 {
927 case itype:
928 {
929 CORE_ADDR value;
930 if (extension)
931 {
932 value = extended_offset (extension);
933 value = value << 11; /* rom for the original value */
934 value |= inst & 0x7ff; /* eleven bits from instruction */
935 }
936 else
937 {
938 value = inst & 0x7ff;
939 /* FIXME : Consider sign extension */
940 }
941 offset = value;
942 regx = -1;
943 regy = -1;
944 }
945 break;
946 case ritype:
947 case i8type:
948 { /* A register identifier and an offset */
949 /* Most of the fields are the same as I type but the
950 immediate value is of a different length */
951 CORE_ADDR value;
952 if (extension)
953 {
954 value = extended_offset (extension);
955 value = value << 8; /* from the original instruction */
956 value |= inst & 0xff; /* eleven bits from instruction */
957 regx = (extension >> 8) & 0x07; /* or i8 funct */
958 if (value & 0x4000) /* test the sign bit , bit 26 */
959 {
960 value &= ~0x3fff; /* remove the sign bit */
961 value = -value;
962 }
963 }
964 else
965 {
966 value = inst & 0xff; /* 8 bits */
967 regx = (inst >> 8) & 0x07; /* or i8 funct */
968 /* FIXME: Do sign extension , this format needs it */
969 if (value & 0x80) /* THIS CONFUSES ME */
970 {
971 value &= 0xef; /* remove the sign bit */
972 value = -value;
973 }
974 }
975 offset = value;
976 regy = -1;
977 break;
978 }
979 case jalxtype:
980 {
981 unsigned long value;
982 unsigned int nexthalf;
983 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
984 value = value << 16;
985 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
986 value |= nexthalf;
987 offset = value;
988 regx = -1;
989 regy = -1;
990 break;
991 }
992 default:
993 internal_error (__FILE__, __LINE__,
994 "bad switch");
995 }
996 upk->offset = offset;
997 upk->regx = regx;
998 upk->regy = regy;
999 }
1000
1001
1002 static CORE_ADDR
1003 add_offset_16 (CORE_ADDR pc, int offset)
1004 {
1005 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1006
1007 }
1008
1009 static CORE_ADDR
1010 extended_mips16_next_pc (CORE_ADDR pc,
1011 unsigned int extension,
1012 unsigned int insn)
1013 {
1014 int op = (insn >> 11);
1015 switch (op)
1016 {
1017 case 2: /* Branch */
1018 {
1019 CORE_ADDR offset;
1020 struct upk_mips16 upk;
1021 unpack_mips16 (pc, extension, insn, itype, &upk);
1022 offset = upk.offset;
1023 if (offset & 0x800)
1024 {
1025 offset &= 0xeff;
1026 offset = -offset;
1027 }
1028 pc += (offset << 1) + 2;
1029 break;
1030 }
1031 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1032 {
1033 struct upk_mips16 upk;
1034 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1035 pc = add_offset_16 (pc, upk.offset);
1036 if ((insn >> 10) & 0x01) /* Exchange mode */
1037 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1038 else
1039 pc |= 0x01;
1040 break;
1041 }
1042 case 4: /* beqz */
1043 {
1044 struct upk_mips16 upk;
1045 int reg;
1046 unpack_mips16 (pc, extension, insn, ritype, &upk);
1047 reg = read_signed_register (upk.regx);
1048 if (reg == 0)
1049 pc += (upk.offset << 1) + 2;
1050 else
1051 pc += 2;
1052 break;
1053 }
1054 case 5: /* bnez */
1055 {
1056 struct upk_mips16 upk;
1057 int reg;
1058 unpack_mips16 (pc, extension, insn, ritype, &upk);
1059 reg = read_signed_register (upk.regx);
1060 if (reg != 0)
1061 pc += (upk.offset << 1) + 2;
1062 else
1063 pc += 2;
1064 break;
1065 }
1066 case 12: /* I8 Formats btez btnez */
1067 {
1068 struct upk_mips16 upk;
1069 int reg;
1070 unpack_mips16 (pc, extension, insn, i8type, &upk);
1071 /* upk.regx contains the opcode */
1072 reg = read_signed_register (24); /* Test register is 24 */
1073 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1074 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1075 /* pc = add_offset_16(pc,upk.offset) ; */
1076 pc += (upk.offset << 1) + 2;
1077 else
1078 pc += 2;
1079 break;
1080 }
1081 case 29: /* RR Formats JR, JALR, JALR-RA */
1082 {
1083 struct upk_mips16 upk;
1084 /* upk.fmt = rrtype; */
1085 op = insn & 0x1f;
1086 if (op == 0)
1087 {
1088 int reg;
1089 upk.regx = (insn >> 8) & 0x07;
1090 upk.regy = (insn >> 5) & 0x07;
1091 switch (upk.regy)
1092 {
1093 case 0:
1094 reg = upk.regx;
1095 break;
1096 case 1:
1097 reg = 31;
1098 break; /* Function return instruction */
1099 case 2:
1100 reg = upk.regx;
1101 break;
1102 default:
1103 reg = 31;
1104 break; /* BOGUS Guess */
1105 }
1106 pc = read_signed_register (reg);
1107 }
1108 else
1109 pc += 2;
1110 break;
1111 }
1112 case 30:
1113 /* This is an instruction extension. Fetch the real instruction
1114 (which follows the extension) and decode things based on
1115 that. */
1116 {
1117 pc += 2;
1118 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1119 break;
1120 }
1121 default:
1122 {
1123 pc += 2;
1124 break;
1125 }
1126 }
1127 return pc;
1128 }
1129
1130 CORE_ADDR
1131 mips16_next_pc (CORE_ADDR pc)
1132 {
1133 unsigned int insn = fetch_mips_16 (pc);
1134 return extended_mips16_next_pc (pc, 0, insn);
1135 }
1136
1137 /* The mips_next_pc function supports single_step when the remote
1138 target monitor or stub is not developed enough to do a single_step.
1139 It works by decoding the current instruction and predicting where a
1140 branch will go. This isnt hard because all the data is available.
1141 The MIPS32 and MIPS16 variants are quite different */
1142 CORE_ADDR
1143 mips_next_pc (CORE_ADDR pc)
1144 {
1145 if (pc & 0x01)
1146 return mips16_next_pc (pc);
1147 else
1148 return mips32_next_pc (pc);
1149 }
1150
1151 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1152 NULL). */
1153
1154 void
1155 mips_find_saved_regs (struct frame_info *fci)
1156 {
1157 int ireg;
1158 CORE_ADDR reg_position;
1159 /* r0 bit means kernel trap */
1160 int kernel_trap;
1161 /* What registers have been saved? Bitmasks. */
1162 unsigned long gen_mask, float_mask;
1163 mips_extra_func_info_t proc_desc;
1164 t_inst inst;
1165
1166 frame_saved_regs_zalloc (fci);
1167
1168 /* If it is the frame for sigtramp, the saved registers are located
1169 in a sigcontext structure somewhere on the stack.
1170 If the stack layout for sigtramp changes we might have to change these
1171 constants and the companion fixup_sigtramp in mdebugread.c */
1172 #ifndef SIGFRAME_BASE
1173 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1174 above the sigtramp frame. */
1175 #define SIGFRAME_BASE MIPS_REGSIZE
1176 /* FIXME! Are these correct?? */
1177 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1178 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1179 #define SIGFRAME_FPREGSAVE_OFF \
1180 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1181 #endif
1182 #ifndef SIGFRAME_REG_SIZE
1183 /* FIXME! Is this correct?? */
1184 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1185 #endif
1186 if (fci->signal_handler_caller)
1187 {
1188 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1189 {
1190 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1191 + ireg * SIGFRAME_REG_SIZE;
1192 fci->saved_regs[ireg] = reg_position;
1193 }
1194 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1195 {
1196 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1197 + ireg * SIGFRAME_REG_SIZE;
1198 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1199 }
1200 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1201 return;
1202 }
1203
1204 proc_desc = fci->extra_info->proc_desc;
1205 if (proc_desc == NULL)
1206 /* I'm not sure how/whether this can happen. Normally when we can't
1207 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1208 and set the saved_regs right away. */
1209 return;
1210
1211 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1212 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1213 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1214
1215 if ( /* In any frame other than the innermost or a frame interrupted by
1216 a signal, we assume that all registers have been saved.
1217 This assumes that all register saves in a function happen before
1218 the first function call. */
1219 (fci->next == NULL || fci->next->signal_handler_caller)
1220
1221 /* In a dummy frame we know exactly where things are saved. */
1222 && !PROC_DESC_IS_DUMMY (proc_desc)
1223
1224 /* Don't bother unless we are inside a function prologue. Outside the
1225 prologue, we know where everything is. */
1226
1227 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
1228
1229 /* Not sure exactly what kernel_trap means, but if it means
1230 the kernel saves the registers without a prologue doing it,
1231 we better not examine the prologue to see whether registers
1232 have been saved yet. */
1233 && !kernel_trap)
1234 {
1235 /* We need to figure out whether the registers that the proc_desc
1236 claims are saved have been saved yet. */
1237
1238 CORE_ADDR addr;
1239
1240 /* Bitmasks; set if we have found a save for the register. */
1241 unsigned long gen_save_found = 0;
1242 unsigned long float_save_found = 0;
1243 int instlen;
1244
1245 /* If the address is odd, assume this is MIPS16 code. */
1246 addr = PROC_LOW_ADDR (proc_desc);
1247 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1248
1249 /* Scan through this function's instructions preceding the current
1250 PC, and look for those that save registers. */
1251 while (addr < fci->pc)
1252 {
1253 inst = mips_fetch_instruction (addr);
1254 if (pc_is_mips16 (addr))
1255 mips16_decode_reg_save (inst, &gen_save_found);
1256 else
1257 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1258 addr += instlen;
1259 }
1260 gen_mask = gen_save_found;
1261 float_mask = float_save_found;
1262 }
1263
1264 /* Fill in the offsets for the registers which gen_mask says
1265 were saved. */
1266 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1267 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1268 if (gen_mask & 0x80000000)
1269 {
1270 fci->saved_regs[ireg] = reg_position;
1271 reg_position -= MIPS_SAVED_REGSIZE;
1272 }
1273
1274 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1275 of that normally used by gcc. Therefore, we have to fetch the first
1276 instruction of the function, and if it's an entry instruction that
1277 saves $s0 or $s1, correct their saved addresses. */
1278 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1279 {
1280 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1281 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1282 {
1283 int reg;
1284 int sreg_count = (inst >> 6) & 3;
1285
1286 /* Check if the ra register was pushed on the stack. */
1287 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1288 if (inst & 0x20)
1289 reg_position -= MIPS_SAVED_REGSIZE;
1290
1291 /* Check if the s0 and s1 registers were pushed on the stack. */
1292 for (reg = 16; reg < sreg_count + 16; reg++)
1293 {
1294 fci->saved_regs[reg] = reg_position;
1295 reg_position -= MIPS_SAVED_REGSIZE;
1296 }
1297 }
1298 }
1299
1300 /* Fill in the offsets for the registers which float_mask says
1301 were saved. */
1302 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1303
1304 /* The freg_offset points to where the first *double* register
1305 is saved. So skip to the high-order word. */
1306 if (!GDB_TARGET_IS_MIPS64)
1307 reg_position += MIPS_SAVED_REGSIZE;
1308
1309 /* Fill in the offsets for the float registers which float_mask says
1310 were saved. */
1311 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1312 if (float_mask & 0x80000000)
1313 {
1314 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
1315 reg_position -= MIPS_SAVED_REGSIZE;
1316 }
1317
1318 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1319 }
1320
1321 static CORE_ADDR
1322 read_next_frame_reg (struct frame_info *fi, int regno)
1323 {
1324 for (; fi; fi = fi->next)
1325 {
1326 /* We have to get the saved sp from the sigcontext
1327 if it is a signal handler frame. */
1328 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1329 return fi->frame;
1330 else
1331 {
1332 if (fi->saved_regs == NULL)
1333 mips_find_saved_regs (fi);
1334 if (fi->saved_regs[regno])
1335 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
1336 }
1337 }
1338 return read_signed_register (regno);
1339 }
1340
1341 /* mips_addr_bits_remove - remove useless address bits */
1342
1343 CORE_ADDR
1344 mips_addr_bits_remove (CORE_ADDR addr)
1345 {
1346 if (GDB_TARGET_IS_MIPS64)
1347 {
1348 if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff))
1349 {
1350 /* This hack is a work-around for existing boards using
1351 PMON, the simulator, and any other 64-bit targets that
1352 doesn't have true 64-bit addressing. On these targets,
1353 the upper 32 bits of addresses are ignored by the
1354 hardware. Thus, the PC or SP are likely to have been
1355 sign extended to all 1s by instruction sequences that
1356 load 32-bit addresses. For example, a typical piece of
1357 code that loads an address is this:
1358 lui $r2, <upper 16 bits>
1359 ori $r2, <lower 16 bits>
1360 But the lui sign-extends the value such that the upper 32
1361 bits may be all 1s. The workaround is simply to mask off
1362 these bits. In the future, gcc may be changed to support
1363 true 64-bit addressing, and this masking will have to be
1364 disabled. */
1365 addr &= (CORE_ADDR) 0xffffffff;
1366 }
1367 }
1368 else if (mips_mask_address_p ())
1369 {
1370 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1371 masking off bits, instead, the actual target should be asking
1372 for the address to be converted to a valid pointer. */
1373 /* Even when GDB is configured for some 32-bit targets
1374 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1375 so CORE_ADDR is 64 bits. So we still have to mask off
1376 useless bits from addresses. */
1377 addr &= (CORE_ADDR) 0xffffffff;
1378 }
1379 return addr;
1380 }
1381
1382 void
1383 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1384 {
1385 CORE_ADDR pc, tmp;
1386
1387 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
1388 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
1389 tmp = mips_skip_stub (pc);
1390 prev->pc = tmp ? tmp : pc;
1391 }
1392
1393
1394 CORE_ADDR
1395 mips_frame_saved_pc (struct frame_info *frame)
1396 {
1397 CORE_ADDR saved_pc;
1398 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
1399 /* We have to get the saved pc from the sigcontext
1400 if it is a signal handler frame. */
1401 int pcreg = frame->signal_handler_caller ? PC_REGNUM
1402 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1403
1404 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1405 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1406 else
1407 saved_pc = read_next_frame_reg (frame, pcreg);
1408
1409 return ADDR_BITS_REMOVE (saved_pc);
1410 }
1411
1412 static struct mips_extra_func_info temp_proc_desc;
1413 static CORE_ADDR temp_saved_regs[NUM_REGS];
1414
1415 /* Set a register's saved stack address in temp_saved_regs. If an address
1416 has already been set for this register, do nothing; this way we will
1417 only recognize the first save of a given register in a function prologue.
1418 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1419
1420 static void
1421 set_reg_offset (int regno, CORE_ADDR offset)
1422 {
1423 if (temp_saved_regs[regno] == 0)
1424 temp_saved_regs[regno] = offset;
1425 }
1426
1427
1428 /* Test whether the PC points to the return instruction at the
1429 end of a function. */
1430
1431 static int
1432 mips_about_to_return (CORE_ADDR pc)
1433 {
1434 if (pc_is_mips16 (pc))
1435 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1436 generates a "jr $ra"; other times it generates code to load
1437 the return address from the stack to an accessible register (such
1438 as $a3), then a "jr" using that register. This second case
1439 is almost impossible to distinguish from an indirect jump
1440 used for switch statements, so we don't even try. */
1441 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1442 else
1443 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1444 }
1445
1446
1447 /* This fencepost looks highly suspicious to me. Removing it also
1448 seems suspicious as it could affect remote debugging across serial
1449 lines. */
1450
1451 static CORE_ADDR
1452 heuristic_proc_start (CORE_ADDR pc)
1453 {
1454 CORE_ADDR start_pc;
1455 CORE_ADDR fence;
1456 int instlen;
1457 int seen_adjsp = 0;
1458
1459 pc = ADDR_BITS_REMOVE (pc);
1460 start_pc = pc;
1461 fence = start_pc - heuristic_fence_post;
1462 if (start_pc == 0)
1463 return 0;
1464
1465 if (heuristic_fence_post == UINT_MAX
1466 || fence < VM_MIN_ADDRESS)
1467 fence = VM_MIN_ADDRESS;
1468
1469 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1470
1471 /* search back for previous return */
1472 for (start_pc -= instlen;; start_pc -= instlen)
1473 if (start_pc < fence)
1474 {
1475 /* It's not clear to me why we reach this point when
1476 stop_soon_quietly, but with this test, at least we
1477 don't print out warnings for every child forked (eg, on
1478 decstation). 22apr93 rich@cygnus.com. */
1479 if (!stop_soon_quietly)
1480 {
1481 static int blurb_printed = 0;
1482
1483 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1484 paddr_nz (pc));
1485
1486 if (!blurb_printed)
1487 {
1488 /* This actually happens frequently in embedded
1489 development, when you first connect to a board
1490 and your stack pointer and pc are nowhere in
1491 particular. This message needs to give people
1492 in that situation enough information to
1493 determine that it's no big deal. */
1494 printf_filtered ("\n\
1495 GDB is unable to find the start of the function at 0x%s\n\
1496 and thus can't determine the size of that function's stack frame.\n\
1497 This means that GDB may be unable to access that stack frame, or\n\
1498 the frames below it.\n\
1499 This problem is most likely caused by an invalid program counter or\n\
1500 stack pointer.\n\
1501 However, if you think GDB should simply search farther back\n\
1502 from 0x%s for code which looks like the beginning of a\n\
1503 function, you can increase the range of the search using the `set\n\
1504 heuristic-fence-post' command.\n",
1505 paddr_nz (pc), paddr_nz (pc));
1506 blurb_printed = 1;
1507 }
1508 }
1509
1510 return 0;
1511 }
1512 else if (pc_is_mips16 (start_pc))
1513 {
1514 unsigned short inst;
1515
1516 /* On MIPS16, any one of the following is likely to be the
1517 start of a function:
1518 entry
1519 addiu sp,-n
1520 daddiu sp,-n
1521 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1522 inst = mips_fetch_instruction (start_pc);
1523 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1524 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1525 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1526 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1527 break;
1528 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1529 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1530 seen_adjsp = 1;
1531 else
1532 seen_adjsp = 0;
1533 }
1534 else if (mips_about_to_return (start_pc))
1535 {
1536 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1537 break;
1538 }
1539
1540 return start_pc;
1541 }
1542
1543 /* Fetch the immediate value from a MIPS16 instruction.
1544 If the previous instruction was an EXTEND, use it to extend
1545 the upper bits of the immediate value. This is a helper function
1546 for mips16_heuristic_proc_desc. */
1547
1548 static int
1549 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1550 unsigned short inst, /* current instruction */
1551 int nbits, /* number of bits in imm field */
1552 int scale, /* scale factor to be applied to imm */
1553 int is_signed) /* is the imm field signed? */
1554 {
1555 int offset;
1556
1557 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1558 {
1559 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1560 if (offset & 0x8000) /* check for negative extend */
1561 offset = 0 - (0x10000 - (offset & 0xffff));
1562 return offset | (inst & 0x1f);
1563 }
1564 else
1565 {
1566 int max_imm = 1 << nbits;
1567 int mask = max_imm - 1;
1568 int sign_bit = max_imm >> 1;
1569
1570 offset = inst & mask;
1571 if (is_signed && (offset & sign_bit))
1572 offset = 0 - (max_imm - offset);
1573 return offset * scale;
1574 }
1575 }
1576
1577
1578 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1579 stream from start_pc to limit_pc. */
1580
1581 static void
1582 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1583 struct frame_info *next_frame, CORE_ADDR sp)
1584 {
1585 CORE_ADDR cur_pc;
1586 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1587 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1588 unsigned inst = 0; /* current instruction */
1589 unsigned entry_inst = 0; /* the entry instruction */
1590 int reg, offset;
1591
1592 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1593 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1594
1595 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1596 {
1597 /* Save the previous instruction. If it's an EXTEND, we'll extract
1598 the immediate offset extension from it in mips16_get_imm. */
1599 prev_inst = inst;
1600
1601 /* Fetch and decode the instruction. */
1602 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1603 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1604 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1605 {
1606 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1607 if (offset < 0) /* negative stack adjustment? */
1608 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
1609 else
1610 /* Exit loop if a positive stack adjustment is found, which
1611 usually means that the stack cleanup code in the function
1612 epilogue is reached. */
1613 break;
1614 }
1615 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1616 {
1617 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1618 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1619 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1620 set_reg_offset (reg, sp + offset);
1621 }
1622 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1623 {
1624 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1625 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1626 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
1627 set_reg_offset (reg, sp + offset);
1628 }
1629 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1630 {
1631 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1632 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1633 set_reg_offset (RA_REGNUM, sp + offset);
1634 }
1635 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1636 {
1637 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1638 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
1639 set_reg_offset (RA_REGNUM, sp + offset);
1640 }
1641 else if (inst == 0x673d) /* move $s1, $sp */
1642 {
1643 frame_addr = sp;
1644 PROC_FRAME_REG (&temp_proc_desc) = 17;
1645 }
1646 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1647 {
1648 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1649 frame_addr = sp + offset;
1650 PROC_FRAME_REG (&temp_proc_desc) = 17;
1651 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1652 }
1653 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1654 {
1655 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1656 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1657 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1658 set_reg_offset (reg, frame_addr + offset);
1659 }
1660 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1661 {
1662 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1663 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1664 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1665 set_reg_offset (reg, frame_addr + offset);
1666 }
1667 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1668 entry_inst = inst; /* save for later processing */
1669 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1670 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
1671 }
1672
1673 /* The entry instruction is typically the first instruction in a function,
1674 and it stores registers at offsets relative to the value of the old SP
1675 (before the prologue). But the value of the sp parameter to this
1676 function is the new SP (after the prologue has been executed). So we
1677 can't calculate those offsets until we've seen the entire prologue,
1678 and can calculate what the old SP must have been. */
1679 if (entry_inst != 0)
1680 {
1681 int areg_count = (entry_inst >> 8) & 7;
1682 int sreg_count = (entry_inst >> 6) & 3;
1683
1684 /* The entry instruction always subtracts 32 from the SP. */
1685 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
1686
1687 /* Now we can calculate what the SP must have been at the
1688 start of the function prologue. */
1689 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
1690
1691 /* Check if a0-a3 were saved in the caller's argument save area. */
1692 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1693 {
1694 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1695 set_reg_offset (reg, sp + offset);
1696 offset += MIPS_SAVED_REGSIZE;
1697 }
1698
1699 /* Check if the ra register was pushed on the stack. */
1700 offset = -4;
1701 if (entry_inst & 0x20)
1702 {
1703 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1704 set_reg_offset (RA_REGNUM, sp + offset);
1705 offset -= MIPS_SAVED_REGSIZE;
1706 }
1707
1708 /* Check if the s0 and s1 registers were pushed on the stack. */
1709 for (reg = 16; reg < sreg_count + 16; reg++)
1710 {
1711 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1712 set_reg_offset (reg, sp + offset);
1713 offset -= MIPS_SAVED_REGSIZE;
1714 }
1715 }
1716 }
1717
1718 static void
1719 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1720 struct frame_info *next_frame, CORE_ADDR sp)
1721 {
1722 CORE_ADDR cur_pc;
1723 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1724 restart:
1725 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1726 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
1727 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1728 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1729 {
1730 unsigned long inst, high_word, low_word;
1731 int reg;
1732
1733 /* Fetch the instruction. */
1734 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1735
1736 /* Save some code by pre-extracting some useful fields. */
1737 high_word = (inst >> 16) & 0xffff;
1738 low_word = inst & 0xffff;
1739 reg = high_word & 0x1f;
1740
1741 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1742 || high_word == 0x23bd /* addi $sp,$sp,-i */
1743 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1744 {
1745 if (low_word & 0x8000) /* negative stack adjustment? */
1746 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
1747 else
1748 /* Exit loop if a positive stack adjustment is found, which
1749 usually means that the stack cleanup code in the function
1750 epilogue is reached. */
1751 break;
1752 }
1753 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1754 {
1755 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1756 set_reg_offset (reg, sp + low_word);
1757 }
1758 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1759 {
1760 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1761 but the register size used is only 32 bits. Make the address
1762 for the saved register point to the lower 32 bits. */
1763 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1764 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1765 }
1766 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1767 {
1768 /* Old gcc frame, r30 is virtual frame pointer. */
1769 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1770 frame_addr = sp + low_word;
1771 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1772 {
1773 unsigned alloca_adjust;
1774 PROC_FRAME_REG (&temp_proc_desc) = 30;
1775 frame_addr = read_next_frame_reg (next_frame, 30);
1776 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1777 if (alloca_adjust > 0)
1778 {
1779 /* FP > SP + frame_size. This may be because
1780 * of an alloca or somethings similar.
1781 * Fix sp to "pre-alloca" value, and try again.
1782 */
1783 sp += alloca_adjust;
1784 goto restart;
1785 }
1786 }
1787 }
1788 /* move $30,$sp. With different versions of gas this will be either
1789 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1790 Accept any one of these. */
1791 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1792 {
1793 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1794 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1795 {
1796 unsigned alloca_adjust;
1797 PROC_FRAME_REG (&temp_proc_desc) = 30;
1798 frame_addr = read_next_frame_reg (next_frame, 30);
1799 alloca_adjust = (unsigned) (frame_addr - sp);
1800 if (alloca_adjust > 0)
1801 {
1802 /* FP > SP + frame_size. This may be because
1803 * of an alloca or somethings similar.
1804 * Fix sp to "pre-alloca" value, and try again.
1805 */
1806 sp += alloca_adjust;
1807 goto restart;
1808 }
1809 }
1810 }
1811 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1812 {
1813 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1814 set_reg_offset (reg, frame_addr + low_word);
1815 }
1816 }
1817 }
1818
1819 static mips_extra_func_info_t
1820 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1821 struct frame_info *next_frame)
1822 {
1823 CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM);
1824
1825 if (start_pc == 0)
1826 return NULL;
1827 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
1828 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
1829 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
1830 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
1831 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
1832
1833 if (start_pc + 200 < limit_pc)
1834 limit_pc = start_pc + 200;
1835 if (pc_is_mips16 (start_pc))
1836 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1837 else
1838 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1839 return &temp_proc_desc;
1840 }
1841
1842 static mips_extra_func_info_t
1843 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
1844 {
1845 CORE_ADDR startaddr;
1846 mips_extra_func_info_t proc_desc;
1847 struct block *b = block_for_pc (pc);
1848 struct symbol *sym;
1849
1850 find_pc_partial_function (pc, NULL, &startaddr, NULL);
1851 if (addrptr)
1852 *addrptr = startaddr;
1853 if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0))
1854 sym = NULL;
1855 else
1856 {
1857 if (startaddr > BLOCK_START (b))
1858 /* This is the "pathological" case referred to in a comment in
1859 print_frame_info. It might be better to move this check into
1860 symbol reading. */
1861 sym = NULL;
1862 else
1863 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
1864 }
1865
1866 /* If we never found a PDR for this function in symbol reading, then
1867 examine prologues to find the information. */
1868 if (sym)
1869 {
1870 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
1871 if (PROC_FRAME_REG (proc_desc) == -1)
1872 return NULL;
1873 else
1874 return proc_desc;
1875 }
1876 else
1877 return NULL;
1878 }
1879
1880
1881 static mips_extra_func_info_t
1882 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame)
1883 {
1884 mips_extra_func_info_t proc_desc;
1885 CORE_ADDR startaddr;
1886
1887 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
1888
1889 if (proc_desc)
1890 {
1891 /* IF this is the topmost frame AND
1892 * (this proc does not have debugging information OR
1893 * the PC is in the procedure prologue)
1894 * THEN create a "heuristic" proc_desc (by analyzing
1895 * the actual code) to replace the "official" proc_desc.
1896 */
1897 if (next_frame == NULL)
1898 {
1899 struct symtab_and_line val;
1900 struct symbol *proc_symbol =
1901 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
1902
1903 if (proc_symbol)
1904 {
1905 val = find_pc_line (BLOCK_START
1906 (SYMBOL_BLOCK_VALUE (proc_symbol)),
1907 0);
1908 val.pc = val.end ? val.end : pc;
1909 }
1910 if (!proc_symbol || pc < val.pc)
1911 {
1912 mips_extra_func_info_t found_heuristic =
1913 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
1914 pc, next_frame);
1915 if (found_heuristic)
1916 proc_desc = found_heuristic;
1917 }
1918 }
1919 }
1920 else
1921 {
1922 /* Is linked_proc_desc_table really necessary? It only seems to be used
1923 by procedure call dummys. However, the procedures being called ought
1924 to have their own proc_descs, and even if they don't,
1925 heuristic_proc_desc knows how to create them! */
1926
1927 register struct linked_proc_info *link;
1928
1929 for (link = linked_proc_desc_table; link; link = link->next)
1930 if (PROC_LOW_ADDR (&link->info) <= pc
1931 && PROC_HIGH_ADDR (&link->info) > pc)
1932 return &link->info;
1933
1934 if (startaddr == 0)
1935 startaddr = heuristic_proc_start (pc);
1936
1937 proc_desc =
1938 heuristic_proc_desc (startaddr, pc, next_frame);
1939 }
1940 return proc_desc;
1941 }
1942
1943 static CORE_ADDR
1944 get_frame_pointer (struct frame_info *frame,
1945 mips_extra_func_info_t proc_desc)
1946 {
1947 return ADDR_BITS_REMOVE (
1948 read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) +
1949 PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
1950 }
1951
1952 mips_extra_func_info_t cached_proc_desc;
1953
1954 CORE_ADDR
1955 mips_frame_chain (struct frame_info *frame)
1956 {
1957 mips_extra_func_info_t proc_desc;
1958 CORE_ADDR tmp;
1959 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
1960
1961 if (saved_pc == 0 || inside_entry_file (saved_pc))
1962 return 0;
1963
1964 /* Check if the PC is inside a call stub. If it is, fetch the
1965 PC of the caller of that stub. */
1966 if ((tmp = mips_skip_stub (saved_pc)) != 0)
1967 saved_pc = tmp;
1968
1969 /* Look up the procedure descriptor for this PC. */
1970 proc_desc = find_proc_desc (saved_pc, frame);
1971 if (!proc_desc)
1972 return 0;
1973
1974 cached_proc_desc = proc_desc;
1975
1976 /* If no frame pointer and frame size is zero, we must be at end
1977 of stack (or otherwise hosed). If we don't check frame size,
1978 we loop forever if we see a zero size frame. */
1979 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
1980 && PROC_FRAME_OFFSET (proc_desc) == 0
1981 /* The previous frame from a sigtramp frame might be frameless
1982 and have frame size zero. */
1983 && !frame->signal_handler_caller)
1984 return 0;
1985 else
1986 return get_frame_pointer (frame, proc_desc);
1987 }
1988
1989 void
1990 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
1991 {
1992 int regnum;
1993
1994 /* Use proc_desc calculated in frame_chain */
1995 mips_extra_func_info_t proc_desc =
1996 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next);
1997
1998 fci->extra_info = (struct frame_extra_info *)
1999 frame_obstack_alloc (sizeof (struct frame_extra_info));
2000
2001 fci->saved_regs = NULL;
2002 fci->extra_info->proc_desc =
2003 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2004 if (proc_desc)
2005 {
2006 /* Fixup frame-pointer - only needed for top frame */
2007 /* This may not be quite right, if proc has a real frame register.
2008 Get the value of the frame relative sp, procedure might have been
2009 interrupted by a signal at it's very start. */
2010 if (fci->pc == PROC_LOW_ADDR (proc_desc)
2011 && !PROC_DESC_IS_DUMMY (proc_desc))
2012 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
2013 else
2014 fci->frame = get_frame_pointer (fci->next, proc_desc);
2015
2016 if (proc_desc == &temp_proc_desc)
2017 {
2018 char *name;
2019
2020 /* Do not set the saved registers for a sigtramp frame,
2021 mips_find_saved_registers will do that for us.
2022 We can't use fci->signal_handler_caller, it is not yet set. */
2023 find_pc_partial_function (fci->pc, &name,
2024 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2025 if (!IN_SIGTRAMP (fci->pc, name))
2026 {
2027 frame_saved_regs_zalloc (fci);
2028 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2029 fci->saved_regs[PC_REGNUM]
2030 = fci->saved_regs[RA_REGNUM];
2031 }
2032 }
2033
2034 /* hack: if argument regs are saved, guess these contain args */
2035 /* assume we can't tell how many args for now */
2036 fci->extra_info->num_args = -1;
2037 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2038 {
2039 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2040 {
2041 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
2042 break;
2043 }
2044 }
2045 }
2046 }
2047
2048 /* MIPS stack frames are almost impenetrable. When execution stops,
2049 we basically have to look at symbol information for the function
2050 that we stopped in, which tells us *which* register (if any) is
2051 the base of the frame pointer, and what offset from that register
2052 the frame itself is at.
2053
2054 This presents a problem when trying to examine a stack in memory
2055 (that isn't executing at the moment), using the "frame" command. We
2056 don't have a PC, nor do we have any registers except SP.
2057
2058 This routine takes two arguments, SP and PC, and tries to make the
2059 cached frames look as if these two arguments defined a frame on the
2060 cache. This allows the rest of info frame to extract the important
2061 arguments without difficulty. */
2062
2063 struct frame_info *
2064 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2065 {
2066 if (argc != 2)
2067 error ("MIPS frame specifications require two arguments: sp and pc");
2068
2069 return create_new_frame (argv[0], argv[1]);
2070 }
2071
2072 /* According to the current ABI, should the type be passed in a
2073 floating-point register (assuming that there is space)? When there
2074 is no FPU, FP are not even considered as possibile candidates for
2075 FP registers and, consequently this returns false - forces FP
2076 arguments into integer registers. */
2077
2078 static int
2079 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2080 {
2081 return ((typecode == TYPE_CODE_FLT
2082 || (MIPS_EABI
2083 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2084 && TYPE_NFIELDS (arg_type) == 1
2085 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2086 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2087 }
2088
2089 CORE_ADDR
2090 mips_push_arguments (int nargs,
2091 value_ptr *args,
2092 CORE_ADDR sp,
2093 int struct_return,
2094 CORE_ADDR struct_addr)
2095 {
2096 int argreg;
2097 int float_argreg;
2098 int argnum;
2099 int len = 0;
2100 int stack_offset = 0;
2101
2102 /* Macros to round N up or down to the next A boundary; A must be
2103 a power of two. */
2104 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2105 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2106
2107 /* First ensure that the stack and structure return address (if any)
2108 are properly aligned. The stack has to be at least 64-bit aligned
2109 even on 32-bit machines, because doubles must be 64-bit aligned.
2110 On at least one MIPS variant, stack frames need to be 128-bit
2111 aligned, so we round to this widest known alignment. */
2112 sp = ROUND_DOWN (sp, 16);
2113 struct_addr = ROUND_DOWN (struct_addr, 16);
2114
2115 /* Now make space on the stack for the args. We allocate more
2116 than necessary for EABI, because the first few arguments are
2117 passed in registers, but that's OK. */
2118 for (argnum = 0; argnum < nargs; argnum++)
2119 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_STACK_ARGSIZE);
2120 sp -= ROUND_UP (len, 16);
2121
2122 if (mips_debug)
2123 fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
2124 (long) sp, ROUND_UP (len, 16));
2125
2126 /* Initialize the integer and float register pointers. */
2127 argreg = A0_REGNUM;
2128 float_argreg = FPA0_REGNUM;
2129
2130 /* the struct_return pointer occupies the first parameter-passing reg */
2131 if (struct_return)
2132 {
2133 if (mips_debug)
2134 fprintf_unfiltered (gdb_stdlog,
2135 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2136 argreg, (long) struct_addr);
2137 write_register (argreg++, struct_addr);
2138 if (MIPS_REGS_HAVE_HOME_P)
2139 stack_offset += MIPS_STACK_ARGSIZE;
2140 }
2141
2142 /* Now load as many as possible of the first arguments into
2143 registers, and push the rest onto the stack. Loop thru args
2144 from first to last. */
2145 for (argnum = 0; argnum < nargs; argnum++)
2146 {
2147 char *val;
2148 char valbuf[MAX_REGISTER_RAW_SIZE];
2149 value_ptr arg = args[argnum];
2150 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2151 int len = TYPE_LENGTH (arg_type);
2152 enum type_code typecode = TYPE_CODE (arg_type);
2153
2154 if (mips_debug)
2155 fprintf_unfiltered (gdb_stdlog,
2156 "mips_push_arguments: %d len=%d type=%d",
2157 argnum + 1, len, (int) typecode);
2158
2159 /* The EABI passes structures that do not fit in a register by
2160 reference. In all other cases, pass the structure by value. */
2161 if (MIPS_EABI
2162 && len > MIPS_SAVED_REGSIZE
2163 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2164 {
2165 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2166 typecode = TYPE_CODE_PTR;
2167 len = MIPS_SAVED_REGSIZE;
2168 val = valbuf;
2169 if (mips_debug)
2170 fprintf_unfiltered (gdb_stdlog, " push");
2171 }
2172 else
2173 val = (char *) VALUE_CONTENTS (arg);
2174
2175 /* 32-bit ABIs always start floating point arguments in an
2176 even-numbered floating point register. Round the FP register
2177 up before the check to see if there are any FP registers
2178 left. Non MIPS_EABI targets also pass the FP in the integer
2179 registers so also round up normal registers. */
2180 if (!FP_REGISTER_DOUBLE
2181 && fp_register_arg_p (typecode, arg_type))
2182 {
2183 if ((float_argreg & 1))
2184 float_argreg++;
2185 }
2186
2187 /* Floating point arguments passed in registers have to be
2188 treated specially. On 32-bit architectures, doubles
2189 are passed in register pairs; the even register gets
2190 the low word, and the odd register gets the high word.
2191 On non-EABI processors, the first two floating point arguments are
2192 also copied to general registers, because MIPS16 functions
2193 don't use float registers for arguments. This duplication of
2194 arguments in general registers can't hurt non-MIPS16 functions
2195 because those registers are normally skipped. */
2196 /* MIPS_EABI squeeses a struct that contains a single floating
2197 point value into an FP register instead of pusing it onto the
2198 stack. */
2199 if (fp_register_arg_p (typecode, arg_type)
2200 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2201 {
2202 if (!FP_REGISTER_DOUBLE && len == 8)
2203 {
2204 int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
2205 unsigned long regval;
2206
2207 /* Write the low word of the double to the even register(s). */
2208 regval = extract_unsigned_integer (val + low_offset, 4);
2209 if (mips_debug)
2210 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2211 float_argreg, phex (regval, 4));
2212 write_register (float_argreg++, regval);
2213 if (!MIPS_EABI)
2214 {
2215 if (mips_debug)
2216 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2217 argreg, phex (regval, 4));
2218 write_register (argreg++, regval);
2219 }
2220
2221 /* Write the high word of the double to the odd register(s). */
2222 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2223 if (mips_debug)
2224 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2225 float_argreg, phex (regval, 4));
2226 write_register (float_argreg++, regval);
2227 if (!MIPS_EABI)
2228 {
2229 if (mips_debug)
2230 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2231 argreg, phex (regval, 4));
2232 write_register (argreg++, regval);
2233 }
2234
2235 }
2236 else
2237 {
2238 /* This is a floating point value that fits entirely
2239 in a single register. */
2240 /* On 32 bit ABI's the float_argreg is further adjusted
2241 above to ensure that it is even register aligned. */
2242 LONGEST regval = extract_unsigned_integer (val, len);
2243 if (mips_debug)
2244 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2245 float_argreg, phex (regval, len));
2246 write_register (float_argreg++, regval);
2247 if (!MIPS_EABI)
2248 {
2249 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2250 registers for each argument. The below is (my
2251 guess) to ensure that the corresponding integer
2252 register has reserved the same space. */
2253 if (mips_debug)
2254 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2255 argreg, phex (regval, len));
2256 write_register (argreg, regval);
2257 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
2258 }
2259 }
2260 /* Reserve space for the FP register. */
2261 if (MIPS_REGS_HAVE_HOME_P)
2262 stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE);
2263 }
2264 else
2265 {
2266 /* Copy the argument to general registers or the stack in
2267 register-sized pieces. Large arguments are split between
2268 registers and stack. */
2269 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2270 are treated specially: Irix cc passes them in registers
2271 where gcc sometimes puts them on the stack. For maximum
2272 compatibility, we will put them in both places. */
2273 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2274 (len % MIPS_SAVED_REGSIZE != 0));
2275 /* Note: Floating-point values that didn't fit into an FP
2276 register are only written to memory. */
2277 while (len > 0)
2278 {
2279 /* Rememer if the argument was written to the stack. */
2280 int stack_used_p = 0;
2281 int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2282
2283 if (mips_debug)
2284 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2285 partial_len);
2286
2287 /* Write this portion of the argument to the stack. */
2288 if (argreg > MIPS_LAST_ARG_REGNUM
2289 || odd_sized_struct
2290 || fp_register_arg_p (typecode, arg_type))
2291 {
2292 /* Should shorter than int integer values be
2293 promoted to int before being stored? */
2294 int longword_offset = 0;
2295 CORE_ADDR addr;
2296 stack_used_p = 1;
2297 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
2298 {
2299 if (MIPS_STACK_ARGSIZE == 8 &&
2300 (typecode == TYPE_CODE_INT ||
2301 typecode == TYPE_CODE_PTR ||
2302 typecode == TYPE_CODE_FLT) && len <= 4)
2303 longword_offset = MIPS_STACK_ARGSIZE - len;
2304 else if ((typecode == TYPE_CODE_STRUCT ||
2305 typecode == TYPE_CODE_UNION) &&
2306 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2307 longword_offset = MIPS_STACK_ARGSIZE - len;
2308 }
2309
2310 if (mips_debug)
2311 {
2312 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%lx",
2313 (long) stack_offset);
2314 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
2315 (long) longword_offset);
2316 }
2317
2318 addr = sp + stack_offset + longword_offset;
2319
2320 if (mips_debug)
2321 {
2322 int i;
2323 fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
2324 for (i = 0; i < partial_len; i++)
2325 {
2326 fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
2327 }
2328 }
2329 write_memory (addr, val, partial_len);
2330 }
2331
2332 /* Note!!! This is NOT an else clause. Odd sized
2333 structs may go thru BOTH paths. Floating point
2334 arguments will not. */
2335 /* Write this portion of the argument to a general
2336 purpose register. */
2337 if (argreg <= MIPS_LAST_ARG_REGNUM
2338 && !fp_register_arg_p (typecode, arg_type))
2339 {
2340 LONGEST regval = extract_unsigned_integer (val, partial_len);
2341
2342 /* A non-floating-point argument being passed in a
2343 general register. If a struct or union, and if
2344 the remaining length is smaller than the register
2345 size, we have to adjust the register value on
2346 big endian targets.
2347
2348 It does not seem to be necessary to do the
2349 same for integral types.
2350
2351 Also don't do this adjustment on EABI and O64
2352 binaries. */
2353
2354 if (!MIPS_EABI
2355 && MIPS_SAVED_REGSIZE < 8
2356 && TARGET_BYTE_ORDER == BIG_ENDIAN
2357 && partial_len < MIPS_SAVED_REGSIZE
2358 && (typecode == TYPE_CODE_STRUCT ||
2359 typecode == TYPE_CODE_UNION))
2360 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
2361 TARGET_CHAR_BIT);
2362
2363 if (mips_debug)
2364 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2365 argreg,
2366 phex (regval, MIPS_SAVED_REGSIZE));
2367 write_register (argreg, regval);
2368 argreg++;
2369
2370 /* If this is the old ABI, prevent subsequent floating
2371 point arguments from being passed in floating point
2372 registers. */
2373 if (!MIPS_EABI)
2374 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
2375 }
2376
2377 len -= partial_len;
2378 val += partial_len;
2379
2380 /* Compute the the offset into the stack at which we
2381 will copy the next parameter.
2382
2383 In older ABIs, the caller reserved space for
2384 registers that contained arguments. This was loosely
2385 refered to as their "home". Consequently, space is
2386 always allocated.
2387
2388 In the new EABI (and the NABI32), the stack_offset
2389 only needs to be adjusted when it has been used.. */
2390
2391 if (MIPS_REGS_HAVE_HOME_P || stack_used_p)
2392 stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
2393 }
2394 }
2395 if (mips_debug)
2396 fprintf_unfiltered (gdb_stdlog, "\n");
2397 }
2398
2399 /* Return adjusted stack pointer. */
2400 return sp;
2401 }
2402
2403 CORE_ADDR
2404 mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2405 {
2406 /* Set the return address register to point to the entry
2407 point of the program, where a breakpoint lies in wait. */
2408 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
2409 return sp;
2410 }
2411
2412 static void
2413 mips_push_register (CORE_ADDR * sp, int regno)
2414 {
2415 char buffer[MAX_REGISTER_RAW_SIZE];
2416 int regsize;
2417 int offset;
2418 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
2419 {
2420 regsize = MIPS_SAVED_REGSIZE;
2421 offset = (TARGET_BYTE_ORDER == BIG_ENDIAN
2422 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
2423 : 0);
2424 }
2425 else
2426 {
2427 regsize = REGISTER_RAW_SIZE (regno);
2428 offset = 0;
2429 }
2430 *sp -= regsize;
2431 read_register_gen (regno, buffer);
2432 write_memory (*sp, buffer + offset, regsize);
2433 }
2434
2435 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2436 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2437
2438 void
2439 mips_push_dummy_frame (void)
2440 {
2441 int ireg;
2442 struct linked_proc_info *link = (struct linked_proc_info *)
2443 xmalloc (sizeof (struct linked_proc_info));
2444 mips_extra_func_info_t proc_desc = &link->info;
2445 CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
2446 CORE_ADDR old_sp = sp;
2447 link->next = linked_proc_desc_table;
2448 linked_proc_desc_table = link;
2449
2450 /* FIXME! are these correct ? */
2451 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2452 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2453 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2454 #define FLOAT_SINGLE_REG_SAVE_MASK \
2455 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2456 /*
2457 * The registers we must save are all those not preserved across
2458 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2459 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2460 * and FP Control/Status registers.
2461 *
2462 *
2463 * Dummy frame layout:
2464 * (high memory)
2465 * Saved PC
2466 * Saved MMHI, MMLO, FPC_CSR
2467 * Saved R31
2468 * Saved R28
2469 * ...
2470 * Saved R1
2471 * Saved D18 (i.e. F19, F18)
2472 * ...
2473 * Saved D0 (i.e. F1, F0)
2474 * Argument build area and stack arguments written via mips_push_arguments
2475 * (low memory)
2476 */
2477
2478 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2479 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
2480 PROC_FRAME_OFFSET (proc_desc) = 0;
2481 PROC_FRAME_ADJUST (proc_desc) = 0;
2482 mips_push_register (&sp, PC_REGNUM);
2483 mips_push_register (&sp, HI_REGNUM);
2484 mips_push_register (&sp, LO_REGNUM);
2485 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
2486
2487 /* Save general CPU registers */
2488 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
2489 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2490 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
2491 for (ireg = 32; --ireg >= 0;)
2492 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
2493 mips_push_register (&sp, ireg);
2494
2495 /* Save floating point registers starting with high order word */
2496 PROC_FREG_MASK (proc_desc) =
2497 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
2498 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
2499 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2500 from FP. */
2501 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
2502 for (ireg = 32; --ireg >= 0;)
2503 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
2504 mips_push_register (&sp, ireg + FP0_REGNUM);
2505
2506 /* Update the frame pointer for the call dummy and the stack pointer.
2507 Set the procedure's starting and ending addresses to point to the
2508 call dummy address at the entry point. */
2509 write_register (PUSH_FP_REGNUM, old_sp);
2510 write_register (SP_REGNUM, sp);
2511 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
2512 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
2513 SET_PROC_DESC_IS_DUMMY (proc_desc);
2514 PROC_PC_REG (proc_desc) = RA_REGNUM;
2515 }
2516
2517 void
2518 mips_pop_frame (void)
2519 {
2520 register int regnum;
2521 struct frame_info *frame = get_current_frame ();
2522 CORE_ADDR new_sp = FRAME_FP (frame);
2523
2524 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
2525
2526 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
2527 if (frame->saved_regs == NULL)
2528 mips_find_saved_regs (frame);
2529 for (regnum = 0; regnum < NUM_REGS; regnum++)
2530 {
2531 if (regnum != SP_REGNUM && regnum != PC_REGNUM
2532 && frame->saved_regs[regnum])
2533 write_register (regnum,
2534 read_memory_integer (frame->saved_regs[regnum],
2535 MIPS_SAVED_REGSIZE));
2536 }
2537 write_register (SP_REGNUM, new_sp);
2538 flush_cached_frames ();
2539
2540 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
2541 {
2542 struct linked_proc_info *pi_ptr, *prev_ptr;
2543
2544 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
2545 pi_ptr != NULL;
2546 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
2547 {
2548 if (&pi_ptr->info == proc_desc)
2549 break;
2550 }
2551
2552 if (pi_ptr == NULL)
2553 error ("Can't locate dummy extra frame info\n");
2554
2555 if (prev_ptr != NULL)
2556 prev_ptr->next = pi_ptr->next;
2557 else
2558 linked_proc_desc_table = pi_ptr->next;
2559
2560 xfree (pi_ptr);
2561
2562 write_register (HI_REGNUM,
2563 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
2564 MIPS_SAVED_REGSIZE));
2565 write_register (LO_REGNUM,
2566 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
2567 MIPS_SAVED_REGSIZE));
2568 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
2569 write_register (FCRCS_REGNUM,
2570 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
2571 MIPS_SAVED_REGSIZE));
2572 }
2573 }
2574
2575 static void
2576 mips_print_register (int regnum, int all)
2577 {
2578 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2579
2580 /* Get the data in raw format. */
2581 if (read_relative_register_raw_bytes (regnum, raw_buffer))
2582 {
2583 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
2584 return;
2585 }
2586
2587 /* If an even floating point register, also print as double. */
2588 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
2589 && !((regnum - FP0_REGNUM) & 1))
2590 if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2591 {
2592 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
2593
2594 read_relative_register_raw_bytes (regnum, dbuffer);
2595 read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE);
2596 REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer);
2597
2598 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
2599 val_print (builtin_type_double, dbuffer, 0, 0,
2600 gdb_stdout, 0, 1, 0, Val_pretty_default);
2601 printf_filtered ("); ");
2602 }
2603 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
2604
2605 /* The problem with printing numeric register names (r26, etc.) is that
2606 the user can't use them on input. Probably the best solution is to
2607 fix it so that either the numeric or the funky (a2, etc.) names
2608 are accepted on input. */
2609 if (regnum < MIPS_NUMREGS)
2610 printf_filtered ("(r%d): ", regnum);
2611 else
2612 printf_filtered (": ");
2613
2614 /* If virtual format is floating, print it that way. */
2615 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2616 if (FP_REGISTER_DOUBLE)
2617 { /* show 8-byte floats as float AND double: */
2618 int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
2619
2620 printf_filtered (" (float) ");
2621 val_print (builtin_type_float, raw_buffer + offset, 0, 0,
2622 gdb_stdout, 0, 1, 0, Val_pretty_default);
2623 printf_filtered (", (double) ");
2624 val_print (builtin_type_double, raw_buffer, 0, 0,
2625 gdb_stdout, 0, 1, 0, Val_pretty_default);
2626 }
2627 else
2628 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
2629 gdb_stdout, 0, 1, 0, Val_pretty_default);
2630 /* Else print as integer in hex. */
2631 else
2632 {
2633 int offset;
2634
2635 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
2636 offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
2637 else
2638 offset = 0;
2639
2640 print_scalar_formatted (raw_buffer + offset,
2641 REGISTER_VIRTUAL_TYPE (regnum),
2642 'x', 0, gdb_stdout);
2643 }
2644 }
2645
2646 /* Replacement for generic do_registers_info.
2647 Print regs in pretty columns. */
2648
2649 static int
2650 do_fp_register_row (int regnum)
2651 { /* do values for FP (float) regs */
2652 char *raw_buffer[2];
2653 char *dbl_buffer;
2654 /* use HI and LO to control the order of combining two flt regs */
2655 int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN);
2656 int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN);
2657 double doub, flt1, flt2; /* doubles extracted from raw hex data */
2658 int inv1, inv2, inv3;
2659
2660 raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
2661 raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
2662 dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
2663
2664 /* Get the data in raw format. */
2665 if (read_relative_register_raw_bytes (regnum, raw_buffer[HI]))
2666 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2667 if (REGISTER_RAW_SIZE (regnum) == 4)
2668 {
2669 /* 4-byte registers: we can fit two registers per row. */
2670 /* Also print every pair of 4-byte regs as an 8-byte double. */
2671 if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO]))
2672 error ("can't read register %d (%s)",
2673 regnum + 1, REGISTER_NAME (regnum + 1));
2674
2675 /* copy the two floats into one double, and unpack both */
2676 memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
2677 flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1);
2678 flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2);
2679 doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
2680
2681 printf_filtered (" %-5s", REGISTER_NAME (regnum));
2682 if (inv1)
2683 printf_filtered (": <invalid float>");
2684 else
2685 printf_filtered ("%-17.9g", flt1);
2686
2687 printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
2688 if (inv2)
2689 printf_filtered (": <invalid float>");
2690 else
2691 printf_filtered ("%-17.9g", flt2);
2692
2693 printf_filtered (" dbl: ");
2694 if (inv3)
2695 printf_filtered ("<invalid double>");
2696 else
2697 printf_filtered ("%-24.17g", doub);
2698 printf_filtered ("\n");
2699
2700 /* may want to do hex display here (future enhancement) */
2701 regnum += 2;
2702 }
2703 else
2704 { /* eight byte registers: print each one as float AND as double. */
2705 int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
2706
2707 memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
2708 flt1 = unpack_double (builtin_type_float,
2709 &raw_buffer[HI][offset], &inv1);
2710 doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
2711
2712 printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
2713 if (inv1)
2714 printf_filtered ("<invalid float>");
2715 else
2716 printf_filtered ("flt: %-17.9g", flt1);
2717
2718 printf_filtered (" dbl: ");
2719 if (inv3)
2720 printf_filtered ("<invalid double>");
2721 else
2722 printf_filtered ("%-24.17g", doub);
2723
2724 printf_filtered ("\n");
2725 /* may want to do hex display here (future enhancement) */
2726 regnum++;
2727 }
2728 return regnum;
2729 }
2730
2731 /* Print a row's worth of GP (int) registers, with name labels above */
2732
2733 static int
2734 do_gp_register_row (int regnum)
2735 {
2736 /* do values for GP (int) regs */
2737 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2738 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
2739 int col, byte;
2740 int start_regnum = regnum;
2741 int numregs = NUM_REGS;
2742
2743
2744 /* For GP registers, we print a separate row of names above the vals */
2745 printf_filtered (" ");
2746 for (col = 0; col < ncols && regnum < numregs; regnum++)
2747 {
2748 if (*REGISTER_NAME (regnum) == '\0')
2749 continue; /* unused register */
2750 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2751 break; /* end the row: reached FP register */
2752 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
2753 REGISTER_NAME (regnum));
2754 col++;
2755 }
2756 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
2757 start_regnum); /* print the R0 to R31 names */
2758
2759 regnum = start_regnum; /* go back to start of row */
2760 /* now print the values in hex, 4 or 8 to the row */
2761 for (col = 0; col < ncols && regnum < numregs; regnum++)
2762 {
2763 if (*REGISTER_NAME (regnum) == '\0')
2764 continue; /* unused register */
2765 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2766 break; /* end row: reached FP register */
2767 /* OK: get the data in raw format. */
2768 if (read_relative_register_raw_bytes (regnum, raw_buffer))
2769 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2770 /* pad small registers */
2771 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
2772 printf_filtered (" ");
2773 /* Now print the register value in hex, endian order. */
2774 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
2775 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
2776 byte < REGISTER_RAW_SIZE (regnum);
2777 byte++)
2778 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
2779 else
2780 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
2781 byte >= 0;
2782 byte--)
2783 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
2784 printf_filtered (" ");
2785 col++;
2786 }
2787 if (col > 0) /* ie. if we actually printed anything... */
2788 printf_filtered ("\n");
2789
2790 return regnum;
2791 }
2792
2793 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2794
2795 void
2796 mips_do_registers_info (int regnum, int fpregs)
2797 {
2798 if (regnum != -1) /* do one specified register */
2799 {
2800 if (*(REGISTER_NAME (regnum)) == '\0')
2801 error ("Not a valid register for the current processor type");
2802
2803 mips_print_register (regnum, 0);
2804 printf_filtered ("\n");
2805 }
2806 else
2807 /* do all (or most) registers */
2808 {
2809 regnum = 0;
2810 while (regnum < NUM_REGS)
2811 {
2812 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2813 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
2814 regnum = do_fp_register_row (regnum); /* FP regs */
2815 else
2816 regnum += MIPS_NUMREGS; /* skip floating point regs */
2817 else
2818 regnum = do_gp_register_row (regnum); /* GP (int) regs */
2819 }
2820 }
2821 }
2822
2823 /* Return number of args passed to a frame. described by FIP.
2824 Can return -1, meaning no way to tell. */
2825
2826 int
2827 mips_frame_num_args (struct frame_info *frame)
2828 {
2829 return -1;
2830 }
2831
2832 /* Is this a branch with a delay slot? */
2833
2834 static int is_delayed (unsigned long);
2835
2836 static int
2837 is_delayed (unsigned long insn)
2838 {
2839 int i;
2840 for (i = 0; i < NUMOPCODES; ++i)
2841 if (mips_opcodes[i].pinfo != INSN_MACRO
2842 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
2843 break;
2844 return (i < NUMOPCODES
2845 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
2846 | INSN_COND_BRANCH_DELAY
2847 | INSN_COND_BRANCH_LIKELY)));
2848 }
2849
2850 int
2851 mips_step_skips_delay (CORE_ADDR pc)
2852 {
2853 char buf[MIPS_INSTLEN];
2854
2855 /* There is no branch delay slot on MIPS16. */
2856 if (pc_is_mips16 (pc))
2857 return 0;
2858
2859 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
2860 /* If error reading memory, guess that it is not a delayed branch. */
2861 return 0;
2862 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
2863 }
2864
2865
2866 /* Skip the PC past function prologue instructions (32-bit version).
2867 This is a helper function for mips_skip_prologue. */
2868
2869 static CORE_ADDR
2870 mips32_skip_prologue (CORE_ADDR pc)
2871 {
2872 t_inst inst;
2873 CORE_ADDR end_pc;
2874 int seen_sp_adjust = 0;
2875 int load_immediate_bytes = 0;
2876
2877 /* Skip the typical prologue instructions. These are the stack adjustment
2878 instruction and the instructions that save registers on the stack
2879 or in the gcc frame. */
2880 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
2881 {
2882 unsigned long high_word;
2883
2884 inst = mips_fetch_instruction (pc);
2885 high_word = (inst >> 16) & 0xffff;
2886
2887 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
2888 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
2889 seen_sp_adjust = 1;
2890 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
2891 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
2892 seen_sp_adjust = 1;
2893 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2894 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2895 && (inst & 0x001F0000)) /* reg != $zero */
2896 continue;
2897
2898 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2899 continue;
2900 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
2901 /* sx reg,n($s8) */
2902 continue; /* reg != $zero */
2903
2904 /* move $s8,$sp. With different versions of gas this will be either
2905 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2906 Accept any one of these. */
2907 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2908 continue;
2909
2910 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2911 continue;
2912 else if (high_word == 0x3c1c) /* lui $gp,n */
2913 continue;
2914 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
2915 continue;
2916 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2917 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
2918 continue;
2919 /* The following instructions load $at or $t0 with an immediate
2920 value in preparation for a stack adjustment via
2921 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2922 a local variable, so we accept them only before a stack adjustment
2923 instruction was seen. */
2924 else if (!seen_sp_adjust)
2925 {
2926 if (high_word == 0x3c01 || /* lui $at,n */
2927 high_word == 0x3c08) /* lui $t0,n */
2928 {
2929 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
2930 continue;
2931 }
2932 else if (high_word == 0x3421 || /* ori $at,$at,n */
2933 high_word == 0x3508 || /* ori $t0,$t0,n */
2934 high_word == 0x3401 || /* ori $at,$zero,n */
2935 high_word == 0x3408) /* ori $t0,$zero,n */
2936 {
2937 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
2938 continue;
2939 }
2940 else
2941 break;
2942 }
2943 else
2944 break;
2945 }
2946
2947 /* In a frameless function, we might have incorrectly
2948 skipped some load immediate instructions. Undo the skipping
2949 if the load immediate was not followed by a stack adjustment. */
2950 if (load_immediate_bytes && !seen_sp_adjust)
2951 pc -= load_immediate_bytes;
2952 return pc;
2953 }
2954
2955 /* Skip the PC past function prologue instructions (16-bit version).
2956 This is a helper function for mips_skip_prologue. */
2957
2958 static CORE_ADDR
2959 mips16_skip_prologue (CORE_ADDR pc)
2960 {
2961 CORE_ADDR end_pc;
2962 int extend_bytes = 0;
2963 int prev_extend_bytes;
2964
2965 /* Table of instructions likely to be found in a function prologue. */
2966 static struct
2967 {
2968 unsigned short inst;
2969 unsigned short mask;
2970 }
2971 table[] =
2972 {
2973 {
2974 0x6300, 0xff00
2975 }
2976 , /* addiu $sp,offset */
2977 {
2978 0xfb00, 0xff00
2979 }
2980 , /* daddiu $sp,offset */
2981 {
2982 0xd000, 0xf800
2983 }
2984 , /* sw reg,n($sp) */
2985 {
2986 0xf900, 0xff00
2987 }
2988 , /* sd reg,n($sp) */
2989 {
2990 0x6200, 0xff00
2991 }
2992 , /* sw $ra,n($sp) */
2993 {
2994 0xfa00, 0xff00
2995 }
2996 , /* sd $ra,n($sp) */
2997 {
2998 0x673d, 0xffff
2999 }
3000 , /* move $s1,sp */
3001 {
3002 0xd980, 0xff80
3003 }
3004 , /* sw $a0-$a3,n($s1) */
3005 {
3006 0x6704, 0xff1c
3007 }
3008 , /* move reg,$a0-$a3 */
3009 {
3010 0xe809, 0xf81f
3011 }
3012 , /* entry pseudo-op */
3013 {
3014 0x0100, 0xff00
3015 }
3016 , /* addiu $s1,$sp,n */
3017 {
3018 0, 0
3019 } /* end of table marker */
3020 };
3021
3022 /* Skip the typical prologue instructions. These are the stack adjustment
3023 instruction and the instructions that save registers on the stack
3024 or in the gcc frame. */
3025 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
3026 {
3027 unsigned short inst;
3028 int i;
3029
3030 inst = mips_fetch_instruction (pc);
3031
3032 /* Normally we ignore an extend instruction. However, if it is
3033 not followed by a valid prologue instruction, we must adjust
3034 the pc back over the extend so that it won't be considered
3035 part of the prologue. */
3036 if ((inst & 0xf800) == 0xf000) /* extend */
3037 {
3038 extend_bytes = MIPS16_INSTLEN;
3039 continue;
3040 }
3041 prev_extend_bytes = extend_bytes;
3042 extend_bytes = 0;
3043
3044 /* Check for other valid prologue instructions besides extend. */
3045 for (i = 0; table[i].mask != 0; i++)
3046 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
3047 break;
3048 if (table[i].mask != 0) /* it was in table? */
3049 continue; /* ignore it */
3050 else
3051 /* non-prologue */
3052 {
3053 /* Return the current pc, adjusted backwards by 2 if
3054 the previous instruction was an extend. */
3055 return pc - prev_extend_bytes;
3056 }
3057 }
3058 return pc;
3059 }
3060
3061 /* To skip prologues, I use this predicate. Returns either PC itself
3062 if the code at PC does not look like a function prologue; otherwise
3063 returns an address that (if we're lucky) follows the prologue. If
3064 LENIENT, then we must skip everything which is involved in setting
3065 up the frame (it's OK to skip more, just so long as we don't skip
3066 anything which might clobber the registers which are being saved.
3067 We must skip more in the case where part of the prologue is in the
3068 delay slot of a non-prologue instruction). */
3069
3070 CORE_ADDR
3071 mips_skip_prologue (CORE_ADDR pc)
3072 {
3073 /* See if we can determine the end of the prologue via the symbol table.
3074 If so, then return either PC, or the PC after the prologue, whichever
3075 is greater. */
3076
3077 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
3078
3079 if (post_prologue_pc != 0)
3080 return max (pc, post_prologue_pc);
3081
3082 /* Can't determine prologue from the symbol table, need to examine
3083 instructions. */
3084
3085 if (pc_is_mips16 (pc))
3086 return mips16_skip_prologue (pc);
3087 else
3088 return mips32_skip_prologue (pc);
3089 }
3090
3091 /* Determine how a return value is stored within the MIPS register
3092 file, given the return type `valtype'. */
3093
3094 struct return_value_word
3095 {
3096 int len;
3097 int reg;
3098 int reg_offset;
3099 int buf_offset;
3100 };
3101
3102 static void
3103 return_value_location (struct type *valtype,
3104 struct return_value_word *hi,
3105 struct return_value_word *lo)
3106 {
3107 int len = TYPE_LENGTH (valtype);
3108
3109 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
3110 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
3111 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
3112 {
3113 if (!FP_REGISTER_DOUBLE && len == 8)
3114 {
3115 /* We need to break a 64bit float in two 32 bit halves and
3116 spread them across a floating-point register pair. */
3117 lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
3118 hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4;
3119 lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN
3120 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
3121 ? 4 : 0);
3122 hi->reg_offset = lo->reg_offset;
3123 lo->reg = FP0_REGNUM + 0;
3124 hi->reg = FP0_REGNUM + 1;
3125 lo->len = 4;
3126 hi->len = 4;
3127 }
3128 else
3129 {
3130 /* The floating point value fits in a single floating-point
3131 register. */
3132 lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN
3133 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
3134 && len == 4)
3135 ? 4 : 0);
3136 lo->reg = FP0_REGNUM;
3137 lo->len = len;
3138 lo->buf_offset = 0;
3139 hi->len = 0;
3140 hi->reg_offset = 0;
3141 hi->buf_offset = 0;
3142 hi->reg = 0;
3143 }
3144 }
3145 else
3146 {
3147 /* Locate a result possibly spread across two registers. */
3148 int regnum = 2;
3149 lo->reg = regnum + 0;
3150 hi->reg = regnum + 1;
3151 if (TARGET_BYTE_ORDER == BIG_ENDIAN
3152 && len < MIPS_SAVED_REGSIZE)
3153 {
3154 /* "un-left-justify" the value in the low register */
3155 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
3156 lo->len = len;
3157 hi->reg_offset = 0;
3158 hi->len = 0;
3159 }
3160 else if (TARGET_BYTE_ORDER == BIG_ENDIAN
3161 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
3162 && len < MIPS_SAVED_REGSIZE * 2
3163 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3164 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3165 {
3166 /* "un-left-justify" the value spread across two registers. */
3167 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
3168 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
3169 hi->reg_offset = 0;
3170 hi->len = len - lo->len;
3171 }
3172 else
3173 {
3174 /* Only perform a partial copy of the second register. */
3175 lo->reg_offset = 0;
3176 hi->reg_offset = 0;
3177 if (len > MIPS_SAVED_REGSIZE)
3178 {
3179 lo->len = MIPS_SAVED_REGSIZE;
3180 hi->len = len - MIPS_SAVED_REGSIZE;
3181 }
3182 else
3183 {
3184 lo->len = len;
3185 hi->len = 0;
3186 }
3187 }
3188 if (TARGET_BYTE_ORDER == BIG_ENDIAN
3189 && REGISTER_RAW_SIZE (regnum) == 8
3190 && MIPS_SAVED_REGSIZE == 4)
3191 {
3192 /* Account for the fact that only the least-signficant part
3193 of the register is being used */
3194 lo->reg_offset += 4;
3195 hi->reg_offset += 4;
3196 }
3197 lo->buf_offset = 0;
3198 hi->buf_offset = lo->len;
3199 }
3200 }
3201
3202 /* Given a return value in `regbuf' with a type `valtype', extract and
3203 copy its value into `valbuf'. */
3204
3205 void
3206 mips_extract_return_value (struct type *valtype,
3207 char regbuf[REGISTER_BYTES],
3208 char *valbuf)
3209 {
3210 struct return_value_word lo;
3211 struct return_value_word hi;
3212 return_value_location (valtype, &lo, &hi);
3213
3214 memcpy (valbuf + lo.buf_offset,
3215 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
3216 lo.len);
3217
3218 if (hi.len > 0)
3219 memcpy (valbuf + hi.buf_offset,
3220 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
3221 hi.len);
3222 }
3223
3224 /* Given a return value in `valbuf' with a type `valtype', write it's
3225 value into the appropriate register. */
3226
3227 void
3228 mips_store_return_value (struct type *valtype, char *valbuf)
3229 {
3230 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3231 struct return_value_word lo;
3232 struct return_value_word hi;
3233 return_value_location (valtype, &lo, &hi);
3234
3235 memset (raw_buffer, 0, sizeof (raw_buffer));
3236 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3237 write_register_bytes (REGISTER_BYTE (lo.reg),
3238 raw_buffer,
3239 REGISTER_RAW_SIZE (lo.reg));
3240
3241 if (hi.len > 0)
3242 {
3243 memset (raw_buffer, 0, sizeof (raw_buffer));
3244 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3245 write_register_bytes (REGISTER_BYTE (hi.reg),
3246 raw_buffer,
3247 REGISTER_RAW_SIZE (hi.reg));
3248 }
3249 }
3250
3251 /* Exported procedure: Is PC in the signal trampoline code */
3252
3253 int
3254 in_sigtramp (CORE_ADDR pc, char *ignore)
3255 {
3256 if (sigtramp_address == 0)
3257 fixup_sigtramp ();
3258 return (pc >= sigtramp_address && pc < sigtramp_end);
3259 }
3260
3261 /* Root of all "set mips "/"show mips " commands. This will eventually be
3262 used for all MIPS-specific commands. */
3263
3264 static void
3265 show_mips_command (char *args, int from_tty)
3266 {
3267 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
3268 }
3269
3270 static void
3271 set_mips_command (char *args, int from_tty)
3272 {
3273 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3274 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
3275 }
3276
3277 /* Commands to show/set the MIPS FPU type. */
3278
3279 static void
3280 show_mipsfpu_command (char *args, int from_tty)
3281 {
3282 char *msg;
3283 char *fpu;
3284 switch (MIPS_FPU_TYPE)
3285 {
3286 case MIPS_FPU_SINGLE:
3287 fpu = "single-precision";
3288 break;
3289 case MIPS_FPU_DOUBLE:
3290 fpu = "double-precision";
3291 break;
3292 case MIPS_FPU_NONE:
3293 fpu = "absent (none)";
3294 break;
3295 default:
3296 internal_error (__FILE__, __LINE__, "bad switch");
3297 }
3298 if (mips_fpu_type_auto)
3299 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3300 fpu);
3301 else
3302 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3303 fpu);
3304 }
3305
3306
3307 static void
3308 set_mipsfpu_command (char *args, int from_tty)
3309 {
3310 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3311 show_mipsfpu_command (args, from_tty);
3312 }
3313
3314 static void
3315 set_mipsfpu_single_command (char *args, int from_tty)
3316 {
3317 mips_fpu_type = MIPS_FPU_SINGLE;
3318 mips_fpu_type_auto = 0;
3319 if (GDB_MULTI_ARCH)
3320 {
3321 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
3322 }
3323 }
3324
3325 static void
3326 set_mipsfpu_double_command (char *args, int from_tty)
3327 {
3328 mips_fpu_type = MIPS_FPU_DOUBLE;
3329 mips_fpu_type_auto = 0;
3330 if (GDB_MULTI_ARCH)
3331 {
3332 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
3333 }
3334 }
3335
3336 static void
3337 set_mipsfpu_none_command (char *args, int from_tty)
3338 {
3339 mips_fpu_type = MIPS_FPU_NONE;
3340 mips_fpu_type_auto = 0;
3341 if (GDB_MULTI_ARCH)
3342 {
3343 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
3344 }
3345 }
3346
3347 static void
3348 set_mipsfpu_auto_command (char *args, int from_tty)
3349 {
3350 mips_fpu_type_auto = 1;
3351 }
3352
3353 /* Command to set the processor type. */
3354
3355 void
3356 mips_set_processor_type_command (char *args, int from_tty)
3357 {
3358 int i;
3359
3360 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
3361 {
3362 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3363 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3364 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
3365
3366 /* Restore the value. */
3367 tmp_mips_processor_type = xstrdup (mips_processor_type);
3368
3369 return;
3370 }
3371
3372 if (!mips_set_processor_type (tmp_mips_processor_type))
3373 {
3374 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
3375 /* Restore its value. */
3376 tmp_mips_processor_type = xstrdup (mips_processor_type);
3377 }
3378 }
3379
3380 static void
3381 mips_show_processor_type_command (char *args, int from_tty)
3382 {
3383 }
3384
3385 /* Modify the actual processor type. */
3386
3387 int
3388 mips_set_processor_type (char *str)
3389 {
3390 int i, j;
3391
3392 if (str == NULL)
3393 return 0;
3394
3395 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3396 {
3397 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
3398 {
3399 mips_processor_type = str;
3400 mips_processor_reg_names = mips_processor_type_table[i].regnames;
3401 return 1;
3402 /* FIXME tweak fpu flag too */
3403 }
3404 }
3405
3406 return 0;
3407 }
3408
3409 /* Attempt to identify the particular processor model by reading the
3410 processor id. */
3411
3412 char *
3413 mips_read_processor_type (void)
3414 {
3415 CORE_ADDR prid;
3416
3417 prid = read_register (PRID_REGNUM);
3418
3419 if ((prid & ~0xf) == 0x700)
3420 return savestring ("r3041", strlen ("r3041"));
3421
3422 return NULL;
3423 }
3424
3425 /* Just like reinit_frame_cache, but with the right arguments to be
3426 callable as an sfunc. */
3427
3428 static void
3429 reinit_frame_cache_sfunc (char *args, int from_tty,
3430 struct cmd_list_element *c)
3431 {
3432 reinit_frame_cache ();
3433 }
3434
3435 int
3436 gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info)
3437 {
3438 mips_extra_func_info_t proc_desc;
3439
3440 /* Search for the function containing this address. Set the low bit
3441 of the address when searching, in case we were given an even address
3442 that is the start of a 16-bit function. If we didn't do this,
3443 the search would fail because the symbol table says the function
3444 starts at an odd address, i.e. 1 byte past the given address. */
3445 memaddr = ADDR_BITS_REMOVE (memaddr);
3446 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
3447
3448 /* Make an attempt to determine if this is a 16-bit function. If
3449 the procedure descriptor exists and the address therein is odd,
3450 it's definitely a 16-bit function. Otherwise, we have to just
3451 guess that if the address passed in is odd, it's 16-bits. */
3452 if (proc_desc)
3453 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ?
3454 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3455 else
3456 info->mach = pc_is_mips16 (memaddr) ?
3457 bfd_mach_mips16 : TM_PRINT_INSN_MACH;
3458
3459 /* Round down the instruction address to the appropriate boundary. */
3460 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
3461
3462 /* Call the appropriate disassembler based on the target endian-ness. */
3463 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
3464 return print_insn_big_mips (memaddr, info);
3465 else
3466 return print_insn_little_mips (memaddr, info);
3467 }
3468
3469 /* Old-style breakpoint macros.
3470 The IDT board uses an unusual breakpoint value, and sometimes gets
3471 confused when it sees the usual MIPS breakpoint instruction. */
3472
3473 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3474 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3475 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3476 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3477 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3478 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3479 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3480 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3481
3482 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3483 counter value to determine whether a 16- or 32-bit breakpoint should be
3484 used. It returns a pointer to a string of bytes that encode a breakpoint
3485 instruction, stores the length of the string to *lenptr, and adjusts pc
3486 (if necessary) to point to the actual memory location where the
3487 breakpoint should be inserted. */
3488
3489 unsigned char *
3490 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
3491 {
3492 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
3493 {
3494 if (pc_is_mips16 (*pcptr))
3495 {
3496 static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT;
3497 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3498 *lenptr = sizeof (mips16_big_breakpoint);
3499 return mips16_big_breakpoint;
3500 }
3501 else
3502 {
3503 static char big_breakpoint[] = BIG_BREAKPOINT;
3504 static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
3505 static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
3506
3507 *lenptr = sizeof (big_breakpoint);
3508
3509 if (strcmp (target_shortname, "mips") == 0)
3510 return idt_big_breakpoint;
3511 else if (strcmp (target_shortname, "ddb") == 0
3512 || strcmp (target_shortname, "pmon") == 0
3513 || strcmp (target_shortname, "lsi") == 0)
3514 return pmon_big_breakpoint;
3515 else
3516 return big_breakpoint;
3517 }
3518 }
3519 else
3520 {
3521 if (pc_is_mips16 (*pcptr))
3522 {
3523 static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT;
3524 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
3525 *lenptr = sizeof (mips16_little_breakpoint);
3526 return mips16_little_breakpoint;
3527 }
3528 else
3529 {
3530 static char little_breakpoint[] = LITTLE_BREAKPOINT;
3531 static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT;
3532 static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT;
3533
3534 *lenptr = sizeof (little_breakpoint);
3535
3536 if (strcmp (target_shortname, "mips") == 0)
3537 return idt_little_breakpoint;
3538 else if (strcmp (target_shortname, "ddb") == 0
3539 || strcmp (target_shortname, "pmon") == 0
3540 || strcmp (target_shortname, "lsi") == 0)
3541 return pmon_little_breakpoint;
3542 else
3543 return little_breakpoint;
3544 }
3545 }
3546 }
3547
3548 /* If PC is in a mips16 call or return stub, return the address of the target
3549 PC, which is either the callee or the caller. There are several
3550 cases which must be handled:
3551
3552 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3553 target PC is in $31 ($ra).
3554 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3555 and the target PC is in $2.
3556 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3557 before the jal instruction, this is effectively a call stub
3558 and the the target PC is in $2. Otherwise this is effectively
3559 a return stub and the target PC is in $18.
3560
3561 See the source code for the stubs in gcc/config/mips/mips16.S for
3562 gory details.
3563
3564 This function implements the SKIP_TRAMPOLINE_CODE macro.
3565 */
3566
3567 CORE_ADDR
3568 mips_skip_stub (CORE_ADDR pc)
3569 {
3570 char *name;
3571 CORE_ADDR start_addr;
3572
3573 /* Find the starting address and name of the function containing the PC. */
3574 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
3575 return 0;
3576
3577 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3578 target PC is in $31 ($ra). */
3579 if (strcmp (name, "__mips16_ret_sf") == 0
3580 || strcmp (name, "__mips16_ret_df") == 0)
3581 return read_signed_register (RA_REGNUM);
3582
3583 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3584 {
3585 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3586 and the target PC is in $2. */
3587 if (name[19] >= '0' && name[19] <= '9')
3588 return read_signed_register (2);
3589
3590 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3591 before the jal instruction, this is effectively a call stub
3592 and the the target PC is in $2. Otherwise this is effectively
3593 a return stub and the target PC is in $18. */
3594 else if (name[19] == 's' || name[19] == 'd')
3595 {
3596 if (pc == start_addr)
3597 {
3598 /* Check if the target of the stub is a compiler-generated
3599 stub. Such a stub for a function bar might have a name
3600 like __fn_stub_bar, and might look like this:
3601 mfc1 $4,$f13
3602 mfc1 $5,$f12
3603 mfc1 $6,$f15
3604 mfc1 $7,$f14
3605 la $1,bar (becomes a lui/addiu pair)
3606 jr $1
3607 So scan down to the lui/addi and extract the target
3608 address from those two instructions. */
3609
3610 CORE_ADDR target_pc = read_signed_register (2);
3611 t_inst inst;
3612 int i;
3613
3614 /* See if the name of the target function is __fn_stub_*. */
3615 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
3616 return target_pc;
3617 if (strncmp (name, "__fn_stub_", 10) != 0
3618 && strcmp (name, "etext") != 0
3619 && strcmp (name, "_etext") != 0)
3620 return target_pc;
3621
3622 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3623 The limit on the search is arbitrarily set to 20
3624 instructions. FIXME. */
3625 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
3626 {
3627 inst = mips_fetch_instruction (target_pc);
3628 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
3629 pc = (inst << 16) & 0xffff0000; /* high word */
3630 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
3631 return pc | (inst & 0xffff); /* low word */
3632 }
3633
3634 /* Couldn't find the lui/addui pair, so return stub address. */
3635 return target_pc;
3636 }
3637 else
3638 /* This is the 'return' part of a call stub. The return
3639 address is in $r18. */
3640 return read_signed_register (18);
3641 }
3642 }
3643 return 0; /* not a stub */
3644 }
3645
3646
3647 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3648 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3649
3650 int
3651 mips_in_call_stub (CORE_ADDR pc, char *name)
3652 {
3653 CORE_ADDR start_addr;
3654
3655 /* Find the starting address of the function containing the PC. If the
3656 caller didn't give us a name, look it up at the same time. */
3657 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
3658 return 0;
3659
3660 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3661 {
3662 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3663 if (name[19] >= '0' && name[19] <= '9')
3664 return 1;
3665 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3666 before the jal instruction, this is effectively a call stub. */
3667 else if (name[19] == 's' || name[19] == 'd')
3668 return pc == start_addr;
3669 }
3670
3671 return 0; /* not a stub */
3672 }
3673
3674
3675 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3676 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3677
3678 int
3679 mips_in_return_stub (CORE_ADDR pc, char *name)
3680 {
3681 CORE_ADDR start_addr;
3682
3683 /* Find the starting address of the function containing the PC. */
3684 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
3685 return 0;
3686
3687 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3688 if (strcmp (name, "__mips16_ret_sf") == 0
3689 || strcmp (name, "__mips16_ret_df") == 0)
3690 return 1;
3691
3692 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3693 i.e. after the jal instruction, this is effectively a return stub. */
3694 if (strncmp (name, "__mips16_call_stub_", 19) == 0
3695 && (name[19] == 's' || name[19] == 'd')
3696 && pc != start_addr)
3697 return 1;
3698
3699 return 0; /* not a stub */
3700 }
3701
3702
3703 /* Return non-zero if the PC is in a library helper function that should
3704 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3705
3706 int
3707 mips_ignore_helper (CORE_ADDR pc)
3708 {
3709 char *name;
3710
3711 /* Find the starting address and name of the function containing the PC. */
3712 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
3713 return 0;
3714
3715 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3716 that we want to ignore. */
3717 return (strcmp (name, "__mips16_ret_sf") == 0
3718 || strcmp (name, "__mips16_ret_df") == 0);
3719 }
3720
3721
3722 /* Return a location where we can set a breakpoint that will be hit
3723 when an inferior function call returns. This is normally the
3724 program's entry point. Executables that don't have an entry
3725 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3726 whose address is the location where the breakpoint should be placed. */
3727
3728 CORE_ADDR
3729 mips_call_dummy_address (void)
3730 {
3731 struct minimal_symbol *sym;
3732
3733 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
3734 if (sym)
3735 return SYMBOL_VALUE_ADDRESS (sym);
3736 else
3737 return entry_point_address ();
3738 }
3739
3740
3741 /* If the current gcc for this target does not produce correct debugging
3742 information for float parameters, both prototyped and unprototyped, then
3743 define this macro. This forces gdb to always assume that floats are
3744 passed as doubles and then converted in the callee.
3745
3746 For the mips chip, it appears that the debug info marks the parameters as
3747 floats regardless of whether the function is prototyped, but the actual
3748 values are passed as doubles for the non-prototyped case and floats for
3749 the prototyped case. Thus we choose to make the non-prototyped case work
3750 for C and break the prototyped case, since the non-prototyped case is
3751 probably much more common. (FIXME). */
3752
3753 static int
3754 mips_coerce_float_to_double (struct type *formal, struct type *actual)
3755 {
3756 return current_language->la_language == language_c;
3757 }
3758
3759 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3760 the register stored on the stack (32) is different to its real raw
3761 size (64). The below ensures that registers are fetched from the
3762 stack using their ABI size and then stored into the RAW_BUFFER
3763 using their raw size.
3764
3765 The alternative to adding this function would be to add an ABI
3766 macro - REGISTER_STACK_SIZE(). */
3767
3768 static void
3769 mips_get_saved_register (char *raw_buffer,
3770 int *optimized,
3771 CORE_ADDR *addrp,
3772 struct frame_info *frame,
3773 int regnum,
3774 enum lval_type *lval)
3775 {
3776 CORE_ADDR addr;
3777
3778 if (!target_has_registers)
3779 error ("No registers.");
3780
3781 /* Normal systems don't optimize out things with register numbers. */
3782 if (optimized != NULL)
3783 *optimized = 0;
3784 addr = find_saved_register (frame, regnum);
3785 if (addr != 0)
3786 {
3787 if (lval != NULL)
3788 *lval = lval_memory;
3789 if (regnum == SP_REGNUM)
3790 {
3791 if (raw_buffer != NULL)
3792 {
3793 /* Put it back in target format. */
3794 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
3795 (LONGEST) addr);
3796 }
3797 if (addrp != NULL)
3798 *addrp = 0;
3799 return;
3800 }
3801 if (raw_buffer != NULL)
3802 {
3803 LONGEST val;
3804 if (regnum < 32)
3805 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3806 saved. */
3807 val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
3808 else
3809 val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
3810 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
3811 }
3812 }
3813 else
3814 {
3815 if (lval != NULL)
3816 *lval = lval_register;
3817 addr = REGISTER_BYTE (regnum);
3818 if (raw_buffer != NULL)
3819 read_register_gen (regnum, raw_buffer);
3820 }
3821 if (addrp != NULL)
3822 *addrp = addr;
3823 }
3824
3825 /* Immediately after a function call, return the saved pc.
3826 Can't always go through the frames for this because on some machines
3827 the new frame is not set up until the new function executes
3828 some instructions. */
3829
3830 static CORE_ADDR
3831 mips_saved_pc_after_call (struct frame_info *frame)
3832 {
3833 return read_signed_register (RA_REGNUM);
3834 }
3835
3836
3837 /* Convert a dbx stab register number (from `r' declaration) to a gdb
3838 REGNUM */
3839
3840 static int
3841 mips_stab_reg_to_regnum (int num)
3842 {
3843 if (num < 32)
3844 return num;
3845 else
3846 return num + FP0_REGNUM - 38;
3847 }
3848
3849 /* Convert a ecoff register number to a gdb REGNUM */
3850
3851 static int
3852 mips_ecoff_reg_to_regnum (int num)
3853 {
3854 if (num < 32)
3855 return num;
3856 else
3857 return num + FP0_REGNUM - 32;
3858 }
3859
3860 static struct gdbarch *
3861 mips_gdbarch_init (struct gdbarch_info info,
3862 struct gdbarch_list *arches)
3863 {
3864 static LONGEST mips_call_dummy_words[] =
3865 {0};
3866 struct gdbarch *gdbarch;
3867 struct gdbarch_tdep *tdep;
3868 int elf_flags;
3869 enum mips_abi mips_abi;
3870
3871 /* Extract the elf_flags if available */
3872 if (info.abfd != NULL
3873 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
3874 elf_flags = elf_elfheader (info.abfd)->e_flags;
3875 else
3876 elf_flags = 0;
3877
3878 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3879 switch ((elf_flags & EF_MIPS_ABI))
3880 {
3881 case E_MIPS_ABI_O32:
3882 mips_abi = MIPS_ABI_O32;
3883 break;
3884 case E_MIPS_ABI_O64:
3885 mips_abi = MIPS_ABI_O64;
3886 break;
3887 case E_MIPS_ABI_EABI32:
3888 mips_abi = MIPS_ABI_EABI32;
3889 break;
3890 case E_MIPS_ABI_EABI64:
3891 mips_abi = MIPS_ABI_EABI64;
3892 break;
3893 default:
3894 if ((elf_flags & EF_MIPS_ABI2))
3895 mips_abi = MIPS_ABI_N32;
3896 else
3897 mips_abi = MIPS_ABI_UNKNOWN;
3898 break;
3899 }
3900
3901 /* Try the architecture for any hint of the corect ABI */
3902 if (mips_abi == MIPS_ABI_UNKNOWN
3903 && info.bfd_arch_info != NULL
3904 && info.bfd_arch_info->arch == bfd_arch_mips)
3905 {
3906 switch (info.bfd_arch_info->mach)
3907 {
3908 case bfd_mach_mips3900:
3909 mips_abi = MIPS_ABI_EABI32;
3910 break;
3911 case bfd_mach_mips4100:
3912 case bfd_mach_mips5000:
3913 mips_abi = MIPS_ABI_EABI64;
3914 break;
3915 }
3916 }
3917 #ifdef MIPS_DEFAULT_ABI
3918 if (mips_abi == MIPS_ABI_UNKNOWN)
3919 mips_abi = MIPS_DEFAULT_ABI;
3920 #endif
3921
3922 if (gdbarch_debug)
3923 {
3924 fprintf_unfiltered (gdb_stdlog,
3925 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3926 elf_flags);
3927 fprintf_unfiltered (gdb_stdlog,
3928 "mips_gdbarch_init: mips_abi = %d\n",
3929 mips_abi);
3930 }
3931
3932 /* try to find a pre-existing architecture */
3933 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3934 arches != NULL;
3935 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3936 {
3937 /* MIPS needs to be pedantic about which ABI the object is
3938 using. */
3939 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
3940 continue;
3941 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
3942 continue;
3943 return arches->gdbarch;
3944 }
3945
3946 /* Need a new architecture. Fill in a target specific vector. */
3947 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
3948 gdbarch = gdbarch_alloc (&info, tdep);
3949 tdep->elf_flags = elf_flags;
3950
3951 /* Initially set everything according to the ABI. */
3952 set_gdbarch_short_bit (gdbarch, 16);
3953 set_gdbarch_int_bit (gdbarch, 32);
3954 set_gdbarch_float_bit (gdbarch, 32);
3955 set_gdbarch_double_bit (gdbarch, 64);
3956 set_gdbarch_long_double_bit (gdbarch, 64);
3957 tdep->mips_abi = mips_abi;
3958 switch (mips_abi)
3959 {
3960 case MIPS_ABI_O32:
3961 tdep->mips_abi_string = "o32";
3962 tdep->mips_default_saved_regsize = 4;
3963 tdep->mips_default_stack_argsize = 4;
3964 tdep->mips_fp_register_double = 0;
3965 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
3966 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
3967 tdep->mips_regs_have_home_p = 1;
3968 tdep->gdb_target_is_mips64 = 0;
3969 tdep->default_mask_address_p = 0;
3970 set_gdbarch_long_bit (gdbarch, 32);
3971 set_gdbarch_ptr_bit (gdbarch, 32);
3972 set_gdbarch_long_long_bit (gdbarch, 64);
3973 break;
3974 case MIPS_ABI_O64:
3975 tdep->mips_abi_string = "o64";
3976 tdep->mips_default_saved_regsize = 8;
3977 tdep->mips_default_stack_argsize = 8;
3978 tdep->mips_fp_register_double = 1;
3979 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
3980 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
3981 tdep->mips_regs_have_home_p = 1;
3982 tdep->gdb_target_is_mips64 = 1;
3983 tdep->default_mask_address_p = 0;
3984 set_gdbarch_long_bit (gdbarch, 32);
3985 set_gdbarch_ptr_bit (gdbarch, 32);
3986 set_gdbarch_long_long_bit (gdbarch, 64);
3987 break;
3988 case MIPS_ABI_EABI32:
3989 tdep->mips_abi_string = "eabi32";
3990 tdep->mips_default_saved_regsize = 4;
3991 tdep->mips_default_stack_argsize = 4;
3992 tdep->mips_fp_register_double = 0;
3993 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
3994 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
3995 tdep->mips_regs_have_home_p = 0;
3996 tdep->gdb_target_is_mips64 = 0;
3997 tdep->default_mask_address_p = 0;
3998 set_gdbarch_long_bit (gdbarch, 32);
3999 set_gdbarch_ptr_bit (gdbarch, 32);
4000 set_gdbarch_long_long_bit (gdbarch, 64);
4001 break;
4002 case MIPS_ABI_EABI64:
4003 tdep->mips_abi_string = "eabi64";
4004 tdep->mips_default_saved_regsize = 8;
4005 tdep->mips_default_stack_argsize = 8;
4006 tdep->mips_fp_register_double = 1;
4007 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4008 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4009 tdep->mips_regs_have_home_p = 0;
4010 tdep->gdb_target_is_mips64 = 1;
4011 tdep->default_mask_address_p = 0;
4012 set_gdbarch_long_bit (gdbarch, 64);
4013 set_gdbarch_ptr_bit (gdbarch, 64);
4014 set_gdbarch_long_long_bit (gdbarch, 64);
4015 break;
4016 case MIPS_ABI_N32:
4017 tdep->mips_abi_string = "n32";
4018 tdep->mips_default_saved_regsize = 4;
4019 tdep->mips_default_stack_argsize = 8;
4020 tdep->mips_fp_register_double = 1;
4021 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4022 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4023 tdep->mips_regs_have_home_p = 0;
4024 tdep->gdb_target_is_mips64 = 0;
4025 tdep->default_mask_address_p = 0;
4026 set_gdbarch_long_bit (gdbarch, 32);
4027 set_gdbarch_ptr_bit (gdbarch, 32);
4028 set_gdbarch_long_long_bit (gdbarch, 64);
4029 break;
4030 default:
4031 tdep->mips_abi_string = "default";
4032 tdep->mips_default_saved_regsize = MIPS_REGSIZE;
4033 tdep->mips_default_stack_argsize = MIPS_REGSIZE;
4034 tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8);
4035 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
4036 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
4037 tdep->mips_regs_have_home_p = 1;
4038 tdep->gdb_target_is_mips64 = 0;
4039 tdep->default_mask_address_p = 0;
4040 set_gdbarch_long_bit (gdbarch, 32);
4041 set_gdbarch_ptr_bit (gdbarch, 32);
4042 set_gdbarch_long_long_bit (gdbarch, 64);
4043 break;
4044 }
4045
4046 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4047 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4048 comment:
4049
4050 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4051 flag in object files because to do so would make it impossible to
4052 link with libraries compiled without "-gp32". This is
4053 unnecessarily restrictive.
4054
4055 We could solve this problem by adding "-gp32" multilibs to gcc,
4056 but to set this flag before gcc is built with such multilibs will
4057 break too many systems.''
4058
4059 But even more unhelpfully, the default linker output target for
4060 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4061 for 64-bit programs - you need to change the ABI to change this,
4062 and not all gcc targets support that currently. Therefore using
4063 this flag to detect 32-bit mode would do the wrong thing given
4064 the current gcc - it would make GDB treat these 64-bit programs
4065 as 32-bit programs by default. */
4066
4067 /* enable/disable the MIPS FPU */
4068 if (!mips_fpu_type_auto)
4069 tdep->mips_fpu_type = mips_fpu_type;
4070 else if (info.bfd_arch_info != NULL
4071 && info.bfd_arch_info->arch == bfd_arch_mips)
4072 switch (info.bfd_arch_info->mach)
4073 {
4074 case bfd_mach_mips3900:
4075 case bfd_mach_mips4100:
4076 case bfd_mach_mips4111:
4077 tdep->mips_fpu_type = MIPS_FPU_NONE;
4078 break;
4079 case bfd_mach_mips4650:
4080 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
4081 break;
4082 default:
4083 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4084 break;
4085 }
4086 else
4087 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
4088
4089 /* MIPS version of register names. NOTE: At present the MIPS
4090 register name management is part way between the old -
4091 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4092 Further work on it is required. */
4093 set_gdbarch_register_name (gdbarch, mips_register_name);
4094 set_gdbarch_read_pc (gdbarch, mips_read_pc);
4095 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4096 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4097 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
4098 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4099 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4100
4101 /* Map debug register numbers onto internal register numbers. */
4102 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
4103 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum);
4104
4105 /* Initialize a frame */
4106 set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
4107
4108 /* MIPS version of CALL_DUMMY */
4109
4110 set_gdbarch_call_dummy_p (gdbarch, 1);
4111 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4112 set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
4113 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4114 set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address);
4115 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4116 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
4117 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4118 set_gdbarch_call_dummy_length (gdbarch, 0);
4119 set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
4120 set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words);
4121 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words));
4122 set_gdbarch_push_return_address (gdbarch, mips_push_return_address);
4123 set_gdbarch_push_arguments (gdbarch, mips_push_arguments);
4124 set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not);
4125 set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double);
4126
4127 set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
4128 set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
4129
4130 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4131 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
4132 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4133 set_gdbarch_ieee_float (gdbarch, 1);
4134
4135 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
4136 set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
4137
4138 return gdbarch;
4139 }
4140
4141 static void
4142 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4143 {
4144 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4145 if (tdep != NULL)
4146 {
4147 int ef_mips_arch;
4148 int ef_mips_32bitmode;
4149 /* determine the ISA */
4150 switch (tdep->elf_flags & EF_MIPS_ARCH)
4151 {
4152 case E_MIPS_ARCH_1:
4153 ef_mips_arch = 1;
4154 break;
4155 case E_MIPS_ARCH_2:
4156 ef_mips_arch = 2;
4157 break;
4158 case E_MIPS_ARCH_3:
4159 ef_mips_arch = 3;
4160 break;
4161 case E_MIPS_ARCH_4:
4162 ef_mips_arch = 4;
4163 break;
4164 default:
4165 ef_mips_arch = 0;
4166 break;
4167 }
4168 /* determine the size of a pointer */
4169 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
4170 fprintf_unfiltered (file,
4171 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4172 tdep->elf_flags);
4173 fprintf_unfiltered (file,
4174 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4175 ef_mips_32bitmode);
4176 fprintf_unfiltered (file,
4177 "mips_dump_tdep: ef_mips_arch = %d\n",
4178 ef_mips_arch);
4179 fprintf_unfiltered (file,
4180 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4181 tdep->mips_abi,
4182 tdep->mips_abi_string);
4183 fprintf_unfiltered (file,
4184 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4185 mips_mask_address_p (),
4186 tdep->default_mask_address_p);
4187 }
4188 fprintf_unfiltered (file,
4189 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4190 FP_REGISTER_DOUBLE);
4191 fprintf_unfiltered (file,
4192 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4193 MIPS_DEFAULT_FPU_TYPE,
4194 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
4195 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4196 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4197 : "???"));
4198 fprintf_unfiltered (file,
4199 "mips_dump_tdep: MIPS_EABI = %d\n",
4200 MIPS_EABI);
4201 fprintf_unfiltered (file,
4202 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4203 MIPS_LAST_FP_ARG_REGNUM,
4204 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
4205 fprintf_unfiltered (file,
4206 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4207 MIPS_FPU_TYPE,
4208 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
4209 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
4210 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
4211 : "???"));
4212 fprintf_unfiltered (file,
4213 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4214 MIPS_DEFAULT_SAVED_REGSIZE);
4215 fprintf_unfiltered (file,
4216 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4217 FP_REGISTER_DOUBLE);
4218 fprintf_unfiltered (file,
4219 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4220 MIPS_REGS_HAVE_HOME_P);
4221 fprintf_unfiltered (file,
4222 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4223 MIPS_DEFAULT_STACK_ARGSIZE);
4224 fprintf_unfiltered (file,
4225 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4226 MIPS_STACK_ARGSIZE);
4227 fprintf_unfiltered (file,
4228 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4229 MIPS_REGSIZE);
4230 fprintf_unfiltered (file,
4231 "mips_dump_tdep: A0_REGNUM = %d\n",
4232 A0_REGNUM);
4233 fprintf_unfiltered (file,
4234 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4235 XSTRING (ADDR_BITS_REMOVE(ADDR)));
4236 fprintf_unfiltered (file,
4237 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4238 XSTRING (ATTACH_DETACH));
4239 fprintf_unfiltered (file,
4240 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4241 BADVADDR_REGNUM);
4242 fprintf_unfiltered (file,
4243 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4244 fprintf_unfiltered (file,
4245 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4246 CAUSE_REGNUM);
4247 fprintf_unfiltered (file,
4248 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4249 CPLUS_MARKER);
4250 fprintf_unfiltered (file,
4251 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4252 DEFAULT_MIPS_TYPE);
4253 fprintf_unfiltered (file,
4254 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4255 XSTRING (DO_REGISTERS_INFO));
4256 fprintf_unfiltered (file,
4257 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4258 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
4259 fprintf_unfiltered (file,
4260 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4261 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
4262 fprintf_unfiltered (file,
4263 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4264 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM)));
4265 fprintf_unfiltered (file,
4266 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4267 FCRCS_REGNUM);
4268 fprintf_unfiltered (file,
4269 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4270 FCRIR_REGNUM);
4271 fprintf_unfiltered (file,
4272 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4273 FIRST_EMBED_REGNUM);
4274 fprintf_unfiltered (file,
4275 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4276 FPA0_REGNUM);
4277 fprintf_unfiltered (file,
4278 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4279 GDB_TARGET_IS_MIPS64);
4280 fprintf_unfiltered (file,
4281 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4282 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC)));
4283 fprintf_unfiltered (file,
4284 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4285 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC)));
4286 fprintf_unfiltered (file,
4287 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4288 GEN_REG_SAVE_MASK);
4289 fprintf_unfiltered (file,
4290 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4291 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
4292 fprintf_unfiltered (file,
4293 "mips_dump_tdep: HI_REGNUM = %d\n",
4294 HI_REGNUM);
4295 fprintf_unfiltered (file,
4296 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4297 fprintf_unfiltered (file,
4298 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4299 fprintf_unfiltered (file,
4300 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4301 XSTRING (IGNORE_HELPER_CALL (PC)));
4302 fprintf_unfiltered (file,
4303 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4304 XSTRING (INIT_FRAME_PC (FROMLEAF, PREV)));
4305 fprintf_unfiltered (file,
4306 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4307 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF, PREV)));
4308 fprintf_unfiltered (file,
4309 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4310 XSTRING (IN_SIGTRAMP (PC, NAME)));
4311 fprintf_unfiltered (file,
4312 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4313 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
4314 fprintf_unfiltered (file,
4315 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4316 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
4317 fprintf_unfiltered (file,
4318 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4319 fprintf_unfiltered (file,
4320 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4321 LAST_EMBED_REGNUM);
4322 fprintf_unfiltered (file,
4323 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4324 fprintf_unfiltered (file,
4325 "mips_dump_tdep: LO_REGNUM = %d\n",
4326 LO_REGNUM);
4327 #ifdef MACHINE_CPROC_FP_OFFSET
4328 fprintf_unfiltered (file,
4329 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4330 MACHINE_CPROC_FP_OFFSET);
4331 #endif
4332 #ifdef MACHINE_CPROC_PC_OFFSET
4333 fprintf_unfiltered (file,
4334 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4335 MACHINE_CPROC_PC_OFFSET);
4336 #endif
4337 #ifdef MACHINE_CPROC_SP_OFFSET
4338 fprintf_unfiltered (file,
4339 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4340 MACHINE_CPROC_SP_OFFSET);
4341 #endif
4342 fprintf_unfiltered (file,
4343 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4344 fprintf_unfiltered (file,
4345 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4346 fprintf_unfiltered (file,
4347 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4348 MIPS16_INSTLEN);
4349 fprintf_unfiltered (file,
4350 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4351 fprintf_unfiltered (file,
4352 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4353 fprintf_unfiltered (file,
4354 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4355 fprintf_unfiltered (file,
4356 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4357 MIPS_INSTLEN);
4358 fprintf_unfiltered (file,
4359 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4360 MIPS_LAST_ARG_REGNUM,
4361 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
4362 fprintf_unfiltered (file,
4363 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4364 MIPS_NUMREGS);
4365 fprintf_unfiltered (file,
4366 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4367 fprintf_unfiltered (file,
4368 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4369 MIPS_SAVED_REGSIZE);
4370 fprintf_unfiltered (file,
4371 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4372 fprintf_unfiltered (file,
4373 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4374 XSTRING (MSYMBOL_SIZE (MSYM)));
4375 fprintf_unfiltered (file,
4376 "mips_dump_tdep: OP_LDFPR = used?\n");
4377 fprintf_unfiltered (file,
4378 "mips_dump_tdep: OP_LDGPR = used?\n");
4379 fprintf_unfiltered (file,
4380 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4381 fprintf_unfiltered (file,
4382 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4383 fprintf_unfiltered (file,
4384 "mips_dump_tdep: PRID_REGNUM = %d\n",
4385 PRID_REGNUM);
4386 fprintf_unfiltered (file,
4387 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4388 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME)));
4389 fprintf_unfiltered (file,
4390 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4391 fprintf_unfiltered (file,
4392 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4393 fprintf_unfiltered (file,
4394 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4395 fprintf_unfiltered (file,
4396 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4397 fprintf_unfiltered (file,
4398 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4399 fprintf_unfiltered (file,
4400 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4401 fprintf_unfiltered (file,
4402 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4403 fprintf_unfiltered (file,
4404 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4405 fprintf_unfiltered (file,
4406 "mips_dump_tdep: PROC_PC_REG = function?\n");
4407 fprintf_unfiltered (file,
4408 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4409 fprintf_unfiltered (file,
4410 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4411 fprintf_unfiltered (file,
4412 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4413 fprintf_unfiltered (file,
4414 "mips_dump_tdep: PS_REGNUM = %d\n",
4415 PS_REGNUM);
4416 fprintf_unfiltered (file,
4417 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4418 PUSH_FP_REGNUM);
4419 fprintf_unfiltered (file,
4420 "mips_dump_tdep: RA_REGNUM = %d\n",
4421 RA_REGNUM);
4422 fprintf_unfiltered (file,
4423 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4424 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4425 fprintf_unfiltered (file,
4426 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4427 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER)));
4428 fprintf_unfiltered (file,
4429 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4430 fprintf_unfiltered (file,
4431 "mips_dump_tdep: ROUND_DOWN = function?\n");
4432 fprintf_unfiltered (file,
4433 "mips_dump_tdep: ROUND_UP = function?\n");
4434 #ifdef SAVED_BYTES
4435 fprintf_unfiltered (file,
4436 "mips_dump_tdep: SAVED_BYTES = %d\n",
4437 SAVED_BYTES);
4438 #endif
4439 #ifdef SAVED_FP
4440 fprintf_unfiltered (file,
4441 "mips_dump_tdep: SAVED_FP = %d\n",
4442 SAVED_FP);
4443 #endif
4444 #ifdef SAVED_PC
4445 fprintf_unfiltered (file,
4446 "mips_dump_tdep: SAVED_PC = %d\n",
4447 SAVED_PC);
4448 #endif
4449 fprintf_unfiltered (file,
4450 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4451 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
4452 fprintf_unfiltered (file,
4453 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4454 fprintf_unfiltered (file,
4455 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4456 SIGFRAME_BASE);
4457 fprintf_unfiltered (file,
4458 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4459 SIGFRAME_FPREGSAVE_OFF);
4460 fprintf_unfiltered (file,
4461 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4462 SIGFRAME_PC_OFF);
4463 fprintf_unfiltered (file,
4464 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4465 SIGFRAME_REGSAVE_OFF);
4466 fprintf_unfiltered (file,
4467 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4468 SIGFRAME_REG_SIZE);
4469 fprintf_unfiltered (file,
4470 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4471 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
4472 fprintf_unfiltered (file,
4473 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4474 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
4475 fprintf_unfiltered (file,
4476 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4477 SOFTWARE_SINGLE_STEP_P ());
4478 fprintf_unfiltered (file,
4479 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4480 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
4481 #ifdef STACK_END_ADDR
4482 fprintf_unfiltered (file,
4483 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4484 STACK_END_ADDR);
4485 #endif
4486 fprintf_unfiltered (file,
4487 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4488 XSTRING (STEP_SKIPS_DELAY (PC)));
4489 fprintf_unfiltered (file,
4490 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4491 STEP_SKIPS_DELAY_P);
4492 fprintf_unfiltered (file,
4493 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4494 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
4495 fprintf_unfiltered (file,
4496 "mips_dump_tdep: T9_REGNUM = %d\n",
4497 T9_REGNUM);
4498 fprintf_unfiltered (file,
4499 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4500 fprintf_unfiltered (file,
4501 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4502 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
4503 fprintf_unfiltered (file,
4504 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4505 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
4506 fprintf_unfiltered (file,
4507 "mips_dump_tdep: TARGET_MIPS = used?\n");
4508 fprintf_unfiltered (file,
4509 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4510 XSTRING (TM_PRINT_INSN_MACH));
4511 #ifdef TRACE_CLEAR
4512 fprintf_unfiltered (file,
4513 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4514 XSTRING (TRACE_CLEAR (THREAD, STATE)));
4515 #endif
4516 #ifdef TRACE_FLAVOR
4517 fprintf_unfiltered (file,
4518 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4519 TRACE_FLAVOR);
4520 #endif
4521 #ifdef TRACE_FLAVOR_SIZE
4522 fprintf_unfiltered (file,
4523 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4524 TRACE_FLAVOR_SIZE);
4525 #endif
4526 #ifdef TRACE_SET
4527 fprintf_unfiltered (file,
4528 "mips_dump_tdep: TRACE_SET # %s\n",
4529 XSTRING (TRACE_SET (X,STATE)));
4530 #endif
4531 fprintf_unfiltered (file,
4532 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4533 #ifdef UNUSED_REGNUM
4534 fprintf_unfiltered (file,
4535 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4536 UNUSED_REGNUM);
4537 #endif
4538 fprintf_unfiltered (file,
4539 "mips_dump_tdep: V0_REGNUM = %d\n",
4540 V0_REGNUM);
4541 fprintf_unfiltered (file,
4542 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4543 (long) VM_MIN_ADDRESS);
4544 #ifdef VX_NUM_REGS
4545 fprintf_unfiltered (file,
4546 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4547 VX_NUM_REGS);
4548 #endif
4549 fprintf_unfiltered (file,
4550 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4551 ZERO_REGNUM);
4552 fprintf_unfiltered (file,
4553 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4554 _PROC_MAGIC_);
4555 }
4556
4557 void
4558 _initialize_mips_tdep (void)
4559 {
4560 static struct cmd_list_element *mipsfpulist = NULL;
4561 struct cmd_list_element *c;
4562
4563 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
4564 if (!tm_print_insn) /* Someone may have already set it */
4565 tm_print_insn = gdb_print_insn_mips;
4566
4567 /* Add root prefix command for all "set mips"/"show mips" commands */
4568 add_prefix_cmd ("mips", no_class, set_mips_command,
4569 "Various MIPS specific commands.",
4570 &setmipscmdlist, "set mips ", 0, &setlist);
4571
4572 add_prefix_cmd ("mips", no_class, show_mips_command,
4573 "Various MIPS specific commands.",
4574 &showmipscmdlist, "show mips ", 0, &showlist);
4575
4576 /* Allow the user to override the saved register size. */
4577 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4578 class_obscure,
4579 size_enums,
4580 &mips_saved_regsize_string, "\
4581 Set size of general purpose registers saved on the stack.\n\
4582 This option can be set to one of:\n\
4583 32 - Force GDB to treat saved GP registers as 32-bit\n\
4584 64 - Force GDB to treat saved GP registers as 64-bit\n\
4585 auto - Allow GDB to use the target's default setting or autodetect the\n\
4586 saved GP register size from information contained in the executable.\n\
4587 (default: auto)",
4588 &setmipscmdlist),
4589 &showmipscmdlist);
4590
4591 /* Allow the user to override the argument stack size. */
4592 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4593 class_obscure,
4594 size_enums,
4595 &mips_stack_argsize_string, "\
4596 Set the amount of stack space reserved for each argument.\n\
4597 This option can be set to one of:\n\
4598 32 - Force GDB to allocate 32-bit chunks per argument\n\
4599 64 - Force GDB to allocate 64-bit chunks per argument\n\
4600 auto - Allow GDB to determine the correct setting from the current\n\
4601 target and executable (default)",
4602 &setmipscmdlist),
4603 &showmipscmdlist);
4604
4605 /* Let the user turn off floating point and set the fence post for
4606 heuristic_proc_start. */
4607
4608 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
4609 "Set use of MIPS floating-point coprocessor.",
4610 &mipsfpulist, "set mipsfpu ", 0, &setlist);
4611 add_cmd ("single", class_support, set_mipsfpu_single_command,
4612 "Select single-precision MIPS floating-point coprocessor.",
4613 &mipsfpulist);
4614 add_cmd ("double", class_support, set_mipsfpu_double_command,
4615 "Select double-precision MIPS floating-point coprocessor.",
4616 &mipsfpulist);
4617 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
4618 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
4619 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
4620 add_cmd ("none", class_support, set_mipsfpu_none_command,
4621 "Select no MIPS floating-point coprocessor.",
4622 &mipsfpulist);
4623 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
4624 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
4625 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
4626 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
4627 "Select MIPS floating-point coprocessor automatically.",
4628 &mipsfpulist);
4629 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
4630 "Show current use of MIPS floating-point coprocessor target.",
4631 &showlist);
4632
4633 #if !GDB_MULTI_ARCH
4634 c = add_set_cmd ("processor", class_support, var_string_noescape,
4635 (char *) &tmp_mips_processor_type,
4636 "Set the type of MIPS processor in use.\n\
4637 Set this to be able to access processor-type-specific registers.\n\
4638 ",
4639 &setlist);
4640 c->function.cfunc = mips_set_processor_type_command;
4641 c = add_show_from_set (c, &showlist);
4642 c->function.cfunc = mips_show_processor_type_command;
4643
4644 tmp_mips_processor_type = xstrdup (DEFAULT_MIPS_TYPE);
4645 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE), 0);
4646 #endif
4647
4648 /* We really would like to have both "0" and "unlimited" work, but
4649 command.c doesn't deal with that. So make it a var_zinteger
4650 because the user can always use "999999" or some such for unlimited. */
4651 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
4652 (char *) &heuristic_fence_post,
4653 "\
4654 Set the distance searched for the start of a function.\n\
4655 If you are debugging a stripped executable, GDB needs to search through the\n\
4656 program for the start of a function. This command sets the distance of the\n\
4657 search. The only need to set it is when debugging a stripped executable.",
4658 &setlist);
4659 /* We need to throw away the frame cache when we set this, since it
4660 might change our ability to get backtraces. */
4661 c->function.sfunc = reinit_frame_cache_sfunc;
4662 add_show_from_set (c, &showlist);
4663
4664 /* Allow the user to control whether the upper bits of 64-bit
4665 addresses should be zeroed. */
4666 c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var,
4667 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4668 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4669 the correct value.\n",
4670 &setmipscmdlist);
4671 add_cmd ("mask-address", no_class, show_mask_address,
4672 "Show current mask-address value", &showmipscmdlist);
4673
4674 /* Allow the user to control the size of 32 bit registers within the
4675 raw remote packet. */
4676 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4677 class_obscure,
4678 var_boolean,
4679 (char *)&mips64_transfers_32bit_regs_p, "\
4680 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4681 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4682 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4683 64 bits for others. Use \"off\" to disable compatibility mode",
4684 &setlist),
4685 &showlist);
4686
4687 /* Debug this files internals. */
4688 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
4689 &mips_debug, "Set mips debugging.\n\
4690 When non-zero, mips specific debugging is enabled.", &setdebuglist),
4691 &showdebuglist);
4692 }
4693
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