gdb/
[deliverable/binutils-gdb.git] / gdb / mn10300-tdep.c
1 /* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger.
2
3 Copyright (C) 1996-2005, 2007-2012 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "arch-utils.h"
22 #include "dis-asm.h"
23 #include "gdbtypes.h"
24 #include "regcache.h"
25 #include "gdb_string.h"
26 #include "gdb_assert.h"
27 #include "gdbcore.h" /* For write_memory_unsigned_integer. */
28 #include "value.h"
29 #include "gdbtypes.h"
30 #include "frame.h"
31 #include "frame-unwind.h"
32 #include "frame-base.h"
33 #include "symtab.h"
34 #include "dwarf2-frame.h"
35 #include "osabi.h"
36 #include "infcall.h"
37 #include "prologue-value.h"
38 #include "target.h"
39
40 #include "mn10300-tdep.h"
41
42
43 /* The am33-2 has 64 registers. */
44 #define MN10300_MAX_NUM_REGS 64
45
46 /* This structure holds the results of a prologue analysis. */
47 struct mn10300_prologue
48 {
49 /* The architecture for which we generated this prologue info. */
50 struct gdbarch *gdbarch;
51
52 /* The offset from the frame base to the stack pointer --- always
53 zero or negative.
54
55 Calling this a "size" is a bit misleading, but given that the
56 stack grows downwards, using offsets for everything keeps one
57 from going completely sign-crazy: you never change anything's
58 sign for an ADD instruction; always change the second operand's
59 sign for a SUB instruction; and everything takes care of
60 itself. */
61 int frame_size;
62
63 /* Non-zero if this function has initialized the frame pointer from
64 the stack pointer, zero otherwise. */
65 int has_frame_ptr;
66
67 /* If has_frame_ptr is non-zero, this is the offset from the frame
68 base to where the frame pointer points. This is always zero or
69 negative. */
70 int frame_ptr_offset;
71
72 /* The address of the first instruction at which the frame has been
73 set up and the arguments are where the debug info says they are
74 --- as best as we can tell. */
75 CORE_ADDR prologue_end;
76
77 /* reg_offset[R] is the offset from the CFA at which register R is
78 saved, or 1 if register R has not been saved. (Real values are
79 always zero or negative.) */
80 int reg_offset[MN10300_MAX_NUM_REGS];
81 };
82
83
84 /* Compute the alignment required by a type. */
85
86 static int
87 mn10300_type_align (struct type *type)
88 {
89 int i, align = 1;
90
91 switch (TYPE_CODE (type))
92 {
93 case TYPE_CODE_INT:
94 case TYPE_CODE_ENUM:
95 case TYPE_CODE_SET:
96 case TYPE_CODE_RANGE:
97 case TYPE_CODE_CHAR:
98 case TYPE_CODE_BOOL:
99 case TYPE_CODE_FLT:
100 case TYPE_CODE_PTR:
101 case TYPE_CODE_REF:
102 return TYPE_LENGTH (type);
103
104 case TYPE_CODE_COMPLEX:
105 return TYPE_LENGTH (type) / 2;
106
107 case TYPE_CODE_STRUCT:
108 case TYPE_CODE_UNION:
109 for (i = 0; i < TYPE_NFIELDS (type); i++)
110 {
111 int falign = mn10300_type_align (TYPE_FIELD_TYPE (type, i));
112 while (align < falign)
113 align <<= 1;
114 }
115 return align;
116
117 case TYPE_CODE_ARRAY:
118 /* HACK! Structures containing arrays, even small ones, are not
119 elligible for returning in registers. */
120 return 256;
121
122 case TYPE_CODE_TYPEDEF:
123 return mn10300_type_align (check_typedef (type));
124
125 default:
126 internal_error (__FILE__, __LINE__, _("bad switch"));
127 }
128 }
129
130 /* Should call_function allocate stack space for a struct return? */
131 static int
132 mn10300_use_struct_convention (struct type *type)
133 {
134 /* Structures bigger than a pair of words can't be returned in
135 registers. */
136 if (TYPE_LENGTH (type) > 8)
137 return 1;
138
139 switch (TYPE_CODE (type))
140 {
141 case TYPE_CODE_STRUCT:
142 case TYPE_CODE_UNION:
143 /* Structures with a single field are handled as the field
144 itself. */
145 if (TYPE_NFIELDS (type) == 1)
146 return mn10300_use_struct_convention (TYPE_FIELD_TYPE (type, 0));
147
148 /* Structures with word or double-word size are passed in memory, as
149 long as they require at least word alignment. */
150 if (mn10300_type_align (type) >= 4)
151 return 0;
152
153 return 1;
154
155 /* Arrays are addressable, so they're never returned in
156 registers. This condition can only hold when the array is
157 the only field of a struct or union. */
158 case TYPE_CODE_ARRAY:
159 return 1;
160
161 case TYPE_CODE_TYPEDEF:
162 return mn10300_use_struct_convention (check_typedef (type));
163
164 default:
165 return 0;
166 }
167 }
168
169 static void
170 mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type,
171 struct regcache *regcache, const void *valbuf)
172 {
173 int len = TYPE_LENGTH (type);
174 int reg, regsz;
175
176 if (TYPE_CODE (type) == TYPE_CODE_PTR)
177 reg = 4;
178 else
179 reg = 0;
180
181 regsz = register_size (gdbarch, reg);
182
183 if (len <= regsz)
184 regcache_raw_write_part (regcache, reg, 0, len, valbuf);
185 else if (len <= 2 * regsz)
186 {
187 regcache_raw_write (regcache, reg, valbuf);
188 gdb_assert (regsz == register_size (gdbarch, reg + 1));
189 regcache_raw_write_part (regcache, reg+1, 0,
190 len - regsz, (char *) valbuf + regsz);
191 }
192 else
193 internal_error (__FILE__, __LINE__,
194 _("Cannot store return value %d bytes long."), len);
195 }
196
197 static void
198 mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type,
199 struct regcache *regcache, void *valbuf)
200 {
201 char buf[MAX_REGISTER_SIZE];
202 int len = TYPE_LENGTH (type);
203 int reg, regsz;
204
205 if (TYPE_CODE (type) == TYPE_CODE_PTR)
206 reg = 4;
207 else
208 reg = 0;
209
210 regsz = register_size (gdbarch, reg);
211 if (len <= regsz)
212 {
213 regcache_raw_read (regcache, reg, buf);
214 memcpy (valbuf, buf, len);
215 }
216 else if (len <= 2 * regsz)
217 {
218 regcache_raw_read (regcache, reg, buf);
219 memcpy (valbuf, buf, regsz);
220 gdb_assert (regsz == register_size (gdbarch, reg + 1));
221 regcache_raw_read (regcache, reg + 1, buf);
222 memcpy ((char *) valbuf + regsz, buf, len - regsz);
223 }
224 else
225 internal_error (__FILE__, __LINE__,
226 _("Cannot extract return value %d bytes long."), len);
227 }
228
229 /* Determine, for architecture GDBARCH, how a return value of TYPE
230 should be returned. If it is supposed to be returned in registers,
231 and READBUF is non-zero, read the appropriate value from REGCACHE,
232 and copy it into READBUF. If WRITEBUF is non-zero, write the value
233 from WRITEBUF into REGCACHE. */
234
235 static enum return_value_convention
236 mn10300_return_value (struct gdbarch *gdbarch, struct value *function,
237 struct type *type, struct regcache *regcache,
238 gdb_byte *readbuf, const gdb_byte *writebuf)
239 {
240 if (mn10300_use_struct_convention (type))
241 return RETURN_VALUE_STRUCT_CONVENTION;
242
243 if (readbuf)
244 mn10300_extract_return_value (gdbarch, type, regcache, readbuf);
245 if (writebuf)
246 mn10300_store_return_value (gdbarch, type, regcache, writebuf);
247
248 return RETURN_VALUE_REGISTER_CONVENTION;
249 }
250
251 static char *
252 register_name (int reg, char **regs, long sizeof_regs)
253 {
254 if (reg < 0 || reg >= sizeof_regs / sizeof (regs[0]))
255 return NULL;
256 else
257 return regs[reg];
258 }
259
260 static const char *
261 mn10300_generic_register_name (struct gdbarch *gdbarch, int reg)
262 {
263 static char *regs[] =
264 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
265 "sp", "pc", "mdr", "psw", "lir", "lar", "", "",
266 "", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "fp"
268 };
269 return register_name (reg, regs, sizeof regs);
270 }
271
272
273 static const char *
274 am33_register_name (struct gdbarch *gdbarch, int reg)
275 {
276 static char *regs[] =
277 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
278 "sp", "pc", "mdr", "psw", "lir", "lar", "",
279 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
280 "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", ""
281 };
282 return register_name (reg, regs, sizeof regs);
283 }
284
285 static const char *
286 am33_2_register_name (struct gdbarch *gdbarch, int reg)
287 {
288 static char *regs[] =
289 {
290 "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
291 "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
292 "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
293 "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
294 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
295 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
296 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
297 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
298 };
299 return register_name (reg, regs, sizeof regs);
300 }
301
302 static struct type *
303 mn10300_register_type (struct gdbarch *gdbarch, int reg)
304 {
305 return builtin_type (gdbarch)->builtin_int;
306 }
307
308 static CORE_ADDR
309 mn10300_read_pc (struct regcache *regcache)
310 {
311 ULONGEST val;
312 regcache_cooked_read_unsigned (regcache, E_PC_REGNUM, &val);
313 return val;
314 }
315
316 static void
317 mn10300_write_pc (struct regcache *regcache, CORE_ADDR val)
318 {
319 regcache_cooked_write_unsigned (regcache, E_PC_REGNUM, val);
320 }
321
322 /* The breakpoint instruction must be the same size as the smallest
323 instruction in the instruction set.
324
325 The Matsushita mn10x00 processors have single byte instructions
326 so we need a single byte breakpoint. Matsushita hasn't defined
327 one, so we defined it ourselves. */
328
329 const static unsigned char *
330 mn10300_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
331 int *bp_size)
332 {
333 static char breakpoint[] = {0xff};
334 *bp_size = 1;
335 return breakpoint;
336 }
337
338 /* Model the semantics of pushing a register onto the stack. This
339 is a helper function for mn10300_analyze_prologue, below. */
340 static void
341 push_reg (pv_t *regs, struct pv_area *stack, int regnum)
342 {
343 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
344 pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[regnum]);
345 }
346
347 /* Translate an "r" register number extracted from an instruction encoding
348 into a GDB register number. Adapted from a simulator function
349 of the same name; see am33.igen. */
350 static int
351 translate_rreg (int rreg)
352 {
353 /* The higher register numbers actually correspond to the
354 basic machine's address and data registers. */
355 if (rreg > 7 && rreg < 12)
356 return E_A0_REGNUM + rreg - 8;
357 else if (rreg > 11 && rreg < 16)
358 return E_D0_REGNUM + rreg - 12;
359 else
360 return E_E0_REGNUM + rreg;
361 }
362
363 /* Find saved registers in a 'struct pv_area'; we pass this to pv_area_scan.
364
365 If VALUE is a saved register, ADDR says it was saved at a constant
366 offset from the frame base, and SIZE indicates that the whole
367 register was saved, record its offset in RESULT_UNTYPED. */
368 static void
369 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
370 {
371 struct mn10300_prologue *result = (struct mn10300_prologue *) result_untyped;
372
373 if (value.kind == pvk_register
374 && value.k == 0
375 && pv_is_register (addr, E_SP_REGNUM)
376 && size == register_size (result->gdbarch, value.reg))
377 result->reg_offset[value.reg] = addr.k;
378 }
379
380 /* Analyze the prologue to determine where registers are saved,
381 the end of the prologue, etc. The result of this analysis is
382 returned in RESULT. See struct mn10300_prologue above for more
383 information. */
384 static void
385 mn10300_analyze_prologue (struct gdbarch *gdbarch,
386 CORE_ADDR start_pc, CORE_ADDR limit_pc,
387 struct mn10300_prologue *result)
388 {
389 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
390 CORE_ADDR pc, next_pc;
391 int rn;
392 pv_t regs[MN10300_MAX_NUM_REGS];
393 struct pv_area *stack;
394 struct cleanup *back_to;
395 CORE_ADDR after_last_frame_setup_insn = start_pc;
396 int am33_mode = AM33_MODE (gdbarch);
397
398 memset (result, 0, sizeof (*result));
399 result->gdbarch = gdbarch;
400
401 for (rn = 0; rn < MN10300_MAX_NUM_REGS; rn++)
402 {
403 regs[rn] = pv_register (rn, 0);
404 result->reg_offset[rn] = 1;
405 }
406 stack = make_pv_area (E_SP_REGNUM, gdbarch_addr_bit (gdbarch));
407 back_to = make_cleanup_free_pv_area (stack);
408
409 /* The typical call instruction will have saved the return address on the
410 stack. Space for the return address has already been preallocated in
411 the caller's frame. It's possible, such as when using -mrelax with gcc
412 that other registers were saved as well. If this happens, we really
413 have no chance of deciphering the frame. DWARF info can save the day
414 when this happens. */
415 pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[E_PC_REGNUM]);
416
417 pc = start_pc;
418 while (pc < limit_pc)
419 {
420 int status;
421 gdb_byte instr[2];
422
423 /* Instructions can be as small as one byte; however, we usually
424 need at least two bytes to do the decoding, so fetch that many
425 to begin with. */
426 status = target_read_memory (pc, instr, 2);
427 if (status != 0)
428 break;
429
430 /* movm [regs], sp */
431 if (instr[0] == 0xcf)
432 {
433 gdb_byte save_mask;
434
435 save_mask = instr[1];
436
437 if ((save_mask & movm_exreg0_bit) && am33_mode)
438 {
439 push_reg (regs, stack, E_E2_REGNUM);
440 push_reg (regs, stack, E_E3_REGNUM);
441 }
442 if ((save_mask & movm_exreg1_bit) && am33_mode)
443 {
444 push_reg (regs, stack, E_E4_REGNUM);
445 push_reg (regs, stack, E_E5_REGNUM);
446 push_reg (regs, stack, E_E6_REGNUM);
447 push_reg (regs, stack, E_E7_REGNUM);
448 }
449 if ((save_mask & movm_exother_bit) && am33_mode)
450 {
451 push_reg (regs, stack, E_E0_REGNUM);
452 push_reg (regs, stack, E_E1_REGNUM);
453 push_reg (regs, stack, E_MDRQ_REGNUM);
454 push_reg (regs, stack, E_MCRH_REGNUM);
455 push_reg (regs, stack, E_MCRL_REGNUM);
456 push_reg (regs, stack, E_MCVF_REGNUM);
457 }
458 if (save_mask & movm_d2_bit)
459 push_reg (regs, stack, E_D2_REGNUM);
460 if (save_mask & movm_d3_bit)
461 push_reg (regs, stack, E_D3_REGNUM);
462 if (save_mask & movm_a2_bit)
463 push_reg (regs, stack, E_A2_REGNUM);
464 if (save_mask & movm_a3_bit)
465 push_reg (regs, stack, E_A3_REGNUM);
466 if (save_mask & movm_other_bit)
467 {
468 push_reg (regs, stack, E_D0_REGNUM);
469 push_reg (regs, stack, E_D1_REGNUM);
470 push_reg (regs, stack, E_A0_REGNUM);
471 push_reg (regs, stack, E_A1_REGNUM);
472 push_reg (regs, stack, E_MDR_REGNUM);
473 push_reg (regs, stack, E_LIR_REGNUM);
474 push_reg (regs, stack, E_LAR_REGNUM);
475 /* The `other' bit leaves a blank area of four bytes at
476 the beginning of its block of saved registers, making
477 it 32 bytes long in total. */
478 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
479 }
480
481 pc += 2;
482 after_last_frame_setup_insn = pc;
483 }
484 /* mov sp, aN */
485 else if ((instr[0] & 0xfc) == 0x3c)
486 {
487 int aN = instr[0] & 0x03;
488
489 regs[E_A0_REGNUM + aN] = regs[E_SP_REGNUM];
490
491 pc += 1;
492 if (aN == 3)
493 after_last_frame_setup_insn = pc;
494 }
495 /* mov aM, aN */
496 else if ((instr[0] & 0xf0) == 0x90
497 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
498 {
499 int aN = instr[0] & 0x03;
500 int aM = (instr[0] & 0x0c) >> 2;
501
502 regs[E_A0_REGNUM + aN] = regs[E_A0_REGNUM + aM];
503
504 pc += 1;
505 }
506 /* mov dM, dN */
507 else if ((instr[0] & 0xf0) == 0x80
508 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
509 {
510 int dN = instr[0] & 0x03;
511 int dM = (instr[0] & 0x0c) >> 2;
512
513 regs[E_D0_REGNUM + dN] = regs[E_D0_REGNUM + dM];
514
515 pc += 1;
516 }
517 /* mov aM, dN */
518 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xd0)
519 {
520 int dN = instr[1] & 0x03;
521 int aM = (instr[1] & 0x0c) >> 2;
522
523 regs[E_D0_REGNUM + dN] = regs[E_A0_REGNUM + aM];
524
525 pc += 2;
526 }
527 /* mov dM, aN */
528 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xe0)
529 {
530 int aN = instr[1] & 0x03;
531 int dM = (instr[1] & 0x0c) >> 2;
532
533 regs[E_A0_REGNUM + aN] = regs[E_D0_REGNUM + dM];
534
535 pc += 2;
536 }
537 /* add imm8, SP */
538 else if (instr[0] == 0xf8 && instr[1] == 0xfe)
539 {
540 gdb_byte buf[1];
541 LONGEST imm8;
542
543
544 status = target_read_memory (pc + 2, buf, 1);
545 if (status != 0)
546 break;
547
548 imm8 = extract_signed_integer (buf, 1, byte_order);
549 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm8);
550
551 pc += 3;
552 /* Stack pointer adjustments are frame related. */
553 after_last_frame_setup_insn = pc;
554 }
555 /* add imm16, SP */
556 else if (instr[0] == 0xfa && instr[1] == 0xfe)
557 {
558 gdb_byte buf[2];
559 LONGEST imm16;
560
561 status = target_read_memory (pc + 2, buf, 2);
562 if (status != 0)
563 break;
564
565 imm16 = extract_signed_integer (buf, 2, byte_order);
566 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm16);
567
568 pc += 4;
569 /* Stack pointer adjustments are frame related. */
570 after_last_frame_setup_insn = pc;
571 }
572 /* add imm32, SP */
573 else if (instr[0] == 0xfc && instr[1] == 0xfe)
574 {
575 gdb_byte buf[4];
576 LONGEST imm32;
577
578 status = target_read_memory (pc + 2, buf, 4);
579 if (status != 0)
580 break;
581
582
583 imm32 = extract_signed_integer (buf, 4, byte_order);
584 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm32);
585
586 pc += 6;
587 /* Stack pointer adjustments are frame related. */
588 after_last_frame_setup_insn = pc;
589 }
590 /* add imm8, aN */
591 else if ((instr[0] & 0xfc) == 0x20)
592 {
593 int aN;
594 LONGEST imm8;
595
596 aN = instr[0] & 0x03;
597 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
598
599 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
600 imm8);
601
602 pc += 2;
603 }
604 /* add imm16, aN */
605 else if (instr[0] == 0xfa && (instr[1] & 0xfc) == 0xd0)
606 {
607 int aN;
608 LONGEST imm16;
609 gdb_byte buf[2];
610
611 aN = instr[1] & 0x03;
612
613 status = target_read_memory (pc + 2, buf, 2);
614 if (status != 0)
615 break;
616
617
618 imm16 = extract_signed_integer (buf, 2, byte_order);
619
620 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
621 imm16);
622
623 pc += 4;
624 }
625 /* add imm32, aN */
626 else if (instr[0] == 0xfc && (instr[1] & 0xfc) == 0xd0)
627 {
628 int aN;
629 LONGEST imm32;
630 gdb_byte buf[4];
631
632 aN = instr[1] & 0x03;
633
634 status = target_read_memory (pc + 2, buf, 4);
635 if (status != 0)
636 break;
637
638 imm32 = extract_signed_integer (buf, 2, byte_order);
639
640 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
641 imm32);
642 pc += 6;
643 }
644 /* fmov fsM, (rN) */
645 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x30)
646 {
647 int fsM, sM, Y, rN;
648 gdb_byte buf[1];
649
650 Y = (instr[1] & 0x02) >> 1;
651
652 status = target_read_memory (pc + 2, buf, 1);
653 if (status != 0)
654 break;
655
656 sM = (buf[0] & 0xf0) >> 4;
657 rN = buf[0] & 0x0f;
658 fsM = (Y << 4) | sM;
659
660 pv_area_store (stack, regs[translate_rreg (rN)], 4,
661 regs[E_FS0_REGNUM + fsM]);
662
663 pc += 3;
664 }
665 /* fmov fsM, (sp) */
666 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x34)
667 {
668 int fsM, sM, Y;
669 gdb_byte buf[1];
670
671 Y = (instr[1] & 0x02) >> 1;
672
673 status = target_read_memory (pc + 2, buf, 1);
674 if (status != 0)
675 break;
676
677 sM = (buf[0] & 0xf0) >> 4;
678 fsM = (Y << 4) | sM;
679
680 pv_area_store (stack, regs[E_SP_REGNUM], 4,
681 regs[E_FS0_REGNUM + fsM]);
682
683 pc += 3;
684 }
685 /* fmov fsM, (rN, rI) */
686 else if (instr[0] == 0xfb && instr[1] == 0x37)
687 {
688 int fsM, sM, Z, rN, rI;
689 gdb_byte buf[2];
690
691
692 status = target_read_memory (pc + 2, buf, 2);
693 if (status != 0)
694 break;
695
696 rI = (buf[0] & 0xf0) >> 4;
697 rN = buf[0] & 0x0f;
698 sM = (buf[1] & 0xf0) >> 4;
699 Z = (buf[1] & 0x02) >> 1;
700 fsM = (Z << 4) | sM;
701
702 pv_area_store (stack,
703 pv_add (regs[translate_rreg (rN)],
704 regs[translate_rreg (rI)]),
705 4, regs[E_FS0_REGNUM + fsM]);
706
707 pc += 4;
708 }
709 /* fmov fsM, (d8, rN) */
710 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x30)
711 {
712 int fsM, sM, Y, rN;
713 LONGEST d8;
714 gdb_byte buf[2];
715
716 Y = (instr[1] & 0x02) >> 1;
717
718 status = target_read_memory (pc + 2, buf, 2);
719 if (status != 0)
720 break;
721
722 sM = (buf[0] & 0xf0) >> 4;
723 rN = buf[0] & 0x0f;
724 fsM = (Y << 4) | sM;
725 d8 = extract_signed_integer (&buf[1], 1, byte_order);
726
727 pv_area_store (stack,
728 pv_add_constant (regs[translate_rreg (rN)], d8),
729 4, regs[E_FS0_REGNUM + fsM]);
730
731 pc += 4;
732 }
733 /* fmov fsM, (d24, rN) */
734 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x30)
735 {
736 int fsM, sM, Y, rN;
737 LONGEST d24;
738 gdb_byte buf[4];
739
740 Y = (instr[1] & 0x02) >> 1;
741
742 status = target_read_memory (pc + 2, buf, 4);
743 if (status != 0)
744 break;
745
746 sM = (buf[0] & 0xf0) >> 4;
747 rN = buf[0] & 0x0f;
748 fsM = (Y << 4) | sM;
749 d24 = extract_signed_integer (&buf[1], 3, byte_order);
750
751 pv_area_store (stack,
752 pv_add_constant (regs[translate_rreg (rN)], d24),
753 4, regs[E_FS0_REGNUM + fsM]);
754
755 pc += 6;
756 }
757 /* fmov fsM, (d32, rN) */
758 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x30)
759 {
760 int fsM, sM, Y, rN;
761 LONGEST d32;
762 gdb_byte buf[5];
763
764 Y = (instr[1] & 0x02) >> 1;
765
766 status = target_read_memory (pc + 2, buf, 5);
767 if (status != 0)
768 break;
769
770 sM = (buf[0] & 0xf0) >> 4;
771 rN = buf[0] & 0x0f;
772 fsM = (Y << 4) | sM;
773 d32 = extract_signed_integer (&buf[1], 4, byte_order);
774
775 pv_area_store (stack,
776 pv_add_constant (regs[translate_rreg (rN)], d32),
777 4, regs[E_FS0_REGNUM + fsM]);
778
779 pc += 7;
780 }
781 /* fmov fsM, (d8, SP) */
782 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x34)
783 {
784 int fsM, sM, Y;
785 LONGEST d8;
786 gdb_byte buf[2];
787
788 Y = (instr[1] & 0x02) >> 1;
789
790 status = target_read_memory (pc + 2, buf, 2);
791 if (status != 0)
792 break;
793
794 sM = (buf[0] & 0xf0) >> 4;
795 fsM = (Y << 4) | sM;
796 d8 = extract_signed_integer (&buf[1], 1, byte_order);
797
798 pv_area_store (stack,
799 pv_add_constant (regs[E_SP_REGNUM], d8),
800 4, regs[E_FS0_REGNUM + fsM]);
801
802 pc += 4;
803 }
804 /* fmov fsM, (d24, SP) */
805 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x34)
806 {
807 int fsM, sM, Y;
808 LONGEST d24;
809 gdb_byte buf[4];
810
811 Y = (instr[1] & 0x02) >> 1;
812
813 status = target_read_memory (pc + 2, buf, 4);
814 if (status != 0)
815 break;
816
817 sM = (buf[0] & 0xf0) >> 4;
818 fsM = (Y << 4) | sM;
819 d24 = extract_signed_integer (&buf[1], 3, byte_order);
820
821 pv_area_store (stack,
822 pv_add_constant (regs[E_SP_REGNUM], d24),
823 4, regs[E_FS0_REGNUM + fsM]);
824
825 pc += 6;
826 }
827 /* fmov fsM, (d32, SP) */
828 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x34)
829 {
830 int fsM, sM, Y;
831 LONGEST d32;
832 gdb_byte buf[5];
833
834 Y = (instr[1] & 0x02) >> 1;
835
836 status = target_read_memory (pc + 2, buf, 5);
837 if (status != 0)
838 break;
839
840 sM = (buf[0] & 0xf0) >> 4;
841 fsM = (Y << 4) | sM;
842 d32 = extract_signed_integer (&buf[1], 4, byte_order);
843
844 pv_area_store (stack,
845 pv_add_constant (regs[E_SP_REGNUM], d32),
846 4, regs[E_FS0_REGNUM + fsM]);
847
848 pc += 7;
849 }
850 /* fmov fsM, (rN+) */
851 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x31)
852 {
853 int fsM, sM, Y, rN, rN_regnum;
854 gdb_byte buf[1];
855
856 Y = (instr[1] & 0x02) >> 1;
857
858 status = target_read_memory (pc + 2, buf, 1);
859 if (status != 0)
860 break;
861
862 sM = (buf[0] & 0xf0) >> 4;
863 rN = buf[0] & 0x0f;
864 fsM = (Y << 4) | sM;
865
866 rN_regnum = translate_rreg (rN);
867
868 pv_area_store (stack, regs[rN_regnum], 4,
869 regs[E_FS0_REGNUM + fsM]);
870 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], 4);
871
872 pc += 3;
873 }
874 /* fmov fsM, (rN+, imm8) */
875 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x31)
876 {
877 int fsM, sM, Y, rN, rN_regnum;
878 LONGEST imm8;
879 gdb_byte buf[2];
880
881 Y = (instr[1] & 0x02) >> 1;
882
883 status = target_read_memory (pc + 2, buf, 2);
884 if (status != 0)
885 break;
886
887 sM = (buf[0] & 0xf0) >> 4;
888 rN = buf[0] & 0x0f;
889 fsM = (Y << 4) | sM;
890 imm8 = extract_signed_integer (&buf[1], 1, byte_order);
891
892 rN_regnum = translate_rreg (rN);
893
894 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
895 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm8);
896
897 pc += 4;
898 }
899 /* fmov fsM, (rN+, imm24) */
900 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x31)
901 {
902 int fsM, sM, Y, rN, rN_regnum;
903 LONGEST imm24;
904 gdb_byte buf[4];
905
906 Y = (instr[1] & 0x02) >> 1;
907
908 status = target_read_memory (pc + 2, buf, 4);
909 if (status != 0)
910 break;
911
912 sM = (buf[0] & 0xf0) >> 4;
913 rN = buf[0] & 0x0f;
914 fsM = (Y << 4) | sM;
915 imm24 = extract_signed_integer (&buf[1], 3, byte_order);
916
917 rN_regnum = translate_rreg (rN);
918
919 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
920 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm24);
921
922 pc += 6;
923 }
924 /* fmov fsM, (rN+, imm32) */
925 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x31)
926 {
927 int fsM, sM, Y, rN, rN_regnum;
928 LONGEST imm32;
929 gdb_byte buf[5];
930
931 Y = (instr[1] & 0x02) >> 1;
932
933 status = target_read_memory (pc + 2, buf, 5);
934 if (status != 0)
935 break;
936
937 sM = (buf[0] & 0xf0) >> 4;
938 rN = buf[0] & 0x0f;
939 fsM = (Y << 4) | sM;
940 imm32 = extract_signed_integer (&buf[1], 4, byte_order);
941
942 rN_regnum = translate_rreg (rN);
943
944 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
945 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm32);
946
947 pc += 7;
948 }
949 /* mov imm8, aN */
950 else if ((instr[0] & 0xf0) == 0x90)
951 {
952 int aN = instr[0] & 0x03;
953 LONGEST imm8;
954
955 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
956
957 regs[E_A0_REGNUM + aN] = pv_constant (imm8);
958 pc += 2;
959 }
960 /* mov imm16, aN */
961 else if ((instr[0] & 0xfc) == 0x24)
962 {
963 int aN = instr[0] & 0x03;
964 gdb_byte buf[2];
965 LONGEST imm16;
966
967 status = target_read_memory (pc + 1, buf, 2);
968 if (status != 0)
969 break;
970
971 imm16 = extract_signed_integer (buf, 2, byte_order);
972 regs[E_A0_REGNUM + aN] = pv_constant (imm16);
973 pc += 3;
974 }
975 /* mov imm32, aN */
976 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xdc))
977 {
978 int aN = instr[1] & 0x03;
979 gdb_byte buf[4];
980 LONGEST imm32;
981
982 status = target_read_memory (pc + 2, buf, 4);
983 if (status != 0)
984 break;
985
986 imm32 = extract_signed_integer (buf, 4, byte_order);
987 regs[E_A0_REGNUM + aN] = pv_constant (imm32);
988 pc += 6;
989 }
990 /* mov imm8, dN */
991 else if ((instr[0] & 0xf0) == 0x80)
992 {
993 int dN = instr[0] & 0x03;
994 LONGEST imm8;
995
996 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
997
998 regs[E_D0_REGNUM + dN] = pv_constant (imm8);
999 pc += 2;
1000 }
1001 /* mov imm16, dN */
1002 else if ((instr[0] & 0xfc) == 0x2c)
1003 {
1004 int dN = instr[0] & 0x03;
1005 gdb_byte buf[2];
1006 LONGEST imm16;
1007
1008 status = target_read_memory (pc + 1, buf, 2);
1009 if (status != 0)
1010 break;
1011
1012 imm16 = extract_signed_integer (buf, 2, byte_order);
1013 regs[E_D0_REGNUM + dN] = pv_constant (imm16);
1014 pc += 3;
1015 }
1016 /* mov imm32, dN */
1017 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xcc))
1018 {
1019 int dN = instr[1] & 0x03;
1020 gdb_byte buf[4];
1021 LONGEST imm32;
1022
1023 status = target_read_memory (pc + 2, buf, 4);
1024 if (status != 0)
1025 break;
1026
1027 imm32 = extract_signed_integer (buf, 4, byte_order);
1028 regs[E_D0_REGNUM + dN] = pv_constant (imm32);
1029 pc += 6;
1030 }
1031 else
1032 {
1033 /* We've hit some instruction that we don't recognize. Hopefully,
1034 we have enough to do prologue analysis. */
1035 break;
1036 }
1037 }
1038
1039 /* Is the frame size (offset, really) a known constant? */
1040 if (pv_is_register (regs[E_SP_REGNUM], E_SP_REGNUM))
1041 result->frame_size = regs[E_SP_REGNUM].k;
1042
1043 /* Was the frame pointer initialized? */
1044 if (pv_is_register (regs[E_A3_REGNUM], E_SP_REGNUM))
1045 {
1046 result->has_frame_ptr = 1;
1047 result->frame_ptr_offset = regs[E_A3_REGNUM].k;
1048 }
1049
1050 /* Record where all the registers were saved. */
1051 pv_area_scan (stack, check_for_saved, (void *) result);
1052
1053 result->prologue_end = after_last_frame_setup_insn;
1054
1055 do_cleanups (back_to);
1056 }
1057
1058 /* Function: skip_prologue
1059 Return the address of the first inst past the prologue of the function. */
1060
1061 static CORE_ADDR
1062 mn10300_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1063 {
1064 const char *name;
1065 CORE_ADDR func_addr, func_end;
1066 struct mn10300_prologue p;
1067
1068 /* Try to find the extent of the function that contains PC. */
1069 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1070 return pc;
1071
1072 mn10300_analyze_prologue (gdbarch, pc, func_end, &p);
1073 return p.prologue_end;
1074 }
1075
1076 /* Wrapper for mn10300_analyze_prologue: find the function start;
1077 use the current frame PC as the limit, then
1078 invoke mn10300_analyze_prologue and return its result. */
1079 static struct mn10300_prologue *
1080 mn10300_analyze_frame_prologue (struct frame_info *this_frame,
1081 void **this_prologue_cache)
1082 {
1083 if (!*this_prologue_cache)
1084 {
1085 CORE_ADDR func_start, stop_addr;
1086
1087 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct mn10300_prologue);
1088
1089 func_start = get_frame_func (this_frame);
1090 stop_addr = get_frame_pc (this_frame);
1091
1092 /* If we couldn't find any function containing the PC, then
1093 just initialize the prologue cache, but don't do anything. */
1094 if (!func_start)
1095 stop_addr = func_start;
1096
1097 mn10300_analyze_prologue (get_frame_arch (this_frame),
1098 func_start, stop_addr, *this_prologue_cache);
1099 }
1100
1101 return *this_prologue_cache;
1102 }
1103
1104 /* Given the next frame and a prologue cache, return this frame's
1105 base. */
1106 static CORE_ADDR
1107 mn10300_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1108 {
1109 struct mn10300_prologue *p
1110 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1111
1112 /* In functions that use alloca, the distance between the stack
1113 pointer and the frame base varies dynamically, so we can't use
1114 the SP plus static information like prologue analysis to find the
1115 frame base. However, such functions must have a frame pointer,
1116 to be able to restore the SP on exit. So whenever we do have a
1117 frame pointer, use that to find the base. */
1118 if (p->has_frame_ptr)
1119 {
1120 CORE_ADDR fp = get_frame_register_unsigned (this_frame, E_A3_REGNUM);
1121 return fp - p->frame_ptr_offset;
1122 }
1123 else
1124 {
1125 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1126 return sp - p->frame_size;
1127 }
1128 }
1129
1130 /* Here is a dummy implementation. */
1131 static struct frame_id
1132 mn10300_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1133 {
1134 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1135 CORE_ADDR pc = get_frame_register_unsigned (this_frame, E_PC_REGNUM);
1136 return frame_id_build (sp, pc);
1137 }
1138
1139 static void
1140 mn10300_frame_this_id (struct frame_info *this_frame,
1141 void **this_prologue_cache,
1142 struct frame_id *this_id)
1143 {
1144 *this_id = frame_id_build (mn10300_frame_base (this_frame,
1145 this_prologue_cache),
1146 get_frame_func (this_frame));
1147
1148 }
1149
1150 static struct value *
1151 mn10300_frame_prev_register (struct frame_info *this_frame,
1152 void **this_prologue_cache, int regnum)
1153 {
1154 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1155 struct mn10300_prologue *p
1156 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1157 CORE_ADDR frame_base = mn10300_frame_base (this_frame, this_prologue_cache);
1158 int reg_size = register_size (get_frame_arch (this_frame), regnum);
1159
1160 if (regnum == E_SP_REGNUM)
1161 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1162
1163 /* If prologue analysis says we saved this register somewhere,
1164 return a description of the stack slot holding it. */
1165 if (p->reg_offset[regnum] != 1)
1166 return frame_unwind_got_memory (this_frame, regnum,
1167 frame_base + p->reg_offset[regnum]);
1168
1169 /* Otherwise, presume we haven't changed the value of this
1170 register, and get it from the next frame. */
1171 return frame_unwind_got_register (this_frame, regnum, regnum);
1172 }
1173
1174 static const struct frame_unwind mn10300_frame_unwind = {
1175 NORMAL_FRAME,
1176 default_frame_unwind_stop_reason,
1177 mn10300_frame_this_id,
1178 mn10300_frame_prev_register,
1179 NULL,
1180 default_frame_sniffer
1181 };
1182
1183 static CORE_ADDR
1184 mn10300_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1185 {
1186 ULONGEST pc;
1187
1188 pc = frame_unwind_register_unsigned (this_frame, E_PC_REGNUM);
1189 return pc;
1190 }
1191
1192 static CORE_ADDR
1193 mn10300_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1194 {
1195 ULONGEST sp;
1196
1197 sp = frame_unwind_register_unsigned (this_frame, E_SP_REGNUM);
1198 return sp;
1199 }
1200
1201 static void
1202 mn10300_frame_unwind_init (struct gdbarch *gdbarch)
1203 {
1204 dwarf2_append_unwinders (gdbarch);
1205 frame_unwind_append_unwinder (gdbarch, &mn10300_frame_unwind);
1206 set_gdbarch_dummy_id (gdbarch, mn10300_dummy_id);
1207 set_gdbarch_unwind_pc (gdbarch, mn10300_unwind_pc);
1208 set_gdbarch_unwind_sp (gdbarch, mn10300_unwind_sp);
1209 }
1210
1211 /* Function: push_dummy_call
1212 *
1213 * Set up machine state for a target call, including
1214 * function arguments, stack, return address, etc.
1215 *
1216 */
1217
1218 static CORE_ADDR
1219 mn10300_push_dummy_call (struct gdbarch *gdbarch,
1220 struct value *target_func,
1221 struct regcache *regcache,
1222 CORE_ADDR bp_addr,
1223 int nargs, struct value **args,
1224 CORE_ADDR sp,
1225 int struct_return,
1226 CORE_ADDR struct_addr)
1227 {
1228 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1229 const int push_size = register_size (gdbarch, E_PC_REGNUM);
1230 int regs_used;
1231 int len, arg_len;
1232 int stack_offset = 0;
1233 int argnum;
1234 char *val, valbuf[MAX_REGISTER_SIZE];
1235
1236 /* This should be a nop, but align the stack just in case something
1237 went wrong. Stacks are four byte aligned on the mn10300. */
1238 sp &= ~3;
1239
1240 /* Now make space on the stack for the args.
1241
1242 XXX This doesn't appear to handle pass-by-invisible reference
1243 arguments. */
1244 regs_used = struct_return ? 1 : 0;
1245 for (len = 0, argnum = 0; argnum < nargs; argnum++)
1246 {
1247 arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3;
1248 while (regs_used < 2 && arg_len > 0)
1249 {
1250 regs_used++;
1251 arg_len -= push_size;
1252 }
1253 len += arg_len;
1254 }
1255
1256 /* Allocate stack space. */
1257 sp -= len;
1258
1259 if (struct_return)
1260 {
1261 regs_used = 1;
1262 regcache_cooked_write_unsigned (regcache, E_D0_REGNUM, struct_addr);
1263 }
1264 else
1265 regs_used = 0;
1266
1267 /* Push all arguments onto the stack. */
1268 for (argnum = 0; argnum < nargs; argnum++)
1269 {
1270 /* FIXME what about structs? Unions? */
1271 if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT
1272 && TYPE_LENGTH (value_type (*args)) > 8)
1273 {
1274 /* Change to pointer-to-type. */
1275 arg_len = push_size;
1276 store_unsigned_integer (valbuf, push_size, byte_order,
1277 value_address (*args));
1278 val = &valbuf[0];
1279 }
1280 else
1281 {
1282 arg_len = TYPE_LENGTH (value_type (*args));
1283 val = (char *) value_contents (*args);
1284 }
1285
1286 while (regs_used < 2 && arg_len > 0)
1287 {
1288 regcache_cooked_write_unsigned (regcache, regs_used,
1289 extract_unsigned_integer (val, push_size, byte_order));
1290 val += push_size;
1291 arg_len -= push_size;
1292 regs_used++;
1293 }
1294
1295 while (arg_len > 0)
1296 {
1297 write_memory (sp + stack_offset, val, push_size);
1298 arg_len -= push_size;
1299 val += push_size;
1300 stack_offset += push_size;
1301 }
1302
1303 args++;
1304 }
1305
1306 /* Make space for the flushback area. */
1307 sp -= 8;
1308
1309 /* Push the return address that contains the magic breakpoint. */
1310 sp -= 4;
1311 write_memory_unsigned_integer (sp, push_size, byte_order, bp_addr);
1312
1313 /* The CPU also writes the return address always into the
1314 MDR register on "call". */
1315 regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr);
1316
1317 /* Update $sp. */
1318 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1319
1320 /* On the mn10300, it's possible to move some of the stack adjustment
1321 and saving of the caller-save registers out of the prologue and
1322 into the call sites. (When using gcc, this optimization can
1323 occur when using the -mrelax switch.) If this occurs, the dwarf2
1324 info will reflect this fact. We can test to see if this is the
1325 case by creating a new frame using the current stack pointer and
1326 the address of the function that we're about to call. We then
1327 unwind SP and see if it's different than the SP of our newly
1328 created frame. If the SP values are the same, the caller is not
1329 expected to allocate any additional stack. On the other hand, if
1330 the SP values are different, the difference determines the
1331 additional stack that must be allocated.
1332
1333 Note that we don't update the return value though because that's
1334 the value of the stack just after pushing the arguments, but prior
1335 to performing the call. This value is needed in order to
1336 construct the frame ID of the dummy call. */
1337 {
1338 CORE_ADDR func_addr = find_function_addr (target_func, NULL);
1339 CORE_ADDR unwound_sp
1340 = mn10300_unwind_sp (gdbarch, create_new_frame (sp, func_addr));
1341 if (sp != unwound_sp)
1342 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM,
1343 sp - (unwound_sp - sp));
1344 }
1345
1346 return sp;
1347 }
1348
1349 /* If DWARF2 is a register number appearing in Dwarf2 debug info, then
1350 mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB
1351 register number. Why don't Dwarf2 and GDB use the same numbering?
1352 Who knows? But since people have object files lying around with
1353 the existing Dwarf2 numbering, and other people have written stubs
1354 to work with the existing GDB, neither of them can change. So we
1355 just have to cope. */
1356 static int
1357 mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2)
1358 {
1359 /* This table is supposed to be shaped like the gdbarch_register_name
1360 initializer in gcc/config/mn10300/mn10300.h. Registers which
1361 appear in GCC's numbering, but have no counterpart in GDB's
1362 world, are marked with a -1. */
1363 static int dwarf2_to_gdb[] = {
1364 0, 1, 2, 3, 4, 5, 6, 7, -1, 8,
1365 15, 16, 17, 18, 19, 20, 21, 22,
1366 32, 33, 34, 35, 36, 37, 38, 39,
1367 40, 41, 42, 43, 44, 45, 46, 47,
1368 48, 49, 50, 51, 52, 53, 54, 55,
1369 56, 57, 58, 59, 60, 61, 62, 63,
1370 9, 11
1371 };
1372
1373 if (dwarf2 < 0
1374 || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb))
1375 {
1376 warning (_("Bogus register number in debug info: %d"), dwarf2);
1377 return -1;
1378 }
1379
1380 return dwarf2_to_gdb[dwarf2];
1381 }
1382
1383 static struct gdbarch *
1384 mn10300_gdbarch_init (struct gdbarch_info info,
1385 struct gdbarch_list *arches)
1386 {
1387 struct gdbarch *gdbarch;
1388 struct gdbarch_tdep *tdep;
1389 int num_regs;
1390
1391 arches = gdbarch_list_lookup_by_info (arches, &info);
1392 if (arches != NULL)
1393 return arches->gdbarch;
1394
1395 tdep = xmalloc (sizeof (struct gdbarch_tdep));
1396 gdbarch = gdbarch_alloc (&info, tdep);
1397
1398 switch (info.bfd_arch_info->mach)
1399 {
1400 case 0:
1401 case bfd_mach_mn10300:
1402 set_gdbarch_register_name (gdbarch, mn10300_generic_register_name);
1403 tdep->am33_mode = 0;
1404 num_regs = 32;
1405 break;
1406 case bfd_mach_am33:
1407 set_gdbarch_register_name (gdbarch, am33_register_name);
1408 tdep->am33_mode = 1;
1409 num_regs = 32;
1410 break;
1411 case bfd_mach_am33_2:
1412 set_gdbarch_register_name (gdbarch, am33_2_register_name);
1413 tdep->am33_mode = 2;
1414 num_regs = 64;
1415 set_gdbarch_fp0_regnum (gdbarch, 32);
1416 break;
1417 default:
1418 internal_error (__FILE__, __LINE__,
1419 _("mn10300_gdbarch_init: Unknown mn10300 variant"));
1420 break;
1421 }
1422
1423 /* By default, chars are unsigned. */
1424 set_gdbarch_char_signed (gdbarch, 0);
1425
1426 /* Registers. */
1427 set_gdbarch_num_regs (gdbarch, num_regs);
1428 set_gdbarch_register_type (gdbarch, mn10300_register_type);
1429 set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue);
1430 set_gdbarch_read_pc (gdbarch, mn10300_read_pc);
1431 set_gdbarch_write_pc (gdbarch, mn10300_write_pc);
1432 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1433 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1434 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum);
1435
1436 /* Stack unwinding. */
1437 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1438 /* Breakpoints. */
1439 set_gdbarch_breakpoint_from_pc (gdbarch, mn10300_breakpoint_from_pc);
1440 /* decr_pc_after_break? */
1441 /* Disassembly. */
1442 set_gdbarch_print_insn (gdbarch, print_insn_mn10300);
1443
1444 /* Stage 2 */
1445 set_gdbarch_return_value (gdbarch, mn10300_return_value);
1446
1447 /* Stage 3 -- get target calls working. */
1448 set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call);
1449 /* set_gdbarch_return_value (store, extract) */
1450
1451
1452 mn10300_frame_unwind_init (gdbarch);
1453
1454 /* Hook in ABI-specific overrides, if they have been registered. */
1455 gdbarch_init_osabi (info, gdbarch);
1456
1457 return gdbarch;
1458 }
1459
1460 /* Dump out the mn10300 specific architecture information. */
1461
1462 static void
1463 mn10300_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
1464 {
1465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1466 fprintf_unfiltered (file, "mn10300_dump_tdep: am33_mode = %d\n",
1467 tdep->am33_mode);
1468 }
1469
1470 /* Provide a prototype to silence -Wmissing-prototypes. */
1471 extern initialize_file_ftype _initialize_mn10300_tdep;
1472
1473 void
1474 _initialize_mn10300_tdep (void)
1475 {
1476 gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep);
1477 }
1478
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