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Delegate opcodes to select disassembler in GDB
[deliverable/binutils-gdb.git] / gdb / nds32-tdep.c
1 /* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2017 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "defs.h"
22 #include "frame.h"
23 #include "frame-unwind.h"
24 #include "frame-base.h"
25 #include "symtab.h"
26 #include "gdbtypes.h"
27 #include "gdbcore.h"
28 #include "value.h"
29 #include "reggroups.h"
30 #include "inferior.h"
31 #include "osabi.h"
32 #include "arch-utils.h"
33 #include "regcache.h"
34 #include "dis-asm.h"
35 #include "user-regs.h"
36 #include "elf-bfd.h"
37 #include "dwarf2-frame.h"
38 #include "remote.h"
39 #include "target-descriptions.h"
40
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
44 #include <algorithm>
45
46 #include "features/nds32.c"
47
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
51 #define N32_SMW_ADM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
53 #define N32_LMW_BIM \
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
55 #define N32_FLDI_SP \
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
57
58 extern void _initialize_nds32_tdep (void);
59
60 /* Use an invalid address value as 'not available' marker. */
61 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
62
63 /* Use an impossible value as invalid offset. */
64 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
65
66 /* Instruction groups for NDS32 epilogue analysis. */
67 enum
68 {
69 /* Instructions used everywhere, not only in epilogue. */
70 INSN_NORMAL,
71 /* Instructions used to reset sp for local vars, arguments, etc. */
72 INSN_RESET_SP,
73 /* Instructions used to recover saved regs and to recover padding. */
74 INSN_RECOVER,
75 /* Instructions used to return to the caller. */
76 INSN_RETURN,
77 /* Instructions used to recover saved regs and to return to the caller. */
78 INSN_RECOVER_RETURN,
79 };
80
81 static const char *const nds32_register_names[] =
82 {
83 /* 32 GPRs. */
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
88 /* PC. */
89 "pc",
90 };
91
92 static const char *const nds32_fdr_register_names[] =
93 {
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 };
99
100 static const char *const nds32_fsr_register_names[] =
101 {
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 };
107
108 /* The number of registers for four FPU configuration options. */
109 const int num_fdr_map[] = { 4, 8, 16, 32 };
110 const int num_fsr_map[] = { 8, 16, 32, 32 };
111
112 /* Aliases for registers. */
113 static const struct
114 {
115 const char *name;
116 const char *alias;
117 } nds32_register_aliases[] =
118 {
119 {"r15", "ta"},
120 {"r26", "p0"},
121 {"r27", "p1"},
122 {"fp", "r28"},
123 {"gp", "r29"},
124 {"lp", "r30"},
125 {"sp", "r31"},
126
127 {"cr0", "cpu_ver"},
128 {"cr1", "icm_cfg"},
129 {"cr2", "dcm_cfg"},
130 {"cr3", "mmu_cfg"},
131 {"cr4", "msc_cfg"},
132 {"cr5", "core_id"},
133 {"cr6", "fucop_exist"},
134 {"cr7", "msc_cfg2"},
135
136 {"ir0", "psw"},
137 {"ir1", "ipsw"},
138 {"ir2", "p_psw"},
139 {"ir3", "ivb"},
140 {"ir4", "eva"},
141 {"ir5", "p_eva"},
142 {"ir6", "itype"},
143 {"ir7", "p_itype"},
144 {"ir8", "merr"},
145 {"ir9", "ipc"},
146 {"ir10", "p_ipc"},
147 {"ir11", "oipc"},
148 {"ir12", "p_p0"},
149 {"ir13", "p_p1"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
152 {"ir16", "sp_usr"},
153 {"ir17", "sp_priv"},
154 {"ir18", "int_pri"},
155 {"ir19", "int_ctrl"},
156 {"ir20", "sp_usr1"},
157 {"ir21", "sp_priv1"},
158 {"ir22", "sp_usr2"},
159 {"ir23", "sp_priv2"},
160 {"ir24", "sp_usr3"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
166
167 {"mr0", "mmu_ctl"},
168 {"mr1", "l1_pptb"},
169 {"mr2", "tlb_vpn"},
170 {"mr3", "tlb_data"},
171 {"mr4", "tlb_misc"},
172 {"mr5", "vlpt_idx"},
173 {"mr6", "ilmb"},
174 {"mr7", "dlmb"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
179
180 {"dr0", "bpc0"},
181 {"dr1", "bpc1"},
182 {"dr2", "bpc2"},
183 {"dr3", "bpc3"},
184 {"dr4", "bpc4"},
185 {"dr5", "bpc5"},
186 {"dr6", "bpc6"},
187 {"dr7", "bpc7"},
188 {"dr8", "bpa0"},
189 {"dr9", "bpa1"},
190 {"dr10", "bpa2"},
191 {"dr11", "bpa3"},
192 {"dr12", "bpa4"},
193 {"dr13", "bpa5"},
194 {"dr14", "bpa6"},
195 {"dr15", "bpa7"},
196 {"dr16", "bpam0"},
197 {"dr17", "bpam1"},
198 {"dr18", "bpam2"},
199 {"dr19", "bpam3"},
200 {"dr20", "bpam4"},
201 {"dr21", "bpam5"},
202 {"dr22", "bpam6"},
203 {"dr23", "bpam7"},
204 {"dr24", "bpv0"},
205 {"dr25", "bpv1"},
206 {"dr26", "bpv2"},
207 {"dr27", "bpv3"},
208 {"dr28", "bpv4"},
209 {"dr29", "bpv5"},
210 {"dr30", "bpv6"},
211 {"dr31", "bpv7"},
212 {"dr32", "bpcid0"},
213 {"dr33", "bpcid1"},
214 {"dr34", "bpcid2"},
215 {"dr35", "bpcid3"},
216 {"dr36", "bpcid4"},
217 {"dr37", "bpcid5"},
218 {"dr38", "bpcid6"},
219 {"dr39", "bpcid7"},
220 {"dr40", "edm_cfg"},
221 {"dr41", "edmsw"},
222 {"dr42", "edm_ctl"},
223 {"dr43", "edm_dtr"},
224 {"dr44", "bpmtc"},
225 {"dr45", "dimbr"},
226 {"dr46", "tecr0"},
227 {"dr47", "tecr1"},
228
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
232
233 {"pfr0", "pfmc0"},
234 {"pfr1", "pfmc1"},
235 {"pfr2", "pfmc2"},
236 {"pfr3", "pfm_ctl"},
237 {"pfr4", "pft_ctl"},
238
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
252
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
255
256 {"idr0", "sdz_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
259
260 {"secur0", "sfcr"},
261 {"secur1", "sign"},
262 {"secur2", "isign"},
263 {"secur3", "p_isign"},
264 };
265
266 /* Value of a register alias. BATON is the regnum of the corresponding
267 register. */
268
269 static struct value *
270 value_of_nds32_reg (struct frame_info *frame, const void *baton)
271 {
272 return value_of_register ((int) (intptr_t) baton, frame);
273 }
274 \f
275 /* Implement the "frame_align" gdbarch method. */
276
277 static CORE_ADDR
278 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
279 {
280 /* 8-byte aligned. */
281 return align_down (sp, 8);
282 }
283
284 /* The same insn machine code is used for little-endian and big-endian. */
285 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
286
287 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
288
289 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
290
291 static int
292 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
293 {
294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
295 const int FSR = 38;
296 const int FDR = FSR + 32;
297
298 if (num >= 0 && num < 32)
299 {
300 /* General-purpose registers (R0 - R31). */
301 return num;
302 }
303 else if (num >= FSR && num < FSR + 32)
304 {
305 /* Single precision floating-point registers (FS0 - FS31). */
306 return num - FSR + tdep->fs0_regnum;
307 }
308 else if (num >= FDR && num < FDR + 32)
309 {
310 /* Double precision floating-point registers (FD0 - FD31). */
311 return num - FDR + NDS32_FD0_REGNUM;
312 }
313
314 /* No match, return a inaccessible register number. */
315 return -1;
316 }
317 \f
318 /* NDS32 register groups. */
319 static struct reggroup *nds32_cr_reggroup;
320 static struct reggroup *nds32_ir_reggroup;
321 static struct reggroup *nds32_mr_reggroup;
322 static struct reggroup *nds32_dr_reggroup;
323 static struct reggroup *nds32_pfr_reggroup;
324 static struct reggroup *nds32_hspr_reggroup;
325 static struct reggroup *nds32_dmar_reggroup;
326 static struct reggroup *nds32_racr_reggroup;
327 static struct reggroup *nds32_idr_reggroup;
328 static struct reggroup *nds32_secur_reggroup;
329
330 static void
331 nds32_init_reggroups (void)
332 {
333 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
334 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
335 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
336 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
337 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
338 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
339 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
340 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
341 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
342 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
343 }
344
345 static void
346 nds32_add_reggroups (struct gdbarch *gdbarch)
347 {
348 /* Add pre-defined register groups. */
349 reggroup_add (gdbarch, general_reggroup);
350 reggroup_add (gdbarch, float_reggroup);
351 reggroup_add (gdbarch, system_reggroup);
352 reggroup_add (gdbarch, all_reggroup);
353 reggroup_add (gdbarch, save_reggroup);
354 reggroup_add (gdbarch, restore_reggroup);
355
356 /* Add NDS32 register groups. */
357 reggroup_add (gdbarch, nds32_cr_reggroup);
358 reggroup_add (gdbarch, nds32_ir_reggroup);
359 reggroup_add (gdbarch, nds32_mr_reggroup);
360 reggroup_add (gdbarch, nds32_dr_reggroup);
361 reggroup_add (gdbarch, nds32_pfr_reggroup);
362 reggroup_add (gdbarch, nds32_hspr_reggroup);
363 reggroup_add (gdbarch, nds32_dmar_reggroup);
364 reggroup_add (gdbarch, nds32_racr_reggroup);
365 reggroup_add (gdbarch, nds32_idr_reggroup);
366 reggroup_add (gdbarch, nds32_secur_reggroup);
367 }
368
369 /* Implement the "register_reggroup_p" gdbarch method. */
370
371 static int
372 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
373 struct reggroup *reggroup)
374 {
375 const char *reg_name;
376 const char *group_name;
377 int ret;
378
379 if (reggroup == all_reggroup)
380 return 1;
381
382 /* General reggroup contains only GPRs and PC. */
383 if (reggroup == general_reggroup)
384 return regnum <= NDS32_PC_REGNUM;
385
386 if (reggroup == float_reggroup || reggroup == save_reggroup
387 || reggroup == restore_reggroup)
388 {
389 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
390 if (ret != -1)
391 return ret;
392
393 return default_register_reggroup_p (gdbarch, regnum, reggroup);
394 }
395
396 if (reggroup == system_reggroup)
397 return (regnum > NDS32_PC_REGNUM)
398 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
399
400 /* The NDS32 reggroup contains registers whose name is prefixed
401 by reggroup name. */
402 reg_name = gdbarch_register_name (gdbarch, regnum);
403 group_name = reggroup_name (reggroup);
404 return !strncmp (reg_name, group_name, strlen (group_name));
405 }
406 \f
407 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
408
409 static struct type *
410 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
411 {
412 regnum -= gdbarch_num_regs (gdbarch);
413
414 /* Currently, only FSRs could be defined as pseudo registers. */
415 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
416 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
417 floatformats_ieee_single);
418
419 warning (_("Unknown nds32 pseudo register %d."), regnum);
420 return NULL;
421 }
422
423 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
424
425 static const char *
426 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
427 {
428 regnum -= gdbarch_num_regs (gdbarch);
429
430 /* Currently, only FSRs could be defined as pseudo registers. */
431 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
432 return nds32_fsr_register_names[regnum];
433
434 warning (_("Unknown nds32 pseudo register %d."), regnum);
435 return NULL;
436 }
437
438 /* Implement the "pseudo_register_read" gdbarch method. */
439
440 static enum register_status
441 nds32_pseudo_register_read (struct gdbarch *gdbarch,
442 struct regcache *regcache, int regnum,
443 gdb_byte *buf)
444 {
445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
446 gdb_byte reg_buf[8];
447 int offset, fdr_regnum;
448 enum register_status status;
449
450 /* This function is registered in nds32_gdbarch_init only after these are
451 set. */
452 gdb_assert (tdep->fpu_freg != -1);
453 gdb_assert (tdep->use_pseudo_fsrs != 0);
454
455 regnum -= gdbarch_num_regs (gdbarch);
456
457 /* Currently, only FSRs could be defined as pseudo registers. */
458 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
459 {
460 /* fs0 is always the most significant half of fd0. */
461 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
462 offset = (regnum & 1) ? 4 : 0;
463 else
464 offset = (regnum & 1) ? 0 : 4;
465
466 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
467 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
468 if (status == REG_VALID)
469 memcpy (buf, reg_buf + offset, 4);
470
471 return status;
472 }
473
474 gdb_assert_not_reached ("invalid pseudo register number");
475 }
476
477 /* Implement the "pseudo_register_write" gdbarch method. */
478
479 static void
480 nds32_pseudo_register_write (struct gdbarch *gdbarch,
481 struct regcache *regcache, int regnum,
482 const gdb_byte *buf)
483 {
484 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
485 gdb_byte reg_buf[8];
486 int offset, fdr_regnum;
487
488 /* This function is registered in nds32_gdbarch_init only after these are
489 set. */
490 gdb_assert (tdep->fpu_freg != -1);
491 gdb_assert (tdep->use_pseudo_fsrs != 0);
492
493 regnum -= gdbarch_num_regs (gdbarch);
494
495 /* Currently, only FSRs could be defined as pseudo registers. */
496 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
497 {
498 /* fs0 is always the most significant half of fd0. */
499 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
500 offset = (regnum & 1) ? 4 : 0;
501 else
502 offset = (regnum & 1) ? 0 : 4;
503
504 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
505 regcache_raw_read (regcache, fdr_regnum, reg_buf);
506 memcpy (reg_buf + offset, buf, 4);
507 regcache_raw_write (regcache, fdr_regnum, reg_buf);
508 return;
509 }
510
511 gdb_assert_not_reached ("invalid pseudo register number");
512 }
513 \f
514 /* Helper function for NDS32 ABI. Return true if FPRs can be used
515 to pass function arguments and return value. */
516
517 static int
518 nds32_abi_use_fpr (int elf_abi)
519 {
520 return elf_abi == E_NDS_ABI_V2FP_PLUS;
521 }
522
523 /* Helper function for NDS32 ABI. Return true if GPRs and stack
524 can be used together to pass an argument. */
525
526 static int
527 nds32_abi_split (int elf_abi)
528 {
529 return elf_abi == E_NDS_ABI_AABI;
530 }
531
532 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
533
534 struct nds32_frame_cache
535 {
536 /* The previous frame's inner most stack address. Used as this
537 frame ID's stack_addr. */
538 CORE_ADDR prev_sp;
539
540 /* The frame's base, optionally used by the high-level debug info. */
541 CORE_ADDR base;
542
543 /* During prologue analysis, keep how far the SP and FP have been offset
544 from the start of the stack frame (as defined by the previous frame's
545 stack pointer).
546 During epilogue analysis, keep how far the SP has been offset from the
547 current stack pointer. */
548 CORE_ADDR sp_offset;
549 CORE_ADDR fp_offset;
550
551 /* The address of the first instruction in this function. */
552 CORE_ADDR pc;
553
554 /* Saved registers. */
555 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
556 };
557
558 /* Allocate and initialize a frame cache. */
559
560 static struct nds32_frame_cache *
561 nds32_alloc_frame_cache (void)
562 {
563 struct nds32_frame_cache *cache;
564 int i;
565
566 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
567
568 /* Initialize fp_offset to check if FP is set in prologue. */
569 cache->fp_offset = INVALID_OFFSET;
570
571 /* Saved registers. We initialize these to -1 since zero is a valid
572 offset. */
573 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
574 cache->saved_regs[i] = REG_UNAVAIL;
575
576 return cache;
577 }
578
579 /* Helper function for instructions used to push multiple words. */
580
581 static void
582 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
583 int enable4)
584 {
585 CORE_ADDR sp_offset = cache->sp_offset;
586 int i;
587
588 /* Check LP, GP, FP in enable4. */
589 for (i = 1; i <= 3; i++)
590 {
591 if ((enable4 >> i) & 0x1)
592 {
593 sp_offset += 4;
594 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
595 }
596 }
597
598 /* Skip case where re == rb == sp. */
599 if ((rb < REG_FP) && (re < REG_FP))
600 {
601 for (i = re; i >= rb; i--)
602 {
603 sp_offset += 4;
604 cache->saved_regs[i] = sp_offset;
605 }
606 }
607
608 /* For sp, update the offset. */
609 cache->sp_offset = sp_offset;
610 }
611
612 /* Analyze the instructions within the given address range. If CACHE
613 is non-NULL, fill it in. Return the first address beyond the given
614 address range. If CACHE is NULL, return the first address not
615 recognized as a prologue instruction. */
616
617 static CORE_ADDR
618 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
619 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
620 {
621 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
622 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
623 /* Current scanning status. */
624 int in_prologue_bb = 0;
625 int val_ta = 0;
626 uint32_t insn, insn_len;
627
628 for (; pc < limit_pc; pc += insn_len)
629 {
630 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
631
632 if ((insn & 0x80000000) == 0)
633 {
634 /* 32-bit instruction */
635 insn_len = 4;
636
637 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
638 {
639 /* addi $sp, $sp, imm15s */
640 int imm15s = N32_IMM15S (insn);
641
642 if (imm15s < 0)
643 {
644 if (cache != NULL)
645 cache->sp_offset += -imm15s;
646
647 in_prologue_bb = 1;
648 continue;
649 }
650 }
651 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
652 {
653 /* addi $fp, $sp, imm15s */
654 int imm15s = N32_IMM15S (insn);
655
656 if (imm15s > 0)
657 {
658 if (cache != NULL)
659 cache->fp_offset = cache->sp_offset - imm15s;
660
661 in_prologue_bb = 1;
662 continue;
663 }
664 }
665 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
666 && N32_RA5 (insn) == REG_SP)
667 {
668 /* smw.adm Rb, [$sp], Re, enable4 */
669 if (cache != NULL)
670 nds32_push_multiple_words (cache, N32_RT5 (insn),
671 N32_RB5 (insn),
672 N32_LSMW_ENABLE4 (insn));
673 in_prologue_bb = 1;
674 continue;
675 }
676 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
677 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
678 {
679 /* add $sp, $sp, $ta */
680 /* add $sp, $ta, $sp */
681 if (val_ta < 0)
682 {
683 if (cache != NULL)
684 cache->sp_offset += -val_ta;
685
686 in_prologue_bb = 1;
687 continue;
688 }
689 }
690 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
691 {
692 /* movi $ta, imm20s */
693 if (cache != NULL)
694 val_ta = N32_IMM20S (insn);
695
696 continue;
697 }
698 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
699 {
700 /* sethi $ta, imm20u */
701 if (cache != NULL)
702 val_ta = N32_IMM20U (insn) << 12;
703
704 continue;
705 }
706 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
707 {
708 /* ori $ta, $ta, imm15u */
709 if (cache != NULL)
710 val_ta |= N32_IMM15U (insn);
711
712 continue;
713 }
714 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
715 {
716 /* addi $ta, $ta, imm15s */
717 if (cache != NULL)
718 val_ta += N32_IMM15S (insn);
719
720 continue;
721 }
722 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
723 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
724 {
725 /* add $gp, $ta, $gp */
726 /* add $gp, $gp, $ta */
727 in_prologue_bb = 1;
728 continue;
729 }
730 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
731 {
732 /* movi $gp, imm20s */
733 in_prologue_bb = 1;
734 continue;
735 }
736 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
737 {
738 /* sethi $gp, imm20u */
739 in_prologue_bb = 1;
740 continue;
741 }
742 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
743 {
744 /* ori $gp, $gp, imm15u */
745 in_prologue_bb = 1;
746 continue;
747 }
748 else
749 {
750 /* Jump/Branch insns never appear in prologue basic block.
751 The loop can be escaped early when these insns are met. */
752 if (in_prologue_bb == 1)
753 {
754 int op = N32_OP6 (insn);
755
756 if (op == N32_OP6_JI
757 || op == N32_OP6_JREG
758 || op == N32_OP6_BR1
759 || op == N32_OP6_BR2
760 || op == N32_OP6_BR3)
761 break;
762 }
763 }
764
765 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
766 && __GF (insn, 12, 3) == 0)
767 {
768 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
769 normal form (bit [12] == 0) is used. */
770
771 /* fsdi FDt, [$sp + (imm12s << 2)] */
772 if (N32_RA5 (insn) == REG_SP)
773 continue;
774 }
775
776 /* The optimizer might shove anything into the prologue, if
777 we build up cache (cache != NULL) from analyzing prologue,
778 we just skip what we don't recognize and analyze further to
779 make cache as complete as possible. However, if we skip
780 prologue, we'll stop immediately on unrecognized
781 instruction. */
782 if (cache == NULL)
783 break;
784 }
785 else
786 {
787 /* 16-bit instruction */
788 insn_len = 2;
789
790 insn >>= 16;
791
792 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
793 {
794 /* addi10s.sp */
795 int imm10s = N16_IMM10S (insn);
796
797 if (imm10s < 0)
798 {
799 if (cache != NULL)
800 cache->sp_offset += -imm10s;
801
802 in_prologue_bb = 1;
803 continue;
804 }
805 }
806 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
807 {
808 /* push25 */
809 if (cache != NULL)
810 {
811 int imm8u = (insn & 0x1f) << 3;
812 int re = (insn >> 5) & 0x3;
813 const int reg_map[] = { 6, 8, 10, 14 };
814
815 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
816 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
817
818 /* Operation 2 -- sp = sp - (imm5u << 3) */
819 cache->sp_offset += imm8u;
820 }
821
822 in_prologue_bb = 1;
823 continue;
824 }
825 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
826 {
827 /* add5.pc $gp */
828 in_prologue_bb = 1;
829 continue;
830 }
831 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
832 {
833 /* movi55 $gp, imm5s */
834 in_prologue_bb = 1;
835 continue;
836 }
837 else
838 {
839 /* Jump/Branch insns never appear in prologue basic block.
840 The loop can be escaped early when these insns are met. */
841 if (in_prologue_bb == 1)
842 {
843 uint32_t insn5 = CHOP_BITS (insn, 5);
844 uint32_t insn8 = CHOP_BITS (insn, 8);
845 uint32_t insn38 = CHOP_BITS (insn, 11);
846
847 if (insn5 == N16_TYPE5 (JR5, 0)
848 || insn5 == N16_TYPE5 (JRAL5, 0)
849 || insn5 == N16_TYPE5 (RET5, 0)
850 || insn8 == N16_TYPE8 (J8, 0)
851 || insn8 == N16_TYPE8 (BEQZS8, 0)
852 || insn8 == N16_TYPE8 (BNEZS8, 0)
853 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
854 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
855 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
856 || insn38 == N16_TYPE38 (BNES38, 0, 0))
857 break;
858 }
859 }
860
861 /* The optimizer might shove anything into the prologue, if
862 we build up cache (cache != NULL) from analyzing prologue,
863 we just skip what we don't recognize and analyze further to
864 make cache as complete as possible. However, if we skip
865 prologue, we'll stop immediately on unrecognized
866 instruction. */
867 if (cache == NULL)
868 break;
869 }
870 }
871
872 return pc;
873 }
874
875 /* Implement the "skip_prologue" gdbarch method.
876
877 Find the end of function prologue. */
878
879 static CORE_ADDR
880 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
881 {
882 CORE_ADDR func_addr, limit_pc;
883
884 /* See if we can determine the end of the prologue via the symbol table.
885 If so, then return either PC, or the PC after the prologue, whichever
886 is greater. */
887 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
888 {
889 CORE_ADDR post_prologue_pc
890 = skip_prologue_using_sal (gdbarch, func_addr);
891 if (post_prologue_pc != 0)
892 return std::max (pc, post_prologue_pc);
893 }
894
895 /* Can't determine prologue from the symbol table, need to examine
896 instructions. */
897
898 /* Find an upper limit on the function prologue using the debug
899 information. If the debug information could not be used to provide
900 that bound, then use an arbitrary large number as the upper bound. */
901 limit_pc = skip_prologue_using_sal (gdbarch, pc);
902 if (limit_pc == 0)
903 limit_pc = pc + 128; /* Magic. */
904
905 /* Find the end of prologue. */
906 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
907 }
908
909 /* Allocate and fill in *THIS_CACHE with information about the prologue of
910 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
911 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
912
913 static struct nds32_frame_cache *
914 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
915 {
916 struct gdbarch *gdbarch = get_frame_arch (this_frame);
917 struct nds32_frame_cache *cache;
918 CORE_ADDR current_pc;
919 ULONGEST prev_sp;
920 ULONGEST this_base;
921 int i;
922
923 if (*this_cache)
924 return (struct nds32_frame_cache *) *this_cache;
925
926 cache = nds32_alloc_frame_cache ();
927 *this_cache = cache;
928
929 cache->pc = get_frame_func (this_frame);
930 current_pc = get_frame_pc (this_frame);
931 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
932
933 /* Compute the previous frame's stack pointer (which is also the
934 frame's ID's stack address), and this frame's base pointer. */
935 if (cache->fp_offset != INVALID_OFFSET)
936 {
937 /* FP is set in prologue, so it can be used to calculate other info. */
938 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
939 prev_sp = this_base + cache->fp_offset;
940 }
941 else
942 {
943 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
944 prev_sp = this_base + cache->sp_offset;
945 }
946
947 cache->prev_sp = prev_sp;
948 cache->base = this_base;
949
950 /* Adjust all the saved registers such that they contain addresses
951 instead of offsets. */
952 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
953 if (cache->saved_regs[i] != REG_UNAVAIL)
954 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
955
956 return cache;
957 }
958
959 /* Implement the "this_id" frame_unwind method.
960
961 Our frame ID for a normal frame is the current function's starting
962 PC and the caller's SP when we were called. */
963
964 static void
965 nds32_frame_this_id (struct frame_info *this_frame,
966 void **this_cache, struct frame_id *this_id)
967 {
968 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
969
970 /* This marks the outermost frame. */
971 if (cache->prev_sp == 0)
972 return;
973
974 *this_id = frame_id_build (cache->prev_sp, cache->pc);
975 }
976
977 /* Implement the "prev_register" frame_unwind method. */
978
979 static struct value *
980 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
981 int regnum)
982 {
983 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
984
985 if (regnum == NDS32_SP_REGNUM)
986 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
987
988 /* The PC of the previous frame is stored in the LP register of
989 the current frame. */
990 if (regnum == NDS32_PC_REGNUM)
991 regnum = NDS32_LP_REGNUM;
992
993 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
994 return frame_unwind_got_memory (this_frame, regnum,
995 cache->saved_regs[regnum]);
996
997 return frame_unwind_got_register (this_frame, regnum, regnum);
998 }
999
1000 static const struct frame_unwind nds32_frame_unwind =
1001 {
1002 NORMAL_FRAME,
1003 default_frame_unwind_stop_reason,
1004 nds32_frame_this_id,
1005 nds32_frame_prev_register,
1006 NULL,
1007 default_frame_sniffer,
1008 };
1009
1010 /* Return the frame base address of *THIS_FRAME. */
1011
1012 static CORE_ADDR
1013 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1014 {
1015 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1016
1017 return cache->base;
1018 }
1019
1020 static const struct frame_base nds32_frame_base =
1021 {
1022 &nds32_frame_unwind,
1023 nds32_frame_base_address,
1024 nds32_frame_base_address,
1025 nds32_frame_base_address
1026 };
1027 \f
1028 /* Helper function for instructions used to pop multiple words. */
1029
1030 static void
1031 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1032 int enable4)
1033 {
1034 CORE_ADDR sp_offset = cache->sp_offset;
1035 int i;
1036
1037 /* Skip case where re == rb == sp. */
1038 if ((rb < REG_FP) && (re < REG_FP))
1039 {
1040 for (i = rb; i <= re; i++)
1041 {
1042 cache->saved_regs[i] = sp_offset;
1043 sp_offset += 4;
1044 }
1045 }
1046
1047 /* Check FP, GP, LP in enable4. */
1048 for (i = 3; i >= 1; i--)
1049 {
1050 if ((enable4 >> i) & 0x1)
1051 {
1052 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1053 sp_offset += 4;
1054 }
1055 }
1056
1057 /* For sp, update the offset. */
1058 cache->sp_offset = sp_offset;
1059 }
1060
1061 /* The instruction sequences in NDS32 epilogue are
1062
1063 INSN_RESET_SP (optional)
1064 (If exists, this must be the first instruction in epilogue
1065 and the stack has not been destroyed.).
1066 INSN_RECOVER (optional).
1067 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1068
1069 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1070 the necessary information will be recorded. */
1071
1072 static inline int
1073 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1074 struct nds32_frame_cache *cache)
1075 {
1076 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1077 && N32_IMM15S (insn) > 0)
1078 /* addi $sp, $sp, imm15s */
1079 return INSN_RESET_SP;
1080 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1081 && N32_IMM15S (insn) < 0)
1082 /* addi $sp, $fp, imm15s */
1083 return INSN_RESET_SP;
1084 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1085 && N32_RA5 (insn) == REG_SP)
1086 {
1087 /* lmw.bim Rb, [$sp], Re, enable4 */
1088 if (cache != NULL)
1089 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1090 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1091
1092 return INSN_RECOVER;
1093 }
1094 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1095 /* ret $lp */
1096 return INSN_RETURN;
1097 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1098 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1099 /* add $sp, $sp, $ta */
1100 /* add $sp, $ta, $sp */
1101 return INSN_RESET_SP;
1102 else if (abi_use_fpr
1103 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1104 {
1105 if (__GF (insn, 12, 1) == 0)
1106 /* fldi FDt, [$sp + (imm12s << 2)] */
1107 return INSN_RECOVER;
1108 else
1109 {
1110 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1111 int offset = N32_IMM12S (insn) << 2;
1112
1113 if (offset == 8 || offset == 12)
1114 {
1115 if (cache != NULL)
1116 cache->sp_offset += offset;
1117
1118 return INSN_RECOVER;
1119 }
1120 }
1121 }
1122
1123 return INSN_NORMAL;
1124 }
1125
1126 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1127 the necessary information will be recorded. */
1128
1129 static inline int
1130 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1131 {
1132 if (insn == N16_TYPE5 (RET5, REG_LP))
1133 /* ret5 $lp */
1134 return INSN_RETURN;
1135 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1136 {
1137 /* addi10s.sp */
1138 int imm10s = N16_IMM10S (insn);
1139
1140 if (imm10s > 0)
1141 {
1142 if (cache != NULL)
1143 cache->sp_offset += imm10s;
1144
1145 return INSN_RECOVER;
1146 }
1147 }
1148 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1149 {
1150 /* pop25 */
1151 if (cache != NULL)
1152 {
1153 int imm8u = (insn & 0x1f) << 3;
1154 int re = (insn >> 5) & 0x3;
1155 const int reg_map[] = { 6, 8, 10, 14 };
1156
1157 /* Operation 1 -- sp = sp + (imm5u << 3) */
1158 cache->sp_offset += imm8u;
1159
1160 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1161 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1162 }
1163
1164 /* Operation 3 -- ret $lp */
1165 return INSN_RECOVER_RETURN;
1166 }
1167
1168 return INSN_NORMAL;
1169 }
1170
1171 /* Analyze a reasonable amount of instructions from the given PC to find
1172 the instruction used to return to the caller. Return 1 if the 'return'
1173 instruction could be found, 0 otherwise.
1174
1175 If CACHE is non-NULL, fill it in. */
1176
1177 static int
1178 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1179 struct nds32_frame_cache *cache)
1180 {
1181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1182 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1183 CORE_ADDR limit_pc;
1184 uint32_t insn, insn_len;
1185 int insn_type = INSN_NORMAL;
1186
1187 if (abi_use_fpr)
1188 limit_pc = pc + 48;
1189 else
1190 limit_pc = pc + 16;
1191
1192 for (; pc < limit_pc; pc += insn_len)
1193 {
1194 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1195
1196 if ((insn & 0x80000000) == 0)
1197 {
1198 /* 32-bit instruction */
1199 insn_len = 4;
1200
1201 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1202 if (insn_type == INSN_RETURN)
1203 return 1;
1204 else if (insn_type == INSN_RECOVER)
1205 continue;
1206 }
1207 else
1208 {
1209 /* 16-bit instruction */
1210 insn_len = 2;
1211
1212 insn >>= 16;
1213 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1214 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1215 return 1;
1216 else if (insn_type == INSN_RECOVER)
1217 continue;
1218 }
1219
1220 /* Stop the scan if this is an unexpected instruction. */
1221 break;
1222 }
1223
1224 return 0;
1225 }
1226
1227 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1228
1229 static int
1230 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1231 {
1232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1233 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1234 int insn_type = INSN_NORMAL;
1235 int ret_found = 0;
1236 uint32_t insn;
1237
1238 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1239
1240 if ((insn & 0x80000000) == 0)
1241 {
1242 /* 32-bit instruction */
1243
1244 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1245 }
1246 else
1247 {
1248 /* 16-bit instruction */
1249
1250 insn >>= 16;
1251 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1252 }
1253
1254 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1255 return 0;
1256
1257 /* Search the required 'return' instruction within the following reasonable
1258 instructions. */
1259 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1260 if (ret_found == 0)
1261 return 0;
1262
1263 /* Scan backwards to make sure that the last instruction has adjusted
1264 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1265 just a heuristic, so the false positives will be acceptable. */
1266 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1267
1268 /* Only 16-bit instructions are possible at addr - 2. */
1269 if ((insn & 0x80000000) != 0)
1270 {
1271 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1272
1273 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1274 if (insn_type == INSN_RECOVER)
1275 return 1;
1276 }
1277
1278 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1279
1280 /* If this is a 16-bit instruction at addr - 4, then there must be another
1281 16-bit instruction at addr - 2, so only 32-bit instructions need to
1282 be analyzed here. */
1283 if ((insn & 0x80000000) == 0)
1284 {
1285 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1286
1287 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1288 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1289 return 1;
1290 }
1291
1292 return 0;
1293 }
1294
1295 /* Implement the "sniffer" frame_unwind method. */
1296
1297 static int
1298 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1299 struct frame_info *this_frame, void **this_cache)
1300 {
1301 if (frame_relative_level (this_frame) == 0)
1302 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1303 get_frame_pc (this_frame));
1304 else
1305 return 0;
1306 }
1307
1308 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1309 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1310 allocated. Return a pointer to the current nds32_frame_cache in
1311 *THIS_CACHE. */
1312
1313 static struct nds32_frame_cache *
1314 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1315 {
1316 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1317 struct nds32_frame_cache *cache;
1318 CORE_ADDR current_pc, current_sp;
1319 int i;
1320
1321 if (*this_cache)
1322 return (struct nds32_frame_cache *) *this_cache;
1323
1324 cache = nds32_alloc_frame_cache ();
1325 *this_cache = cache;
1326
1327 cache->pc = get_frame_func (this_frame);
1328 current_pc = get_frame_pc (this_frame);
1329 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1330
1331 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1332 cache->prev_sp = current_sp + cache->sp_offset;
1333
1334 /* Adjust all the saved registers such that they contain addresses
1335 instead of offsets. */
1336 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1337 if (cache->saved_regs[i] != REG_UNAVAIL)
1338 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1339
1340 return cache;
1341 }
1342
1343 /* Implement the "this_id" frame_unwind method. */
1344
1345 static void
1346 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1347 void **this_cache, struct frame_id *this_id)
1348 {
1349 struct nds32_frame_cache *cache
1350 = nds32_epilogue_frame_cache (this_frame, this_cache);
1351
1352 /* This marks the outermost frame. */
1353 if (cache->prev_sp == 0)
1354 return;
1355
1356 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1357 }
1358
1359 /* Implement the "prev_register" frame_unwind method. */
1360
1361 static struct value *
1362 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1363 void **this_cache, int regnum)
1364 {
1365 struct nds32_frame_cache *cache
1366 = nds32_epilogue_frame_cache (this_frame, this_cache);
1367
1368 if (regnum == NDS32_SP_REGNUM)
1369 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1370
1371 /* The PC of the previous frame is stored in the LP register of
1372 the current frame. */
1373 if (regnum == NDS32_PC_REGNUM)
1374 regnum = NDS32_LP_REGNUM;
1375
1376 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1377 return frame_unwind_got_memory (this_frame, regnum,
1378 cache->saved_regs[regnum]);
1379
1380 return frame_unwind_got_register (this_frame, regnum, regnum);
1381 }
1382
1383 static const struct frame_unwind nds32_epilogue_frame_unwind =
1384 {
1385 NORMAL_FRAME,
1386 default_frame_unwind_stop_reason,
1387 nds32_epilogue_frame_this_id,
1388 nds32_epilogue_frame_prev_register,
1389 NULL,
1390 nds32_epilogue_frame_sniffer
1391 };
1392 \f
1393 /* Implement the "dummy_id" gdbarch method. */
1394
1395 static struct frame_id
1396 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1397 {
1398 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1399
1400 return frame_id_build (sp, get_frame_pc (this_frame));
1401 }
1402
1403 /* Implement the "unwind_pc" gdbarch method. */
1404
1405 static CORE_ADDR
1406 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1407 {
1408 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1409 }
1410
1411 /* Implement the "unwind_sp" gdbarch method. */
1412
1413 static CORE_ADDR
1414 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1415 {
1416 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1417 }
1418 \f
1419 /* Floating type and struct type that has only one floating type member
1420 can pass value using FPU registers (when FPU ABI is used). */
1421
1422 static int
1423 nds32_check_calling_use_fpr (struct type *type)
1424 {
1425 struct type *t;
1426 enum type_code typecode;
1427
1428 t = type;
1429 while (1)
1430 {
1431 t = check_typedef (t);
1432 typecode = TYPE_CODE (t);
1433 if (typecode != TYPE_CODE_STRUCT)
1434 break;
1435 else if (TYPE_NFIELDS (t) != 1)
1436 return 0;
1437 else
1438 t = TYPE_FIELD_TYPE (t, 0);
1439 }
1440
1441 return typecode == TYPE_CODE_FLT;
1442 }
1443
1444 /* Return the alignment (in bytes) of the given type. */
1445
1446 static int
1447 nds32_type_align (struct type *type)
1448 {
1449 int n;
1450 int align;
1451 int falign;
1452
1453 type = check_typedef (type);
1454 switch (TYPE_CODE (type))
1455 {
1456 default:
1457 /* Should never happen. */
1458 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1459 return 4;
1460
1461 case TYPE_CODE_PTR:
1462 case TYPE_CODE_ENUM:
1463 case TYPE_CODE_INT:
1464 case TYPE_CODE_FLT:
1465 case TYPE_CODE_SET:
1466 case TYPE_CODE_RANGE:
1467 case TYPE_CODE_REF:
1468 case TYPE_CODE_CHAR:
1469 case TYPE_CODE_BOOL:
1470 return TYPE_LENGTH (type);
1471
1472 case TYPE_CODE_ARRAY:
1473 case TYPE_CODE_COMPLEX:
1474 return nds32_type_align (TYPE_TARGET_TYPE (type));
1475
1476 case TYPE_CODE_STRUCT:
1477 case TYPE_CODE_UNION:
1478 align = 1;
1479 for (n = 0; n < TYPE_NFIELDS (type); n++)
1480 {
1481 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1482 if (falign > align)
1483 align = falign;
1484 }
1485 return align;
1486 }
1487 }
1488
1489 /* Implement the "push_dummy_call" gdbarch method. */
1490
1491 static CORE_ADDR
1492 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1493 struct regcache *regcache, CORE_ADDR bp_addr,
1494 int nargs, struct value **args, CORE_ADDR sp,
1495 int struct_return, CORE_ADDR struct_addr)
1496 {
1497 const int REND = 6; /* End for register offset. */
1498 int goff = 0; /* Current gpr offset for argument. */
1499 int foff = 0; /* Current fpr offset for argument. */
1500 int soff = 0; /* Current stack offset for argument. */
1501 int i;
1502 ULONGEST regval;
1503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1504 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1505 struct type *func_type = value_type (function);
1506 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1507 int abi_split = nds32_abi_split (tdep->elf_abi);
1508
1509 /* Set the return address. For the NDS32, the return breakpoint is
1510 always at BP_ADDR. */
1511 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1512
1513 /* If STRUCT_RETURN is true, then the struct return address (in
1514 STRUCT_ADDR) will consume the first argument-passing register.
1515 Both adjust the register count and store that value. */
1516 if (struct_return)
1517 {
1518 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1519 goff++;
1520 }
1521
1522 /* Now make sure there's space on the stack */
1523 for (i = 0; i < nargs; i++)
1524 {
1525 struct type *type = value_type (args[i]);
1526 int align = nds32_type_align (type);
1527
1528 /* If align is zero, it may be an empty struct.
1529 Just ignore the argument of empty struct. */
1530 if (align == 0)
1531 continue;
1532
1533 sp -= TYPE_LENGTH (type);
1534 sp = align_down (sp, align);
1535 }
1536
1537 /* Stack must be 8-byte aligned. */
1538 sp = align_down (sp, 8);
1539
1540 soff = 0;
1541 for (i = 0; i < nargs; i++)
1542 {
1543 const gdb_byte *val;
1544 int align, len;
1545 struct type *type;
1546 int calling_use_fpr;
1547 int use_fpr = 0;
1548
1549 type = value_type (args[i]);
1550 calling_use_fpr = nds32_check_calling_use_fpr (type);
1551 len = TYPE_LENGTH (type);
1552 align = nds32_type_align (type);
1553 val = value_contents (args[i]);
1554
1555 /* The size of a composite type larger than 4 bytes will be rounded
1556 up to the nearest multiple of 4. */
1557 if (len > 4)
1558 len = align_up (len, 4);
1559
1560 /* Variadic functions are handled differently between AABI and ABI2FP+.
1561
1562 For AABI, the caller pushes arguments in registers, callee stores
1563 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1564 Therefore, we don't have to handle variadic functions specially.
1565
1566 For ABI2FP+, the caller pushes only named arguments in registers
1567 and pushes all unnamed arguments in stack. */
1568
1569 if (abi_use_fpr && TYPE_VARARGS (func_type)
1570 && i >= TYPE_NFIELDS (func_type))
1571 goto use_stack;
1572
1573 /* Try to use FPRs to pass arguments only when
1574 1. The program is built using toolchain with FPU support.
1575 2. The type of this argument can use FPR to pass value. */
1576 use_fpr = abi_use_fpr && calling_use_fpr;
1577
1578 if (use_fpr)
1579 {
1580 if (tdep->fpu_freg == -1)
1581 goto error_no_fpr;
1582
1583 /* Adjust alignment. */
1584 if ((align >> 2) > 0)
1585 foff = align_up (foff, align >> 2);
1586
1587 if (foff < REND)
1588 {
1589 switch (len)
1590 {
1591 case 4:
1592 regcache_cooked_write (regcache,
1593 tdep->fs0_regnum + foff, val);
1594 foff++;
1595 break;
1596 case 8:
1597 regcache_cooked_write (regcache,
1598 NDS32_FD0_REGNUM + (foff >> 1), val);
1599 foff += 2;
1600 break;
1601 default:
1602 /* Long double? */
1603 internal_error (__FILE__, __LINE__,
1604 "Do not know how to handle %d-byte double.\n",
1605 len);
1606 break;
1607 }
1608 continue;
1609 }
1610 }
1611 else
1612 {
1613 /*
1614 When passing arguments using GPRs,
1615
1616 * A composite type not larger than 4 bytes is passed in $rN.
1617 The format is as if the value is loaded with load instruction
1618 of corresponding size (e.g., LB, LH, LW).
1619
1620 For example,
1621
1622 r0
1623 31 0
1624 LITTLE: [x x b a]
1625 BIG: [x x a b]
1626
1627 * Otherwise, a composite type is passed in consecutive registers.
1628 The size is rounded up to the nearest multiple of 4.
1629 The successive registers hold the parts of the argument as if
1630 were loaded using lmw instructions.
1631
1632 For example,
1633
1634 r0 r1
1635 31 0 31 0
1636 LITTLE: [d c b a] [x x x e]
1637 BIG: [a b c d] [e x x x]
1638 */
1639
1640 /* Adjust alignment. */
1641 if ((align >> 2) > 0)
1642 goff = align_up (goff, align >> 2);
1643
1644 if (len <= (REND - goff) * 4)
1645 {
1646 /* This argument can be passed wholly via GPRs. */
1647 while (len > 0)
1648 {
1649 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1650 byte_order);
1651 regcache_cooked_write_unsigned (regcache,
1652 NDS32_R0_REGNUM + goff,
1653 regval);
1654 len -= 4;
1655 val += 4;
1656 goff++;
1657 }
1658 continue;
1659 }
1660 else if (abi_split)
1661 {
1662 /* Some parts of this argument can be passed via GPRs. */
1663 while (goff < REND)
1664 {
1665 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1666 byte_order);
1667 regcache_cooked_write_unsigned (regcache,
1668 NDS32_R0_REGNUM + goff,
1669 regval);
1670 len -= 4;
1671 val += 4;
1672 goff++;
1673 }
1674 }
1675 }
1676
1677 use_stack:
1678 /*
1679 When pushing (split parts of) an argument into stack,
1680
1681 * A composite type not larger than 4 bytes is copied to different
1682 base address.
1683 In little-endian, the first byte of this argument is aligned
1684 at the low address of the next free word.
1685 In big-endian, the last byte of this argument is aligned
1686 at the high address of the next free word.
1687
1688 For example,
1689
1690 sp [ - ] [ c ] hi
1691 [ c ] [ b ]
1692 [ b ] [ a ]
1693 [ a ] [ - ] lo
1694 LITTLE BIG
1695 */
1696
1697 /* Adjust alignment. */
1698 soff = align_up (soff, align);
1699
1700 while (len > 0)
1701 {
1702 int rlen = (len > 4) ? 4 : len;
1703
1704 if (byte_order == BFD_ENDIAN_BIG)
1705 write_memory (sp + soff + 4 - rlen, val, rlen);
1706 else
1707 write_memory (sp + soff, val, rlen);
1708
1709 len -= 4;
1710 val += 4;
1711 soff += 4;
1712 }
1713 }
1714
1715 /* Finally, update the SP register. */
1716 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1717
1718 return sp;
1719
1720 error_no_fpr:
1721 /* If use_fpr, but no floating-point register exists,
1722 then it is an error. */
1723 error (_("Fail to call. FPU registers are required."));
1724 }
1725 \f
1726 /* Read, for architecture GDBARCH, a function return value of TYPE
1727 from REGCACHE, and copy that into VALBUF. */
1728
1729 static void
1730 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1731 struct regcache *regcache, gdb_byte *valbuf)
1732 {
1733 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1734 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1735 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1736 int calling_use_fpr;
1737 int len;
1738
1739 calling_use_fpr = nds32_check_calling_use_fpr (type);
1740 len = TYPE_LENGTH (type);
1741
1742 if (abi_use_fpr && calling_use_fpr)
1743 {
1744 if (len == 4)
1745 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1746 else if (len == 8)
1747 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1748 else
1749 internal_error (__FILE__, __LINE__,
1750 _("Cannot extract return value of %d bytes "
1751 "long floating-point."), len);
1752 }
1753 else
1754 {
1755 /*
1756 When returning result,
1757
1758 * A composite type not larger than 4 bytes is returned in $r0.
1759 The format is as if the result is loaded with load instruction
1760 of corresponding size (e.g., LB, LH, LW).
1761
1762 For example,
1763
1764 r0
1765 31 0
1766 LITTLE: [x x b a]
1767 BIG: [x x a b]
1768
1769 * Otherwise, a composite type not larger than 8 bytes is returned
1770 in $r0 and $r1.
1771 In little-endian, the first word is loaded in $r0.
1772 In big-endian, the last word is loaded in $r1.
1773
1774 For example,
1775
1776 r0 r1
1777 31 0 31 0
1778 LITTLE: [d c b a] [x x x e]
1779 BIG: [x x x a] [b c d e]
1780 */
1781
1782 ULONGEST tmp;
1783
1784 if (len < 4)
1785 {
1786 /* By using store_unsigned_integer we avoid having to do
1787 anything special for small big-endian values. */
1788 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1789 store_unsigned_integer (valbuf, len, byte_order, tmp);
1790 }
1791 else if (len == 4)
1792 {
1793 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1794 }
1795 else if (len < 8)
1796 {
1797 int len1, len2;
1798
1799 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1800 len2 = len - len1;
1801
1802 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1803 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1804
1805 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1806 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1807 }
1808 else
1809 {
1810 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1811 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1812 }
1813 }
1814 }
1815
1816 /* Write, for architecture GDBARCH, a function return value of TYPE
1817 from VALBUF into REGCACHE. */
1818
1819 static void
1820 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1821 struct regcache *regcache, const gdb_byte *valbuf)
1822 {
1823 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1824 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1825 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1826 int calling_use_fpr;
1827 int len;
1828
1829 calling_use_fpr = nds32_check_calling_use_fpr (type);
1830 len = TYPE_LENGTH (type);
1831
1832 if (abi_use_fpr && calling_use_fpr)
1833 {
1834 if (len == 4)
1835 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1836 else if (len == 8)
1837 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1838 else
1839 internal_error (__FILE__, __LINE__,
1840 _("Cannot store return value of %d bytes "
1841 "long floating-point."), len);
1842 }
1843 else
1844 {
1845 ULONGEST regval;
1846
1847 if (len < 4)
1848 {
1849 regval = extract_unsigned_integer (valbuf, len, byte_order);
1850 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1851 }
1852 else if (len == 4)
1853 {
1854 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1855 }
1856 else if (len < 8)
1857 {
1858 int len1, len2;
1859
1860 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1861 len2 = len - len1;
1862
1863 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1864 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1865
1866 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1867 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1868 regval);
1869 }
1870 else
1871 {
1872 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1873 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1874 }
1875 }
1876 }
1877
1878 /* Implement the "return_value" gdbarch method.
1879
1880 Determine, for architecture GDBARCH, how a return value of TYPE
1881 should be returned. If it is supposed to be returned in registers,
1882 and READBUF is non-zero, read the appropriate value from REGCACHE,
1883 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1884 from WRITEBUF into REGCACHE. */
1885
1886 static enum return_value_convention
1887 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1888 struct type *type, struct regcache *regcache,
1889 gdb_byte *readbuf, const gdb_byte *writebuf)
1890 {
1891 if (TYPE_LENGTH (type) > 8)
1892 {
1893 return RETURN_VALUE_STRUCT_CONVENTION;
1894 }
1895 else
1896 {
1897 if (readbuf != NULL)
1898 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1899 if (writebuf != NULL)
1900 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1901
1902 return RETURN_VALUE_REGISTER_CONVENTION;
1903 }
1904 }
1905 \f
1906 /* Implement the "get_longjmp_target" gdbarch method. */
1907
1908 static int
1909 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1910 {
1911 gdb_byte buf[4];
1912 CORE_ADDR jb_addr;
1913 struct gdbarch *gdbarch = get_frame_arch (frame);
1914 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1915
1916 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1917
1918 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1919 return 0;
1920
1921 *pc = extract_unsigned_integer (buf, 4, byte_order);
1922 return 1;
1923 }
1924 \f
1925 /* Validate the given TDESC, and fixed-number some registers in it.
1926 Return 0 if the given TDESC does not contain the required feature
1927 or not contain required registers. */
1928
1929 static int
1930 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1931 struct tdesc_arch_data *tdesc_data,
1932 int *fpu_freg, int *use_pseudo_fsrs)
1933 {
1934 const struct tdesc_feature *feature;
1935 int i, valid_p;
1936
1937 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1938 if (feature == NULL)
1939 return 0;
1940
1941 valid_p = 1;
1942 /* Validate and fixed-number R0-R10. */
1943 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1944 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1945 nds32_register_names[i]);
1946
1947 /* Validate R15. */
1948 valid_p &= tdesc_unnumbered_register (feature,
1949 nds32_register_names[NDS32_TA_REGNUM]);
1950
1951 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1952 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1953 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1954 nds32_register_names[i]);
1955
1956 if (!valid_p)
1957 return 0;
1958
1959 /* Fixed-number R11-R27. */
1960 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1961 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1962
1963 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1964 if (feature != NULL)
1965 {
1966 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1967 int freg = -1;
1968
1969 /* Guess FPU configuration via listed registers. */
1970 if (tdesc_unnumbered_register (feature, "fd31"))
1971 freg = 3;
1972 else if (tdesc_unnumbered_register (feature, "fd15"))
1973 freg = 2;
1974 else if (tdesc_unnumbered_register (feature, "fd7"))
1975 freg = 1;
1976 else if (tdesc_unnumbered_register (feature, "fd3"))
1977 freg = 0;
1978
1979 if (freg == -1)
1980 /* Required FDR is not found. */
1981 return 0;
1982 else
1983 *fpu_freg = freg;
1984
1985 /* Validate and fixed-number required FDRs. */
1986 num_fdr_regs = num_fdr_map[freg];
1987 for (i = 0; i < num_fdr_regs; i++)
1988 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1989 NDS32_FD0_REGNUM + i,
1990 nds32_fdr_register_names[i]);
1991 if (!valid_p)
1992 return 0;
1993
1994 /* Count the number of listed FSRs, and fixed-number them if present. */
1995 num_fsr_regs = num_fsr_map[freg];
1996 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1997 num_listed_fsr = 0;
1998 for (i = 0; i < num_fsr_regs; i++)
1999 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
2000 fs0_regnum + i,
2001 nds32_fsr_register_names[i]);
2002
2003 if (num_listed_fsr == 0)
2004 /* No required FSRs are listed explicitly, make them pseudo registers
2005 of FDRs. */
2006 *use_pseudo_fsrs = 1;
2007 else if (num_listed_fsr == num_fsr_regs)
2008 /* All required FSRs are listed explicitly. */
2009 *use_pseudo_fsrs = 0;
2010 else
2011 /* Some required FSRs are missing. */
2012 return 0;
2013 }
2014
2015 return 1;
2016 }
2017
2018 /* Initialize the current architecture based on INFO. If possible,
2019 re-use an architecture from ARCHES, which is a list of
2020 architectures already created during this debugging session.
2021
2022 Called e.g. at program startup, when reading a core file, and when
2023 reading a binary file. */
2024
2025 static struct gdbarch *
2026 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2027 {
2028 struct gdbarch *gdbarch;
2029 struct gdbarch_tdep *tdep;
2030 struct gdbarch_list *best_arch;
2031 struct tdesc_arch_data *tdesc_data = NULL;
2032 const struct target_desc *tdesc = info.target_desc;
2033 int elf_abi = E_NDS_ABI_AABI;
2034 int fpu_freg = -1;
2035 int use_pseudo_fsrs = 0;
2036 int i, num_regs, maxregs;
2037
2038 /* Extract the elf_flags if available. */
2039 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2040 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2041
2042 /* If there is already a candidate, use it. */
2043 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2044 best_arch != NULL;
2045 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2046 {
2047 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2048
2049 if (idep->elf_abi != elf_abi)
2050 continue;
2051
2052 /* Found a match. */
2053 break;
2054 }
2055
2056 if (best_arch != NULL)
2057 return best_arch->gdbarch;
2058
2059 if (!tdesc_has_registers (tdesc))
2060 tdesc = tdesc_nds32;
2061
2062 tdesc_data = tdesc_data_alloc ();
2063
2064 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2065 {
2066 tdesc_data_cleanup (tdesc_data);
2067 return NULL;
2068 }
2069
2070 /* Allocate space for the new architecture. */
2071 tdep = XCNEW (struct gdbarch_tdep);
2072 tdep->fpu_freg = fpu_freg;
2073 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2074 tdep->fs0_regnum = -1;
2075 tdep->elf_abi = elf_abi;
2076
2077 gdbarch = gdbarch_alloc (&info, tdep);
2078
2079 set_gdbarch_wchar_bit (gdbarch, 16);
2080 set_gdbarch_wchar_signed (gdbarch, 0);
2081
2082 if (fpu_freg == -1)
2083 num_regs = NDS32_NUM_REGS;
2084 else if (use_pseudo_fsrs == 1)
2085 {
2086 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2087 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2088 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2089 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2090 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2091
2092 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2093 }
2094 else
2095 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2096
2097 set_gdbarch_num_regs (gdbarch, num_regs);
2098 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2099
2100 /* Cache the register number of fs0. */
2101 if (fpu_freg != -1)
2102 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2103
2104 /* Add NDS32 register aliases. To avoid search in user register name space,
2105 user_reg_map_name_to_regnum is not used. */
2106 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2107 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2108 {
2109 int regnum, j;
2110
2111 regnum = -1;
2112 /* Search register name space. */
2113 for (j = 0; j < maxregs; j++)
2114 {
2115 const char *regname = gdbarch_register_name (gdbarch, j);
2116
2117 if (regname != NULL
2118 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2119 {
2120 regnum = j;
2121 break;
2122 }
2123 }
2124
2125 /* Try next alias entry if the given name can not be found in register
2126 name space. */
2127 if (regnum == -1)
2128 continue;
2129
2130 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2131 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2132 }
2133
2134 nds32_add_reggroups (gdbarch);
2135
2136 /* Hook in ABI-specific overrides, if they have been registered. */
2137 info.tdep_info = (void *) tdesc_data;
2138 gdbarch_init_osabi (info, gdbarch);
2139
2140 /* Override tdesc_register callbacks for system registers. */
2141 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2142
2143 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2144 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2145 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2146 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2147 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2148 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2149
2150 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2151 set_gdbarch_return_value (gdbarch, nds32_return_value);
2152 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2153
2154 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2155 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2156 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2157 nds32_breakpoint::kind_from_pc);
2158 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2159 nds32_breakpoint::bp_from_kind);
2160
2161 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2162 frame_base_set_default (gdbarch, &nds32_frame_base);
2163
2164 /* Handle longjmp. */
2165 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2166
2167 /* The order of appending is the order it check frame. */
2168 dwarf2_append_unwinders (gdbarch);
2169 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2170 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2171
2172 return gdbarch;
2173 }
2174
2175 void
2176 _initialize_nds32_tdep (void)
2177 {
2178 /* Initialize gdbarch. */
2179 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2180
2181 initialize_tdesc_nds32 ();
2182 nds32_init_reggroups ();
2183 }
GDB Binutils - Deliverables
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