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[deliverable/binutils-gdb.git] / gdb / nds32-tdep.c
1 /* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2017 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "defs.h"
22 #include "frame.h"
23 #include "frame-unwind.h"
24 #include "frame-base.h"
25 #include "symtab.h"
26 #include "gdbtypes.h"
27 #include "gdbcore.h"
28 #include "value.h"
29 #include "reggroups.h"
30 #include "inferior.h"
31 #include "osabi.h"
32 #include "arch-utils.h"
33 #include "regcache.h"
34 #include "dis-asm.h"
35 #include "user-regs.h"
36 #include "elf-bfd.h"
37 #include "dwarf2-frame.h"
38 #include "remote.h"
39 #include "target-descriptions.h"
40
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
44 #include <algorithm>
45
46 #include "features/nds32.c"
47
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
51 #define N32_SMW_ADM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
53 #define N32_LMW_BIM \
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
55 #define N32_FLDI_SP \
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
57
58 extern void _initialize_nds32_tdep (void);
59
60 /* Use an invalid address value as 'not available' marker. */
61 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
62
63 /* Use an impossible value as invalid offset. */
64 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
65
66 /* Instruction groups for NDS32 epilogue analysis. */
67 enum
68 {
69 /* Instructions used everywhere, not only in epilogue. */
70 INSN_NORMAL,
71 /* Instructions used to reset sp for local vars, arguments, etc. */
72 INSN_RESET_SP,
73 /* Instructions used to recover saved regs and to recover padding. */
74 INSN_RECOVER,
75 /* Instructions used to return to the caller. */
76 INSN_RETURN,
77 /* Instructions used to recover saved regs and to return to the caller. */
78 INSN_RECOVER_RETURN,
79 };
80
81 static const char *const nds32_register_names[] =
82 {
83 /* 32 GPRs. */
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
88 /* PC. */
89 "pc",
90 };
91
92 static const char *const nds32_fdr_register_names[] =
93 {
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 };
99
100 static const char *const nds32_fsr_register_names[] =
101 {
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 };
107
108 /* The number of registers for four FPU configuration options. */
109 const int num_fdr_map[] = { 4, 8, 16, 32 };
110 const int num_fsr_map[] = { 8, 16, 32, 32 };
111
112 /* Aliases for registers. */
113 static const struct
114 {
115 const char *name;
116 const char *alias;
117 } nds32_register_aliases[] =
118 {
119 {"r15", "ta"},
120 {"r26", "p0"},
121 {"r27", "p1"},
122 {"fp", "r28"},
123 {"gp", "r29"},
124 {"lp", "r30"},
125 {"sp", "r31"},
126
127 {"cr0", "cpu_ver"},
128 {"cr1", "icm_cfg"},
129 {"cr2", "dcm_cfg"},
130 {"cr3", "mmu_cfg"},
131 {"cr4", "msc_cfg"},
132 {"cr5", "core_id"},
133 {"cr6", "fucop_exist"},
134 {"cr7", "msc_cfg2"},
135
136 {"ir0", "psw"},
137 {"ir1", "ipsw"},
138 {"ir2", "p_psw"},
139 {"ir3", "ivb"},
140 {"ir4", "eva"},
141 {"ir5", "p_eva"},
142 {"ir6", "itype"},
143 {"ir7", "p_itype"},
144 {"ir8", "merr"},
145 {"ir9", "ipc"},
146 {"ir10", "p_ipc"},
147 {"ir11", "oipc"},
148 {"ir12", "p_p0"},
149 {"ir13", "p_p1"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
152 {"ir16", "sp_usr"},
153 {"ir17", "sp_priv"},
154 {"ir18", "int_pri"},
155 {"ir19", "int_ctrl"},
156 {"ir20", "sp_usr1"},
157 {"ir21", "sp_priv1"},
158 {"ir22", "sp_usr2"},
159 {"ir23", "sp_priv2"},
160 {"ir24", "sp_usr3"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
166
167 {"mr0", "mmu_ctl"},
168 {"mr1", "l1_pptb"},
169 {"mr2", "tlb_vpn"},
170 {"mr3", "tlb_data"},
171 {"mr4", "tlb_misc"},
172 {"mr5", "vlpt_idx"},
173 {"mr6", "ilmb"},
174 {"mr7", "dlmb"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
179
180 {"dr0", "bpc0"},
181 {"dr1", "bpc1"},
182 {"dr2", "bpc2"},
183 {"dr3", "bpc3"},
184 {"dr4", "bpc4"},
185 {"dr5", "bpc5"},
186 {"dr6", "bpc6"},
187 {"dr7", "bpc7"},
188 {"dr8", "bpa0"},
189 {"dr9", "bpa1"},
190 {"dr10", "bpa2"},
191 {"dr11", "bpa3"},
192 {"dr12", "bpa4"},
193 {"dr13", "bpa5"},
194 {"dr14", "bpa6"},
195 {"dr15", "bpa7"},
196 {"dr16", "bpam0"},
197 {"dr17", "bpam1"},
198 {"dr18", "bpam2"},
199 {"dr19", "bpam3"},
200 {"dr20", "bpam4"},
201 {"dr21", "bpam5"},
202 {"dr22", "bpam6"},
203 {"dr23", "bpam7"},
204 {"dr24", "bpv0"},
205 {"dr25", "bpv1"},
206 {"dr26", "bpv2"},
207 {"dr27", "bpv3"},
208 {"dr28", "bpv4"},
209 {"dr29", "bpv5"},
210 {"dr30", "bpv6"},
211 {"dr31", "bpv7"},
212 {"dr32", "bpcid0"},
213 {"dr33", "bpcid1"},
214 {"dr34", "bpcid2"},
215 {"dr35", "bpcid3"},
216 {"dr36", "bpcid4"},
217 {"dr37", "bpcid5"},
218 {"dr38", "bpcid6"},
219 {"dr39", "bpcid7"},
220 {"dr40", "edm_cfg"},
221 {"dr41", "edmsw"},
222 {"dr42", "edm_ctl"},
223 {"dr43", "edm_dtr"},
224 {"dr44", "bpmtc"},
225 {"dr45", "dimbr"},
226 {"dr46", "tecr0"},
227 {"dr47", "tecr1"},
228
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
232
233 {"pfr0", "pfmc0"},
234 {"pfr1", "pfmc1"},
235 {"pfr2", "pfmc2"},
236 {"pfr3", "pfm_ctl"},
237 {"pfr4", "pft_ctl"},
238
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
252
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
255
256 {"idr0", "sdz_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
259
260 {"secur0", "sfcr"},
261 {"secur1", "sign"},
262 {"secur2", "isign"},
263 {"secur3", "p_isign"},
264 };
265
266 /* Value of a register alias. BATON is the regnum of the corresponding
267 register. */
268
269 static struct value *
270 value_of_nds32_reg (struct frame_info *frame, const void *baton)
271 {
272 return value_of_register ((int) (intptr_t) baton, frame);
273 }
274 \f
275 /* Implement the "frame_align" gdbarch method. */
276
277 static CORE_ADDR
278 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
279 {
280 /* 8-byte aligned. */
281 return align_down (sp, 8);
282 }
283
284 /* The same insn machine code is used for little-endian and big-endian. */
285 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
286
287 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
288
289 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
290
291 static int
292 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
293 {
294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
295 const int FSR = 38;
296 const int FDR = FSR + 32;
297
298 if (num >= 0 && num < 32)
299 {
300 /* General-purpose registers (R0 - R31). */
301 return num;
302 }
303 else if (num >= FSR && num < FSR + 32)
304 {
305 /* Single precision floating-point registers (FS0 - FS31). */
306 return num - FSR + tdep->fs0_regnum;
307 }
308 else if (num >= FDR && num < FDR + 32)
309 {
310 /* Double precision floating-point registers (FD0 - FD31). */
311 return num - FDR + NDS32_FD0_REGNUM;
312 }
313
314 /* No match, return a inaccessible register number. */
315 return -1;
316 }
317 \f
318 /* NDS32 register groups. */
319 static struct reggroup *nds32_cr_reggroup;
320 static struct reggroup *nds32_ir_reggroup;
321 static struct reggroup *nds32_mr_reggroup;
322 static struct reggroup *nds32_dr_reggroup;
323 static struct reggroup *nds32_pfr_reggroup;
324 static struct reggroup *nds32_hspr_reggroup;
325 static struct reggroup *nds32_dmar_reggroup;
326 static struct reggroup *nds32_racr_reggroup;
327 static struct reggroup *nds32_idr_reggroup;
328 static struct reggroup *nds32_secur_reggroup;
329
330 static void
331 nds32_init_reggroups (void)
332 {
333 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
334 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
335 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
336 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
337 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
338 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
339 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
340 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
341 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
342 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
343 }
344
345 static void
346 nds32_add_reggroups (struct gdbarch *gdbarch)
347 {
348 /* Add pre-defined register groups. */
349 reggroup_add (gdbarch, general_reggroup);
350 reggroup_add (gdbarch, float_reggroup);
351 reggroup_add (gdbarch, system_reggroup);
352 reggroup_add (gdbarch, all_reggroup);
353 reggroup_add (gdbarch, save_reggroup);
354 reggroup_add (gdbarch, restore_reggroup);
355
356 /* Add NDS32 register groups. */
357 reggroup_add (gdbarch, nds32_cr_reggroup);
358 reggroup_add (gdbarch, nds32_ir_reggroup);
359 reggroup_add (gdbarch, nds32_mr_reggroup);
360 reggroup_add (gdbarch, nds32_dr_reggroup);
361 reggroup_add (gdbarch, nds32_pfr_reggroup);
362 reggroup_add (gdbarch, nds32_hspr_reggroup);
363 reggroup_add (gdbarch, nds32_dmar_reggroup);
364 reggroup_add (gdbarch, nds32_racr_reggroup);
365 reggroup_add (gdbarch, nds32_idr_reggroup);
366 reggroup_add (gdbarch, nds32_secur_reggroup);
367 }
368
369 /* Implement the "register_reggroup_p" gdbarch method. */
370
371 static int
372 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
373 struct reggroup *reggroup)
374 {
375 const char *reg_name;
376 const char *group_name;
377 int ret;
378
379 if (reggroup == all_reggroup)
380 return 1;
381
382 /* General reggroup contains only GPRs and PC. */
383 if (reggroup == general_reggroup)
384 return regnum <= NDS32_PC_REGNUM;
385
386 if (reggroup == float_reggroup || reggroup == save_reggroup
387 || reggroup == restore_reggroup)
388 {
389 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
390 if (ret != -1)
391 return ret;
392
393 return default_register_reggroup_p (gdbarch, regnum, reggroup);
394 }
395
396 if (reggroup == system_reggroup)
397 return (regnum > NDS32_PC_REGNUM)
398 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
399
400 /* The NDS32 reggroup contains registers whose name is prefixed
401 by reggroup name. */
402 reg_name = gdbarch_register_name (gdbarch, regnum);
403 group_name = reggroup_name (reggroup);
404 return !strncmp (reg_name, group_name, strlen (group_name));
405 }
406 \f
407 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
408
409 static struct type *
410 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
411 {
412 regnum -= gdbarch_num_regs (gdbarch);
413
414 /* Currently, only FSRs could be defined as pseudo registers. */
415 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
416 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
417 floatformats_ieee_single);
418
419 warning (_("Unknown nds32 pseudo register %d."), regnum);
420 return NULL;
421 }
422
423 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
424
425 static const char *
426 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
427 {
428 regnum -= gdbarch_num_regs (gdbarch);
429
430 /* Currently, only FSRs could be defined as pseudo registers. */
431 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
432 return nds32_fsr_register_names[regnum];
433
434 warning (_("Unknown nds32 pseudo register %d."), regnum);
435 return NULL;
436 }
437
438 /* Implement the "pseudo_register_read" gdbarch method. */
439
440 static enum register_status
441 nds32_pseudo_register_read (struct gdbarch *gdbarch,
442 struct regcache *regcache, int regnum,
443 gdb_byte *buf)
444 {
445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
446 gdb_byte reg_buf[8];
447 int offset, fdr_regnum;
448 enum register_status status = REG_UNKNOWN;
449
450 /* Sanity check. */
451 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
452 return status;
453
454 regnum -= gdbarch_num_regs (gdbarch);
455
456 /* Currently, only FSRs could be defined as pseudo registers. */
457 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
458 {
459 /* fs0 is always the most significant half of fd0. */
460 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
461 offset = (regnum & 1) ? 4 : 0;
462 else
463 offset = (regnum & 1) ? 0 : 4;
464
465 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
466 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
467 if (status == REG_VALID)
468 memcpy (buf, reg_buf + offset, 4);
469 }
470
471 return status;
472 }
473
474 /* Implement the "pseudo_register_write" gdbarch method. */
475
476 static void
477 nds32_pseudo_register_write (struct gdbarch *gdbarch,
478 struct regcache *regcache, int regnum,
479 const gdb_byte *buf)
480 {
481 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
482 gdb_byte reg_buf[8];
483 int offset, fdr_regnum;
484
485 /* Sanity check. */
486 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
487 return;
488
489 regnum -= gdbarch_num_regs (gdbarch);
490
491 /* Currently, only FSRs could be defined as pseudo registers. */
492 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
493 {
494 /* fs0 is always the most significant half of fd0. */
495 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
496 offset = (regnum & 1) ? 4 : 0;
497 else
498 offset = (regnum & 1) ? 0 : 4;
499
500 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
501 regcache_raw_read (regcache, fdr_regnum, reg_buf);
502 memcpy (reg_buf + offset, buf, 4);
503 regcache_raw_write (regcache, fdr_regnum, reg_buf);
504 }
505 }
506 \f
507 /* Helper function for NDS32 ABI. Return true if FPRs can be used
508 to pass function arguments and return value. */
509
510 static int
511 nds32_abi_use_fpr (int elf_abi)
512 {
513 return elf_abi == E_NDS_ABI_V2FP_PLUS;
514 }
515
516 /* Helper function for NDS32 ABI. Return true if GPRs and stack
517 can be used together to pass an argument. */
518
519 static int
520 nds32_abi_split (int elf_abi)
521 {
522 return elf_abi == E_NDS_ABI_AABI;
523 }
524
525 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
526
527 struct nds32_frame_cache
528 {
529 /* The previous frame's inner most stack address. Used as this
530 frame ID's stack_addr. */
531 CORE_ADDR prev_sp;
532
533 /* The frame's base, optionally used by the high-level debug info. */
534 CORE_ADDR base;
535
536 /* During prologue analysis, keep how far the SP and FP have been offset
537 from the start of the stack frame (as defined by the previous frame's
538 stack pointer).
539 During epilogue analysis, keep how far the SP has been offset from the
540 current stack pointer. */
541 CORE_ADDR sp_offset;
542 CORE_ADDR fp_offset;
543
544 /* The address of the first instruction in this function. */
545 CORE_ADDR pc;
546
547 /* Saved registers. */
548 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
549 };
550
551 /* Allocate and initialize a frame cache. */
552
553 static struct nds32_frame_cache *
554 nds32_alloc_frame_cache (void)
555 {
556 struct nds32_frame_cache *cache;
557 int i;
558
559 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
560
561 /* Initialize fp_offset to check if FP is set in prologue. */
562 cache->fp_offset = INVALID_OFFSET;
563
564 /* Saved registers. We initialize these to -1 since zero is a valid
565 offset. */
566 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
567 cache->saved_regs[i] = REG_UNAVAIL;
568
569 return cache;
570 }
571
572 /* Helper function for instructions used to push multiple words. */
573
574 static void
575 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
576 int enable4)
577 {
578 CORE_ADDR sp_offset = cache->sp_offset;
579 int i;
580
581 /* Check LP, GP, FP in enable4. */
582 for (i = 1; i <= 3; i++)
583 {
584 if ((enable4 >> i) & 0x1)
585 {
586 sp_offset += 4;
587 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
588 }
589 }
590
591 /* Skip case where re == rb == sp. */
592 if ((rb < REG_FP) && (re < REG_FP))
593 {
594 for (i = re; i >= rb; i--)
595 {
596 sp_offset += 4;
597 cache->saved_regs[i] = sp_offset;
598 }
599 }
600
601 /* For sp, update the offset. */
602 cache->sp_offset = sp_offset;
603 }
604
605 /* Analyze the instructions within the given address range. If CACHE
606 is non-NULL, fill it in. Return the first address beyond the given
607 address range. If CACHE is NULL, return the first address not
608 recognized as a prologue instruction. */
609
610 static CORE_ADDR
611 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
612 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
613 {
614 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
615 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
616 /* Current scanning status. */
617 int in_prologue_bb = 0;
618 int val_ta = 0;
619 uint32_t insn, insn_len;
620
621 for (; pc < limit_pc; pc += insn_len)
622 {
623 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
624
625 if ((insn & 0x80000000) == 0)
626 {
627 /* 32-bit instruction */
628 insn_len = 4;
629
630 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
631 {
632 /* addi $sp, $sp, imm15s */
633 int imm15s = N32_IMM15S (insn);
634
635 if (imm15s < 0)
636 {
637 if (cache != NULL)
638 cache->sp_offset += -imm15s;
639
640 in_prologue_bb = 1;
641 continue;
642 }
643 }
644 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
645 {
646 /* addi $fp, $sp, imm15s */
647 int imm15s = N32_IMM15S (insn);
648
649 if (imm15s > 0)
650 {
651 if (cache != NULL)
652 cache->fp_offset = cache->sp_offset - imm15s;
653
654 in_prologue_bb = 1;
655 continue;
656 }
657 }
658 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
659 && N32_RA5 (insn) == REG_SP)
660 {
661 /* smw.adm Rb, [$sp], Re, enable4 */
662 if (cache != NULL)
663 nds32_push_multiple_words (cache, N32_RT5 (insn),
664 N32_RB5 (insn),
665 N32_LSMW_ENABLE4 (insn));
666 in_prologue_bb = 1;
667 continue;
668 }
669 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
670 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
671 {
672 /* add $sp, $sp, $ta */
673 /* add $sp, $ta, $sp */
674 if (val_ta < 0)
675 {
676 if (cache != NULL)
677 cache->sp_offset += -val_ta;
678
679 in_prologue_bb = 1;
680 continue;
681 }
682 }
683 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
684 {
685 /* movi $ta, imm20s */
686 if (cache != NULL)
687 val_ta = N32_IMM20S (insn);
688
689 continue;
690 }
691 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
692 {
693 /* sethi $ta, imm20u */
694 if (cache != NULL)
695 val_ta = N32_IMM20U (insn) << 12;
696
697 continue;
698 }
699 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
700 {
701 /* ori $ta, $ta, imm15u */
702 if (cache != NULL)
703 val_ta |= N32_IMM15U (insn);
704
705 continue;
706 }
707 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
708 {
709 /* addi $ta, $ta, imm15s */
710 if (cache != NULL)
711 val_ta += N32_IMM15S (insn);
712
713 continue;
714 }
715 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
716 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
717 {
718 /* add $gp, $ta, $gp */
719 /* add $gp, $gp, $ta */
720 in_prologue_bb = 1;
721 continue;
722 }
723 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
724 {
725 /* movi $gp, imm20s */
726 in_prologue_bb = 1;
727 continue;
728 }
729 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
730 {
731 /* sethi $gp, imm20u */
732 in_prologue_bb = 1;
733 continue;
734 }
735 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
736 {
737 /* ori $gp, $gp, imm15u */
738 in_prologue_bb = 1;
739 continue;
740 }
741 else
742 {
743 /* Jump/Branch insns never appear in prologue basic block.
744 The loop can be escaped early when these insns are met. */
745 if (in_prologue_bb == 1)
746 {
747 int op = N32_OP6 (insn);
748
749 if (op == N32_OP6_JI
750 || op == N32_OP6_JREG
751 || op == N32_OP6_BR1
752 || op == N32_OP6_BR2
753 || op == N32_OP6_BR3)
754 break;
755 }
756 }
757
758 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
759 && __GF (insn, 12, 3) == 0)
760 {
761 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
762 normal form (bit [12] == 0) is used. */
763
764 /* fsdi FDt, [$sp + (imm12s << 2)] */
765 if (N32_RA5 (insn) == REG_SP)
766 continue;
767 }
768
769 /* The optimizer might shove anything into the prologue, if
770 we build up cache (cache != NULL) from analyzing prologue,
771 we just skip what we don't recognize and analyze further to
772 make cache as complete as possible. However, if we skip
773 prologue, we'll stop immediately on unrecognized
774 instruction. */
775 if (cache == NULL)
776 break;
777 }
778 else
779 {
780 /* 16-bit instruction */
781 insn_len = 2;
782
783 insn >>= 16;
784
785 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
786 {
787 /* addi10s.sp */
788 int imm10s = N16_IMM10S (insn);
789
790 if (imm10s < 0)
791 {
792 if (cache != NULL)
793 cache->sp_offset += -imm10s;
794
795 in_prologue_bb = 1;
796 continue;
797 }
798 }
799 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
800 {
801 /* push25 */
802 if (cache != NULL)
803 {
804 int imm8u = (insn & 0x1f) << 3;
805 int re = (insn >> 5) & 0x3;
806 const int reg_map[] = { 6, 8, 10, 14 };
807
808 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
809 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
810
811 /* Operation 2 -- sp = sp - (imm5u << 3) */
812 cache->sp_offset += imm8u;
813 }
814
815 in_prologue_bb = 1;
816 continue;
817 }
818 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
819 {
820 /* add5.pc $gp */
821 in_prologue_bb = 1;
822 continue;
823 }
824 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
825 {
826 /* movi55 $gp, imm5s */
827 in_prologue_bb = 1;
828 continue;
829 }
830 else
831 {
832 /* Jump/Branch insns never appear in prologue basic block.
833 The loop can be escaped early when these insns are met. */
834 if (in_prologue_bb == 1)
835 {
836 uint32_t insn5 = CHOP_BITS (insn, 5);
837 uint32_t insn8 = CHOP_BITS (insn, 8);
838 uint32_t insn38 = CHOP_BITS (insn, 11);
839
840 if (insn5 == N16_TYPE5 (JR5, 0)
841 || insn5 == N16_TYPE5 (JRAL5, 0)
842 || insn5 == N16_TYPE5 (RET5, 0)
843 || insn8 == N16_TYPE8 (J8, 0)
844 || insn8 == N16_TYPE8 (BEQZS8, 0)
845 || insn8 == N16_TYPE8 (BNEZS8, 0)
846 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
847 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
848 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
849 || insn38 == N16_TYPE38 (BNES38, 0, 0))
850 break;
851 }
852 }
853
854 /* The optimizer might shove anything into the prologue, if
855 we build up cache (cache != NULL) from analyzing prologue,
856 we just skip what we don't recognize and analyze further to
857 make cache as complete as possible. However, if we skip
858 prologue, we'll stop immediately on unrecognized
859 instruction. */
860 if (cache == NULL)
861 break;
862 }
863 }
864
865 return pc;
866 }
867
868 /* Implement the "skip_prologue" gdbarch method.
869
870 Find the end of function prologue. */
871
872 static CORE_ADDR
873 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
874 {
875 CORE_ADDR func_addr, limit_pc;
876
877 /* See if we can determine the end of the prologue via the symbol table.
878 If so, then return either PC, or the PC after the prologue, whichever
879 is greater. */
880 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
881 {
882 CORE_ADDR post_prologue_pc
883 = skip_prologue_using_sal (gdbarch, func_addr);
884 if (post_prologue_pc != 0)
885 return std::max (pc, post_prologue_pc);
886 }
887
888 /* Can't determine prologue from the symbol table, need to examine
889 instructions. */
890
891 /* Find an upper limit on the function prologue using the debug
892 information. If the debug information could not be used to provide
893 that bound, then use an arbitrary large number as the upper bound. */
894 limit_pc = skip_prologue_using_sal (gdbarch, pc);
895 if (limit_pc == 0)
896 limit_pc = pc + 128; /* Magic. */
897
898 /* Find the end of prologue. */
899 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
900 }
901
902 /* Allocate and fill in *THIS_CACHE with information about the prologue of
903 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
904 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
905
906 static struct nds32_frame_cache *
907 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
908 {
909 struct gdbarch *gdbarch = get_frame_arch (this_frame);
910 struct nds32_frame_cache *cache;
911 CORE_ADDR current_pc;
912 ULONGEST prev_sp;
913 ULONGEST this_base;
914 int i;
915
916 if (*this_cache)
917 return (struct nds32_frame_cache *) *this_cache;
918
919 cache = nds32_alloc_frame_cache ();
920 *this_cache = cache;
921
922 cache->pc = get_frame_func (this_frame);
923 current_pc = get_frame_pc (this_frame);
924 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
925
926 /* Compute the previous frame's stack pointer (which is also the
927 frame's ID's stack address), and this frame's base pointer. */
928 if (cache->fp_offset != INVALID_OFFSET)
929 {
930 /* FP is set in prologue, so it can be used to calculate other info. */
931 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
932 prev_sp = this_base + cache->fp_offset;
933 }
934 else
935 {
936 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
937 prev_sp = this_base + cache->sp_offset;
938 }
939
940 cache->prev_sp = prev_sp;
941 cache->base = this_base;
942
943 /* Adjust all the saved registers such that they contain addresses
944 instead of offsets. */
945 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
946 if (cache->saved_regs[i] != REG_UNAVAIL)
947 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
948
949 return cache;
950 }
951
952 /* Implement the "this_id" frame_unwind method.
953
954 Our frame ID for a normal frame is the current function's starting
955 PC and the caller's SP when we were called. */
956
957 static void
958 nds32_frame_this_id (struct frame_info *this_frame,
959 void **this_cache, struct frame_id *this_id)
960 {
961 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
962
963 /* This marks the outermost frame. */
964 if (cache->prev_sp == 0)
965 return;
966
967 *this_id = frame_id_build (cache->prev_sp, cache->pc);
968 }
969
970 /* Implement the "prev_register" frame_unwind method. */
971
972 static struct value *
973 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
974 int regnum)
975 {
976 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
977
978 if (regnum == NDS32_SP_REGNUM)
979 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
980
981 /* The PC of the previous frame is stored in the LP register of
982 the current frame. */
983 if (regnum == NDS32_PC_REGNUM)
984 regnum = NDS32_LP_REGNUM;
985
986 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
987 return frame_unwind_got_memory (this_frame, regnum,
988 cache->saved_regs[regnum]);
989
990 return frame_unwind_got_register (this_frame, regnum, regnum);
991 }
992
993 static const struct frame_unwind nds32_frame_unwind =
994 {
995 NORMAL_FRAME,
996 default_frame_unwind_stop_reason,
997 nds32_frame_this_id,
998 nds32_frame_prev_register,
999 NULL,
1000 default_frame_sniffer,
1001 };
1002
1003 /* Return the frame base address of *THIS_FRAME. */
1004
1005 static CORE_ADDR
1006 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1007 {
1008 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1009
1010 return cache->base;
1011 }
1012
1013 static const struct frame_base nds32_frame_base =
1014 {
1015 &nds32_frame_unwind,
1016 nds32_frame_base_address,
1017 nds32_frame_base_address,
1018 nds32_frame_base_address
1019 };
1020 \f
1021 /* Helper function for instructions used to pop multiple words. */
1022
1023 static void
1024 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1025 int enable4)
1026 {
1027 CORE_ADDR sp_offset = cache->sp_offset;
1028 int i;
1029
1030 /* Skip case where re == rb == sp. */
1031 if ((rb < REG_FP) && (re < REG_FP))
1032 {
1033 for (i = rb; i <= re; i++)
1034 {
1035 cache->saved_regs[i] = sp_offset;
1036 sp_offset += 4;
1037 }
1038 }
1039
1040 /* Check FP, GP, LP in enable4. */
1041 for (i = 3; i >= 1; i--)
1042 {
1043 if ((enable4 >> i) & 0x1)
1044 {
1045 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1046 sp_offset += 4;
1047 }
1048 }
1049
1050 /* For sp, update the offset. */
1051 cache->sp_offset = sp_offset;
1052 }
1053
1054 /* The instruction sequences in NDS32 epilogue are
1055
1056 INSN_RESET_SP (optional)
1057 (If exists, this must be the first instruction in epilogue
1058 and the stack has not been destroyed.).
1059 INSN_RECOVER (optional).
1060 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1061
1062 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1063 the necessary information will be recorded. */
1064
1065 static inline int
1066 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1067 struct nds32_frame_cache *cache)
1068 {
1069 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1070 && N32_IMM15S (insn) > 0)
1071 /* addi $sp, $sp, imm15s */
1072 return INSN_RESET_SP;
1073 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1074 && N32_IMM15S (insn) < 0)
1075 /* addi $sp, $fp, imm15s */
1076 return INSN_RESET_SP;
1077 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1078 && N32_RA5 (insn) == REG_SP)
1079 {
1080 /* lmw.bim Rb, [$sp], Re, enable4 */
1081 if (cache != NULL)
1082 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1083 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1084
1085 return INSN_RECOVER;
1086 }
1087 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1088 /* ret $lp */
1089 return INSN_RETURN;
1090 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1091 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1092 /* add $sp, $sp, $ta */
1093 /* add $sp, $ta, $sp */
1094 return INSN_RESET_SP;
1095 else if (abi_use_fpr
1096 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1097 {
1098 if (__GF (insn, 12, 1) == 0)
1099 /* fldi FDt, [$sp + (imm12s << 2)] */
1100 return INSN_RECOVER;
1101 else
1102 {
1103 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1104 int offset = N32_IMM12S (insn) << 2;
1105
1106 if (offset == 8 || offset == 12)
1107 {
1108 if (cache != NULL)
1109 cache->sp_offset += offset;
1110
1111 return INSN_RECOVER;
1112 }
1113 }
1114 }
1115
1116 return INSN_NORMAL;
1117 }
1118
1119 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1120 the necessary information will be recorded. */
1121
1122 static inline int
1123 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1124 {
1125 if (insn == N16_TYPE5 (RET5, REG_LP))
1126 /* ret5 $lp */
1127 return INSN_RETURN;
1128 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1129 {
1130 /* addi10s.sp */
1131 int imm10s = N16_IMM10S (insn);
1132
1133 if (imm10s > 0)
1134 {
1135 if (cache != NULL)
1136 cache->sp_offset += imm10s;
1137
1138 return INSN_RECOVER;
1139 }
1140 }
1141 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1142 {
1143 /* pop25 */
1144 if (cache != NULL)
1145 {
1146 int imm8u = (insn & 0x1f) << 3;
1147 int re = (insn >> 5) & 0x3;
1148 const int reg_map[] = { 6, 8, 10, 14 };
1149
1150 /* Operation 1 -- sp = sp + (imm5u << 3) */
1151 cache->sp_offset += imm8u;
1152
1153 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1154 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1155 }
1156
1157 /* Operation 3 -- ret $lp */
1158 return INSN_RECOVER_RETURN;
1159 }
1160
1161 return INSN_NORMAL;
1162 }
1163
1164 /* Analyze a reasonable amount of instructions from the given PC to find
1165 the instruction used to return to the caller. Return 1 if the 'return'
1166 instruction could be found, 0 otherwise.
1167
1168 If CACHE is non-NULL, fill it in. */
1169
1170 static int
1171 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1172 struct nds32_frame_cache *cache)
1173 {
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1176 CORE_ADDR limit_pc;
1177 uint32_t insn, insn_len;
1178 int insn_type = INSN_NORMAL;
1179
1180 if (abi_use_fpr)
1181 limit_pc = pc + 48;
1182 else
1183 limit_pc = pc + 16;
1184
1185 for (; pc < limit_pc; pc += insn_len)
1186 {
1187 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1188
1189 if ((insn & 0x80000000) == 0)
1190 {
1191 /* 32-bit instruction */
1192 insn_len = 4;
1193
1194 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1195 if (insn_type == INSN_RETURN)
1196 return 1;
1197 else if (insn_type == INSN_RECOVER)
1198 continue;
1199 }
1200 else
1201 {
1202 /* 16-bit instruction */
1203 insn_len = 2;
1204
1205 insn >>= 16;
1206 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1207 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1208 return 1;
1209 else if (insn_type == INSN_RECOVER)
1210 continue;
1211 }
1212
1213 /* Stop the scan if this is an unexpected instruction. */
1214 break;
1215 }
1216
1217 return 0;
1218 }
1219
1220 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1221
1222 static int
1223 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1224 {
1225 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1226 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1227 int insn_type = INSN_NORMAL;
1228 int ret_found = 0;
1229 uint32_t insn;
1230
1231 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1232
1233 if ((insn & 0x80000000) == 0)
1234 {
1235 /* 32-bit instruction */
1236
1237 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1238 }
1239 else
1240 {
1241 /* 16-bit instruction */
1242
1243 insn >>= 16;
1244 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1245 }
1246
1247 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1248 return 0;
1249
1250 /* Search the required 'return' instruction within the following reasonable
1251 instructions. */
1252 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1253 if (ret_found == 0)
1254 return 0;
1255
1256 /* Scan backwards to make sure that the last instruction has adjusted
1257 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1258 just a heuristic, so the false positives will be acceptable. */
1259 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1260
1261 /* Only 16-bit instructions are possible at addr - 2. */
1262 if ((insn & 0x80000000) != 0)
1263 {
1264 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1265
1266 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1267 if (insn_type == INSN_RECOVER)
1268 return 1;
1269 }
1270
1271 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1272
1273 /* If this is a 16-bit instruction at addr - 4, then there must be another
1274 16-bit instruction at addr - 2, so only 32-bit instructions need to
1275 be analyzed here. */
1276 if ((insn & 0x80000000) == 0)
1277 {
1278 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1279
1280 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1281 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1282 return 1;
1283 }
1284
1285 return 0;
1286 }
1287
1288 /* Implement the "sniffer" frame_unwind method. */
1289
1290 static int
1291 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1292 struct frame_info *this_frame, void **this_cache)
1293 {
1294 if (frame_relative_level (this_frame) == 0)
1295 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1296 get_frame_pc (this_frame));
1297 else
1298 return 0;
1299 }
1300
1301 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1302 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1303 allocated. Return a pointer to the current nds32_frame_cache in
1304 *THIS_CACHE. */
1305
1306 static struct nds32_frame_cache *
1307 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1308 {
1309 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1310 struct nds32_frame_cache *cache;
1311 CORE_ADDR current_pc, current_sp;
1312 int i;
1313
1314 if (*this_cache)
1315 return (struct nds32_frame_cache *) *this_cache;
1316
1317 cache = nds32_alloc_frame_cache ();
1318 *this_cache = cache;
1319
1320 cache->pc = get_frame_func (this_frame);
1321 current_pc = get_frame_pc (this_frame);
1322 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1323
1324 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1325 cache->prev_sp = current_sp + cache->sp_offset;
1326
1327 /* Adjust all the saved registers such that they contain addresses
1328 instead of offsets. */
1329 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1330 if (cache->saved_regs[i] != REG_UNAVAIL)
1331 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1332
1333 return cache;
1334 }
1335
1336 /* Implement the "this_id" frame_unwind method. */
1337
1338 static void
1339 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1340 void **this_cache, struct frame_id *this_id)
1341 {
1342 struct nds32_frame_cache *cache
1343 = nds32_epilogue_frame_cache (this_frame, this_cache);
1344
1345 /* This marks the outermost frame. */
1346 if (cache->prev_sp == 0)
1347 return;
1348
1349 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1350 }
1351
1352 /* Implement the "prev_register" frame_unwind method. */
1353
1354 static struct value *
1355 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1356 void **this_cache, int regnum)
1357 {
1358 struct nds32_frame_cache *cache
1359 = nds32_epilogue_frame_cache (this_frame, this_cache);
1360
1361 if (regnum == NDS32_SP_REGNUM)
1362 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1363
1364 /* The PC of the previous frame is stored in the LP register of
1365 the current frame. */
1366 if (regnum == NDS32_PC_REGNUM)
1367 regnum = NDS32_LP_REGNUM;
1368
1369 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1370 return frame_unwind_got_memory (this_frame, regnum,
1371 cache->saved_regs[regnum]);
1372
1373 return frame_unwind_got_register (this_frame, regnum, regnum);
1374 }
1375
1376 static const struct frame_unwind nds32_epilogue_frame_unwind =
1377 {
1378 NORMAL_FRAME,
1379 default_frame_unwind_stop_reason,
1380 nds32_epilogue_frame_this_id,
1381 nds32_epilogue_frame_prev_register,
1382 NULL,
1383 nds32_epilogue_frame_sniffer
1384 };
1385 \f
1386 /* Implement the "dummy_id" gdbarch method. */
1387
1388 static struct frame_id
1389 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1390 {
1391 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1392
1393 return frame_id_build (sp, get_frame_pc (this_frame));
1394 }
1395
1396 /* Implement the "unwind_pc" gdbarch method. */
1397
1398 static CORE_ADDR
1399 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1400 {
1401 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1402 }
1403
1404 /* Implement the "unwind_sp" gdbarch method. */
1405
1406 static CORE_ADDR
1407 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1408 {
1409 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1410 }
1411 \f
1412 /* Floating type and struct type that has only one floating type member
1413 can pass value using FPU registers (when FPU ABI is used). */
1414
1415 static int
1416 nds32_check_calling_use_fpr (struct type *type)
1417 {
1418 struct type *t;
1419 enum type_code typecode;
1420
1421 t = type;
1422 while (1)
1423 {
1424 t = check_typedef (t);
1425 typecode = TYPE_CODE (t);
1426 if (typecode != TYPE_CODE_STRUCT)
1427 break;
1428 else if (TYPE_NFIELDS (t) != 1)
1429 return 0;
1430 else
1431 t = TYPE_FIELD_TYPE (t, 0);
1432 }
1433
1434 return typecode == TYPE_CODE_FLT;
1435 }
1436
1437 /* Return the alignment (in bytes) of the given type. */
1438
1439 static int
1440 nds32_type_align (struct type *type)
1441 {
1442 int n;
1443 int align;
1444 int falign;
1445
1446 type = check_typedef (type);
1447 switch (TYPE_CODE (type))
1448 {
1449 default:
1450 /* Should never happen. */
1451 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1452 return 4;
1453
1454 case TYPE_CODE_PTR:
1455 case TYPE_CODE_ENUM:
1456 case TYPE_CODE_INT:
1457 case TYPE_CODE_FLT:
1458 case TYPE_CODE_SET:
1459 case TYPE_CODE_RANGE:
1460 case TYPE_CODE_REF:
1461 case TYPE_CODE_CHAR:
1462 case TYPE_CODE_BOOL:
1463 return TYPE_LENGTH (type);
1464
1465 case TYPE_CODE_ARRAY:
1466 case TYPE_CODE_COMPLEX:
1467 return nds32_type_align (TYPE_TARGET_TYPE (type));
1468
1469 case TYPE_CODE_STRUCT:
1470 case TYPE_CODE_UNION:
1471 align = 1;
1472 for (n = 0; n < TYPE_NFIELDS (type); n++)
1473 {
1474 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1475 if (falign > align)
1476 align = falign;
1477 }
1478 return align;
1479 }
1480 }
1481
1482 /* Implement the "push_dummy_call" gdbarch method. */
1483
1484 static CORE_ADDR
1485 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1486 struct regcache *regcache, CORE_ADDR bp_addr,
1487 int nargs, struct value **args, CORE_ADDR sp,
1488 int struct_return, CORE_ADDR struct_addr)
1489 {
1490 const int REND = 6; /* End for register offset. */
1491 int goff = 0; /* Current gpr offset for argument. */
1492 int foff = 0; /* Current fpr offset for argument. */
1493 int soff = 0; /* Current stack offset for argument. */
1494 int i;
1495 ULONGEST regval;
1496 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1498 struct type *func_type = value_type (function);
1499 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1500 int abi_split = nds32_abi_split (tdep->elf_abi);
1501
1502 /* Set the return address. For the NDS32, the return breakpoint is
1503 always at BP_ADDR. */
1504 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1505
1506 /* If STRUCT_RETURN is true, then the struct return address (in
1507 STRUCT_ADDR) will consume the first argument-passing register.
1508 Both adjust the register count and store that value. */
1509 if (struct_return)
1510 {
1511 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1512 goff++;
1513 }
1514
1515 /* Now make sure there's space on the stack */
1516 for (i = 0; i < nargs; i++)
1517 {
1518 struct type *type = value_type (args[i]);
1519 int align = nds32_type_align (type);
1520
1521 /* If align is zero, it may be an empty struct.
1522 Just ignore the argument of empty struct. */
1523 if (align == 0)
1524 continue;
1525
1526 sp -= TYPE_LENGTH (type);
1527 sp = align_down (sp, align);
1528 }
1529
1530 /* Stack must be 8-byte aligned. */
1531 sp = align_down (sp, 8);
1532
1533 soff = 0;
1534 for (i = 0; i < nargs; i++)
1535 {
1536 const gdb_byte *val;
1537 int align, len;
1538 struct type *type;
1539 int calling_use_fpr;
1540 int use_fpr = 0;
1541
1542 type = value_type (args[i]);
1543 calling_use_fpr = nds32_check_calling_use_fpr (type);
1544 len = TYPE_LENGTH (type);
1545 align = nds32_type_align (type);
1546 val = value_contents (args[i]);
1547
1548 /* The size of a composite type larger than 4 bytes will be rounded
1549 up to the nearest multiple of 4. */
1550 if (len > 4)
1551 len = align_up (len, 4);
1552
1553 /* Variadic functions are handled differently between AABI and ABI2FP+.
1554
1555 For AABI, the caller pushes arguments in registers, callee stores
1556 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1557 Therefore, we don't have to handle variadic functions specially.
1558
1559 For ABI2FP+, the caller pushes only named arguments in registers
1560 and pushes all unnamed arguments in stack. */
1561
1562 if (abi_use_fpr && TYPE_VARARGS (func_type)
1563 && i >= TYPE_NFIELDS (func_type))
1564 goto use_stack;
1565
1566 /* Try to use FPRs to pass arguments only when
1567 1. The program is built using toolchain with FPU support.
1568 2. The type of this argument can use FPR to pass value. */
1569 use_fpr = abi_use_fpr && calling_use_fpr;
1570
1571 if (use_fpr)
1572 {
1573 if (tdep->fpu_freg == -1)
1574 goto error_no_fpr;
1575
1576 /* Adjust alignment. */
1577 if ((align >> 2) > 0)
1578 foff = align_up (foff, align >> 2);
1579
1580 if (foff < REND)
1581 {
1582 switch (len)
1583 {
1584 case 4:
1585 regcache_cooked_write (regcache,
1586 tdep->fs0_regnum + foff, val);
1587 foff++;
1588 break;
1589 case 8:
1590 regcache_cooked_write (regcache,
1591 NDS32_FD0_REGNUM + (foff >> 1), val);
1592 foff += 2;
1593 break;
1594 default:
1595 /* Long double? */
1596 internal_error (__FILE__, __LINE__,
1597 "Do not know how to handle %d-byte double.\n",
1598 len);
1599 break;
1600 }
1601 continue;
1602 }
1603 }
1604 else
1605 {
1606 /*
1607 When passing arguments using GPRs,
1608
1609 * A composite type not larger than 4 bytes is passed in $rN.
1610 The format is as if the value is loaded with load instruction
1611 of corresponding size (e.g., LB, LH, LW).
1612
1613 For example,
1614
1615 r0
1616 31 0
1617 LITTLE: [x x b a]
1618 BIG: [x x a b]
1619
1620 * Otherwise, a composite type is passed in consecutive registers.
1621 The size is rounded up to the nearest multiple of 4.
1622 The successive registers hold the parts of the argument as if
1623 were loaded using lmw instructions.
1624
1625 For example,
1626
1627 r0 r1
1628 31 0 31 0
1629 LITTLE: [d c b a] [x x x e]
1630 BIG: [a b c d] [e x x x]
1631 */
1632
1633 /* Adjust alignment. */
1634 if ((align >> 2) > 0)
1635 goff = align_up (goff, align >> 2);
1636
1637 if (len <= (REND - goff) * 4)
1638 {
1639 /* This argument can be passed wholly via GPRs. */
1640 while (len > 0)
1641 {
1642 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1643 byte_order);
1644 regcache_cooked_write_unsigned (regcache,
1645 NDS32_R0_REGNUM + goff,
1646 regval);
1647 len -= 4;
1648 val += 4;
1649 goff++;
1650 }
1651 continue;
1652 }
1653 else if (abi_split)
1654 {
1655 /* Some parts of this argument can be passed via GPRs. */
1656 while (goff < REND)
1657 {
1658 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1659 byte_order);
1660 regcache_cooked_write_unsigned (regcache,
1661 NDS32_R0_REGNUM + goff,
1662 regval);
1663 len -= 4;
1664 val += 4;
1665 goff++;
1666 }
1667 }
1668 }
1669
1670 use_stack:
1671 /*
1672 When pushing (split parts of) an argument into stack,
1673
1674 * A composite type not larger than 4 bytes is copied to different
1675 base address.
1676 In little-endian, the first byte of this argument is aligned
1677 at the low address of the next free word.
1678 In big-endian, the last byte of this argument is aligned
1679 at the high address of the next free word.
1680
1681 For example,
1682
1683 sp [ - ] [ c ] hi
1684 [ c ] [ b ]
1685 [ b ] [ a ]
1686 [ a ] [ - ] lo
1687 LITTLE BIG
1688 */
1689
1690 /* Adjust alignment. */
1691 soff = align_up (soff, align);
1692
1693 while (len > 0)
1694 {
1695 int rlen = (len > 4) ? 4 : len;
1696
1697 if (byte_order == BFD_ENDIAN_BIG)
1698 write_memory (sp + soff + 4 - rlen, val, rlen);
1699 else
1700 write_memory (sp + soff, val, rlen);
1701
1702 len -= 4;
1703 val += 4;
1704 soff += 4;
1705 }
1706 }
1707
1708 /* Finally, update the SP register. */
1709 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1710
1711 return sp;
1712
1713 error_no_fpr:
1714 /* If use_fpr, but no floating-point register exists,
1715 then it is an error. */
1716 error (_("Fail to call. FPU registers are required."));
1717 }
1718 \f
1719 /* Read, for architecture GDBARCH, a function return value of TYPE
1720 from REGCACHE, and copy that into VALBUF. */
1721
1722 static void
1723 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1724 struct regcache *regcache, gdb_byte *valbuf)
1725 {
1726 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1727 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1728 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1729 int calling_use_fpr;
1730 int len;
1731
1732 calling_use_fpr = nds32_check_calling_use_fpr (type);
1733 len = TYPE_LENGTH (type);
1734
1735 if (abi_use_fpr && calling_use_fpr)
1736 {
1737 if (len == 4)
1738 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1739 else if (len == 8)
1740 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1741 else
1742 internal_error (__FILE__, __LINE__,
1743 _("Cannot extract return value of %d bytes "
1744 "long floating-point."), len);
1745 }
1746 else
1747 {
1748 /*
1749 When returning result,
1750
1751 * A composite type not larger than 4 bytes is returned in $r0.
1752 The format is as if the result is loaded with load instruction
1753 of corresponding size (e.g., LB, LH, LW).
1754
1755 For example,
1756
1757 r0
1758 31 0
1759 LITTLE: [x x b a]
1760 BIG: [x x a b]
1761
1762 * Otherwise, a composite type not larger than 8 bytes is returned
1763 in $r0 and $r1.
1764 In little-endian, the first word is loaded in $r0.
1765 In big-endian, the last word is loaded in $r1.
1766
1767 For example,
1768
1769 r0 r1
1770 31 0 31 0
1771 LITTLE: [d c b a] [x x x e]
1772 BIG: [x x x a] [b c d e]
1773 */
1774
1775 ULONGEST tmp;
1776
1777 if (len < 4)
1778 {
1779 /* By using store_unsigned_integer we avoid having to do
1780 anything special for small big-endian values. */
1781 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1782 store_unsigned_integer (valbuf, len, byte_order, tmp);
1783 }
1784 else if (len == 4)
1785 {
1786 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1787 }
1788 else if (len < 8)
1789 {
1790 int len1, len2;
1791
1792 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1793 len2 = len - len1;
1794
1795 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1796 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1797
1798 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1799 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1800 }
1801 else
1802 {
1803 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1804 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1805 }
1806 }
1807 }
1808
1809 /* Write, for architecture GDBARCH, a function return value of TYPE
1810 from VALBUF into REGCACHE. */
1811
1812 static void
1813 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1814 struct regcache *regcache, const gdb_byte *valbuf)
1815 {
1816 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1818 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1819 int calling_use_fpr;
1820 int len;
1821
1822 calling_use_fpr = nds32_check_calling_use_fpr (type);
1823 len = TYPE_LENGTH (type);
1824
1825 if (abi_use_fpr && calling_use_fpr)
1826 {
1827 if (len == 4)
1828 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1829 else if (len == 8)
1830 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1831 else
1832 internal_error (__FILE__, __LINE__,
1833 _("Cannot store return value of %d bytes "
1834 "long floating-point."), len);
1835 }
1836 else
1837 {
1838 ULONGEST regval;
1839
1840 if (len < 4)
1841 {
1842 regval = extract_unsigned_integer (valbuf, len, byte_order);
1843 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1844 }
1845 else if (len == 4)
1846 {
1847 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1848 }
1849 else if (len < 8)
1850 {
1851 int len1, len2;
1852
1853 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1854 len2 = len - len1;
1855
1856 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1857 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1858
1859 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1860 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1861 regval);
1862 }
1863 else
1864 {
1865 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1866 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1867 }
1868 }
1869 }
1870
1871 /* Implement the "return_value" gdbarch method.
1872
1873 Determine, for architecture GDBARCH, how a return value of TYPE
1874 should be returned. If it is supposed to be returned in registers,
1875 and READBUF is non-zero, read the appropriate value from REGCACHE,
1876 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1877 from WRITEBUF into REGCACHE. */
1878
1879 static enum return_value_convention
1880 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1881 struct type *type, struct regcache *regcache,
1882 gdb_byte *readbuf, const gdb_byte *writebuf)
1883 {
1884 if (TYPE_LENGTH (type) > 8)
1885 {
1886 return RETURN_VALUE_STRUCT_CONVENTION;
1887 }
1888 else
1889 {
1890 if (readbuf != NULL)
1891 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1892 if (writebuf != NULL)
1893 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1894
1895 return RETURN_VALUE_REGISTER_CONVENTION;
1896 }
1897 }
1898 \f
1899 /* Implement the "get_longjmp_target" gdbarch method. */
1900
1901 static int
1902 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1903 {
1904 gdb_byte buf[4];
1905 CORE_ADDR jb_addr;
1906 struct gdbarch *gdbarch = get_frame_arch (frame);
1907 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1908
1909 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1910
1911 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1912 return 0;
1913
1914 *pc = extract_unsigned_integer (buf, 4, byte_order);
1915 return 1;
1916 }
1917 \f
1918 /* Validate the given TDESC, and fixed-number some registers in it.
1919 Return 0 if the given TDESC does not contain the required feature
1920 or not contain required registers. */
1921
1922 static int
1923 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1924 struct tdesc_arch_data *tdesc_data,
1925 int *fpu_freg, int *use_pseudo_fsrs)
1926 {
1927 const struct tdesc_feature *feature;
1928 int i, valid_p;
1929
1930 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1931 if (feature == NULL)
1932 return 0;
1933
1934 valid_p = 1;
1935 /* Validate and fixed-number R0-R10. */
1936 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1937 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1938 nds32_register_names[i]);
1939
1940 /* Validate R15. */
1941 valid_p &= tdesc_unnumbered_register (feature,
1942 nds32_register_names[NDS32_TA_REGNUM]);
1943
1944 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1945 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1946 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1947 nds32_register_names[i]);
1948
1949 if (!valid_p)
1950 return 0;
1951
1952 /* Fixed-number R11-R27. */
1953 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1954 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1955
1956 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1957 if (feature != NULL)
1958 {
1959 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1960 int freg = -1;
1961
1962 /* Guess FPU configuration via listed registers. */
1963 if (tdesc_unnumbered_register (feature, "fd31"))
1964 freg = 3;
1965 else if (tdesc_unnumbered_register (feature, "fd15"))
1966 freg = 2;
1967 else if (tdesc_unnumbered_register (feature, "fd7"))
1968 freg = 1;
1969 else if (tdesc_unnumbered_register (feature, "fd3"))
1970 freg = 0;
1971
1972 if (freg == -1)
1973 /* Required FDR is not found. */
1974 return 0;
1975 else
1976 *fpu_freg = freg;
1977
1978 /* Validate and fixed-number required FDRs. */
1979 num_fdr_regs = num_fdr_map[freg];
1980 for (i = 0; i < num_fdr_regs; i++)
1981 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1982 NDS32_FD0_REGNUM + i,
1983 nds32_fdr_register_names[i]);
1984 if (!valid_p)
1985 return 0;
1986
1987 /* Count the number of listed FSRs, and fixed-number them if present. */
1988 num_fsr_regs = num_fsr_map[freg];
1989 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1990 num_listed_fsr = 0;
1991 for (i = 0; i < num_fsr_regs; i++)
1992 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1993 fs0_regnum + i,
1994 nds32_fsr_register_names[i]);
1995
1996 if (num_listed_fsr == 0)
1997 /* No required FSRs are listed explicitly, make them pseudo registers
1998 of FDRs. */
1999 *use_pseudo_fsrs = 1;
2000 else if (num_listed_fsr == num_fsr_regs)
2001 /* All required FSRs are listed explicitly. */
2002 *use_pseudo_fsrs = 0;
2003 else
2004 /* Some required FSRs are missing. */
2005 return 0;
2006 }
2007
2008 return 1;
2009 }
2010
2011 /* Initialize the current architecture based on INFO. If possible,
2012 re-use an architecture from ARCHES, which is a list of
2013 architectures already created during this debugging session.
2014
2015 Called e.g. at program startup, when reading a core file, and when
2016 reading a binary file. */
2017
2018 static struct gdbarch *
2019 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2020 {
2021 struct gdbarch *gdbarch;
2022 struct gdbarch_tdep *tdep;
2023 struct gdbarch_list *best_arch;
2024 struct tdesc_arch_data *tdesc_data = NULL;
2025 const struct target_desc *tdesc = info.target_desc;
2026 int elf_abi = E_NDS_ABI_AABI;
2027 int fpu_freg = -1;
2028 int use_pseudo_fsrs = 0;
2029 int i, num_regs, maxregs;
2030
2031 /* Extract the elf_flags if available. */
2032 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2033 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2034
2035 /* If there is already a candidate, use it. */
2036 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2037 best_arch != NULL;
2038 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2039 {
2040 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2041
2042 if (idep->elf_abi != elf_abi)
2043 continue;
2044
2045 /* Found a match. */
2046 break;
2047 }
2048
2049 if (best_arch != NULL)
2050 return best_arch->gdbarch;
2051
2052 if (!tdesc_has_registers (tdesc))
2053 tdesc = tdesc_nds32;
2054
2055 tdesc_data = tdesc_data_alloc ();
2056
2057 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2058 {
2059 tdesc_data_cleanup (tdesc_data);
2060 return NULL;
2061 }
2062
2063 /* Allocate space for the new architecture. */
2064 tdep = XCNEW (struct gdbarch_tdep);
2065 tdep->fpu_freg = fpu_freg;
2066 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2067 tdep->fs0_regnum = -1;
2068 tdep->elf_abi = elf_abi;
2069
2070 gdbarch = gdbarch_alloc (&info, tdep);
2071
2072 if (fpu_freg == -1)
2073 num_regs = NDS32_NUM_REGS;
2074 else if (use_pseudo_fsrs == 1)
2075 {
2076 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2077 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2078 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2079 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2080 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2081
2082 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2083 }
2084 else
2085 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2086
2087 set_gdbarch_num_regs (gdbarch, num_regs);
2088 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2089
2090 /* Cache the register number of fs0. */
2091 if (fpu_freg != -1)
2092 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2093
2094 /* Add NDS32 register aliases. To avoid search in user register name space,
2095 user_reg_map_name_to_regnum is not used. */
2096 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2097 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2098 {
2099 int regnum, j;
2100
2101 regnum = -1;
2102 /* Search register name space. */
2103 for (j = 0; j < maxregs; j++)
2104 {
2105 const char *regname = gdbarch_register_name (gdbarch, j);
2106
2107 if (regname != NULL
2108 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2109 {
2110 regnum = j;
2111 break;
2112 }
2113 }
2114
2115 /* Try next alias entry if the given name can not be found in register
2116 name space. */
2117 if (regnum == -1)
2118 continue;
2119
2120 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2121 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2122 }
2123
2124 nds32_add_reggroups (gdbarch);
2125
2126 /* Hook in ABI-specific overrides, if they have been registered. */
2127 info.tdep_info = (void *) tdesc_data;
2128 gdbarch_init_osabi (info, gdbarch);
2129
2130 /* Override tdesc_register callbacks for system registers. */
2131 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2132
2133 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2134 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2135 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2136 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2137 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2138 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2139
2140 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2141 set_gdbarch_return_value (gdbarch, nds32_return_value);
2142 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2143
2144 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2145 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2146 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2147 nds32_breakpoint::kind_from_pc);
2148 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2149 nds32_breakpoint::bp_from_kind);
2150
2151 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2152 frame_base_set_default (gdbarch, &nds32_frame_base);
2153
2154 set_gdbarch_print_insn (gdbarch, print_insn_nds32);
2155
2156 /* Handle longjmp. */
2157 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2158
2159 /* The order of appending is the order it check frame. */
2160 dwarf2_append_unwinders (gdbarch);
2161 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2162 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2163
2164 return gdbarch;
2165 }
2166
2167 void
2168 _initialize_nds32_tdep (void)
2169 {
2170 /* Initialize gdbarch. */
2171 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2172
2173 initialize_tdesc_nds32 ();
2174 nds32_init_reggroups ();
2175 }
GDB Binutils - Deliverables
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