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gdb/nds32: Use type_align instead of nds32_type_align
[deliverable/binutils-gdb.git] / gdb / nds32-tdep.c
1 /* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2019 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "defs.h"
22 #include "frame.h"
23 #include "frame-unwind.h"
24 #include "frame-base.h"
25 #include "symtab.h"
26 #include "gdbtypes.h"
27 #include "gdbcore.h"
28 #include "value.h"
29 #include "reggroups.h"
30 #include "inferior.h"
31 #include "osabi.h"
32 #include "arch-utils.h"
33 #include "regcache.h"
34 #include "dis-asm.h"
35 #include "user-regs.h"
36 #include "elf-bfd.h"
37 #include "dwarf2-frame.h"
38 #include "remote.h"
39 #include "target-descriptions.h"
40
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
44 #include <algorithm>
45
46 #include "features/nds32.c"
47
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
51 #define N32_SMW_ADM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
53 #define N32_LMW_BIM \
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
55 #define N32_FLDI_SP \
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
57
58 /* Use an invalid address value as 'not available' marker. */
59 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
60
61 /* Use an impossible value as invalid offset. */
62 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
63
64 /* Instruction groups for NDS32 epilogue analysis. */
65 enum
66 {
67 /* Instructions used everywhere, not only in epilogue. */
68 INSN_NORMAL,
69 /* Instructions used to reset sp for local vars, arguments, etc. */
70 INSN_RESET_SP,
71 /* Instructions used to recover saved regs and to recover padding. */
72 INSN_RECOVER,
73 /* Instructions used to return to the caller. */
74 INSN_RETURN,
75 /* Instructions used to recover saved regs and to return to the caller. */
76 INSN_RECOVER_RETURN,
77 };
78
79 static const char *const nds32_register_names[] =
80 {
81 /* 32 GPRs. */
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
86 /* PC. */
87 "pc",
88 };
89
90 static const char *const nds32_fdr_register_names[] =
91 {
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
96 };
97
98 static const char *const nds32_fsr_register_names[] =
99 {
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
104 };
105
106 /* The number of registers for four FPU configuration options. */
107 const int num_fdr_map[] = { 4, 8, 16, 32 };
108 const int num_fsr_map[] = { 8, 16, 32, 32 };
109
110 /* Aliases for registers. */
111 static const struct
112 {
113 const char *name;
114 const char *alias;
115 } nds32_register_aliases[] =
116 {
117 {"r15", "ta"},
118 {"r26", "p0"},
119 {"r27", "p1"},
120 {"fp", "r28"},
121 {"gp", "r29"},
122 {"lp", "r30"},
123 {"sp", "r31"},
124
125 {"cr0", "cpu_ver"},
126 {"cr1", "icm_cfg"},
127 {"cr2", "dcm_cfg"},
128 {"cr3", "mmu_cfg"},
129 {"cr4", "msc_cfg"},
130 {"cr5", "core_id"},
131 {"cr6", "fucop_exist"},
132 {"cr7", "msc_cfg2"},
133
134 {"ir0", "psw"},
135 {"ir1", "ipsw"},
136 {"ir2", "p_psw"},
137 {"ir3", "ivb"},
138 {"ir4", "eva"},
139 {"ir5", "p_eva"},
140 {"ir6", "itype"},
141 {"ir7", "p_itype"},
142 {"ir8", "merr"},
143 {"ir9", "ipc"},
144 {"ir10", "p_ipc"},
145 {"ir11", "oipc"},
146 {"ir12", "p_p0"},
147 {"ir13", "p_p1"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
150 {"ir16", "sp_usr"},
151 {"ir17", "sp_priv"},
152 {"ir18", "int_pri"},
153 {"ir19", "int_ctrl"},
154 {"ir20", "sp_usr1"},
155 {"ir21", "sp_priv1"},
156 {"ir22", "sp_usr2"},
157 {"ir23", "sp_priv2"},
158 {"ir24", "sp_usr3"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
164
165 {"mr0", "mmu_ctl"},
166 {"mr1", "l1_pptb"},
167 {"mr2", "tlb_vpn"},
168 {"mr3", "tlb_data"},
169 {"mr4", "tlb_misc"},
170 {"mr5", "vlpt_idx"},
171 {"mr6", "ilmb"},
172 {"mr7", "dlmb"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
177
178 {"dr0", "bpc0"},
179 {"dr1", "bpc1"},
180 {"dr2", "bpc2"},
181 {"dr3", "bpc3"},
182 {"dr4", "bpc4"},
183 {"dr5", "bpc5"},
184 {"dr6", "bpc6"},
185 {"dr7", "bpc7"},
186 {"dr8", "bpa0"},
187 {"dr9", "bpa1"},
188 {"dr10", "bpa2"},
189 {"dr11", "bpa3"},
190 {"dr12", "bpa4"},
191 {"dr13", "bpa5"},
192 {"dr14", "bpa6"},
193 {"dr15", "bpa7"},
194 {"dr16", "bpam0"},
195 {"dr17", "bpam1"},
196 {"dr18", "bpam2"},
197 {"dr19", "bpam3"},
198 {"dr20", "bpam4"},
199 {"dr21", "bpam5"},
200 {"dr22", "bpam6"},
201 {"dr23", "bpam7"},
202 {"dr24", "bpv0"},
203 {"dr25", "bpv1"},
204 {"dr26", "bpv2"},
205 {"dr27", "bpv3"},
206 {"dr28", "bpv4"},
207 {"dr29", "bpv5"},
208 {"dr30", "bpv6"},
209 {"dr31", "bpv7"},
210 {"dr32", "bpcid0"},
211 {"dr33", "bpcid1"},
212 {"dr34", "bpcid2"},
213 {"dr35", "bpcid3"},
214 {"dr36", "bpcid4"},
215 {"dr37", "bpcid5"},
216 {"dr38", "bpcid6"},
217 {"dr39", "bpcid7"},
218 {"dr40", "edm_cfg"},
219 {"dr41", "edmsw"},
220 {"dr42", "edm_ctl"},
221 {"dr43", "edm_dtr"},
222 {"dr44", "bpmtc"},
223 {"dr45", "dimbr"},
224 {"dr46", "tecr0"},
225 {"dr47", "tecr1"},
226
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
230
231 {"pfr0", "pfmc0"},
232 {"pfr1", "pfmc1"},
233 {"pfr2", "pfmc2"},
234 {"pfr3", "pfm_ctl"},
235 {"pfr4", "pft_ctl"},
236
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
250
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
253
254 {"idr0", "sdz_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
257
258 {"secur0", "sfcr"},
259 {"secur1", "sign"},
260 {"secur2", "isign"},
261 {"secur3", "p_isign"},
262 };
263
264 /* Value of a register alias. BATON is the regnum of the corresponding
265 register. */
266
267 static struct value *
268 value_of_nds32_reg (struct frame_info *frame, const void *baton)
269 {
270 return value_of_register ((int) (intptr_t) baton, frame);
271 }
272 \f
273 /* Implement the "frame_align" gdbarch method. */
274
275 static CORE_ADDR
276 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
277 {
278 /* 8-byte aligned. */
279 return align_down (sp, 8);
280 }
281
282 /* The same insn machine code is used for little-endian and big-endian. */
283 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
284
285 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
286
287 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
288
289 static int
290 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
291 {
292 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
293 const int FSR = 38;
294 const int FDR = FSR + 32;
295
296 if (num >= 0 && num < 32)
297 {
298 /* General-purpose registers (R0 - R31). */
299 return num;
300 }
301 else if (num >= FSR && num < FSR + 32)
302 {
303 /* Single precision floating-point registers (FS0 - FS31). */
304 return num - FSR + tdep->fs0_regnum;
305 }
306 else if (num >= FDR && num < FDR + 32)
307 {
308 /* Double precision floating-point registers (FD0 - FD31). */
309 return num - FDR + NDS32_FD0_REGNUM;
310 }
311
312 /* No match, return a inaccessible register number. */
313 return -1;
314 }
315 \f
316 /* NDS32 register groups. */
317 static struct reggroup *nds32_cr_reggroup;
318 static struct reggroup *nds32_ir_reggroup;
319 static struct reggroup *nds32_mr_reggroup;
320 static struct reggroup *nds32_dr_reggroup;
321 static struct reggroup *nds32_pfr_reggroup;
322 static struct reggroup *nds32_hspr_reggroup;
323 static struct reggroup *nds32_dmar_reggroup;
324 static struct reggroup *nds32_racr_reggroup;
325 static struct reggroup *nds32_idr_reggroup;
326 static struct reggroup *nds32_secur_reggroup;
327
328 static void
329 nds32_init_reggroups (void)
330 {
331 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
332 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
333 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
334 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
335 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
336 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
337 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
338 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
339 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
340 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
341 }
342
343 static void
344 nds32_add_reggroups (struct gdbarch *gdbarch)
345 {
346 /* Add pre-defined register groups. */
347 reggroup_add (gdbarch, general_reggroup);
348 reggroup_add (gdbarch, float_reggroup);
349 reggroup_add (gdbarch, system_reggroup);
350 reggroup_add (gdbarch, all_reggroup);
351 reggroup_add (gdbarch, save_reggroup);
352 reggroup_add (gdbarch, restore_reggroup);
353
354 /* Add NDS32 register groups. */
355 reggroup_add (gdbarch, nds32_cr_reggroup);
356 reggroup_add (gdbarch, nds32_ir_reggroup);
357 reggroup_add (gdbarch, nds32_mr_reggroup);
358 reggroup_add (gdbarch, nds32_dr_reggroup);
359 reggroup_add (gdbarch, nds32_pfr_reggroup);
360 reggroup_add (gdbarch, nds32_hspr_reggroup);
361 reggroup_add (gdbarch, nds32_dmar_reggroup);
362 reggroup_add (gdbarch, nds32_racr_reggroup);
363 reggroup_add (gdbarch, nds32_idr_reggroup);
364 reggroup_add (gdbarch, nds32_secur_reggroup);
365 }
366
367 /* Implement the "register_reggroup_p" gdbarch method. */
368
369 static int
370 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
371 struct reggroup *reggroup)
372 {
373 const char *reg_name;
374 const char *group_name;
375 int ret;
376
377 if (reggroup == all_reggroup)
378 return 1;
379
380 /* General reggroup contains only GPRs and PC. */
381 if (reggroup == general_reggroup)
382 return regnum <= NDS32_PC_REGNUM;
383
384 if (reggroup == float_reggroup || reggroup == save_reggroup
385 || reggroup == restore_reggroup)
386 {
387 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
388 if (ret != -1)
389 return ret;
390
391 return default_register_reggroup_p (gdbarch, regnum, reggroup);
392 }
393
394 if (reggroup == system_reggroup)
395 return (regnum > NDS32_PC_REGNUM)
396 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
397
398 /* The NDS32 reggroup contains registers whose name is prefixed
399 by reggroup name. */
400 reg_name = gdbarch_register_name (gdbarch, regnum);
401 group_name = reggroup_name (reggroup);
402 return !strncmp (reg_name, group_name, strlen (group_name));
403 }
404 \f
405 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
406
407 static struct type *
408 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
409 {
410 regnum -= gdbarch_num_regs (gdbarch);
411
412 /* Currently, only FSRs could be defined as pseudo registers. */
413 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
414 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
415 floatformats_ieee_single);
416
417 warning (_("Unknown nds32 pseudo register %d."), regnum);
418 return NULL;
419 }
420
421 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
422
423 static const char *
424 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
425 {
426 regnum -= gdbarch_num_regs (gdbarch);
427
428 /* Currently, only FSRs could be defined as pseudo registers. */
429 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
430 return nds32_fsr_register_names[regnum];
431
432 warning (_("Unknown nds32 pseudo register %d."), regnum);
433 return NULL;
434 }
435
436 /* Implement the "pseudo_register_read" gdbarch method. */
437
438 static enum register_status
439 nds32_pseudo_register_read (struct gdbarch *gdbarch,
440 readable_regcache *regcache, int regnum,
441 gdb_byte *buf)
442 {
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 gdb_byte reg_buf[8];
445 int offset, fdr_regnum;
446 enum register_status status;
447
448 /* This function is registered in nds32_gdbarch_init only after these are
449 set. */
450 gdb_assert (tdep->fpu_freg != -1);
451 gdb_assert (tdep->use_pseudo_fsrs != 0);
452
453 regnum -= gdbarch_num_regs (gdbarch);
454
455 /* Currently, only FSRs could be defined as pseudo registers. */
456 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
457 {
458 /* fs0 is always the most significant half of fd0. */
459 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
460 offset = (regnum & 1) ? 4 : 0;
461 else
462 offset = (regnum & 1) ? 0 : 4;
463
464 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
465 status = regcache->raw_read (fdr_regnum, reg_buf);
466 if (status == REG_VALID)
467 memcpy (buf, reg_buf + offset, 4);
468
469 return status;
470 }
471
472 gdb_assert_not_reached ("invalid pseudo register number");
473 }
474
475 /* Implement the "pseudo_register_write" gdbarch method. */
476
477 static void
478 nds32_pseudo_register_write (struct gdbarch *gdbarch,
479 struct regcache *regcache, int regnum,
480 const gdb_byte *buf)
481 {
482 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
483 gdb_byte reg_buf[8];
484 int offset, fdr_regnum;
485
486 /* This function is registered in nds32_gdbarch_init only after these are
487 set. */
488 gdb_assert (tdep->fpu_freg != -1);
489 gdb_assert (tdep->use_pseudo_fsrs != 0);
490
491 regnum -= gdbarch_num_regs (gdbarch);
492
493 /* Currently, only FSRs could be defined as pseudo registers. */
494 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
495 {
496 /* fs0 is always the most significant half of fd0. */
497 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
498 offset = (regnum & 1) ? 4 : 0;
499 else
500 offset = (regnum & 1) ? 0 : 4;
501
502 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
503 regcache->raw_read (fdr_regnum, reg_buf);
504 memcpy (reg_buf + offset, buf, 4);
505 regcache->raw_write (fdr_regnum, reg_buf);
506 return;
507 }
508
509 gdb_assert_not_reached ("invalid pseudo register number");
510 }
511 \f
512 /* Helper function for NDS32 ABI. Return true if FPRs can be used
513 to pass function arguments and return value. */
514
515 static int
516 nds32_abi_use_fpr (int elf_abi)
517 {
518 return elf_abi == E_NDS_ABI_V2FP_PLUS;
519 }
520
521 /* Helper function for NDS32 ABI. Return true if GPRs and stack
522 can be used together to pass an argument. */
523
524 static int
525 nds32_abi_split (int elf_abi)
526 {
527 return elf_abi == E_NDS_ABI_AABI;
528 }
529
530 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
531
532 struct nds32_frame_cache
533 {
534 /* The previous frame's inner most stack address. Used as this
535 frame ID's stack_addr. */
536 CORE_ADDR prev_sp;
537
538 /* The frame's base, optionally used by the high-level debug info. */
539 CORE_ADDR base;
540
541 /* During prologue analysis, keep how far the SP and FP have been offset
542 from the start of the stack frame (as defined by the previous frame's
543 stack pointer).
544 During epilogue analysis, keep how far the SP has been offset from the
545 current stack pointer. */
546 CORE_ADDR sp_offset;
547 CORE_ADDR fp_offset;
548
549 /* The address of the first instruction in this function. */
550 CORE_ADDR pc;
551
552 /* Saved registers. */
553 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
554 };
555
556 /* Allocate and initialize a frame cache. */
557
558 static struct nds32_frame_cache *
559 nds32_alloc_frame_cache (void)
560 {
561 struct nds32_frame_cache *cache;
562 int i;
563
564 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
565
566 /* Initialize fp_offset to check if FP is set in prologue. */
567 cache->fp_offset = INVALID_OFFSET;
568
569 /* Saved registers. We initialize these to -1 since zero is a valid
570 offset. */
571 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
572 cache->saved_regs[i] = REG_UNAVAIL;
573
574 return cache;
575 }
576
577 /* Helper function for instructions used to push multiple words. */
578
579 static void
580 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
581 int enable4)
582 {
583 CORE_ADDR sp_offset = cache->sp_offset;
584 int i;
585
586 /* Check LP, GP, FP in enable4. */
587 for (i = 1; i <= 3; i++)
588 {
589 if ((enable4 >> i) & 0x1)
590 {
591 sp_offset += 4;
592 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
593 }
594 }
595
596 /* Skip case where re == rb == sp. */
597 if ((rb < REG_FP) && (re < REG_FP))
598 {
599 for (i = re; i >= rb; i--)
600 {
601 sp_offset += 4;
602 cache->saved_regs[i] = sp_offset;
603 }
604 }
605
606 /* For sp, update the offset. */
607 cache->sp_offset = sp_offset;
608 }
609
610 /* Analyze the instructions within the given address range. If CACHE
611 is non-NULL, fill it in. Return the first address beyond the given
612 address range. If CACHE is NULL, return the first address not
613 recognized as a prologue instruction. */
614
615 static CORE_ADDR
616 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
617 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
618 {
619 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
620 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
621 /* Current scanning status. */
622 int in_prologue_bb = 0;
623 int val_ta = 0;
624 uint32_t insn, insn_len;
625
626 for (; pc < limit_pc; pc += insn_len)
627 {
628 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
629
630 if ((insn & 0x80000000) == 0)
631 {
632 /* 32-bit instruction */
633 insn_len = 4;
634
635 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
636 {
637 /* addi $sp, $sp, imm15s */
638 int imm15s = N32_IMM15S (insn);
639
640 if (imm15s < 0)
641 {
642 if (cache != NULL)
643 cache->sp_offset += -imm15s;
644
645 in_prologue_bb = 1;
646 continue;
647 }
648 }
649 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
650 {
651 /* addi $fp, $sp, imm15s */
652 int imm15s = N32_IMM15S (insn);
653
654 if (imm15s > 0)
655 {
656 if (cache != NULL)
657 cache->fp_offset = cache->sp_offset - imm15s;
658
659 in_prologue_bb = 1;
660 continue;
661 }
662 }
663 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
664 && N32_RA5 (insn) == REG_SP)
665 {
666 /* smw.adm Rb, [$sp], Re, enable4 */
667 if (cache != NULL)
668 nds32_push_multiple_words (cache, N32_RT5 (insn),
669 N32_RB5 (insn),
670 N32_LSMW_ENABLE4 (insn));
671 in_prologue_bb = 1;
672 continue;
673 }
674 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
675 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
676 {
677 /* add $sp, $sp, $ta */
678 /* add $sp, $ta, $sp */
679 if (val_ta < 0)
680 {
681 if (cache != NULL)
682 cache->sp_offset += -val_ta;
683
684 in_prologue_bb = 1;
685 continue;
686 }
687 }
688 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
689 {
690 /* movi $ta, imm20s */
691 if (cache != NULL)
692 val_ta = N32_IMM20S (insn);
693
694 continue;
695 }
696 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
697 {
698 /* sethi $ta, imm20u */
699 if (cache != NULL)
700 val_ta = N32_IMM20U (insn) << 12;
701
702 continue;
703 }
704 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
705 {
706 /* ori $ta, $ta, imm15u */
707 if (cache != NULL)
708 val_ta |= N32_IMM15U (insn);
709
710 continue;
711 }
712 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
713 {
714 /* addi $ta, $ta, imm15s */
715 if (cache != NULL)
716 val_ta += N32_IMM15S (insn);
717
718 continue;
719 }
720 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
721 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
722 {
723 /* add $gp, $ta, $gp */
724 /* add $gp, $gp, $ta */
725 in_prologue_bb = 1;
726 continue;
727 }
728 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
729 {
730 /* movi $gp, imm20s */
731 in_prologue_bb = 1;
732 continue;
733 }
734 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
735 {
736 /* sethi $gp, imm20u */
737 in_prologue_bb = 1;
738 continue;
739 }
740 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
741 {
742 /* ori $gp, $gp, imm15u */
743 in_prologue_bb = 1;
744 continue;
745 }
746 else
747 {
748 /* Jump/Branch insns never appear in prologue basic block.
749 The loop can be escaped early when these insns are met. */
750 if (in_prologue_bb == 1)
751 {
752 int op = N32_OP6 (insn);
753
754 if (op == N32_OP6_JI
755 || op == N32_OP6_JREG
756 || op == N32_OP6_BR1
757 || op == N32_OP6_BR2
758 || op == N32_OP6_BR3)
759 break;
760 }
761 }
762
763 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
764 && __GF (insn, 12, 3) == 0)
765 {
766 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
767 normal form (bit [12] == 0) is used. */
768
769 /* fsdi FDt, [$sp + (imm12s << 2)] */
770 if (N32_RA5 (insn) == REG_SP)
771 continue;
772 }
773
774 /* The optimizer might shove anything into the prologue, if
775 we build up cache (cache != NULL) from analyzing prologue,
776 we just skip what we don't recognize and analyze further to
777 make cache as complete as possible. However, if we skip
778 prologue, we'll stop immediately on unrecognized
779 instruction. */
780 if (cache == NULL)
781 break;
782 }
783 else
784 {
785 /* 16-bit instruction */
786 insn_len = 2;
787
788 insn >>= 16;
789
790 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
791 {
792 /* addi10s.sp */
793 int imm10s = N16_IMM10S (insn);
794
795 if (imm10s < 0)
796 {
797 if (cache != NULL)
798 cache->sp_offset += -imm10s;
799
800 in_prologue_bb = 1;
801 continue;
802 }
803 }
804 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
805 {
806 /* push25 */
807 if (cache != NULL)
808 {
809 int imm8u = (insn & 0x1f) << 3;
810 int re = (insn >> 5) & 0x3;
811 const int reg_map[] = { 6, 8, 10, 14 };
812
813 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
814 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
815
816 /* Operation 2 -- sp = sp - (imm5u << 3) */
817 cache->sp_offset += imm8u;
818 }
819
820 in_prologue_bb = 1;
821 continue;
822 }
823 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
824 {
825 /* add5.pc $gp */
826 in_prologue_bb = 1;
827 continue;
828 }
829 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
830 {
831 /* movi55 $gp, imm5s */
832 in_prologue_bb = 1;
833 continue;
834 }
835 else
836 {
837 /* Jump/Branch insns never appear in prologue basic block.
838 The loop can be escaped early when these insns are met. */
839 if (in_prologue_bb == 1)
840 {
841 uint32_t insn5 = CHOP_BITS (insn, 5);
842 uint32_t insn8 = CHOP_BITS (insn, 8);
843 uint32_t insn38 = CHOP_BITS (insn, 11);
844
845 if (insn5 == N16_TYPE5 (JR5, 0)
846 || insn5 == N16_TYPE5 (JRAL5, 0)
847 || insn5 == N16_TYPE5 (RET5, 0)
848 || insn8 == N16_TYPE8 (J8, 0)
849 || insn8 == N16_TYPE8 (BEQZS8, 0)
850 || insn8 == N16_TYPE8 (BNEZS8, 0)
851 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
852 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
853 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
854 || insn38 == N16_TYPE38 (BNES38, 0, 0))
855 break;
856 }
857 }
858
859 /* The optimizer might shove anything into the prologue, if
860 we build up cache (cache != NULL) from analyzing prologue,
861 we just skip what we don't recognize and analyze further to
862 make cache as complete as possible. However, if we skip
863 prologue, we'll stop immediately on unrecognized
864 instruction. */
865 if (cache == NULL)
866 break;
867 }
868 }
869
870 return pc;
871 }
872
873 /* Implement the "skip_prologue" gdbarch method.
874
875 Find the end of function prologue. */
876
877 static CORE_ADDR
878 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
879 {
880 CORE_ADDR func_addr, limit_pc;
881
882 /* See if we can determine the end of the prologue via the symbol table.
883 If so, then return either PC, or the PC after the prologue, whichever
884 is greater. */
885 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
886 {
887 CORE_ADDR post_prologue_pc
888 = skip_prologue_using_sal (gdbarch, func_addr);
889 if (post_prologue_pc != 0)
890 return std::max (pc, post_prologue_pc);
891 }
892
893 /* Can't determine prologue from the symbol table, need to examine
894 instructions. */
895
896 /* Find an upper limit on the function prologue using the debug
897 information. If the debug information could not be used to provide
898 that bound, then use an arbitrary large number as the upper bound. */
899 limit_pc = skip_prologue_using_sal (gdbarch, pc);
900 if (limit_pc == 0)
901 limit_pc = pc + 128; /* Magic. */
902
903 /* Find the end of prologue. */
904 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
905 }
906
907 /* Allocate and fill in *THIS_CACHE with information about the prologue of
908 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
909 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
910
911 static struct nds32_frame_cache *
912 nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
913 {
914 struct gdbarch *gdbarch = get_frame_arch (this_frame);
915 struct nds32_frame_cache *cache;
916 CORE_ADDR current_pc;
917 ULONGEST prev_sp;
918 ULONGEST this_base;
919 int i;
920
921 if (*this_cache)
922 return (struct nds32_frame_cache *) *this_cache;
923
924 cache = nds32_alloc_frame_cache ();
925 *this_cache = cache;
926
927 cache->pc = get_frame_func (this_frame);
928 current_pc = get_frame_pc (this_frame);
929 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
930
931 /* Compute the previous frame's stack pointer (which is also the
932 frame's ID's stack address), and this frame's base pointer. */
933 if (cache->fp_offset != INVALID_OFFSET)
934 {
935 /* FP is set in prologue, so it can be used to calculate other info. */
936 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
937 prev_sp = this_base + cache->fp_offset;
938 }
939 else
940 {
941 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
942 prev_sp = this_base + cache->sp_offset;
943 }
944
945 cache->prev_sp = prev_sp;
946 cache->base = this_base;
947
948 /* Adjust all the saved registers such that they contain addresses
949 instead of offsets. */
950 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
951 if (cache->saved_regs[i] != REG_UNAVAIL)
952 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
953
954 return cache;
955 }
956
957 /* Implement the "this_id" frame_unwind method.
958
959 Our frame ID for a normal frame is the current function's starting
960 PC and the caller's SP when we were called. */
961
962 static void
963 nds32_frame_this_id (struct frame_info *this_frame,
964 void **this_cache, struct frame_id *this_id)
965 {
966 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
967
968 /* This marks the outermost frame. */
969 if (cache->prev_sp == 0)
970 return;
971
972 *this_id = frame_id_build (cache->prev_sp, cache->pc);
973 }
974
975 /* Implement the "prev_register" frame_unwind method. */
976
977 static struct value *
978 nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
979 int regnum)
980 {
981 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
982
983 if (regnum == NDS32_SP_REGNUM)
984 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
985
986 /* The PC of the previous frame is stored in the LP register of
987 the current frame. */
988 if (regnum == NDS32_PC_REGNUM)
989 regnum = NDS32_LP_REGNUM;
990
991 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
992 return frame_unwind_got_memory (this_frame, regnum,
993 cache->saved_regs[regnum]);
994
995 return frame_unwind_got_register (this_frame, regnum, regnum);
996 }
997
998 static const struct frame_unwind nds32_frame_unwind =
999 {
1000 NORMAL_FRAME,
1001 default_frame_unwind_stop_reason,
1002 nds32_frame_this_id,
1003 nds32_frame_prev_register,
1004 NULL,
1005 default_frame_sniffer,
1006 };
1007
1008 /* Return the frame base address of *THIS_FRAME. */
1009
1010 static CORE_ADDR
1011 nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1012 {
1013 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1014
1015 return cache->base;
1016 }
1017
1018 static const struct frame_base nds32_frame_base =
1019 {
1020 &nds32_frame_unwind,
1021 nds32_frame_base_address,
1022 nds32_frame_base_address,
1023 nds32_frame_base_address
1024 };
1025 \f
1026 /* Helper function for instructions used to pop multiple words. */
1027
1028 static void
1029 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1030 int enable4)
1031 {
1032 CORE_ADDR sp_offset = cache->sp_offset;
1033 int i;
1034
1035 /* Skip case where re == rb == sp. */
1036 if ((rb < REG_FP) && (re < REG_FP))
1037 {
1038 for (i = rb; i <= re; i++)
1039 {
1040 cache->saved_regs[i] = sp_offset;
1041 sp_offset += 4;
1042 }
1043 }
1044
1045 /* Check FP, GP, LP in enable4. */
1046 for (i = 3; i >= 1; i--)
1047 {
1048 if ((enable4 >> i) & 0x1)
1049 {
1050 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1051 sp_offset += 4;
1052 }
1053 }
1054
1055 /* For sp, update the offset. */
1056 cache->sp_offset = sp_offset;
1057 }
1058
1059 /* The instruction sequences in NDS32 epilogue are
1060
1061 INSN_RESET_SP (optional)
1062 (If exists, this must be the first instruction in epilogue
1063 and the stack has not been destroyed.).
1064 INSN_RECOVER (optional).
1065 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1066
1067 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1068 the necessary information will be recorded. */
1069
1070 static inline int
1071 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1072 struct nds32_frame_cache *cache)
1073 {
1074 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1075 && N32_IMM15S (insn) > 0)
1076 /* addi $sp, $sp, imm15s */
1077 return INSN_RESET_SP;
1078 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1079 && N32_IMM15S (insn) < 0)
1080 /* addi $sp, $fp, imm15s */
1081 return INSN_RESET_SP;
1082 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1083 && N32_RA5 (insn) == REG_SP)
1084 {
1085 /* lmw.bim Rb, [$sp], Re, enable4 */
1086 if (cache != NULL)
1087 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1088 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1089
1090 return INSN_RECOVER;
1091 }
1092 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1093 /* ret $lp */
1094 return INSN_RETURN;
1095 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1096 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1097 /* add $sp, $sp, $ta */
1098 /* add $sp, $ta, $sp */
1099 return INSN_RESET_SP;
1100 else if (abi_use_fpr
1101 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1102 {
1103 if (__GF (insn, 12, 1) == 0)
1104 /* fldi FDt, [$sp + (imm12s << 2)] */
1105 return INSN_RECOVER;
1106 else
1107 {
1108 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1109 int offset = N32_IMM12S (insn) << 2;
1110
1111 if (offset == 8 || offset == 12)
1112 {
1113 if (cache != NULL)
1114 cache->sp_offset += offset;
1115
1116 return INSN_RECOVER;
1117 }
1118 }
1119 }
1120
1121 return INSN_NORMAL;
1122 }
1123
1124 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1125 the necessary information will be recorded. */
1126
1127 static inline int
1128 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1129 {
1130 if (insn == N16_TYPE5 (RET5, REG_LP))
1131 /* ret5 $lp */
1132 return INSN_RETURN;
1133 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1134 {
1135 /* addi10s.sp */
1136 int imm10s = N16_IMM10S (insn);
1137
1138 if (imm10s > 0)
1139 {
1140 if (cache != NULL)
1141 cache->sp_offset += imm10s;
1142
1143 return INSN_RECOVER;
1144 }
1145 }
1146 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1147 {
1148 /* pop25 */
1149 if (cache != NULL)
1150 {
1151 int imm8u = (insn & 0x1f) << 3;
1152 int re = (insn >> 5) & 0x3;
1153 const int reg_map[] = { 6, 8, 10, 14 };
1154
1155 /* Operation 1 -- sp = sp + (imm5u << 3) */
1156 cache->sp_offset += imm8u;
1157
1158 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1159 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1160 }
1161
1162 /* Operation 3 -- ret $lp */
1163 return INSN_RECOVER_RETURN;
1164 }
1165
1166 return INSN_NORMAL;
1167 }
1168
1169 /* Analyze a reasonable amount of instructions from the given PC to find
1170 the instruction used to return to the caller. Return 1 if the 'return'
1171 instruction could be found, 0 otherwise.
1172
1173 If CACHE is non-NULL, fill it in. */
1174
1175 static int
1176 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1177 struct nds32_frame_cache *cache)
1178 {
1179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1180 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1181 CORE_ADDR limit_pc;
1182 uint32_t insn, insn_len;
1183 int insn_type = INSN_NORMAL;
1184
1185 if (abi_use_fpr)
1186 limit_pc = pc + 48;
1187 else
1188 limit_pc = pc + 16;
1189
1190 for (; pc < limit_pc; pc += insn_len)
1191 {
1192 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1193
1194 if ((insn & 0x80000000) == 0)
1195 {
1196 /* 32-bit instruction */
1197 insn_len = 4;
1198
1199 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1200 if (insn_type == INSN_RETURN)
1201 return 1;
1202 else if (insn_type == INSN_RECOVER)
1203 continue;
1204 }
1205 else
1206 {
1207 /* 16-bit instruction */
1208 insn_len = 2;
1209
1210 insn >>= 16;
1211 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1212 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1213 return 1;
1214 else if (insn_type == INSN_RECOVER)
1215 continue;
1216 }
1217
1218 /* Stop the scan if this is an unexpected instruction. */
1219 break;
1220 }
1221
1222 return 0;
1223 }
1224
1225 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1226
1227 static int
1228 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1229 {
1230 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1231 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1232 int insn_type = INSN_NORMAL;
1233 int ret_found = 0;
1234 uint32_t insn;
1235
1236 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1237
1238 if ((insn & 0x80000000) == 0)
1239 {
1240 /* 32-bit instruction */
1241
1242 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1243 }
1244 else
1245 {
1246 /* 16-bit instruction */
1247
1248 insn >>= 16;
1249 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1250 }
1251
1252 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1253 return 0;
1254
1255 /* Search the required 'return' instruction within the following reasonable
1256 instructions. */
1257 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1258 if (ret_found == 0)
1259 return 0;
1260
1261 /* Scan backwards to make sure that the last instruction has adjusted
1262 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1263 just a heuristic, so the false positives will be acceptable. */
1264 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1265
1266 /* Only 16-bit instructions are possible at addr - 2. */
1267 if ((insn & 0x80000000) != 0)
1268 {
1269 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1270
1271 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1272 if (insn_type == INSN_RECOVER)
1273 return 1;
1274 }
1275
1276 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1277
1278 /* If this is a 16-bit instruction at addr - 4, then there must be another
1279 16-bit instruction at addr - 2, so only 32-bit instructions need to
1280 be analyzed here. */
1281 if ((insn & 0x80000000) == 0)
1282 {
1283 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1284
1285 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1286 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1287 return 1;
1288 }
1289
1290 return 0;
1291 }
1292
1293 /* Implement the "sniffer" frame_unwind method. */
1294
1295 static int
1296 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1297 struct frame_info *this_frame, void **this_cache)
1298 {
1299 if (frame_relative_level (this_frame) == 0)
1300 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1301 get_frame_pc (this_frame));
1302 else
1303 return 0;
1304 }
1305
1306 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1307 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1308 allocated. Return a pointer to the current nds32_frame_cache in
1309 *THIS_CACHE. */
1310
1311 static struct nds32_frame_cache *
1312 nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1313 {
1314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1315 struct nds32_frame_cache *cache;
1316 CORE_ADDR current_pc, current_sp;
1317 int i;
1318
1319 if (*this_cache)
1320 return (struct nds32_frame_cache *) *this_cache;
1321
1322 cache = nds32_alloc_frame_cache ();
1323 *this_cache = cache;
1324
1325 cache->pc = get_frame_func (this_frame);
1326 current_pc = get_frame_pc (this_frame);
1327 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1328
1329 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1330 cache->prev_sp = current_sp + cache->sp_offset;
1331
1332 /* Adjust all the saved registers such that they contain addresses
1333 instead of offsets. */
1334 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1335 if (cache->saved_regs[i] != REG_UNAVAIL)
1336 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1337
1338 return cache;
1339 }
1340
1341 /* Implement the "this_id" frame_unwind method. */
1342
1343 static void
1344 nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1345 void **this_cache, struct frame_id *this_id)
1346 {
1347 struct nds32_frame_cache *cache
1348 = nds32_epilogue_frame_cache (this_frame, this_cache);
1349
1350 /* This marks the outermost frame. */
1351 if (cache->prev_sp == 0)
1352 return;
1353
1354 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1355 }
1356
1357 /* Implement the "prev_register" frame_unwind method. */
1358
1359 static struct value *
1360 nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1361 void **this_cache, int regnum)
1362 {
1363 struct nds32_frame_cache *cache
1364 = nds32_epilogue_frame_cache (this_frame, this_cache);
1365
1366 if (regnum == NDS32_SP_REGNUM)
1367 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1368
1369 /* The PC of the previous frame is stored in the LP register of
1370 the current frame. */
1371 if (regnum == NDS32_PC_REGNUM)
1372 regnum = NDS32_LP_REGNUM;
1373
1374 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1375 return frame_unwind_got_memory (this_frame, regnum,
1376 cache->saved_regs[regnum]);
1377
1378 return frame_unwind_got_register (this_frame, regnum, regnum);
1379 }
1380
1381 static const struct frame_unwind nds32_epilogue_frame_unwind =
1382 {
1383 NORMAL_FRAME,
1384 default_frame_unwind_stop_reason,
1385 nds32_epilogue_frame_this_id,
1386 nds32_epilogue_frame_prev_register,
1387 NULL,
1388 nds32_epilogue_frame_sniffer
1389 };
1390 \f
1391 /* Implement the "dummy_id" gdbarch method. */
1392
1393 static struct frame_id
1394 nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1395 {
1396 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1397
1398 return frame_id_build (sp, get_frame_pc (this_frame));
1399 }
1400
1401 /* Implement the "unwind_pc" gdbarch method. */
1402
1403 static CORE_ADDR
1404 nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1405 {
1406 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1407 }
1408
1409 /* Implement the "unwind_sp" gdbarch method. */
1410
1411 static CORE_ADDR
1412 nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1413 {
1414 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1415 }
1416 \f
1417 /* Floating type and struct type that has only one floating type member
1418 can pass value using FPU registers (when FPU ABI is used). */
1419
1420 static int
1421 nds32_check_calling_use_fpr (struct type *type)
1422 {
1423 struct type *t;
1424 enum type_code typecode;
1425
1426 t = type;
1427 while (1)
1428 {
1429 t = check_typedef (t);
1430 typecode = TYPE_CODE (t);
1431 if (typecode != TYPE_CODE_STRUCT)
1432 break;
1433 else if (TYPE_NFIELDS (t) != 1)
1434 return 0;
1435 else
1436 t = TYPE_FIELD_TYPE (t, 0);
1437 }
1438
1439 return typecode == TYPE_CODE_FLT;
1440 }
1441
1442 /* Implement the "push_dummy_call" gdbarch method. */
1443
1444 static CORE_ADDR
1445 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1446 struct regcache *regcache, CORE_ADDR bp_addr,
1447 int nargs, struct value **args, CORE_ADDR sp,
1448 function_call_return_method return_method,
1449 CORE_ADDR struct_addr)
1450 {
1451 const int REND = 6; /* End for register offset. */
1452 int goff = 0; /* Current gpr offset for argument. */
1453 int foff = 0; /* Current fpr offset for argument. */
1454 int soff = 0; /* Current stack offset for argument. */
1455 int i;
1456 ULONGEST regval;
1457 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1458 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1459 struct type *func_type = value_type (function);
1460 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1461 int abi_split = nds32_abi_split (tdep->elf_abi);
1462
1463 /* Set the return address. For the NDS32, the return breakpoint is
1464 always at BP_ADDR. */
1465 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1466
1467 /* If STRUCT_RETURN is true, then the struct return address (in
1468 STRUCT_ADDR) will consume the first argument-passing register.
1469 Both adjust the register count and store that value. */
1470 if (return_method == return_method_struct)
1471 {
1472 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1473 goff++;
1474 }
1475
1476 /* Now make sure there's space on the stack */
1477 for (i = 0; i < nargs; i++)
1478 {
1479 struct type *type = value_type (args[i]);
1480 int align = type_align (type);
1481
1482 /* If align is zero, it may be an empty struct.
1483 Just ignore the argument of empty struct. */
1484 if (align == 0)
1485 continue;
1486
1487 sp -= TYPE_LENGTH (type);
1488 sp = align_down (sp, align);
1489 }
1490
1491 /* Stack must be 8-byte aligned. */
1492 sp = align_down (sp, 8);
1493
1494 soff = 0;
1495 for (i = 0; i < nargs; i++)
1496 {
1497 const gdb_byte *val;
1498 int align, len;
1499 struct type *type;
1500 int calling_use_fpr;
1501 int use_fpr = 0;
1502
1503 type = value_type (args[i]);
1504 calling_use_fpr = nds32_check_calling_use_fpr (type);
1505 len = TYPE_LENGTH (type);
1506 align = type_align (type);
1507 val = value_contents (args[i]);
1508
1509 /* The size of a composite type larger than 4 bytes will be rounded
1510 up to the nearest multiple of 4. */
1511 if (len > 4)
1512 len = align_up (len, 4);
1513
1514 /* Variadic functions are handled differently between AABI and ABI2FP+.
1515
1516 For AABI, the caller pushes arguments in registers, callee stores
1517 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1518 Therefore, we don't have to handle variadic functions specially.
1519
1520 For ABI2FP+, the caller pushes only named arguments in registers
1521 and pushes all unnamed arguments in stack. */
1522
1523 if (abi_use_fpr && TYPE_VARARGS (func_type)
1524 && i >= TYPE_NFIELDS (func_type))
1525 goto use_stack;
1526
1527 /* Try to use FPRs to pass arguments only when
1528 1. The program is built using toolchain with FPU support.
1529 2. The type of this argument can use FPR to pass value. */
1530 use_fpr = abi_use_fpr && calling_use_fpr;
1531
1532 if (use_fpr)
1533 {
1534 if (tdep->fpu_freg == -1)
1535 goto error_no_fpr;
1536
1537 /* Adjust alignment. */
1538 if ((align >> 2) > 0)
1539 foff = align_up (foff, align >> 2);
1540
1541 if (foff < REND)
1542 {
1543 switch (len)
1544 {
1545 case 4:
1546 regcache->cooked_write (tdep->fs0_regnum + foff, val);
1547 foff++;
1548 break;
1549 case 8:
1550 regcache->cooked_write (NDS32_FD0_REGNUM + (foff >> 1), val);
1551 foff += 2;
1552 break;
1553 default:
1554 /* Long double? */
1555 internal_error (__FILE__, __LINE__,
1556 "Do not know how to handle %d-byte double.\n",
1557 len);
1558 break;
1559 }
1560 continue;
1561 }
1562 }
1563 else
1564 {
1565 /*
1566 When passing arguments using GPRs,
1567
1568 * A composite type not larger than 4 bytes is passed in $rN.
1569 The format is as if the value is loaded with load instruction
1570 of corresponding size (e.g., LB, LH, LW).
1571
1572 For example,
1573
1574 r0
1575 31 0
1576 LITTLE: [x x b a]
1577 BIG: [x x a b]
1578
1579 * Otherwise, a composite type is passed in consecutive registers.
1580 The size is rounded up to the nearest multiple of 4.
1581 The successive registers hold the parts of the argument as if
1582 were loaded using lmw instructions.
1583
1584 For example,
1585
1586 r0 r1
1587 31 0 31 0
1588 LITTLE: [d c b a] [x x x e]
1589 BIG: [a b c d] [e x x x]
1590 */
1591
1592 /* Adjust alignment. */
1593 if ((align >> 2) > 0)
1594 goff = align_up (goff, align >> 2);
1595
1596 if (len <= (REND - goff) * 4)
1597 {
1598 /* This argument can be passed wholly via GPRs. */
1599 while (len > 0)
1600 {
1601 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1602 byte_order);
1603 regcache_cooked_write_unsigned (regcache,
1604 NDS32_R0_REGNUM + goff,
1605 regval);
1606 len -= 4;
1607 val += 4;
1608 goff++;
1609 }
1610 continue;
1611 }
1612 else if (abi_split)
1613 {
1614 /* Some parts of this argument can be passed via GPRs. */
1615 while (goff < REND)
1616 {
1617 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1618 byte_order);
1619 regcache_cooked_write_unsigned (regcache,
1620 NDS32_R0_REGNUM + goff,
1621 regval);
1622 len -= 4;
1623 val += 4;
1624 goff++;
1625 }
1626 }
1627 }
1628
1629 use_stack:
1630 /*
1631 When pushing (split parts of) an argument into stack,
1632
1633 * A composite type not larger than 4 bytes is copied to different
1634 base address.
1635 In little-endian, the first byte of this argument is aligned
1636 at the low address of the next free word.
1637 In big-endian, the last byte of this argument is aligned
1638 at the high address of the next free word.
1639
1640 For example,
1641
1642 sp [ - ] [ c ] hi
1643 [ c ] [ b ]
1644 [ b ] [ a ]
1645 [ a ] [ - ] lo
1646 LITTLE BIG
1647 */
1648
1649 /* Adjust alignment. */
1650 soff = align_up (soff, align);
1651
1652 while (len > 0)
1653 {
1654 int rlen = (len > 4) ? 4 : len;
1655
1656 if (byte_order == BFD_ENDIAN_BIG)
1657 write_memory (sp + soff + 4 - rlen, val, rlen);
1658 else
1659 write_memory (sp + soff, val, rlen);
1660
1661 len -= 4;
1662 val += 4;
1663 soff += 4;
1664 }
1665 }
1666
1667 /* Finally, update the SP register. */
1668 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1669
1670 return sp;
1671
1672 error_no_fpr:
1673 /* If use_fpr, but no floating-point register exists,
1674 then it is an error. */
1675 error (_("Fail to call. FPU registers are required."));
1676 }
1677 \f
1678 /* Read, for architecture GDBARCH, a function return value of TYPE
1679 from REGCACHE, and copy that into VALBUF. */
1680
1681 static void
1682 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1683 struct regcache *regcache, gdb_byte *valbuf)
1684 {
1685 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1686 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1687 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1688 int calling_use_fpr;
1689 int len;
1690
1691 calling_use_fpr = nds32_check_calling_use_fpr (type);
1692 len = TYPE_LENGTH (type);
1693
1694 if (abi_use_fpr && calling_use_fpr)
1695 {
1696 if (len == 4)
1697 regcache->cooked_read (tdep->fs0_regnum, valbuf);
1698 else if (len == 8)
1699 regcache->cooked_read (NDS32_FD0_REGNUM, valbuf);
1700 else
1701 internal_error (__FILE__, __LINE__,
1702 _("Cannot extract return value of %d bytes "
1703 "long floating-point."), len);
1704 }
1705 else
1706 {
1707 /*
1708 When returning result,
1709
1710 * A composite type not larger than 4 bytes is returned in $r0.
1711 The format is as if the result is loaded with load instruction
1712 of corresponding size (e.g., LB, LH, LW).
1713
1714 For example,
1715
1716 r0
1717 31 0
1718 LITTLE: [x x b a]
1719 BIG: [x x a b]
1720
1721 * Otherwise, a composite type not larger than 8 bytes is returned
1722 in $r0 and $r1.
1723 In little-endian, the first word is loaded in $r0.
1724 In big-endian, the last word is loaded in $r1.
1725
1726 For example,
1727
1728 r0 r1
1729 31 0 31 0
1730 LITTLE: [d c b a] [x x x e]
1731 BIG: [x x x a] [b c d e]
1732 */
1733
1734 ULONGEST tmp;
1735
1736 if (len < 4)
1737 {
1738 /* By using store_unsigned_integer we avoid having to do
1739 anything special for small big-endian values. */
1740 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1741 store_unsigned_integer (valbuf, len, byte_order, tmp);
1742 }
1743 else if (len == 4)
1744 {
1745 regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1746 }
1747 else if (len < 8)
1748 {
1749 int len1, len2;
1750
1751 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1752 len2 = len - len1;
1753
1754 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1755 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1756
1757 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1758 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1759 }
1760 else
1761 {
1762 regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1763 regcache->cooked_read (NDS32_R0_REGNUM + 1, valbuf + 4);
1764 }
1765 }
1766 }
1767
1768 /* Write, for architecture GDBARCH, a function return value of TYPE
1769 from VALBUF into REGCACHE. */
1770
1771 static void
1772 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1773 struct regcache *regcache, const gdb_byte *valbuf)
1774 {
1775 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1776 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1777 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1778 int calling_use_fpr;
1779 int len;
1780
1781 calling_use_fpr = nds32_check_calling_use_fpr (type);
1782 len = TYPE_LENGTH (type);
1783
1784 if (abi_use_fpr && calling_use_fpr)
1785 {
1786 if (len == 4)
1787 regcache->cooked_write (tdep->fs0_regnum, valbuf);
1788 else if (len == 8)
1789 regcache->cooked_write (NDS32_FD0_REGNUM, valbuf);
1790 else
1791 internal_error (__FILE__, __LINE__,
1792 _("Cannot store return value of %d bytes "
1793 "long floating-point."), len);
1794 }
1795 else
1796 {
1797 ULONGEST regval;
1798
1799 if (len < 4)
1800 {
1801 regval = extract_unsigned_integer (valbuf, len, byte_order);
1802 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1803 }
1804 else if (len == 4)
1805 {
1806 regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1807 }
1808 else if (len < 8)
1809 {
1810 int len1, len2;
1811
1812 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1813 len2 = len - len1;
1814
1815 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1816 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1817
1818 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1819 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1820 regval);
1821 }
1822 else
1823 {
1824 regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1825 regcache->cooked_write (NDS32_R0_REGNUM + 1, valbuf + 4);
1826 }
1827 }
1828 }
1829
1830 /* Implement the "return_value" gdbarch method.
1831
1832 Determine, for architecture GDBARCH, how a return value of TYPE
1833 should be returned. If it is supposed to be returned in registers,
1834 and READBUF is non-zero, read the appropriate value from REGCACHE,
1835 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1836 from WRITEBUF into REGCACHE. */
1837
1838 static enum return_value_convention
1839 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1840 struct type *type, struct regcache *regcache,
1841 gdb_byte *readbuf, const gdb_byte *writebuf)
1842 {
1843 if (TYPE_LENGTH (type) > 8)
1844 {
1845 return RETURN_VALUE_STRUCT_CONVENTION;
1846 }
1847 else
1848 {
1849 if (readbuf != NULL)
1850 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1851 if (writebuf != NULL)
1852 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1853
1854 return RETURN_VALUE_REGISTER_CONVENTION;
1855 }
1856 }
1857 \f
1858 /* Implement the "get_longjmp_target" gdbarch method. */
1859
1860 static int
1861 nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1862 {
1863 gdb_byte buf[4];
1864 CORE_ADDR jb_addr;
1865 struct gdbarch *gdbarch = get_frame_arch (frame);
1866 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1867
1868 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1869
1870 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1871 return 0;
1872
1873 *pc = extract_unsigned_integer (buf, 4, byte_order);
1874 return 1;
1875 }
1876 \f
1877 /* Validate the given TDESC, and fixed-number some registers in it.
1878 Return 0 if the given TDESC does not contain the required feature
1879 or not contain required registers. */
1880
1881 static int
1882 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1883 struct tdesc_arch_data *tdesc_data,
1884 int *fpu_freg, int *use_pseudo_fsrs)
1885 {
1886 const struct tdesc_feature *feature;
1887 int i, valid_p;
1888
1889 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1890 if (feature == NULL)
1891 return 0;
1892
1893 valid_p = 1;
1894 /* Validate and fixed-number R0-R10. */
1895 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1896 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1897 nds32_register_names[i]);
1898
1899 /* Validate R15. */
1900 valid_p &= tdesc_unnumbered_register (feature,
1901 nds32_register_names[NDS32_TA_REGNUM]);
1902
1903 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1904 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1905 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1906 nds32_register_names[i]);
1907
1908 if (!valid_p)
1909 return 0;
1910
1911 /* Fixed-number R11-R27. */
1912 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1913 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1914
1915 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1916 if (feature != NULL)
1917 {
1918 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1919 int freg = -1;
1920
1921 /* Guess FPU configuration via listed registers. */
1922 if (tdesc_unnumbered_register (feature, "fd31"))
1923 freg = 3;
1924 else if (tdesc_unnumbered_register (feature, "fd15"))
1925 freg = 2;
1926 else if (tdesc_unnumbered_register (feature, "fd7"))
1927 freg = 1;
1928 else if (tdesc_unnumbered_register (feature, "fd3"))
1929 freg = 0;
1930
1931 if (freg == -1)
1932 /* Required FDR is not found. */
1933 return 0;
1934 else
1935 *fpu_freg = freg;
1936
1937 /* Validate and fixed-number required FDRs. */
1938 num_fdr_regs = num_fdr_map[freg];
1939 for (i = 0; i < num_fdr_regs; i++)
1940 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1941 NDS32_FD0_REGNUM + i,
1942 nds32_fdr_register_names[i]);
1943 if (!valid_p)
1944 return 0;
1945
1946 /* Count the number of listed FSRs, and fixed-number them if present. */
1947 num_fsr_regs = num_fsr_map[freg];
1948 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1949 num_listed_fsr = 0;
1950 for (i = 0; i < num_fsr_regs; i++)
1951 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1952 fs0_regnum + i,
1953 nds32_fsr_register_names[i]);
1954
1955 if (num_listed_fsr == 0)
1956 /* No required FSRs are listed explicitly, make them pseudo registers
1957 of FDRs. */
1958 *use_pseudo_fsrs = 1;
1959 else if (num_listed_fsr == num_fsr_regs)
1960 /* All required FSRs are listed explicitly. */
1961 *use_pseudo_fsrs = 0;
1962 else
1963 /* Some required FSRs are missing. */
1964 return 0;
1965 }
1966
1967 return 1;
1968 }
1969
1970 /* Initialize the current architecture based on INFO. If possible,
1971 re-use an architecture from ARCHES, which is a list of
1972 architectures already created during this debugging session.
1973
1974 Called e.g. at program startup, when reading a core file, and when
1975 reading a binary file. */
1976
1977 static struct gdbarch *
1978 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1979 {
1980 struct gdbarch *gdbarch;
1981 struct gdbarch_tdep *tdep;
1982 struct gdbarch_list *best_arch;
1983 struct tdesc_arch_data *tdesc_data = NULL;
1984 const struct target_desc *tdesc = info.target_desc;
1985 int elf_abi = E_NDS_ABI_AABI;
1986 int fpu_freg = -1;
1987 int use_pseudo_fsrs = 0;
1988 int i, num_regs, maxregs;
1989
1990 /* Extract the elf_flags if available. */
1991 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1992 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
1993
1994 /* If there is already a candidate, use it. */
1995 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
1996 best_arch != NULL;
1997 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
1998 {
1999 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2000
2001 if (idep->elf_abi != elf_abi)
2002 continue;
2003
2004 /* Found a match. */
2005 break;
2006 }
2007
2008 if (best_arch != NULL)
2009 return best_arch->gdbarch;
2010
2011 if (!tdesc_has_registers (tdesc))
2012 tdesc = tdesc_nds32;
2013
2014 tdesc_data = tdesc_data_alloc ();
2015
2016 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2017 {
2018 tdesc_data_cleanup (tdesc_data);
2019 return NULL;
2020 }
2021
2022 /* Allocate space for the new architecture. */
2023 tdep = XCNEW (struct gdbarch_tdep);
2024 tdep->fpu_freg = fpu_freg;
2025 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2026 tdep->fs0_regnum = -1;
2027 tdep->elf_abi = elf_abi;
2028
2029 gdbarch = gdbarch_alloc (&info, tdep);
2030
2031 set_gdbarch_wchar_bit (gdbarch, 16);
2032 set_gdbarch_wchar_signed (gdbarch, 0);
2033
2034 if (fpu_freg == -1)
2035 num_regs = NDS32_NUM_REGS;
2036 else if (use_pseudo_fsrs == 1)
2037 {
2038 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2039 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2040 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2041 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2042 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2043
2044 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2045 }
2046 else
2047 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2048
2049 set_gdbarch_num_regs (gdbarch, num_regs);
2050 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2051
2052 /* Cache the register number of fs0. */
2053 if (fpu_freg != -1)
2054 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2055
2056 /* Add NDS32 register aliases. To avoid search in user register name space,
2057 user_reg_map_name_to_regnum is not used. */
2058 maxregs = gdbarch_num_cooked_regs (gdbarch);
2059 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2060 {
2061 int regnum, j;
2062
2063 regnum = -1;
2064 /* Search register name space. */
2065 for (j = 0; j < maxregs; j++)
2066 {
2067 const char *regname = gdbarch_register_name (gdbarch, j);
2068
2069 if (regname != NULL
2070 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2071 {
2072 regnum = j;
2073 break;
2074 }
2075 }
2076
2077 /* Try next alias entry if the given name can not be found in register
2078 name space. */
2079 if (regnum == -1)
2080 continue;
2081
2082 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2083 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2084 }
2085
2086 nds32_add_reggroups (gdbarch);
2087
2088 /* Hook in ABI-specific overrides, if they have been registered. */
2089 info.tdesc_data = tdesc_data;
2090 gdbarch_init_osabi (info, gdbarch);
2091
2092 /* Override tdesc_register callbacks for system registers. */
2093 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2094
2095 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2096 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2097 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2098 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2099 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2100 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2101
2102 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2103 set_gdbarch_return_value (gdbarch, nds32_return_value);
2104 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2105
2106 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2107 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2108 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2109 nds32_breakpoint::kind_from_pc);
2110 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2111 nds32_breakpoint::bp_from_kind);
2112
2113 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2114 frame_base_set_default (gdbarch, &nds32_frame_base);
2115
2116 /* Handle longjmp. */
2117 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2118
2119 /* The order of appending is the order it check frame. */
2120 dwarf2_append_unwinders (gdbarch);
2121 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2122 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2123
2124 return gdbarch;
2125 }
2126
2127 void
2128 _initialize_nds32_tdep (void)
2129 {
2130 /* Initialize gdbarch. */
2131 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2132
2133 initialize_tdesc_nds32 ();
2134 nds32_init_reggroups ();
2135 }
GDB Binutils - Deliverables
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